JTAG-Adapter

Installation Information

P/N 224341 Revision AB

November 2005
Introduction

Introduction

The JTAG-Adapter is an interface board which connects download cables of different

suppliers to the Motorola standard programming connector.
A programming adapter is used to download the contents of a programmable logic
device or a programmable memory from a PC or workstation to the devices on the
board.

2 JTAG-Adapter
 Connectors

Connectors

The JTAG-Adapter provides the following connectors:

HEADER 10* DSUB 9*

HEADER 8* Power

HEADER 18* Update

Connector

SMD
HEADER 16~
HEADER 20#

Legend:
*= Input Connector
~= Input or Output Connector
#= Output Connector

Figure 1: Location of Connectors

Input Connectors
The JTAG-Adapter provides five input connectors (see figure below).
HEADER 10* DSUB 9*

HEADER 8*

HEADER 18*

HEADER 16~

Figure 2: Location of Input Connectors

JTAG-Adapter 3
Connectors

HEADER 18
HEADER 18 is an 18-pin header which is used for Xilinx EPLD and FPGA program-
ming. The JTAG-Adapter detects which download cable is used. Supported Xilinx
cables are:
• Serial XChecker
• Parallel XChecker III or IV
• MultiLinx cable
The following connector pinouts give information on which signal is assigned to
which pin.

1 VP5 VP5 10
2 GND TDO 11
3 n.c. Reserved 12
4 Reserved n.c. 13
5 Reserved TDI 14
6 Reserved TCK 15
7 Reserved TMS 16
8 Reserved Reserved 17
9 Reserved Reserved 18

Figure 3: HEADER 18 (P40) - Pinout for Xilinx Serial XChecker or MultiLinx Download Cables

1 VP5 VP5 10
2 GND GND 11
3 Reserved n.c. 12
4 n.c. TCK 13
5 n.c. - 14
6 Reserved TDO 15
7 Reserved TDI 16
8 Reserved n.c. 17
9 n.c. TMS 18

Figure 4: HEADER 18 (P40) - Pinout for Xilinx Parallel XChecker III or IV Download Cables

HEADER 8
HEADER 8 is an 8-pin single row header for programming Lattice EPLDs and FPGAs
with one of the following Lattice download cables:
• HW-USB-1A
• pDS4102-DL2(A)
The following connector pinout gives information on which signal is assigned to
which pin.

4 JTAG-Adapter
 Connectors

1 VP5
2 SDO/TDO
3 SDI/TDI
4 ISPEN
5 n.c.
6 MODE/TMS
7 GND
8 SCLK/TCK

Figure 5: HEADER 8 (P70) - Pinout for Lattice Download Cables

HEADER 10
HEADER 10 is a 10-pin double-row header for:
• Programming Lattice EPLDs or FPGAs via the HW7265-DL2(A) cable
• Programming Xilinx EPLDs or FPGAs via the Xilinx Platform Cable USB DLC9
• Programming the Atmel microcontroller (SPI) via an SDK500 cable
• Testing JTAG
The following connector pinouts give information on which signal is assigned to
which pin.

1 TRST GND 2
3 TDI SENSE_GND 4
5 TDO GND 6
7 TMS GND 8
9 TCK GND 10

Figure 6: HEADER 10 - Connector for JTAG Testing

1 TCK GND 2
3 TMS SENSE_GND 4
5 TDI VP5 6
7 TDO GND 8
9 TRST ISP EN 10

Figure 7: HEADER 10 - Pinout for Lattice and Xilinx EPLD or FPGA Programming

1 MOSI GND 2
3 n.c. SENSE_GND 4
5 RESET GND 6
7 SCK GND 8
9 MISO GND 10

Figure 8: HEADER 10 - Connector for SPI Programming

JTAG-Adapter 5
Connectors

HEADER 16
HEADER 16 is a 16-pin double-row header with one JTAG port.
The following connector pinout gives information on which signal is assigned to
which pin.

1 TRST SENSE_GND 2
3 TDI GND 4
5 TDO GND 6
7 TMS GND 8
9 TCK GND 10
11 Reserved GND 12
13 Reserved GND 14
15 Reserved GND 16

Figure 9: HEADER 16 (P50) - Connector for other Programming Cables

DSUB 9
DSUB 9 is a 9-pin DSub connector which can be used for one of the following:
• Connecting a terminal
• Programming I2C devices
The following connector pinout gives information on which signal is assigned to
which pin.

1 DCD 1
6 DSR 6
2 RXD RTS 7
3 TXD CTS 8
4 DTR RI
9 9
5 GND 5

Figure 10: DSUB 9 (P90)

6 JTAG-Adapter
 Connectors

Output Connectors
The JTAG-Adapter provides two output connectors (see figure below).

SMD
HEADER 16~
HEADER 20#

Figure 11: Location of Output Connectors

HEADER 16
HEADER 16 is a 16-pin header which is an alternate output connector for low cost
boards and supports only one JTAG port with a long and a short chain.
The following connector pinout gives information on which signal is assigned to
which pin.

1 TRST SENSE_GND 2
3 TDI GND 4
5 TDO_LONG GND 6
7 TMS GND 8
9 TCK GND 10
11 Reserved GND 12
13 TDO_SHORT GND 14
15 Reserved GND 16

Figure 12: HEADER 16 (P50) - Pinout for JTAG Programming

HEADER 20
HEADER 20 is a 20-pin SMD header which also provides the power supply of the
adapter. It is connected via a 20-pin flat cable to a 21-pin Motorola standard connector
located on the programmable board. The 20-pin SMD header supports:
• JTAG port
• Early JTAG port
• I2C port for BIB

JTAG-Adapter 7
Connectors

• ISP port
• Second I2C port for e.g. SPD
• TTL level serial interface port
• SPI port
The following connector pinouts give information on which signal is assigned to
which pin.

Note: Signal SER_RXD on pin 20 goes from the connected board on HEADER 20
via the JTAG-Adapter to the receive input of a terminal. Signal SER_TXD on pin 9
goes from the transmit output of a terminal via the JTAG-Adapter to the connected
board on HEADER 20.

1 GND JTAG_EARLY_TDO 11
2 JTAG_TRST n.c. 12
3 JTAG_TCK BIB_SDA 13
4 JTAG_TMS BIB_SCK 14
5 JTAG_TDI I2C_VP5 15
6 JTAG_TDO_Long VP5_EARLY 16
7 JTAG_TDO_Short SPD_SDA 17
8 JTAG_EARLY_TMS SPD_SCK 18
9 SER_TXD JTAG_EARLY_TDI 19
10 JTAG_EARLY_TCK SER_RXD 20

Figure 13: SMD HEADER 20 (P30) - Pinout for JTAG, ISP and I2C Programming and Serial Interface Connec-
tion

1 GND SPI_MISO 11
2 JTAG_TRST n.c. 12
3 JTAG_TCK BIB_SDA 13
4 JTAG_TMS BIB_SCK 14
5 JTAG_TDI I2C_VP5 15
6 JTAG_TDO_Long VP5_EARLY 16
7 SPI_RESET1 n.c. 17
8 SPI_SCK SPI_RESET3 18
9 SER_TXD SPI_RESET2 19
10 SPI_MOSI SER_RXD 20

Figure 14: SMD HEADER 20 (P30) - Pinout for SPI, JTAG and I2C Programming and Serial Interface Connec-
tion

Power Connector
A 4-pin hard-disk connector can be used to power the adapter if you want to program
several boards in a row. With the use of the power connector, the power supply is not
intersected when the SMD header is placed on another board and a reconfiguration of
the Xilinx download cables is not necessary.

8 JTAG-Adapter
 Connectors

Update Connector
The Motorola standard connector, a 21-pin SMD connector, is available to update the
JTAG-Adapter firmware. The JTAG-Adapter can be reprogrammed to support new
features. Therefore, a second JTAG-Adapter is necessary.
Power

HEADER 18* Update

Connector

SMD
HEADER 20#

In order to connect two JTAG-Adapters, proceed as follows:

1. Connect the power cable to the power connector of the JTAG-Adapter to be
updated

Power cable

JTAG-Adapter 9
Connectors

2. Connect the 20-pin flat cable to the HEADER 20 of the second JTAG-
Adapter
3. Connect the other side of the cable to the update connector of the JTAG-
Adapter to be updated
HEADER 20 on
second JTAG Adapter

Update connector on
JTAG Adapter to be
updated

4. Connect the Xilinx programming cable (e.g. MultiLinx cable) to the-

HEADER 18 of the second JTAG-Adapter

5. Set all dip switches of SW1 and SW2 of the second JTAG-Adapter to ON
6. Connect the other side of the Xilinx programming cable (e.g. MultiLinx
cable) to the parallel, serial or USB port of the PC or workstation
7. Connect the other end of the power cable to the power supply
8. Program the devices with the Xilinx software (e.g. Impact)

10 JTAG-Adapter
 Connectors

SMD HEADER 21 Connector

The following connector pinouts five information on which signal is assigned to
which pin.

Note: Signal SER_RXD on pin 20 goes from the connected board on HEADER 21
via the JTAG-Adapter to the receive input of a terminal. Signal SER_TXD on pin 9
goes from the transmit output of a terminal via the JTAG-Adapter to the connected
board on HEADER 21.

1 GND
n.c. 12
2 JTAG_TRST
BIB_SDA 13
3 JTAG_TCK
BIB_SCK 14
4 JTAG_TMS
JTAG_TDI I2C_VP5 15
5
VP5_EARLY 16
6 JTAG_TDO_Long
SPD_SDA 17
7 JTAG_TDO_Short
SPD_SCK 18
8 JTAG_EARLY_TMS
JTAG_EARLY_TDI 19
9 SER_TXD
SER_RXD 20
10 JTAG_EARLY_TCK
PROGEN 21
11 JTAG_EARLY_TDO

Figure 15: SMD HEADER 21 - Pinout for JTAG, ISP and I2C Programming and Serial Interface Connection

1 GND
n.c. 12
2 JTAG_TRST
BIB_SDA 13
3 JTAG_TCK
BIB_SCK 14
4 JTAG_TMS
I2C_VP5 15
5 JTAG_TDI
VP5_EARLY 16
6 JTAG_TDO_Long
n.c. 17
7 SPI_RESET1
SPI_RESET3 18
8 SPI_SCK
SPI_RESET2 19
9 SER_TXD
SER_RXD 20
10 SPI_MOSI
PROGEN 21
11 SPI_MISO

Figure 16: SMD HEADER 21 - Pinout for SPI, JTAG and I2C Programming and Serial Interface Connection

JTAG-Adapter 11
Cables

Cables

This section describes the connection of the Xilinx Multilinx cable and the Xilinx Plat-
form Cable USB DLC9.

Xilinx Multilinx Cable

The picture below shows how the Xilinx Multilinx Cable must be connected to
HEADER 18 of the JTAG-Adapter.

Xilinx Platform Cable USB DLC9

This section shows how the Xilinx Platform Cable USB DLC9 must be set up and con-
nected.
1. Set up a bridge between pins 4 and 8 of the little black connector delivered with
the Xilinx Platform Cable

1 2
3 4
5 6
7 8
9 10

12 JTAG-Adapter
 Cables

2. Connect the cables to the little black connector as follows

Yellow (RCK/CCLK) 1 2 Empty
Green (TMS/PROG) 3 4 Empty
White (TDI/DIN) 5 6 Pink (VREF/VREF)
Lilac (TDO/DONE) 7 8 Black (GND/GND)
Grey (_ _ _/INIT) 9 10 Empty

3. Connect the Xilinx adapter to the Xilinx Platform Cable USB

4. Connect the Xilinx Platform Cable USB DLC9 to the HEADER 10 connector of the
Motorola JTAG-Adapter

JTAG-Adapter 13
Switches

Switches

The JTAG-Adapter provides two configuration switches.

SW 2 SW 1

Figure 17: Location of Switches

The switches are used to configure the function of the used input and output connec-
tors. The switch settings required for the possible applications are given in the table
below.

Note: These switch settings are only valid for firmware rev. 8 or later.

Table 1: Required Switch Settings, Part 1

Desired Program- Cable Type PC I/F Input SW2 Further Pos-

Application mable Connector sibilities
Device

JTAG Xilinx MultiLinx USB HEADER 18 See next

Programming EPLDs/ table, rows
FPGAs 1-6

Parallel Parallel HEADER 18 See next

XChecker III table, rows
1-6

Parallel Parallel HEADER 18 See next

XChecker table, rows
IV1) 1-6

Platform USB HEADER 10 See next

Cable USB table, rows
DLC9 1-6

14 JTAG-Adapter
 Switches

Table 1: Required Switch Settings, Part 1 (cont.)

Desired Program- Cable Type PC I/F Input SW2 Further Pos-

Application mable Connector sibilities
Device

Serial Serial HEADER 18 See next

XChecker table, rows
1-6

Lattice HW-USB-1A USB HEADER 8 See next

EPLDs/ table, rows
FPGAs 1-6

pDS4102- Parallel HEADER 10 See next

DL2(A) table, rows
1-6

HW7265- Parallel HEADER 8 See next

DL2(A) table, rows
1-6

I2C I2C Serial Serial DSUB See next

Programming PROMs (9-pin/9- table, rows 7
pin) and 8

SPI Atmega SDK500 Serial HEADER 10 See next

Programming (IPMC) table, rows
9-11

Terminal - Serial Serial DSUB See next

Interface (9-pin/ table, row 12
9-pin)

firmware - - - - See next

revision via table, row 13
LEDs

1. This configuration is only possible if R42 is assembled with a 0 Ohm resistor or if pins 1 and 10
of HEADER 18 are connected.

Table 2: Required Switch Settings, Part 2

No. Destination I/F Output SW1

Selection Connector

1 Short JTAG HEADER 20

Chain

2 Short JTAG HEADER 16

Chain

JTAG-Adapter 15
Switches

Table 2: Required Switch Settings, Part 2 (cont.)

No. Destination I/F Output SW1

Selection Connector

3 Long JTAG HEADER 20

Chain

4 Long JTAG HEADER 16

Chain

5 Early JTAG HEADER 20

Chain

6 Early JTAG HEADER 20

Chain with alter-
nate TDI

7 I2C I/F 1 (BIBs) HEADER 20

8 I2C I/F 2 (SPDs) HEADER 20

9 SPI device 1 HEADER 20

10 SPI device 2 HEADER 20

11 SPI device 3 HEADER 20

12 - HEADER 20

13 - -

16 JTAG-Adapter
 LEDs

LEDs

In order to identify the input and output connectors and the function which takes
place, the JTAG-Adapter provides one multi-color LED per connector.

LED 18 LED 20
LED 12

LED 10

LED 14

LED 16

When the adapter is connected to a board and the board is powered-on, all LEDs
shine shortly orange to indicate that they work and the board is in reset. The statuses
for single LEDs are explained in the following table.
Table 3: Description of LED Display

LED Color LED Status Description

Green Permanent Connector is output connector for JTAG or ISP

Fast blinking No output connector is currently connected to the program-

ming board

Red Permanent Connector is input connector

One or more LEDs fast No input connector is currently connected to the program-
blinking ming adapter

Orange Permanent1) Connector is input connector with alternate pinout

All LEDs fast blinking Switch settings are invalid

1. On the 18-pin header, indicates if a parallel XChecker cable III or IV is connected or on a 10-pin
header, indicates if a JTAG tester cable is connected.

JTAG-Adapter 17
LEDs

If the switches are set in such a way that the firmware revision of the JTAG-Adapter
is displayed via LEDs, one or more LEDs shine permanently orange. Revision 8 is the
latest revision of the JTAG-Adapter until August 2004.
Table 4: Firmware Revision via LEDs

Rev. LED 20 LED 18 LED 12 LED 10 LED 14 LED 16

1 OFF OFF OFF OFF OFF Orange

2 OFF OFF OFF OFF Orange OFF

3 Not used Not used Not used Not used Not used Not used

4 OFF OFF OFF Orange OFF OFF

5 OFF OFF OFF Orange OFF Orange

6 OFF OFF OFF Orange Orange OFF

7 OFF OFF OFF Orange Orange Orange

8 OFF OFF Orange OFF OFF OFF

... ... ... ... ... ... ...

63 Orange Orange Orange Orange Orange Orange

18 JTAG-Adapter
 Revision History

Revision History

SAP Rev. Date Description

No.

222797 AA August 2001 First version

222797 AB February 2004 Added switch configuration descriptions to Table 1 “Required

Switch Settings” on page 2; modified Figure 3 “HEADER 18
(P40) - Pinout for Xilinx Serial XChecker or MultiLinx Down-
load Cables” on page 4; modified Figure 4 “HEADER 18 (P40)
- Pinout for Xilinx Parallel XChecker III or IV Download
Cables” on page 4; modified Figure 5 “HEADER 8 (P70) -
Pinout for Lattice Download Cables” on page 5; added
Figure 9 “HEADER 16 (P50) - Connector for other Program-
ming Cables” on page 6; modified the “Output Connectors”
section on page 7; modified Figure 13 “SMD HEADER 20
(P30) - Pinout for JTAG, ISP and I2C Programming and Serial
Interface Connection” on page 8; Figure 15 “SMD HEADER 21
- Pinout for JTAG, ISP and I2C Programming and Serial Inter-
face Connection” on page 11; modified Figure 12 “HEADER
16 (P50) - Pinout for JTAG Programming” on page 7; updated
Table 4 “Firmware Revision via LEDs” on page 18
Editorial changes

JTAG-Adapter 19
Revision History

SAP Rev. Date Description

No.

224341 AA August 2004 Changed sequence of sections “Connectors” and “Switches;

modified Figure 1 “Location of Connectors” on page 3; added
Figure 2 “Location of Input Connectors” on page 3; modified
the “Input Connectors” section on page 3; modified pin 10 of
Figure 3 “HEADER 18 (P40) - Pinout for Xilinx Serial
XChecker or MultiLinx Download Cables” on page 4 and
Figure 4 “HEADER 18 (P40) - Pinout for Xilinx Parallel
XChecker III or IV Download Cables” on page 4, added
Figure 7 “HEADER 10 - Pinout for Lattice and Xilinx EPLD or
FPGA Programming” on page 5 and Figure 8 “HEADER 10 -
Connector for SPI Programming” on page 5; added Figure 11
“Location of Output Connectors” on page 7; added Figure 14
“SMD HEADER 20 (P30) - Pinout for SPI, JTAG and I2C Pro-
gramming and Serial Interface Connection” on page 8; added
Figure 16 “SMD HEADER 21 - Pinout for SPI, JTAG and I2C
Programming and Serial Interface Connection” on page 11,
modified the “Switches” section on page 14; modified Table 3
“Description of LED Display ” on page 17;
layout and editorial changes

224341 AB November Added information on Xilinx USB cable in the “HEADER 10”
2005 section on page 5 and Table 1 “Required Switch Settings, Part
1” on page 14
Corrected Figure 14 “SMD HEADER 20 (P30) - Pinout for SPI,
JTAG and I2C Programming and Serial Interface Connection”
on page 8 and Figure 16 “SMD HEADER 21 - Pinout for SPI,
JTAG and I2C Programming and Serial Interface Connection”
on page 11
Added note on page 8
Added pictures in the “Update Connector” section on page 9
Added the “Cables” section on page 12
Changed logo from Force Computers to Motorola
Changed copyright from Force Computers to Motorola
Editorial changes

20 JTAG-Adapter
 Copyright

©Copyright 2005 Motorola GmbH

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