1

Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

64Gb NAND FLASH

H27UCG8V(5/F)M
H27UCG8V5M
H27UCG8VFM

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.6 / Jul. 2008 1
 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

Document Title
64Gbit (8Gx8bit) NAND Flash Memory

Revision History

Revision No. History Draft Date Remark

0.0 Initial Draft. Oct. 12. 2007 Preliminary

1) Add H27UCG8VFM Product.

- Text, Figure, DC and Operating Characteristic table are added.

3.3Volt (4CE)
Symbol
Min Typ Max

ICC1 - 15 30

ICC2 - 15 30

ICC3 - 15 30

ICC4 - - 1

0.1 ICC5 - 40 200 Jan. 17. 2008 Preliminary

ILI - - ± 40

ILO - - ± 40

VIH 0.8xVcc - Vcc+0.3

VIL -0.3 - 0.2xVcc

VOH 2.4 - -

VOL - - 0.4

IOL
8 10 -
(R/B)

1) Add VLGA Package.

0.2 Feb. 25. 2008 Preliminary
- Figures & Texts are added.

0.3 1) Correct TLGA to VLGA Mar. 27. 2008 Preliminary

1) Add the text related to the multi-plane copyback function.

- Multi-Plane copyback function must be used in the block which Preliminary
0.4 Apr. 14. 2008
has been programmed with Multi-Plane Page Program.
2) Correct the ball configuration of the LGA packages.

Rev 0.6 / Jul. 2008 2

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H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

1) Correct Table 5. Mode Selection.

CLE ALE CE WE RE WP MODE

L L L H H X During Read (Busy)

↓ ↓ ↓
X X X H H X During Read (Busy)

2) Correct Table 13: Status Register Coding

0.5 Jul. 4. 2008 Preliminary
Pagae Block
IO Read CODING
Program Erase

Ready/ Ready/ Busy: ‘0’ Ready’:

5 Ready/Busy
Busy Busy ‘1’

↓
5 NA NA NA -

1) Correct the number of E/W Cycle.

0.6 Jul. 24. 2008 Preliminary
- 10 K → 5 K

Rev 0.6 / Jul. 2008 3

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H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

FEATURES SUMMARY

HIGH DENSITY NAND FLASH MEMORIES FAST BLOCK ERASE

- Cost effective solutions for mass storage applications - Block erase time: 2.5ms (Typ)
- Multi-Plane block erase time (2blocks) : 2.5ms(Typ)
MULTI-PLANE ARCHITECTURE
- Array is split into two independent planes. Parallel STATUS REGISTER
Operations on both planes are available, halving
Program, read and erase time. ELECTRONIC SIGNATURE
- 1st cycle: Manufacturer Code
NAND INTERFACE - 2nd cycle: Device Code
- x8 bus width - 3rd cycle: Internal chip number, Cell Type, Number of
- Multiplexed address/ Data Simultaneously Programmed Pages.
- Pinout compatibility for all densities - 4th cycle: Page size, Block size, Organization, Spare size
- 5th cycle: Multi-plane information
SUPPLY VOLTAGE
-3.3V device : Vcc = 2.7 V ~3.6 V CHIP ENABLE DON’T CARE
-Simple interface with microcontroller
MEMORY CELL ARRAY
- (4k + 128 ) bytes x 128 pages x 16384 blocks HARDWARE DATA PROTECTION
- Program/Erase locked during Power transitions.
PAGE SIZE
- x8 device : (4096+128 spare) bytes DATA RETENTION
: H27UCG8V(5/F)M - 5 K Program / Erase cycles (with 4bit/512byte ECC)
- 10 Years Data Retention
BLOCK SIZE
- x8 device : (512K+16K) bytes PACKAGE
- H27UCG8V(5/F)MTR
PAGE READ / PROGRAM : 48-pin TSOP1(12 x 20 x 1.2 mm)
- Random access: 60us (Max) - H27UCG8V(5/F)MTR (Lead & Halogen Free)
- Sequential access: 25ns (Min)
- Page program time: 800us (Typ) - H27UCG8VFMYR
- Multi-Plane page program time : 800us (Typ) : 52-VLGA(14 x 18 x 1.0 mm)
- H27UCG8VFMYR (Lead & Halogen Free)
COPY BACK PROGRAM
-Fast page copy

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H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

1.SUMMARY DESCRIPTION

The H27UCG8V(5/F)M is a 9192Mx8bit with spare 256Mx8 bit capacity. The device is offered in 3.3V Vcc Core Power
Supply, 3.3V Input-Output Power Supply. Its NAND cell provides the most cost-effective solution for the solid state
mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve
valid data while old data is erased.
The device contains 16384 blocks, composed by 128 pages consisting in two NAND structures of 32 series connected
Flash cells. Every cell holds two bits. Like all other 4KB page NAND Flash devices, a program operation allows to write
the 4224-byte page in typical 800us and an erase operation can be performed in typical 2.5ms on a 512K-byte block.
In addition to this, thanks to multi-plane architecture, it is possible to program 2 pages a time (one per each plane) or
to read 2 pages a time (one per each plane) to erase 2 blocks a time (again, one per each plane). As a consequence,
multi-plane architecture allows program time reduction and erase time reduction. Data in the page can be read out at
25ns cycle time per byte.
The I/O pins serve as the ports for address and data input/output as well as command input.
This interface allows a reduced pin count and easy migration towards different densities, without any rearrangement
of footprint. Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin.
The on-chip Program/Erase Controller automates all read, program and erase functions including pulse repetition,
where required, and internal verification and margining of data. The modify operations can be locked using the WP
Input.
The output pin R/B (open drain buffer) signals the status of the device during each operation.
In a system with multiple memories the R/B pins can be connected all together to provide a global status signal.
Even the write-intensive systems can take advantage of the H27UCG8V(5/F)M extended reliability of 5 K program/
erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.
The chip supports CE don’t care function. This function allows the direct download of the code from the NAND Flash
memory device by a microcontroller, since the CE transitions do not stop the read operation.
This device includes also extra Features like OTP/Unique ID area.
The H27UCG8V(5/F)M is available in 48 - TSOP1 12 x 20 mm package and 52-VLGA 14 x 18 mm Packages.

1.1 Product List

PART NUMBER ORGANIZATION Vcc RANGE PACKAGE

H27UCG8V(5/F)M 48TSOP1
x8 2.7~3.6 Volt
H27UCG8VFM 52-VLGA

Rev 0.6 / Jul. 2008 5

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H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

9&&

IO7 - IO0 Data Input / Outputs

CLE Command latch enable
&( ,2a,2
ALE Address latch enable
&(
5% CE1, CE2(1) Chip Enable
:(
RE Read Enable
5( 5%
$/( WE Write Enable

&/( WP Write Protect

:3 R/B1, R/B2(2) Ready / Busy

Vcc Power Supply

Vss Ground
NC No Connection
966

Figure1: Logic Diagram Table 1: Signal Names

Note:
1. There are CE1, CE2, CE3 & CE4 (H27UCG8VFM)
2. There are R/B1, R/B2, R/B3 & R/B4 (H27UCG8VFM)

NC 1 48 NC 1&   1&
NC NC 1& 1&
NC NC 1& 1&
NC NC 5% 1&
NC I/O7 ,2
5%
R/B2 I/O6 ,2
5%
R/B1 I/O5 ,2
5%
RE I/O4 ,2
5(
CE1 NC 1&
&(
CE2 NC 1&
&(
NC
NC NAND Flash Vcc
1& 1$1')ODVK 1&
Vcc 12 37
Vss 13 TSOP1 36 Vss
9FF 
7623  9FF
9VV
NC NC
9VV  
&( 1&
NC
NC (2CE) NC
&( &( 1&
CLE &/( 1&
ALE I/O3 ,2
$/(
WE I/O2 ,2
:(
WP I/O1 ,2
:3
NC I/O0 ,2
1&
NC NC 1&
1&
NC NC 1&
1&
NC NC 1& 1&
NC 24 25 NC 1&   1&

Figure 2: 48TSOP1 Contact, x8 Device

Rev 0.6 / Jul. 2008 6

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H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

VLGA (2CE) VLGA (4CE)

OA OA
NC A A
NC /CE4 R/B4
NC CLE /CE1 NC /CE3 CLE /CE1 R/B3
B B
OB VSS VCC
C OB VSS VCC
NC NC
C
ALE NC /CE2 /RE NC NC
ALE NC /CE2 /RE
D D
NC NC NC NC
OC E OC E
NC NC /WE R/B1 R/B2 NC NC NC /WE R/B1 NC
F R/B2
F
/WP VSS /WP VSS
G G
NC IO0 NC NC NC IO0 NC NC
H H
IO1 IO7 IO1 IO7
J J
NC IO2 IO6 NC NC IO2 IO6 NC
OD K OD
NC NC
K
IO3 IO5 NC IO3 IO5 NC
L L
NC VSS IO4 NC NC IO4
OE M OE VSS NC
M
NC VSS VCC Vss NC Vss
VSS VCC
N N
Vcc NC NC Vcc Vcc NC NC Vcc
OF OF
NC NC NC
NC

0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8

Figure 3: 52-VLGA Contact. x8 Device

Rev 0.6 / Jul. 2008 7

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H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

1.2 PIN DESCRIPTION

Pin Name Description

DATA INPUTS/OUTPUTS
The IO pins allow to input command, address and data and to output data during read / program
IO0-IO7
operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O buffer float to
High-Z when the device is deselected or the outputs are disabled.
COMMAND LATCH ENABLE
CLE This input activates the latching of the IO inputs inside the Command Register on the Rising edge of
Write Enable (WE).
ADDRESS LATCH ENABLE
ALE This input activates the latching of the IO inputs inside the Address Register on the Rising edge of
Write Enable (WE).
CHIP ENABLE
CE1, CE2(2) This input controls the selection of the device. When the device is busy CE1 & CE2(2) low does not
deselect the memory.
WRITE ENABLE
WE This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise
edge of WE.
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is
RE
valid tREA after the falling edge of RE which also increments the internal column address counter by
one.
WRITE PROTECT
WP The WP pin, when Low, provides an Hardware protection against undesired modify (program / erase)
operations.
READY BUSY
R/B1, R/B2(3) The Ready/Busy output is an Open Drain pin that signals the state of the memory.
SUPPLY VOLTAGE
Vcc
The Vcc supplies the power for all the operations (Read, Write, Erase).
Vss GROUND
NC NO CONNECTION

Table 2: Pin Description

NOTE:
1. A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple
the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required
during program and erase operations.
2. There are CE1, CE2, CE3 & CE4 pins. (H27UCG8VFM)
3. There are R/B1, R/B2, R/B3 & R/B4 pins. (H27UCG8VFM)

Rev 0.6 / Jul. 2008 8

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H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

1 Page = (4K+128)Bytes
0 Plane 1 Plane
1 Block = (4K+128)Bytes x 128pages
= (512K+16K)Bytes
0 1
1 Device = (512K+16K)Byte x 4096Block
2 3 = 16,896 Mbit
2048 Blocks
. .
per Plane
. .
(4096 Blocks
. .
per device)
4092 4093

4094 4095

I/O0 ~ 7
Page Buffer

4K Bytes 128 Bytes

Figure 4: Array Organization

IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7

1st Cycle A0 A1 A2 A3 A4 A5 A6 A7
2nd Cycle A8 A9 A10 A11 A12 L(1) L(1) L(1)
3rd Cycle A13 A14 A15 A16 A17 A18 A19 A20
4th Cycle A21 A22 A23 A24 A25 A26 A27 A28
5th Cycle A29 A30 A31 A32(2) L(1) L(1) L(1) L(1)

Table 3: Address Cycle Map(x8)

NOTE:
1. L must be set to Low.
2. A32 is set to Low. (H27UCG8VFM)
3. 1st & 2nd cycle are Column Address.
4. 3rd to 5th cycle are Row Address.

Rev 0.6 / Jul. 2008 9

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H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

Acceptable command
FUNCTION 1st CYCLE 2nd CYCLE 3rd CYCLE 4th CYCLE
during busy
PAGE READ 00h 30h - -
READ FOR COPY-BACK 00h 35h - -
READ ID 90h - - -
RESET FFh - - - Yes
PAGE PROGRAM 80h 10h -
MULTI-PLANE PAGE PROGRAM 80h 11h 81h 10h
MULTI-PLANE READ 60h 60h 30h -
COPY BACK PROGRAM 85h 10h - -
MULTI-PLANE COPYBACK PROGRAM 85h 11h 81h 10h
MULTI-PLANE COPYBACK READ 60h 60h 35h -
BLOCK ERASE 60h D0h - -
MULTI-PLANE BLOCK ERASE 60h 60h D0h -
READ STATUS REGISTER 70h - - - Yes
RANDOM DATA INPUT 85h - - -
RANDOM DATA OUTPUT 05h E0h - -
MULTI PLANE RANDOM DATA OUTPUT 00h 05h E0h -
PAGE PROGRAM WITH BACKWARD
80h 11h 80h 10h
COMPATIBILITY (2KB)
COPY BACK PROGRAM WITH
85h 11h 85h 10h
BACKWARD COMPATIBILITY (2KB)

Table 4: Command Set

CLE ALE CE WE RE WP MODE

H L L Rising H X Command Input
Read Mode
L H L Rising H X Address Input(5 cycles)
H L L Rising H H Command Input
Write Mode
L H L Rising H H Address Input(5 cycles)
L L L Rising H H Data Input
L L L H Falling X Data Output
X X X H H X During Read (Busy)
X X X X X H During Program (Busy)
X X X X X H During Erase (Busy)
X X X X X L Write Protect
X X H X X 0V/Vcc Stand By

Table 5: Mode Selection

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H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

2. BUS OPERATIO

There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input,
Data Output, Write Protect, and Standby.
Typically glitches less than 3 ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not
affect bus operations.

2.1 Command Input.

Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip
Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising
edge of Write Enable. Moreover for commands that starts a modifying operation (write/erase) the Write Protect pin must
be high. See figure 6 and table 12 for details of the timings requirements. Command codes are always applied on IO7:0,
disregarding the bus configuration.

2.2 Address Input.

Address Input bus operation allows the insertion of the memory address. Five cycles are required to input the addresses
for the 16Gbit devices. Addresses are accepted with Chip Enable low, Address Latch Enable High, Command Latch
Enable low and Read Enable high and latched on the rising edge of Write Enable. Moreover for commands that starts a
modifying operation (write/erase) the Write Protect pin must be high. See figure 7 and table 12 for details of the timings
requirements. Addresses are always applied on IO(7:0), disregarding the bus configuration.
In addition, addresses over the addressable space are disregarded even if the user sets them during command insertion.

2.3 Data Input.

Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serially and
timed by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command
Latch Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable. See figure 8
and table 12 for details of the timings requirements.

2.4 Data Output.

Data Output bus operation allows to read data from the memory array and to check the status register content, the ID
data. Data can be serially shifted out toggling the Read Enable pin with Chip Enable low, Write Enable High, Address
Latch Enable low, and Command Latch Enable low. See figures 9 to 13 and table 12 for details of the timings require-
ments.

2.5 Write Protect.

Hardware Write Protection is activated when the Write Protect pin is low. In this condition modify operation does not
start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the protec-
tion even during the power up phases.

2.6 Standby
In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced. Stand-by is obtained
holding high, at least for 10us, CE pin.

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H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

3. DEVICE OPERATION

3.1 Page Read.

Page read operation is initiated by writing 00h and 30h to the command register along with five address cycles.
In two consecutive read operaions, the second one need 00h command, which five address cycles and 30h command
initiates that operation.
Two types of operations are available: random read, serial page read. The random read mode is enabled when the
page address is changed. The 4224 bytes of data within the selected page are transfered to the data registers in less
than 60us(tR). The system controller may detect the completion of this data transfer 60us(tR) by analyzing the output
of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 25ns cycle time by
sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the data starting
from the selected column address up to the last column address. The device may output random data in a page
instead of the consecutive sequential data by writing random data output command.
The column address of next data, which is going to be out, may be changed to the address which follows random data
output command.
Random data output can be operated multiple times regardless of how many times it is done in a page.

3.2 Multi-PLANE PAGE READ

Multi-Plane Page Read is an extension of Page Read, for a single plane with 4,224 byte page registers. Since the device
is equipped with two memory planes, activating the two sets of 4,224 byte page registers enables a random read of
two pages. Multi-Plane Page Read is initiated by repeating command 60h followed by three address cycles twice. In
this case only same page of same block can be selected from each plane.
After Read Confirm command(30h) the 8,448 bytes of data within the selected two page are transferred to the data
registers in less than 60us(tR). The system controller can detect the completion of data transfer(tR) by monitoring the
output of R/B pin.
Once the data is loaded into the data registers, the data output of first plane can be read out by issuing command 00h
with Five Address Cycles, command 05h with two column address and finally E0h. The data output of second plane
can be read out using the identical command sequences. The restrictions for Multi-Plane Page Read are shown in Fig-
ure 15. Multi-Plane Read must be used in the block which has been programmed with Multi-Plane Page Program.

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H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

3.3 Page Program.

The device is programmed by page. The number of consecutive partial page programming operation within the same
page without an intervening erase operation must not exceed 1 times. The addressing should be done on each pages
in a block. A page program cycle consists of a serial data loading period in which up to 4224bytes of data may be
loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed
into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command (80h),
followed by the five cycle address inputs and then serial data. The bytes other than those to be programmed do not
need to be loaded. The device supports random data input in a page.
The column address of next data, which will be entered, may be changed to the address which follows random data
input command (85h). Random data input may be operated multiple times regardless of how many times it is done
in a page. The Page Program confirm command (10h) initiates the programming process. Writing 10h alone without
previously entering the serial data will not initiate the programming process. The internal write state controller auto-
matically executes the algorithms and timings necessary for program and verify, thereby freeing the system control-
ler for other tasks. Once the program process starts, the Read Status Register command may be entered to read the
status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or
the Status bit (I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while pro-
gramming is in progress. When the Page Program is complete, the Write Status Bit (I/O 0) may be checked. The
internal write verify detects only errors for "1"s that are not successfully programmed to "0"s.
The command register remains in Read Status command mode until another valid command is written to the com-
mand register. Figure 16 details the sequence.

3.4 Multi-Plane Program.

Device supports multiple plane program: it is possible to program in parallel 2 pages, one per each plane.
A multiple plane program cycle consists of a double serial data loading period in which up to 4224bytes of data may
be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed
into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command (80h),
followed by the five cycle address inputs and then serial data for the 1st page. Address for this page must be within
1st plane (A<20>=0). The data of 1st page other than those to be programmed do not need to be loaded. The device
supports random data input exactly like page program operation. The Dummy Page Program Confirm command (11h)
stops 1st page data input and the device becomes busy for a short time (tDBSY). Once it has become ready again,
81h command must be issued, followed by 2nd page address (5 cycles) and its serial data input. Address for this page
must be within 2nd plane (A<20>=1). Program Confirm command (10h) makes parallel programming of both pages
start. User can check operation status by R/B pin or read status register command, as if it were a normal page pro-
gram; status register command is also available during Dummy Busy time (tDBSY). In case of fail in 1st or 2nd page
program, fail bit of status register will be set: Device supports pass/fail status of each plane. (IO0 : Total, IO1: Plane0,
IO2: Plane1). Figure 18 details the sequence.

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H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

3.5 Block Erase.

The Erase operation is done on a block basis. Block address loading is accomplished in there cycles initiated by an
Erase Setup command (60h). Only address A20 to A31 is valid while A13 to A19 is ignored. The Erase Confirm com-
mand (D0h) following the block address loading initiates the internal erasing process. This two step sequence of setup
followed by execution command ensures that memory contents are not accidentally erased due to external noise con-
ditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase
and erase verify.
Once the erase process starts, the Read Status Register command may be entered to read the status register.
The system controller can detect the completion of an erase by monitoring the R/B output, or the Status bit (I/O 6) of
the Status Register. Only the Read Status command and Reset command are valid while erasing is in progress. When
the erase operation is completed, the Write Status Bit (I/O 0) may be checked.
Figure 19 details the sequence.

3.6 Multi-Plane Erase.

Multiple plane erase, allows parallel erase of two blocks, one per each memory plane.
Block erase setup command (60h) must be repeated two times, each time followed by 1st block and 2nd block address
respectively (3 cycles each). As for block erase, D0h command makes embedded operation start. Multi-plane erase
does not need any Dummy Busy Time between 1st and 2nd block address insertion. Address limitation required for
multiple plane program applies also to multiple plane erase, as well as operation progress can be checked like for mul-
tiple plane program. Figure 20 details the sequence

3.7 Copy-Back Program

Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page
without data reloading when the bit error is not in data stored. Since the time-consuming re-loading cycles are
removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated
and the rest of the block also needs to be copied to the newly assigned free block. Copy-Back operation is a sequential
execution of Read for Copy-Back and of copy-back program with the destination page address. A read operation with
"35h" command and the address of the source page moves the whole 4224-byte data into the internal data buffer. A
bit error is checked by sequential reading the data output. In the case where there is no bit error, the data do not need
to be reloaded. Therefore Copy-Back program operation is initiated by issuing Page-Copy Data-Input command (80h)
with destination page address. Actual programming operation begins after Program Confirm command (15h) is issued.
Once the program process starts, the Read Status Register command (70h) may be entered to read the status register.
The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/
O 6) of the Status Register.
When the Copy-Back Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 21 & Figure 22). The
command register remains in Read Status command mode until another valid command is written to the command
register. During copy-back program, data modification is possible using random data input command (85h) as shown
in Figure 22.
Copy-back program operation is allowed only within same plane.

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H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

3.8 Multi-Plane Copy-Back Program

Multi-Plane Copy-Back Program is an extension of Copy-Back Program, for a single plane with 4224 byte page regis-
ters. Since the device is equipped with two memory planes, activating the two sets of 4224 byte page registers
enables a simultaneous programming of two pages. Figure 23 shows the command sequence for the multi-plane copy-
back operation. Multi-Plane copyback function must be used in the block which has been programmed with Multi-Plane
Page Program.

3.9 Read Status Register.

The device contains a Status Register which may be read to find out whether, program or erase operation is com-
pleted, and whether the program or erase operation is completed successfully. After writing 70h command to the com-
mand register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE,
whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory
connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer
to table 13 for specific Status Register definitions. The command register remains in Status Read mode until further
commands are issued to it. Therefore, if the status register is read during a random read cycle, the read command
(00h) should be given before starting read cycles.

3.10 Read ID.

The device contains a product identification mode, initiated by writing 90h to the command register, followed by an
address input of 00h. Five read cycles sequentially output the manufacturer code (ADh), and the device code and 3rd,
4th, 5th cycle ID, respectively. The command register remains in Read ID mode until further commands are issued to
it. Figure 25 shows the operation sequence, while tables 15 explain the byte meaning.

3.11 Reset.
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state
during random read, program or erase mode, the reset operation will abort these operations. The contents of memory
cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is
cleared to wait for the next command, and the Status Register is cleared to value E0h when WP is high. Refer to table
13 for device status after reset operation. If the device is already in reset state a new reset command will not be
accepted by the command register. The R/B pin goes low for tRST after the Reset command is written. Refer to Figure
28.

Rev 0.6 / Jul. 2008 15

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

4. OTHER FEATURES

4.1 Data Protection & Power On/Off Sequence

The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal
voltage detector disables all functions whenever Vcc is below about 2.0V(3.3V device). WP pin provides hardware pro-
tection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10us is
required before internal circuit gets ready for any command sequences as shown in Figure 29. The two-step command
sequence for program/erase provides additional software protection.

4.2 Ready/Busy.
The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase,
copy-back and random read completion. The R/B pin is normally high and goes to low when the device is busy (after a
reset, read, program, erase operation). It returns to high when the internal controller has finished the operation. The
pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied.
Because pull-up resistor value is related to tR(R/B) and current drain during busy (Ibusy), an appropriate value can be
obtained with the following reference chart (Fig 30). Its value can be determined by the following guidance.

Rev 0.6 / Jul. 2008 16

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

Parameter Symbol Min Typ Max Unit

Valid Block Number NVB 15984 16384 Blocks

Table 6: Valid Blocks Number

NOTE:
1. The 1st block is guaranteed to be a valid block at the time of shipment.
2. This number of valid blocks is based on single plane operations and may be little lower on two plane operations.

Symbol Parameter Value Unit

Ambient Operating Temperature (Commercial Temperature Range) 0 to 70 ℃

TA
Ambient Operating Temperature (Industrial Temperature Range) -40 to 85 ℃
TBIAS Temperature Under Bias -50 to 125 ℃

TSTG Storage Temperature -65 to 150 V

VIO(2) Input or Output Voltage -0.6 to 4.6 V

Vcc Supply Voltage -0.6 to 4.6 V

Table 7: Absolute maximum ratings

NOTE:

1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute
Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of
the device at these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Refer also to the Hynix SURE Program and other relevant quality documents.
2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions.

Rev 0.6 / Jul. 2008 17

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

$a$
$''5(66
5(*,67(5
&2817(5

352*5$0
(5$6( ;
&21752//(5 0ELW0ELW
+9*(1(5$7,21 '
1$1')ODVK (
&
$/(
0(025<$55$< 2
'
&/( (
:( 5
&( &200$1'
:3 ,17(5)$&(
/2*,&
5(

3$*(%8))(5
&200$1'
5(*,67(5
<'(&2'(5

'$7$
5(*,67(5
%8))(56

,2

Figure 5: Block Diagram

NOTE :
1. There are A31 ~ A0 (H27UCG8VFM)

Rev 0.6 / Jul. 2008 18

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

3.3Volt (2CE) 3.3Volt (4CE)

Parameter Symbol Test Conditions Unit
Min Typ Max Min Typ Max
tRC=25ns
Read ICC1 - 20 40 - 15 30 mA
CE=VIL, IOUT=0mA
Operating
Current Program ICC2 - - 20 40 - 15 30 mA
Erase ICC3 - - 20 40 - 15 30 mA
CE=VIH,
Stand-by Current (TTL) ICC4 - - 1 - - 1 mA
WP=0V/Vcc
CE=Vcc-0.2,
Stand-by Current (CMOS) ICC5 - 40 200 - 40 200 uA
WP=0V/Vcc
Input Leakage Current ILI VIN=0 to Vcc (max) - - ± 40 - - ± 40 uA
Output Leakage Current ILO VOUT =0 to Vcc (max) - - ± 40 - - ± 40 uA
Input High Voltage VIH - 0.8xVcc - Vcc+0.3 0.8xVcc - Vcc+0.3 V
Input Low Voltage VIL - -0.3 - 0.2xVcc -0.3 - 0.2xVcc V
Output High Voltage Level VOH IOH=-400uA 2.4 - - 2.4 - - V
Output Low Voltage Level VOL IOL=2.1mA - - 0.4 - - 0.4 V
IOL
Output Low Current (R/B) VOL=0.4V 8 10 - 8 10 - mA
(R/B)

Table 8: DC and Operating Characteristics

Value
Parameter
3.3Volt
Input Pulse Levels 0V to VCC
Input Rise and Fall Times 5ns
Input and Output Timing Levels VCC/2
Output Load (2.7V - 3.6V) 1 TTL GATE and CL=50pF

Table 9: AC Conditions

Rev 0.6 / Jul. 2008 19

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

Item Symbol Test Condition Min Max Unit

Input / Output Capacitance CI/O VIL=0V - 40 pF
Input Capacitance CIN VIN=0V - 40 pF

Table 10: Pin Capacitance (TA=25C, F=1.0MHz)

Parameter Symbol Min Typ Max Unit

Program Time / Multi-Plane Program Time tPROG - 800 2000 us
Dummy Busy Time for Two Plane Program tDBSY - 1 2 us
Number of partial Program Cycles in the same page NOP - - 1 Cycles
Block Erase Time / Multi-Plane Block Erase Time tBERS - 2.5 10 ms

Note : Within a same block. Program time (tPROG) of page group A is faster than that of group B.
The page group A and B are referred to Table 22.

Table 11: Program / Erase Characteristics

Rev 0.6 / Jul. 2008 20

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

3.3V
Parameter Symbol Unit
Min Max
CLE Setup time tCLS 12 ns

CLE Hold time tCLH 5 ns

CE setup time tCS 20 ns

CE hold time tCH 5 ns

WE pulse width tWP 12 ns

ALE setup time tALS 12 ns

ALE hold time tALH 5 ns

Data setup time tDS 12 ns

Data hold time tDH 5 ns

Write Cycle time tWC 25 ns

WE High hold time tWH 10 ns

Data Transfer from Cell to register tR 60 us

ALE to RE Delay tAR 10 ns

CLE to RE Delay tCLR 10 ns

Ready to RE Low tRR 20 ns

RE Pulse Width tRP 12 ns

WE High to Busy tWB 100 ns

Read Cycle Time tRC 25 ns

RE Access Time tREA 20 ns

RE High to Output High Z tRHZ 100 ns

CE High to Output High Z tCHZ 50 ns

CE High to Output hold tCOH 15 ns

RE High to Output Hold tRHOH 15 ns

RE Low to Output Hold tRLOH 5 ns

RE High Hold Time tREH 10 ns

Output High Z to RE low tIR 0 ns

CE Low to RE Low tCR 10 ns

Address to data loading time tADL 70 ns

WE High to RE low tWHR 80 ns

RE High to WE low tRHW 100 ns

Device Resetting Time (Read / Program / Erase) tRST 20/20/500(1) us

Write Protection time tWW(2) 100 ns

Table 12: AC Timing Characteristics

NOTE:
1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us
2. Program / Erase Enable Operation : WP high to WE High.
Program / Erase Disable Operation : WP Low to WE High.

Rev 0.6 / Jul. 2008 21

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

Pagae Block
IO Read CODING
Program Erase

0 Pass / Fail Pass / Fail NA Pass: ‘0’ Fail: ‘1’

1 Plane 0 Pass/Fail Plane 0 Pass/Fail NA Plane 0, Pass : ‘0’ Fail : ‘1’

2 Plane 1 Pass/Fail Plane 1 Pass/Fail NA Plane 1, Pass : ‘0’ Fail : ‘1’

3 NA NA NA -

4 NA NA NA -

5 NA NA NA -

6 Ready/Busy Ready/Busy Ready/Busy Busy: ‘0’ Ready’: ‘1’

Protected: ‘0’
7 Write Protect Write Protect Write Protect
Not Protected: ‘1’

Table 13: Status Register Coding

DEVICE IDENTIFIER CYCLE DESCRIPTION

1st Manufacturer Code

2nd Device Identifier

3rd Internal chip number, cell Type, etc.

4th Page Size, Block Size, Spare Size, Organization

5th Multi-plane information

Table 14: Device Identifier Coding

Bus 1st cycle 2nd cycle

Part Number Voltage 3rd cycle 4th cycle 5th cycle
Width (Manufacture Code) (Device Code)
H27UCG8V5M 3.3V x8 ADh D7h 55h B6h 48h
H27UCG8VFM 3.3V x8 ADh D5h 14h B6h 44h

Table 15: Read ID Data Table

Rev 0.6 / Jul. 2008 22

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

Description IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0

1 0 0
2 0 1
Die / Package
4 1 0
8 1 1
2 Level Cell 0 0
4 Level Cell 0 1
Cell Type
8 Level Cell 1 0
1 1
16 Level Cell
1 0 0
Number of
2 0 1
Simultaneously
4 1 0
Programmed Pages
8 1 1
Interleave Program Not 0
Between multiple chips Supported 1
Not 0
Write Cache
Supported 1

Table 16: 3rd Byte of Device Idendifier Description

Description IO7 IO6 IO5-4 IO3 IO2 IO1-0

1KB 0 0
Page Size 2KB 0 1
(Without Spare Area) 4KB 1 0
8KB 1 1
Spare Area Size 8 0
(Byte / 512Byte) 16 1
50ns 0 0
30ns 0 1
Serial Access Time
25ns 1 0
Reserved 1 1
64K 0 0
Block Size 128K 0 1
(Without Spare Area) 256K 1 0
512KB 1 1
X8 0
Organization
X16 1

Table 17: 4th Byte of Device Identifier Description

Rev 0.6 / Jul. 2008 23

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

Description IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0

1 0 0
2 0 1
Plane Number
4 1 0
8 1 1
512Mb 0 0 0
1Gb 0 0 1
2Gb 0 1 0
Plane Size 4Gb 0 1 1
(w/o redundant Area) 8Gb 1 0 0
Reserved 1 0 1
Reserved 1 1 0
Reserved 1 1 1
Reserved 0 0 0

Table 18: 5rd Byte of Device Idendifier Description

Rev 0.6 / Jul. 2008 24

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

W&/6 W&/+
&/(

W&6 W&+

&(

W:3
:(

W$/6 W$/+

$/(

W'6 W'+

,2[ &RPPDQG

Figure 6: Command Latch Cycle

W&/6

&/(

W&6

W:& W:& W:& W:&

&(

W:3 W:3 W:3 W:3

:(
W:+ W:+ W:+ W:+
W$/6 W$/+ W$/6 W$/+ W$/6 W$/+ W$/6 W$/+ W$/6 W$/+

$/(

W'+ W'+ W'+ W'+ W'+

W'6 W'6 W'6 W'6 W'6

,2[ &RO$GG &RO$GG 5RZ$GG 5RZ$GG 5RZ$GG

Figure 7: Address Latch Cycle

Rev 0.6 / Jul. 2008 25

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

W&/+
&/(

W&+
&(

W:&
W$/6
$/(

W:3 W:3 W:3

:(
W:+ W:+
W'+ W'+ W'+
W'6 W'6 W'6

,2[ ',1 ',1 ',1ILQDO

Figure 8: Input Data Latch Cycle

Rev 0.6 / Jul. 2008 26

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

W5&
&(
W&+=
W5(+
W5($ W5($ W5($ W&2+
5(

W5+= W5+=

W5+2+

,2[ 'RXW 'RXW 'RXW

W55

5%

1RWHV7UDQVLWLRQLVPHDVXUHGDWP9IURPVWHDG\VWDWHYROWDJHZLWKORDG
7KLVSDUDPHWHULVVDPSOHGDQGQRWWHVWHG W&+=W5+=
W5+2+VWDUWVWREHYDOLGZKHQIUHTXHQF\LVORZHUWKDQ0+]

Figure 9: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L)

W&5
&(
W5& W&+=
W53 W5(+ W&2+

5(
W5+=
W5($ W5($
W5/2+ W5+2+

,2[ 'RXW 'RXW

W55

5%

1RWHV7UDQVLWLRQLVPHDVXUHGDWP9IURPVWHDG\VWDWHYROWDJHZLWKORDG
7KLVSDUDPHWHULVVDPSOHGDQGQRWWHVWHG W&+=W5+=
W5/2+LVYDOLGZKHQIUHTXHQF\LVKLJKHUWKDQ0+]
W5+2+VWDUWVWREHYDOLGZKHQIUHTXHQF\LVORZHUWKDQ0+]

Figure 10: Sequential Out Cycle after Read (EDO Type CLE=L, WE=H, ALE=L)

Rev 0.6 / Jul. 2008 27

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

W&/5
&/( W&/6
W&/+

W&6
&(

W&+
W:3
:( W&+=
W&5
W&2+
W:+5

5(
W'+ W5($ W5+=
W'6 W,5
W5+2+

,2[ K 6WDWXV2XWSXW

Figure 11: Status Read Cycle

tCLR

CLE

CE
tWC

WE
tWB
tAR
ALE
tRHZ
tR tRC

RE
tRR

I/Ox 00h Col.Add1 Col.Add2 Row

G Add1 Row Add2 Row Add3 30h Dout N Dout N+ Dout M
Column Address Row Address

Busy
R/B

Figure 12: Read1 Operation (Read One Page)

Rev 0.6 / Jul. 2008 28

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

CLE

CE

WE
tWB tCHZ
tAR tCOH
ALE

tR tRC
RE
tRR

Col. Col. Row Row Row Dout Dout Dout

I/Ox 00h Add1 Add2 Add1 Add2 Add3 30h N N+1 N+2
Column Address Row Address

R/B Busy

Figure 13: Read1 Operation intercepted by CE

Rev 0.6 / Jul. 2008 29

Rev 0.6 / Jul. 2008
&/(

W&/5

&(

:(
W:% W5+:
W:+5
W$5
$/(
W5 W5& W5($

5(

W55

Figure 14: Random Data output

,2[ K &RO$GG &RO$GG 5RZ$GG 5RZ$GG 5RZ$GG K 'RXW1 'RXW1 K &RO$GG &RO$GG (K 'RXW0 'RXW0
&ROXPQ$GGUHVV 5RZ$GGUHVV &ROXPQ$GGUHVV

5% %XV\
64Gbit (8Gx8bit) NAND Flash
H27UCG8V(5/F)M
Preliminary

30
 CLE

Rev 0.6 / Jul. 2008

CE
tWC tWC

WE
tWB

ALE
tR

RE

Row. Row. Row. Row. Row. Row.

60h 60h 30h
I/Ox Add1 Add2 Add3 Add1 Add2 Add3
Row Address Row Address

A13 ~ A19 : Fixed “Low” A13 ~ A19 : Valid

A20 : Fixed “Low” A20 : Fixed “High”
R/B A21 ~ A31 : Fixed “Low” (2CE) A21 ~ A31 : Valid (2CE) Busy
A32 : Valid (2CE) A32 : Valid, It must be the same with 1st Plane. (2CE) 1
* A21 ~ A31 : Fixed “Low” (4CE) * A21 ~ A31 : Valid (4CE)

CLE
tCLR tCLR

CE
tWC tWC

WE
tWHR tWHR

tREA tRHW tREA

ALE
tRC tRC

RE

Col. Col. Row. Row. Row. Col. Col. Dout Dout Col. Col. Row. Row. Row. Col. Col. Dout Dout
00h 05h E0h 00h 05h E0h
I/Ox Add1 Add2 Add1 Add2 Add3 Add1 Add2 N N+1 Add1 Add2 Add1 Add2 Add3 Add1 Add2 M M+1
Column Address Column Address

Figure 15: Multi-Plane Page Read Operation with Random Data Out
Row Address Column Address Row Address Column Address

A0 ~ A12 : Fixed “Low” A0 ~ A12 : Valid A0 ~ A12 : Fixed “Low” A0 ~ A12 : Valid
A13 ~ A19 : Fixed “Low” A13 ~ A19 : Fixed “Low”
R/B A20 : Fixed “Low” A20 : Fixed “High”
A21 ~ A31 : Fixed “Low” (2CE) A21 ~ A31 : Valid (2CE)
1 A32 : Valid, It must be the same with 1st Read Cycle. (2CE) A32 : Valid, It must be the same with 1st Read Cycle. (2CE)
* A21 ~ A31 : Fixed “Low” (4CE) * A21 ~ A31 : Valid (4CE)
64Gbit (8Gx8bit) NAND Flash
H27UCG8V(5/F)M
Preliminary

31
 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

&/(

&(
W:& W:& W:&

:(
W$'/
W:% W352* W:+5

$/(

5(

,2[ K &RO &RO 5RZ 5RZ 5RZ 'LQ 'LQ K K ,2
$GG $GG $GG $GG $GG 1 0
6HULDO'DWD XSWRP%\WH 3URJUDP 5HDG6WDWXV
,QSXW&RPPDQG &ROXPQ$GGUHVV 5RZ$GGUHVV
6HULDO,QSXW &RPPDQG &RPPDQG

5%

,2 6XFFHVVIXO3URJUDP
,2 (UURULQ3URJUDP
127(6W$'/LVWKHWLPHIURPWKH:(ULVLQJHGJHRIILQDODGGUHVVF\FOHWRWKH:(ULVLQJHGJHRIILUVWGDWDF\FOH

Figure 16: Page Program Operation

Rev 0.6 / Jul. 2008 32

Rev 0.6 / Jul. 2008
&/(

&(
W:& W:& W:&

:(
W$'/ W$'/
W:% W352* W:+5

$/(

5(

K &RO$GG &RO$GG 5RZ$GG 5RZ$GG 5RZ$GG 'LQ 'LQ K &RO$GG &RO$GG 'LQ 'LQ K K ,2
,2[ 1 0 - .

Figure 17: Random Data In

6HULDO'DWD 5DQGRP'DWD 3URJUDP 5HDG6WDWXV
,QSXW&RPPDQG &ROXPQ$GGUHVV 5RZ$GGUHVV 6HULDO,QSXW ,QSXW&RPPDQG &ROXPQ$GGUHVV 6HULDO,QSXW &RPPDQG &RPPDQG

5%
127(6W$'/LVWKHWLPHIURPWKH:(ULVLQJHGJHRIILQDODGGUHVVF\FOHWRWKH:(UVLQJHGJHRIILUVWGDWDF\FOH
64Gbit (8Gx8bit) NAND Flash
H27UCG8V(5/F)M
Preliminary

33
 &/(

Rev 0.6 / Jul. 2008

&(
W:&
:(
W:% W'%6< W:% W352* W:+5

$/(

5(
'LQ 'LQ K 'LQ 'LQ
K &RO$GG &RO$GG 5RZ$GG 5RZ$GG 5RZ$GG 1 0 K &RO$GG &RO$GG 5RZ$GG 5RZ$GG 5RZ$GG 1 K K ,2
,2[ 0
6HULDO'DWD XSWR%\WH'DWD 3URJUDP 3URJUDP
,QSXW&RPPDQG &ROXPQ$GGUHVV 3DJH5RZ$GGUHVV &RPPDQG 6HULDO,QSXW &RPPDQG
6HULDO,QSXW 'XPP\ 7UXH

5%
W'%6<XV 7\S
XV 0D[ ,2 6XFFHVVIXO3URJUDPLQSODQH
,2 (UURULQSODQH
,2 6XFFHVVIXO3URJUDPLQSODQH
,2 (UURULQSODQH

([ 7ZR3ODQH3DJH3URJUDP

W'%6< W352*
5%

K $GGUHVV 'DWD,QSXW K K $GGUHVV 'DWD,QSXW K K

,2a
1RWH
&RO$GG 5RZ$GG &RO$GG 5RZ$GG

Figure 18: Multiple plane page program

%\WH'DWD %\WH'DWD

$a$9DOLG $a$9DOLG
$a$)L[HGµ/RZ¶ $a$9DOLG
$)L[HGµ/RZ¶ $)L[HGµ+LJK¶
$a$)L[HGµ/RZ¶ $a$9DOLG
 

1RWH$Q\FRPPDQGEHWZHHQKDQGKLVSURKLEWHGH[FHSWKDQG))+
64Gbit (8Gx8bit) NAND Flash
H27UCG8V(5/F)M
Preliminary

34
 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

&/(

&(
W:&
:(
W:% W%(56

$/(
5(

,2[ K 5RZ$GG 5RZ$GG 5RZ$GG 'K K ,2

%ORFN$GGUHVV
5%
%86<
%ORFN(UDVH6HWXS&RPPDQG 5HDG6WDWXV ,2 6XFFHVVIXO(UDVH
(UDVHFRQILUP&RPPDQG &RPPDQG ,2 (UURULQ(UDVH

Figure 19: Block Erase Operation (Erase One Block)

CLE

CE
tWC tWC

WE
tWB tBERS tWHR

ALE

RE

I/Ox 60h Row Add1 Row Add2 Row Add3 60h Row Add1 Row Add2 Row Add3 D0h 70h I/O

Row Address Row Address

R/B Busy Read Status Command

Block Erase Setup Command1 Block Erase Setup Command2 Erase Confirm Command I/O 1 = 0 Successful Erase in plane 0
I/O 1 = 1 Error in plane 0
I/O 2 = 0 Successful Erase in plane 1
I/O 2 = 1 Error in plane1

Ex.) Address Restriction for Two-Plane Block Erase Operation

R/B tBERS

I/O0~7 60h Address 60h Address D0h 70h

Row Add1,2,3 Row Add1,2,3

A13 ~ A19 : Fixed ‘Low’ A13 ~ A19 : Fixed ‘Low’

A20 : Fixed ‘Low’ A20 : Fixed ‘High’
A21 ~ A31 : Fixed ‘Low’ A21 ~ A31 : Valid
A32 : Valid (2CE) A32 : Valid, It must be the same with 1st Plane. (2CE)

Figure 20: Multiple plane erase operation

Rev 0.6 / Jul. 2008 35

Rev 0.6 / Jul. 2008
&(

&/(

$/(

:(
W:%

5(
W:&
W352*
W5

&RO &RO 5RZ 5RZ 5RZ 'DWD 'DWD &RO &RO 5RZ 5RZ 5RZ
,2[ K DGG DGG DGG DGG K K DGG DGG DGG DGG DGG K K ,2
DGG 1 0
5HDGFRQILUP &RS\EDFN
5HDGFRPPDQG &ROXPQDGGUHVV 3DJHURZDGGUHVV 'DWD2XW &ROXPQDGGUHVV SDJHURZDGGUHVV 3URJUDP
&RPPDQG FRPPDQG

5%

W5 W552*
5%

Figure 21: Copy Back Program Operation

,2 K DGGUHVV K 'DWDRXW K DGGUHVV K K ,2[

&RODGG 5RZDGG &RODGG 5RZDGG

1RWH&RS\EDFNSURJUDPRSHUDWLRQLVDOORZHGRQO\ZLWKLQWKHVDPHSODQH
64Gbit (8Gx8bit) NAND Flash
H27UCG8V(5/F)M
Preliminary

36
 &/(

Rev 0.6 / Jul. 2008

&(
W:&

W:% W:+5
:(
W352*
W:%
$/(
W5 W5&

5( W$'/

&RO &RO 5RZ 5RZ 5RZ 'DWD K

&RO &RO 5RZ 5RZ 5RZ 'DWD K
&RO &RO 'DWD K
K K 'DWD 'DWD 'DWD K ,2
,2[ $GG $GG $GG $GG $GG $GG $GG $GG $GG $GG $GG $GG
&ROXPQ$GGUHVV 5RZ$GGUHVV 5HDO6WDWXV&RPPDQG
'DWD2XW &ROXPQ$GGUHVV 5RZ$GGUHVV &ROXPQ$GGUHVV 'DWD,Q

5%
%XV\
%XV\
&RS\%DFN'DWD ,2 6XFHVVIXO3URJUDP
,QSXW&RPPDQG ,2 (UURULQ3URJUDP

127(6W$'/LVWKHWLPHIURPWKH:(ULVLQJHGJHRIILQDODGGUHVVF\FOHWRWKH:(ULVLQJHGJHRIILUVWGDWDF\FOH

W5 W352*
5%

Figure 22: Copy Back Program Operation with Random Data Input
,2a K DGGUHVV K 'DWDRXW K DGGUHVV 'DWD,Q K DGGUHVV 'DWD,Q K K ,2[

&RODGG 5RZDGG &RODGG 5RZDGG &RODGG

64Gbit (8Gx8bit) NAND Flash
H27UCG8V(5/F)M
Preliminary

37
 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

W5
5%

,2[ K $GGUHVV &\FOH K $GGUHVV &\FOH K

5RZ$GG 5RZ$GG
$a$)L[HG³/RZ´ $a$9DOLG
$)L[HG³/RZ´ $)L[HG³+LJK´ 
$a$)L[HG³/RZ´ $a$9DOLG

5%

,2[ K $GGUHVV &\FOH K $GGUHVV &\FOH (K 'DWD2XWSXW

&RO$GG 5RZ$GG &RO$GG

 $a$)L[HG³/RZ´ $a$9DOLG 
$a$)L[HG³/RZ´
$)L[HG³/RZ´
$a$)L[HG³/RZ´

5%

,2[ K $GGUHVV &\FOH K $GGUHVV &\FOH (K 'DWD2XWSXW

&RO$GG 5RZ$GG &RO$GG

 $a$)L[HG³/RZ´ $a$9DOLG 
$a$)L[HG³/RZ´
$)L[HG³+LJK´
$a$)L[HG³/RZ´

W'%6< W352*
5%

,2[ K $GG &\FOHV K K $GG &\FOHV K K ,2

&RO$GG 5RZ$GG &RO$GG 5RZ$GG


'HVWLQDWLRQ$GGUHVV 'HVWLQDWLRQ$GGUHVV
$a$)L[HG³/RZ´ $a$)L[HG³/RZ´ ,2 6XFFHVVIXO3URJUDPLQSODQH
$a$)L[HG³/RZ´ $a$9DOLG ,2 (UURULQSODQH
$)L[HG³/RZ´ $)L[HG³+LJK´ ,2 6XFFHVVIXO3URJUDPLQSODQH
$a$)L[HG³/RZ´ $a$9DOLG ,2 (UURULQSODQH

Figure 23: Multi-plane copyback program Operation

Rev 0.6 / Jul. 2008 38

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

W5
5%

,2[ K $GGUHVV &\FOH K $GGUHVV &\FOH K

5RZ$GG 5RZ$GG
$a$)L[HG³/RZ´ $a$9DOLG
$)L[HG³/RZ´ $)L[HG³+LJK´ 
$a$)L[HG³/RZ´ $a$9DOLG

5%

,2[ K $GGUHVV &\FOH K $GGUHVV &\FOH (K 'DWD2XWSXW

&RO$GG 5RZ$GG &RO$GG

 $a$)L[HG³/RZ´ $a$9DOLG 
$a$)L[HG³/RZ´
$)L[HG³/RZ´
$a$)L[HG³/RZ´

5%

,2[ K $GGUHVV &\FOH K $GGUHVV &\FOH (K 'DWD2XWSXW

&RO$GG 5RZ$GG &RO$GG

 $a$)L[HG³/RZ´ $a$9DOLG 
$a$)L[HG³/RZ´
$)L[HG³+LJK´
$a$)L[HG³/RZ´
W'%6<

5%

,2[ K $GGUHVV &\FOHV 'DWD K $GGUHVV &\FOHV 'DWD K

&RO$GG 5RZ$GG &RO$GG 


'HVWLQDWLRQ$GGUHVV
$a$9DOLG
$a$)L[HG³/RZ´
$)L[HG³/RZ´
$a$)L[HG³/RZ´
W352*
5%

,2[ K $GGUHVV &\FOHV 'DWD K $GGUHVV &\FOHV 'DWD K

&RO$GG 5RZ$GG &RO$GG

 'HVWLQDWLRQ$GGUHVV
$a$9DOLG
$a$9DOLG
$)L[HG³+LJK´
$a$9DOLG

Note: 1. Copy-Back Program operation is allowed only within the same memory plane.
2. Any command between 11h and 81h is prohibited except 70h and FFh.
Figure 24: Multi-plane Copy-Back Program Operation with Random Data Input

Rev 0.6 / Jul. 2008 39

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

&/(

&(

:(

W$5
$/(

5(
W5($

,2[ K K $'K 'K K %K K

5HDG,'&RPPDQG $GGUHVVF\FOH 0DNHU&RGH 'HYLFH&RGH UG&\FOH WK&\FOH WK&\FOH

Figure 25: Read ID Operation

Rev 0.6 / Jul. 2008 40

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

System Interface Using CE don’t care

To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below.
So, it is possible to connect NAND Flash to a microprocessor. The only function that was removed from standard NAND
Flash to make CE don’t care read operation was disabling of the automatic sequential read function.

&/(

&(GRQ¶WFDUH

&(

:(

$/(

,2[ K 6WDUW$GG &\FOH 'DWD,QSXW 'DWD,QSXW K

Figure 26: Program Operation with CE don’t-care.

&/(
,IVHTXHQWLDOURZUHDGHQDEOHG
&(PXVWEHKHOGORZGXULQJW5 &(GRQ¶WFDUH

&(

5(

$/(

5%
W5

:(

,2[ K 6WDUW$GG &\FOH K 'DWD2XWSXW VHTXHQWLDO

Figure 27: Read Operation with CE don’t-care.

Rev 0.6 / Jul. 2008 41

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

:(

$/(

&/(

5(

,2 ))K

W567

5%

Figure 28: Reset Operation

9 9
9 9

9 &&
9

GRQ¶W GRQ¶W
FDUH FDUH

&( 9,+

9,/ PVPD[ 2SHUDWLRQ 9,/

:3
XVPD[
,QYDOLG GRQ¶W
FDUH
5%

Figure 29: Power On and Data Protection Timing

VTH = 2.5 Volt for 3.3 Volt Supply devices

Rev 0.6 / Jul. 2008 42

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

5S LEXV\
9FF

5HDG\ 9FF
5%
RSHQGUDLQRXWSXW 92/992+9 92+

92/ %XV\

WI WU

*1'

'HYLFH
)LJ5SYVWUWI 5SYVLEXV\
#9FF 97D ƒ&&/ S)

 
LEXV\
Q P
WUWI>V@




LEXV\>$@
Q 

P

 
Q P
 WI   

N N N N
5S RKP
5SYDOXHJXLGHQFH

9FF 0D[ 92/ 0D[ 9

5S PLQ 
,2/™,/ P$™,/

ZKHUH,/LVWKHVXPRIWKHLQSXWFXUUQWVRIDOOGHYLFHVWLHGWRWKH5%SLQ
5S PD[ LVGHWHUPLQHGE\PD[LPXPSHUPLVVLEOHOLPLWRIWU

Figure 30: Ready/Busy Pin electrical specifications

Rev 0.6 / Jul. 2008 43

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

Bad Block Management

Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the
blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and
common source line by a select transistor. The devices are supplied with all the locations inside valid blocks erased(FFh).
The Bad Block Information is written prior to shipping. Any block where the 1st Byte in the spare area of the Last and
(Last-2)th page (if the last page is Bad) does not contain FFh is a Bad Block. The Bad Block Information must be read
before any erase is attempted as the Bad Block Information may be erased. For the system to be able to recognize the
Bad Blocks based on the original information it is recommended to create a Bad Block table following the flowchart
shown in Figure 31. The 1st block, which is placed on 00h block address is guaranteed to be a valid block.

67$57

%ORFN$GGUHVV
%ORFN

,QFUHPHQW
%ORFN$GGUHVV

'DWD  1R 8SGDWH
))K" %DG%ORFNWDEOH

<HV

/DVW 1R
EORFN"

<HV

(1'

Figure 31: Bad Block Management Flowchart

NOTE :
1. Make sure that FFh at the column address 4096 of the last page and last - 2th page.

Rev 0.6 / Jul. 2008 44

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

Bad Block Replacement

Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by copying
the data to a valid block. These additional Bad Blocks can be identified as attempts to program or erase them will give
errors in the Status Register.
The failure of a page program operation does not affect the data in other pages in the same block, the block can be
replaced by re-programming the current data and copying the rest of the replaced block to an available valid block.
Refer to Table 19 and Figure 32 for the recommended procedure to follow if an error occurs during an operation.

Operation Recommended Procedure

Erase Block Replacement
Program Block Replacement
Read ECC (with 4bit/528byte)

Table 19: Block Failure

%ORFN$ %ORFN%


'DWD 'DWD

WK WK
QSDJH )DLOXUH  QSDJH

))K ))K

%XIIHUPHPRU\RIWKHFRQWUROOHU

Figure 32: Bad Block Replacement

NOTE :
1. An error occurs on of the Block A during program or erase operation.
2. Data in Block A is copied to same location in Block B which is valid block.
3. Nth page of block A which is in controller buffer memory is copied into nth page of Block B
4. Bad block table should be updated to prevent from erasing or programming Block A

Rev 0.6 / Jul. 2008 45

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

Write Protect Operation

The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations
are enabled and disabled as follows (Figure 33~36)

:( :(
W :: W ::

,2[ K K ,2[ K K

:3 :3

5% 5%

Figure 33: Enable Programming Figure 34: Disable Programming

:( :(
W ::
W ::

,2[ K 'K ,2[ K 'K

:3 :3

5% 5%

Figure 35: Enable Erasing

Figure 36: Disable Erasing

Rev 0.6 / Jul. 2008 46

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash



H $ $

' %
$ Į /

  ',(
( &
(
&3

Figure 37: 48-TSOP1 - 48-lead Plastic Thin Small Outline, 12 x 20mm, Package Outline

millimeters
Symbol
Min Typ Max
A 1.200

A1 0.050 0.150

A2 0.980 1.030

B 0.170 0.250

C 0.100 0.200

CP 0.100

D 11.910 12.000 12.120

E 19.900 20.000 20.100

E1 18.300 18.400 18.500

e 0.500

L 0.500 0.680

alpha 0 5

Table 20: 48-TSOP1 - 48-lead Plastic Thin Small Outline,

12 x 20mm, Package Mechanical Data

Rev 0.6 / Jul. 2008 47

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

%
%
%
' '

$
%
&
&
'
( &
)
&
* $ $ $
+
-
.
/
0
1

      

FS
 0 & $% FS
 0 & $%

Figure 38: 52-VLGA, 14 x 18mm, Package Outline

(Top view through package)

millimeters
Symbol
Min Typ Max
A 17.90 18.00 18.10
A1 13.00
A2 12.00
B 13.90 14.00 14.10
B1 10.00
B2 6.00
C 1.00
C1 1.50
C2 2.00
D 1.00
D1 1.00
E 0.80 0.90 1.00
CP1 0.65 0.70 0.75
CP2 0.95 1.00 1.05

Table 21: 52-VLGA, 14 x 18mm, Package Mechanical Data

Rev 0.6 / Jul. 2008 48

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

Paired Page Address Information

Paired Page Address Paired Page Address
Group A Group B Group A Group B
ooh 04h 01h 05h
02h 08h 03h 09h
06h 0Ch 07h 0Dh
0Ah 10h 0Bh 11h
0Eh 14h 0Fh 15h
12h 18h 13h 19h
16h 1Ch 17h 1Dh
1Ah 20h 1Bh 21h
1Eh 24h 1Fh 25h
22h 28h 23h 29h
26h 2Ch 27h 2Dh
2Ah 30h 2Bh 31h
2Eh 34h 2Fh 35h
32h 38h 33h 39h
36h 3Ch 37h 3Dh
3Ah 40h 3Bh 41h
3Eh 44h 3Fh 45h
42h 48h 43h 49h
46h 4Ch 47h 4Dh
4Ah 50h 4Bh 51h
4Eh 54h 4Fh 55h
52h 58h 53h 59h
56h 5Ch 57h 5Dh
5Ah 60h 5Bh 61h
5Eh 64h 5Fh 65h
62h 68h 63h 69h
66h 6Ch 67h 6Dh
6Ah 70h 6Bh 71h
6Eh 74h 6Fh 75h
72h 78h 73h 79h
76h 7Ch 77h 7Dh
7Ah 7Eh 7Bh 7Fh

Note: When program operation is abnormally aborted (ex. power-down, reset), not only page data under program
but also paired page data may be damaged.

Table 22: Paired Page Address Information

Rev 0.6 / Jul. 2008 49

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

The backward compatibility (2KByte/page operation)

1. Page program

5% W'%6< W352*

,2a K $GGUHVV 'DWD,QSXW K K $GGUHVV 'DWD,QSXW K K
&RO$GG 5RZ$GG 1RWH &RO$GG 5RZ$GG
XSWR%\WH'DWD XSWR%\WH'DWD
$a$9DOLG $a$9DOLG
$a$)L[HG³/RZ´ $a$9DOLG
$9DOLG $0XVWEHVDPHZLWKWKHSUHYLRXV
$a$)L[HG³/RZ´ $a$9DOLG

Note: Any command between 11h and 80h is prohibited except 70h and FFh.

2. Copy back program

W5
5%

,2[ K $GG &\FOHV K 'DWD2XWSXW

&RO$GG 5RZ$GG

6RXUFH$GGUHVV

W'%6< W352*
5%

K $GG &\FOHV 'DWD K K $GG &\FOHV 'DWD K
,2[
 &RO$GG 5RZ$GG &RO$GG 5RZ$GG
XSWR%\WH'DWD XSWR%\WH'DWD
'HVWLQDWLRQ$GGUHVV 'HVWLQDWLRQ$GGUHVV
$a$9DOLG $a$9DOLG
$a$)L[HG³/RZ´ $a$9DOLG
$0XVWEHVDPHZLWKWKHVRXUFHSODQH $0XVWEHVDPHZLWKWKHVRXUFHSODQH
$a$)L[HG³/RZ´ $a$9DOLG
Note:
1. Copy-Back Program operation is allowed only within the same memory plane.
2. Any command between 11h and 85h is prohibited except 70h and FFh.

Rev 0.6 / Jul. 2008 50

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

3. Copy back program with random data input

W5

5%

,2[ K $GG &\FOHV K 'DWD2XWSXW

&RO$GG 5RZ$GG

6RXUFH$GGUHVV

W'%6<
5%

,2[ K $GG &\FOHV 'DWD K $GG &\FOHV 'DWD K

 &RO$GG 5RZ$GG &RO$GG 

XSWR%\WH'DWD
'HVWLQDWLRQ$GGUHVV
$a$9DOLG
$a$)L[HG³/RZ´
$PXVWEHVDPHZLWKWKHVRXUFHSODQH
$a$)L[HG³/RZ´
W352*
5%

,2[ K $GG &\FOHV 'DWD K $GG &\FOHV 'DWD K

&RO$GG 5RZ$GG &RO$GG


XSWR%\WH'DWD
'HVWLQDWLRQ$GGUHVV
$a$9DOLG
$a$9DOLG
$0XVWEHVDPHZLWKWKHVRUXFHSODQH
$a$9DOLG

Note:
1. Copy-Back Program operation is allowed only within the same memory plane.
2. Any command between 11h and 85h is prohibited except 70h and FFh.

Rev 0.6 / Jul. 2008 51

 Preliminary
H27UCG8V(5/F)M
64Gbit (8Gx8bit) NAND Flash

MARKING INFORMATION - TSOP1 / VLGA

M a rk in g E x a m p le

K O R

H 2 7 U C G 8 V X M x x - x x

Y W W x x

- h y n ix : H yn ix S ym b o l
- KOR : O rigin C o u n try

- H 2 7 U C G 8 V X M x x -x x : P a rt N u m be r
H : H yn ix
2 7 : N A N D Fla sh
U : P o w e r S u p p ly : U (2 .7 V ~ 3 .6 V )
C G : D e n sity : 6 4 G b it
8 : B it O rg an iza tion : 8 (x8 )
V : C la ssifica tion : M u lti Leve l C e ll+ Q u ad ru ple D ie + La rge B lo ck
X : M o de : 5 (2 n C E & 2 R /n B ; S e q u e n tia l R ow R e a d D isa b le )
: F (4 n C E & 4 R /n B ; se q u e n tia l R o w R e a d D isa b le )
M : V e rsio n : 1 st G e n e ra tion
x : P a cka g e T ype : T (4 8 -T S O P 1 ), Y (5 2 -V LG A )
x : P a cka g e M ate rial : B la n k(N o rm a l), R (L e ad & H a lo g e n F re e )

x : B ad B lo ck : B (In clu d ed B ad B lo ck ), S (1 ~ 5 B a d B lock ),

P (A ll G oo d B lock)
x : O p e ra tin g T e m pe ra tu re : C (0 ℃ ~ 7 0 ℃ ), I(-4 0℃ ~ 8 5 ℃ )

- Y : Y e ar (ex: 5= year 2 0 0 5 , 6= year 20 06 )

- w w : W o rk W e ek (e x: 1 2 = w o rk w e ek 1 2 )
- x x : P roce ss C od e
N o te : Fixed Item
- C a p ita l L e tte r : N o n -fixe d Item
- S m a ll L e tte r

Rev 0.6 / Jul. 2008 52