LAU Wy E) COMPUTER: 10 SAP-1 The SAP (Simple-As-Possible) computer has been designed for you, the beginner. The main purpose of SAP is to introduce all the crucial ideas behind computer operation without burying you in unnecessary detail, But even a simple computer like SAP covers many advanced concepts. To avoid bombarding you with too much all at once, we will examine three different generations of the SAP com- puter. SAP-1 is the first stage in the evolution toward modern computers. Although primitive, SAP-1 is a big step for a beginner. So, dig into this chapter; master SAP-I, its architecture, its programming, and its circuits. Then you will be ready for SAP-2. 10-1 ARCHITECTURE Figure 10-1 shows the architecture (structure) of SAP-1, a bus-organized computer. All register outputs to the W bus are three-state; this allows orderly transfer of data. All other register outputs are two-state; these outputs continuously drive the boxes they are connected to. ‘The layout of Fig. 10-1 emphasizes the registers used in SAP-1, For this reason, no attempt has been made to keep all control circuits in one block called the control unit, all input-output circuits in another block called the VO unit, ete Many of the registers of Fig, 10-1 are already familiar from earlier examples and discussions, What follows is a brief description of each box; detailed explanations come later, Program Counter ‘The program is stored at the beginning of the memory with the first instruction at binary address 0000, the second instruction at address 0001, the third at address 0010, and so on. The program counter, which is part of the control unit, counts from 0000 to L111. Its job is t0 send to the memory the address of the next instruction to be fetched and executed. It docs this as follows, 140 ‘The program counter is reset to 0000 before each computer run. When the computer run begins, the program counter sends address. 0000 to the memory. The program counter is then incremented to get 0001, After the first instruction is fetched and executed, the program counter sends address 0001 to the memory. Again the program counter is incre- ‘mented. After the second instruction is fetched and executed, the program counter sends address 0010 to the memory. In this way, the program counter is keeping track of the next instruction to be fetched and executed, The program counter is Tike someone pointing a finger at a list of instructions, saying do this first, do this second, do this third, ete, This is why the program counter is sometimes called a pointer; it points to an address in ‘memory where something important is being stored. Input and MAR Below the program counter is the input and MAR block. It includes the address and data switch registers discussed in Sec. 9-4. These switch registers, which are part ofthe input unit, allow you to send 4 address bits and 8 data bits 10 the RAM. As you recall, instruction and data words are written into the RAM before a computer run ‘The memory address register (MAR) is part of the SAP- | memory. During a computer run, the address in the program counter is latched into the MAR. A bit later, the MAR applies this 4-bit address to the RAM, where a read. ‘operation is performed. ‘The RAM ‘The RAM is a 16 X 8 static TTL RAM. As discussed in Sec. 9-4, you can program the RAM by means of the address and data switch registers. This allows you to store program and data in the memory before a computer run. During a computer run, the RAM receives 4-bit addresses from the MAR anda read operation is performed. In this way the instruction or data word stored in the RAM is placed ‘on the W bus for use in some other part of the computer&p —f fe] }—i, waht ogee Le ia a 2 <4 WY : a =| = 4 pal cx} mane {esp came dae Uy ~ Ww — —» cle Wy Coty BE LElaEs EUTaly Fig. 1041 SAP-1 architecture. Instruction Register ‘The instruction register is part of the control unit. To fetch ‘an instruction from the memory the computer does a memory read operation. This places the contents of the addressed ‘memory location on the W bus. At the same time, the instruction register is set up for loading on the next positive clock edge. ‘The contents of the instruction register are split into two nibbles. The upper nibble is a two-state output that goes directly to the block labeled “*Controlier-sequencet."” The lower nibble is a three-state output that is read onto the W ‘bus when needed. Controller-Sequencer The lower left block contains the controller-sequencer. Before each computer run, a CER signal is sent to the program counter and a CLR signal tothe instruction register. This resets the program counter to 0000 and wipes out the last instruction inthe instruction register. AA clock signal CLK is sent to all buffer registers; this synchronizes the operation ofthe compute, ensuring that things happen when they are supposed to happen, In other words, all register transfers occur on the positive edge of 4 common CLK signal. Notice that a CLK signal also goes to the program counter. The 12 bits that come out of the contoller-sequencer form a word controlling the rest of the computer (like a supervisor telling others what o do,) The 12 wires carrying the contol word are called the control bus ‘The control word has the format of CON = CECE LEE, SubeLaly This word determines how the registers will react to the next postive CLK edge. For instance, a high E> and a low Chapter 10 sap1 141Ts mean thatthe contents ofthe program counter are latched into the MAR on the next positive clock edge. As another ‘example, a low CE and a low Z, mean that the addressed RAM word will be transferred to the accumulator on the next positive clock edge. Later, we will examine the timing diagrams to see exactly when and how these data transfers take place, Accumulator The accumulator (A) is a buffer register that stores inter- mediate answers during a computer nin. In Fig. 10-1 the accumulator has (wo outputs. The two-state output goes directly to the adder-subtracter. The three-state output goes to the W bus, Therefore, the 8-bit accumulator word continuously drives the adder-subtracter; the same word appears on the W bus when E, is high. ‘The Adder-Subtracter SAP-L uses a 2’s-complement adder-subtracter. When S, is low in Fig. 10-1, the sum out of the adder-subtracter is S=A+B When S,, is high, the difference appears AS A+B (Recall that the 2’s complement is equivalent to a decimal sign change.) ‘The adder-subtracter is asynchronous (unclocked); this ‘means that its contents can change as soon as the input words change. When Ey is high, these contents appear on the W bus. B Register The B reginer is another butter repister. It is used in arithmetic operations. A low Ly and postive clock edge load the word on the W bus into the B register. The two- state output of the B register drives the adder-subtracter, supplying the number to be added or subtracted from the contents ofthe accumulator Output Register Example 8-1 discussed the output register. At the end of @ computer run, the accumulator contains the answer to the problem being solved. At this point, we need to transfer the answer to the outside world, This is where the ouput register is used. When E, is high and Zy is low, the next positive clock edge loads the accumulator word into the ‘output register. ‘The output register is often called an ouspur port because processed data can leave the computer through this register. 142 Digital Computer Electronics In microcomputers the output ports are connected (0 int face circuits that dsive peripheral devices like printers, cathode-ray tubes, teletypewriters, and so forth. (An inter face circuit prepares the data to drive each device.) Binary Display ‘The binary display is a row of eight light-emitting diodes (LEDs). Because each LED connects to one flip-lop of the ‘output port, the binary display shows us the contents of the ‘output port, Therefore, after we've transferred an answer from the accumulator to the output port, we can see the answer in binary form. Summary The SAP-1 control unit consists of the program counter, the instruction register, and the controller-sequencer that produces the control word, the clear signals, and the clock signals. The SAP-1 ALU consists of an accumulator, an adder-subtracter, and a B register. The SAP-I memory has. the MAR and a 16 x 8 RAM. The /O unit includes the input programming switches, the output port, and the binary display 10-2 INSTRUCTION SET A computer is a useless pile of hardware until someone programs it. This means loading step-by-step instructions into the memory before the start of a computer run. Before you ean program a computer, however, you must lear its insiruction set, the basic operations it can perform, The SAP-1 instruction set follows. LDA AAs described in Chap. 9, the words in the memory can be symbolized by Ry, R,, Rz, etc. This means that Re is stored at address OH. Ry at address 1H, R, at address 2H, and so LDA stands for “load the accumulator."* A complete LDA instruction includes the hexadecimal address of the data to be loaded. LDA 8H, for example, means “Toad the accumulator with the contents of memory location 8H.” Therefore, given R, = 1111 0000 the execution of LDA 8H results in A= 1111 0000 Similarly, LDA AH means ‘load the accumulator with the contents of memory location AH," LDA FH means “Toad the aceumulator with the contents of memory location FH," and so on.ADD ADD is another SAP-1 instruction. A complete ADD instruction includes the address of the word to be added, For instance, ADD 9H means “‘add the contents of memory location 9H to the accumulator contents”; the sum replaces the original contents of the accumulator. Here's an example, Suppose decimal 2 is in the accu: rmulator and decimal 3 is in memory location 9H, Then A = 00000010 R, = 00000011 During the execution of ADD 9H, the following things happen. First, R, is loaded into the B register to get B 0000 0011 and almost instantly the adder-subtracter forms the sum of Aand B SUM= 0000 0101 Second, this sum is loaded into the accumulator to get A = 0000 0101 The foregoing routine is used for all ADD instructions; the addressed RAM word goes to the B register and the adder-subtracter output to the accumulator. This is why the execution of ADD 9H adds R, to the accumulator contents, the execution of ADD FH adds Ry to the accumulator contents, and so on SUB ‘SUB is another SAP-I instruction. A complete SUB in- struction includes the address of the word fo be subtracted. For example, SUB CH means “subtract the contents of ‘memory location CH from the contents ofthe accumulator"; the difference out of the adder-subtracter then replaces the original contents of the accumulator. For a concrete example, assume that decimal 7 is in the ‘accumulator and decimal 3 is in memory location CH. Then A= 00000111 Re = 00000011 ‘The execution of SUB CH takes place as follows. First, Re is loaded into the B register to get B = 0000 0011 and almost instantly the adder-subtracter forms the ditfer- cence of A and B: DIFF = 0000 0100 Second, this difference is loaded into the accumulator and ‘A = 0000 0100 The foregoing routine applies to all SUB instructions; the addressed RAM word goes to the B register and the ‘adder-subtracter output to the accumulator. This is why the execution of SUB CH subtracts Re from the contents of the accumulator, the execution of SUB EH subtracts Ry from the accumulator, and so on our The instruction OUT tells the SAP-1 computer to transfer the accumulator contents to the output port, After OUT has bbeen executed, you can see the answer (othe problem being solved, OUT is complete by itself; that is, you do not have 10 include an address when using OUT because the instruction does not involve data in the memory HLT HLT stands for halt. This instruction tells the computer to stop processing data, HLT marks the end of a program, similar to the way a period marks the end of a sentence. You must use a HLT instruction at the end of every SAP- 1 program; otherwise, you get computer trash (meaningless answers caused by runaway processing). HLT is complete by itself; you do not have to include @ RAM word when using HLT because this instruction does not involve the memory. Memory-Reference Instructions LDA, ADD, and SUB are called memory-reference instrue- tions because they use data stored in the memory. OUT and HLT, on the other hand, are not memory-reference instructions because they do not involve data stored in the memory Mnemonics LDA, ADD, SUB, OUT, and HLT are the instruction set for SAP-1. Abbreviated instructions like these are called ‘mnemonics (memory aids). Mnemonics are popular in ‘computer work because they remind you of the operation that will take place when the instruction is executed, Table 10-1 summarizes the SAP-1 instruction set. ‘The 8080 and 8085 ‘The 8080 was the first widely used microprocessor. It has 72 instructions. The 8085 is an enhanced version of the 8080 with essentially the same instruction set. To make SAP practical, the SAP instructions will be upward com- chapter 10 sap-1 143TABLE 10-1, SAP-1 INSTRUCTION SET ‘Mnemonic Operation LDA Load RAM data into accumulator ADD Add RAM data to accumulator SUB Sublract RAM data from accumulator OUT Load accumulator data into output register HLT Stop processing patible with the 8080/8085 instruction set. In other words, the SAP-1 instructions LDA, ADD, SUB, OUT, and HLT are 8080/8085 instructions. Likewise, the SAP-2 and SAP. 3 instructions will be part of the 8080/8085 instruction set. Learning SAP instructions is geting you ready for the 8080 and 8085, two widely used microprocessor. EXAMPLE 10-1 Here's a SAP-I program in mnemonie form: Address Mnemonics OH LDA 9H 1H ADD AH 2H ADD BH 3H SUB CH 4H our SH HLT ‘The data in higher memory is Address Data on FFH 7H FFH 8H FFH oH oun AH oH BH 03H cH o4H DH FFH EH FFH FH FFH ‘What does each instruction do? SOLUTION The program is in the low memory, located at addresses OH to SH. The first instruction loads the accumulator with 144 Digital Computer Electronics the contents of memory location 9H, and so the accumulator contents become A 1H ‘The second instruction adds the contents of memory location AH (o the accumulator contents to get a new accumulator total of A = 01H + 02H = 03H Similarly, the third instruction add the contents of memory location BH A = 03H + 03H = 06H The SUB instruction subtracts the contents of memory location CH to get A = 06H — 04H = 02H ‘The OUT instruction loads the accumulator contents into the output port: therefore, the binary display shows (0000 0010 The HLT instruction stops the data processing 10-3 PROGRAMMING SAP-1 To load instruction and data words into the SAP-1 memory we have to use some kind of code that the computer can interpret. Table 10-2 shows the code used in SAP-1. The number 0000 stands for LDA, 0001 for ADD, 0010 for SUB, 1110 for OUT, and 1111 for HLT. Because this code tells the computer which operation to perform, itis called an operation code (op code). [As discussed earlier, the address and data switches of Fig. 9-7 allow you to program the SAP-1 memory. By design, these switches produce a 1 in the up position (U) TABLE 10- OP CODE Op code 0000 001 10 our m0 HLT unand a 0 in the down position (D). When programming the data switches with an instruction, the op code goes into the upper nibble, and the operand (the rest of the instruction) into the lower nibble. For instance, suppose we want to store the following instructions: Address Instruction OH LDA FH 1H ADDEH 2H HLT First, convert cach instruction to binary as follows LDA FH = 0000 1111 ADD EH = 0001 1110 HLT = L111 XXXX In the first instruction, 0000 is the op code for LDA, and 1111 is the binary equivalent of FH, In the second instruc- tion, 0001 is the op code for ADD, and 1110 is the binary equivalent of EH. In the third instruction, 1111 is the op code for HLT, and XXXX are don’t cares because the HLT is not a memory-reference instruction. Next, set up the address and data switches as follows: Address Data DDDD —_ ppD LULU DbbU — DppuUUUUD DDUD —_ UUUUXXXX After each address and data word is set, you press the write button. Since D stores a binary O and U stores a binary 1, the first three memory locations now have these contents: Address Contents 0000 0000 1111 001 001 1110 010 TILL XXXX A final point. Assembly language involves working with mnemonics when writing a program. Machine language involves working with strings of Os and Is. The following examples bring out the distinction between the two lan- guages, EXAMPLE 10-2 ‘Translate the program of Example 10-1 info SAP-1 machine language. SOLUTION Here is the program of Example 10-1: Address Instruction on LDA 9H 1H ADD AH 2H ADD BH 3H SUB CH 4H our SH HLT ‘This program is in assembly language as it now stands. To got it into machine language, we translate it to Os and 1s as follows: Address Instruction 0000 (0000 1001 0001 (0001 1010 0010 0001 1011 0011 010 1100 0100 1110 XXXX o1or TIL XXXX ‘Now the program is in machine language. ‘Any program like the foregoing that’s written in machine language is called an object program, The original program ‘with mnemonics is called a source program. In SAP-| the ‘operator translates the source program into an abject program ‘when programming the address and data switches. ‘A final point. The four MSBs of a SAP-1 machine- language instruction specify the operation, and the four LSBs give the address. Sometimes we refer to the MSBs as the instruction field and to the LSBs as the address field. ‘Symbolically, Instruction = XXXX XXXX Instruction field! Address field EXAMPLE 10-3 How would you program SAP-1 to solve this arithmetic problem? 16 + 20 + 24 ~ 32 ‘The numbers are in decimal form. SOLUTION ‘One way is to use the program of the preceding example, storing the data (16, 20, 24, 32) in memory locations 9H Chapter 10 sap1 145to CH. With Appendix 2, you can convert the decimal data into hexadecimal data to get this assembly-language version Address Contents on LDA oH 1H ADD AH 2H ADD BH 3H SUB CH 4H ouT SH HLT oH XX TH XX 8H XX oH 10H AH 1H BH 18H cH 20H ‘The machine-language version is Address Contents 0000 (0000 1001 001 0001 1010 010 0001 1011 oon 0010 1100 0100 1110 XXXX_ o1or LLL XXXX, onto XXXX XXXX our XXXX XXXX 1000 XXXX XXXX 1001 (0001 0000 10100001 0100 toll ‘001 1000 1100 0010 0000 Notice that the program is stored ahead of the data. In other words, the program is in low memory and the data in high memory. This is essential in SAP-I because the program counter points to address 0000 for the first instruc- tion, 0001 for the second instruction, and so forth. EXAMPLE 10-4 ‘Chunk the program and data of the preceding example by converting to hexadecimal shorthand. SOLUTION Address Contents oH 09H 1H 1AH 2H 1BH 146 digital Computer Blectronics 3H 2CH an EXH SH FXH oH XXH TH XXH 8H XXH oH 10H AH 14H BH 18H. cH 20H ‘This version of the program and data is still considered ‘machine language. Incidentally, negative data is loaded in 2°s-complement form. For example, ~03H is entered as FDH. 10-4 FETCH CYCLE ‘The control unit is the key to a computer's automatic operation, The control unit generates the control words that fetch and execute each instruction. While each instruction is fetched and executed, the computer passes. through different timing states (T states), periods during which register contents change. Let’s find out more about these T states, Ring Counter Barlier, we discussed the SAP-1 ring counter (see Fig. 8-16 for the schematic diagram). Figure 10-2a symbolizes the ring counter, which has an output of T= TLLETT, At the beginning of a computer run, the ring word is, T = 000001 Successive clock pulses produce ring words of T = 000010 T = 000100 T = 001000 T = 010000 T = 100000 ‘Then, the ring counter resets t© 000001, and the eycle repeats. Each ring word represents one T state. Figure 10-2b shows the timing pulses out of the ring counter. The initial state T, starts with a negative clock ‘edge and ends with the next negative clock edge. During this 7 state, the 7; bit out of the ring counter is high. During the next state, Ts is high; the following state has a high Ty; then a high Ty; and so on. As you can sce, theo— CLA cs Te Te TM Ts th Ny w harhickactattctiackael rn ) Fig, 10-2 Ring counter: (a) symbol: (b) clock and timing signals, ring counter produces six T states. Each instruction is fetched and executed during these six T states Notice that a positive CLK edge occurs midway through each T state. The importance of this will be brought out later. Address State The 7, state is called the address state because the address in the program counter (PC) is transferred to the memory address register (MAR) during this state. Figure 10-30 shows the computer sections that are active during this state (active parts are light; inactive parts ate dark), During the address state, Ey and Ly are active; all other control bits are inactive. This means that the controller sequencer is sending out a control word of CON = CyEpL CE o101 TELE, Mrro SUE DaLo ool during this state Increment State Figure 10-3 shows the active parts of SAP-1 during the iate. This state is called the increment stare because the program counter is incremented. During the increment state the controller-sequencer is producing a control word of As you see, the C bit is active, Memory State ‘The T, state is called the memory stae because the addressed RAM instruction is wansfered from the memory t0 the instruction register. Figure 10-3c shows the active parts of SAP-I during the memory state. The only active control bits during this state are CE and Z,, and the word out of the contoller-sequencer is SLE LaLa oor Chapter 10 sap 147con (al Fig. 10-3 Fetch cycle: (a) Ty state; (b) T, sate: (e) Ty state Fetch Cycle ‘The address, inerement, and memory states are called the fetch cycle of SAP-1. During the address state, Ep and ‘are active: this means that the program counter sets up the MAR via the W bus. As shown earlier in Fig. 10-25, a positive clock edge occurs midway through the address state; this loads the MAR with the contents of the PC. Cp is the only active control bit during the increment state. This sets up the program counter to count positive clock edges. Halfway through the increment state a positive clock edge hits the program counter and advances the count by | During the memory state, CE and L, are active. Therefore, the addressed RAM word sets up the instruction register via the W bus. Midway through the memory state. « positive clock edge loads the instruction register with the addressed RAM word, 10-5 EXECUTION CYCLE ‘The next three states (T,, Ts, and T,) are the execution cycle of SAP-1, The register transfers during the execution cycle depend on the particular instruction being executed For instance, LDA 9H requires different register transfers than ADD BH. What follows are the control routines for different SAP-1 instructions, LDA Routine For a concrete discussion, let’s assume that the instruction register has been loaded with LDA 914 IR = 0000 1001 During the 7, state, the instruction field 0000 goes to the ccontroller-sequencer, where it is decoded; the address field 1001 is loaded into the MAR. Figure 10-a shows the 148 igitat computer Electronics fe active pats of SAP-1 during the Ty state. Note that E, and Ty are active; all other contol bits are inactive. ‘During the 7, sate, CE and Ly go low. This means that the addressed data word in the RAM willbe loaded into the accumulator on the next positive clock edge (See Fig 10-4, Tis a no-operation state. During this thd execution state, all registers are inactive (Fig. 10-4), This means that the controllersequencer is sending out a wor! whose bits are all inactive. Nop (pronounced no op) stands for 0 operation.”* The Ty stat ofthe LDA routine is @ nop. Figure 10-5 shows the timing diagram forthe fetch and LDA routines. During the 7; state, Ep and Ly are active; the positive clock edge midway through this state will transfer the address in the program counter to the MAR. During the Ts state, Cp is aetive andthe program counter is incremented on the positive clock edge. During the 7; State, CE and [, are actives when the positive clock edge fvcuts, the addressed RAM word is transferred t0 the instruction egister. The LDA exceution stats with the Ty state, where Ly and E, ae active: on the postive clock cage the address field inthe instruction register is transferred to the MAR. During the Ts state, CE and L are active; this meats thatthe addressed RAM data word is transferred to the accumulutor on the postive clock edge. As you know, the Ts state of the LDA routine is # nop ADD Routine ‘Suppose at the end of the fetch cycle the instruction register contains ADD BH: IR = 0001 1011 Daring the 7 state the instruction field goes to the controller- sequencer and the address field to the MAR (see Fig. 10-6a). During this state E, and Ly are active Control bits CE and Ly are active during the Ts state. This allows the addressed RAM word to set up the Bcon ‘ Fig. 10-4 LDA routine: (a) T, state (b)T, state; (e) T, sate. Fig, 10-8 Fetch and LDA timing diagram. Jerrfe rele pele ele mele real Pe fas y™ rE =r Bas Hel. ram wan feat lef mal +t 2 « BR IE con con fon Bu Tw. con con a io Fig. 10-6 ADD and SUB routines (a) T, states (b) T, state: () 7, state fe Chapter 10. SAP.1 149register (Fig, 10-6b). As usual, loading takes place midway through the state when the positive clock edge hits the CLK input of the B register. During the T, state, E, and [, are active; therefore, the fadder-subtracter sets up the accumulator (Fig. 10-6c) Halfway through this state, the positive clock edge loads the sum into the accumulator. Incidentally, setup time and propagation delay time prevent racing of the accumulator during this final execution state. When the positive clock edge hits in Fig. 10-6c, the accumulator contents change, forcing the adder-subtracter contents to change. The new contents return to the accu- ‘mulator input, but the new contents don’t get there until ‘wo propagation delays after the positive clock edge (one for the accumulator and one for the adder-subtracter). By then it’s too late to set up the accumulator. This prevents accumulator racing (loading more than once on the same clock edge). Figure 10-7 shows the timing diagram for the fetch and ADD routines. The fetch routine is the same as before: the 1, state loads the PC address into the MAR; the T; state increments the program counter; the T; state sends the addressed instruction to the instruction register. frrccienstenetertenate fu Fig, 10-7 Fetch and ADD timing diagram 150 Digital Computer Electronics During the T, state, Z, and Zy are active; on the next positive clock edge, the address field in the instruction register goes to the MAR. During the T, state, CE and Ly ae active; therefore, the addressed RAM word is loaded into the B register midway through the state. During the T, state, Ey and Ly ae active: when the postive clock edge hits, the sum out of the ader-subtracter is stored in the accumulator. ‘SUB Routine ‘The SUB routine is similar to the ADD routine. Figure 10-6a and b show the active parts of SAP-1 during the T, and T; states. During the T, state, a high S, is sent to the aadder-subtracter of Fig. 10-6c. The timing diagram is almost identical to Fig. 10-7. Visualize Sy low during the 7, 0 Ts states and S, high during the T, state, OUT Routine Suppose the instruction register contains the OUT instruction at the end of a fetch cycle. Then R = 1110 XXXX ‘The instruction field goes to the controller-sequencer for decoding. Then the controller-sequencer sends out the ‘control word needed to load the accumulator contents into the output register. Figure 10-8 shows the active sections of SAP-1 during the execution of an OUT instruction. Since E, and Z, are active, the next positive clock edge loads the accumulator contents into the output register during the 7, state. The Ts and 7, states are nops, Figure 10-9 is the timing diagram for the fetch and OUT routings. Again, the fetch cycle is same: address state, increment state, and memory state. During the 7, state, E, and Lo ate active; this transfers the accumulator word to the output register when the positive clock edge occurs. con Fig, 10-8 7, sate of OUT instruction.fptiefe Teele ryelericafetinee Fl cox es i | L T I 7 i 1 i { L T i T 1 1 I T 1 1 i T 1 1 1 1 i Fig, 10-9 Fetch and OUT timing diggram. HLT HLT does not require a control routine because no registers are involved in the execution of an HLT instruction. When the IR contains the instruction field 1111 signals the controller-sequencer to stop processing data. The controller-sequencer stops the computer by turning off the clock (circuitry discussed later) Machine Cycle and Instruction Cycle SAP-I has six T states (three fetch and three execute), These six states are called a machine cyele (sce Fig, 10-10a). It takes one machine cycle to fetch and execute each instruction. The SAP-I clock has a frequency of 1 KHz, equivalent to a period of 1 ms. Therefore, it takes 6 ms for a SAP-1 machine cycle. SAP.2is slightly different because some ofits instructions take more than one machine cycle to fetch and execute. Figure 10-105 shows the timing for an instruction that requires two machine cycles. The first three T states are the fetch cycle; however, the execution cycle requires the next nine T states. This is because two-machine-cycle instruction is more complicated and needs those extra T sates 10 complete the execution, ‘The number of T states needed to fetch and execute an instruction is called the instruction cycle. In SAP-1 the instruction cycle equals the machine cycle. In SAP-2 and ‘other microcomputers the instruction cycle may equal two ‘or more machine cycles, as shown in Fig. 10-100. The instruction cycles for the 8080 and 8085 take from ‘one to five machine cycles (more on this later). EXAMPLE 10-5 ‘The 8080/8085 programming manual says that it takes IR = 1111 Xxx thirteen 7 states to fetch and execute the LDA instruction. ck iw nla nl wlwlnlelolunfw| x Fig. 10-10 (a) SAP-1 instruction cycle; (b) instruction cycle with two machine cycles +} mactneeyoe » Chapter 10 sap1 151If the system clock has a frequency of 2.5 MHz, how long is an instruction cycle? SOLUTION ‘The period of the clock is 1 ieee 2.5MHz— 400s ‘Therefore, each T state lasts 400 ns. Since it takes thirteen T states to fetch and execute the LDA instruction, the instruction cycle lasts for 13 x 400 ns = 5,200 ns = 5.2 ps EXAMPLE 10-6 Figure 10-11 shows the six T states of SAP-1. The positive clock edge occurs halfway through each state. Why is this important? SOLUTION SAP-1 is a bus-organized computer (the common type nowadays). This allows its registers to communicate via the W bus. But reliable loading of a register takes place only when the setup and hold times are satisfied. Waiting half a cycle before loading the register satisfies the setup time; waiting half a cycle after loading satisfies the hold time. This is why the positive clock edge is designed to strike the registers halfway through each T state (Fig. 10-11). There's another reason for waiting half a cycle before loading @ register, When the ENABLE input of the sending register goes active, the contents of this register are suddenly dumped on the W bus. Stray capacitance and lead inductance prevent the bus lines from reaching their correct voltage levels immediately. In other words, we get transients on the W bus and have to wait for them to die out to ensure valid data at the time of loading. The half-cycle delay before clocking allows the data to settle before loading. 10-6 THE SAP-1 MICROPROGRAM We will soon be analyzing the schematic diagram of the SAP-1 computer, but first we need to summarize the execution of SAP-1 instructions in a neat table called a ‘microprogram. Microinstructions The controller-sequencer sends out control words, one uring each T state or clock cycle. These words are like directions telling the rest of the computer what to do. Because it produces a small step in the data processing, cach control word is called a microinstruction. When looking. at the SAP-1 block diagram (Fig. 10-1), we can visualize a steady stream of microinstructions flowing out of the ccontroller-sequencer to the other SAP-I circuits. Macroinstructions ‘The instructions we have been programming with (LDA, ADD, SUB, . . .) are sometimes called macroinstructions to distinguish them from microinstructions, Each SAP-1 ‘macroinstruction is made up of three microinstructions. For example, the LDA macroinstruction consists of the mi- croinstructions in Table 10-3. To simplify the appearance of these microinstruction, we can use hexadecimal chunk- ing as shown in Table 10-4 Table 10-5 shows the SAP-1 microprogram, a listing of each macroinstruction and the microinstructions needed (0 carry it out. This table summarizes the execute routines for the SAP-1 instructions, A similar table can be used with more advanced instruction sets. 10-7 THE SAP-1 SCHEMATIC DIAGRAM In this section we examine the complete schematic diagram for SAP+1, Figures 10-12 to 10-15 show all the chips, wires, and signals. You should refer to these figures throughout the following discussion. Appendix 4 gives additional details for some of the more complicated chips. Fig. 10-11 Positive clock edges occur midway through T states. 152 digital Computer ElectronicsTABLE 10-3 Macro State WDA oT r re TABLE 10-4 ‘Macro State CON Active WDA. IAM Le, ae CH) | ceAL T, 3E3H__ None ‘TABLE 10-5, SAP-1 MICROPROGRAMt Macro State Active LWA TIA La. Tr 23H CEI, T, 363H None ADD TT, TASH T. 2K CEL A ull eg i ST pee Tr 21H CE Ly Ta cee Dees COUN Te eeu) ear T, 33H None T, _3E3H__None TELE, S.&.Lsbo. Program Counter Chips C1, C2, and C3 of Fig. 10-12 ate the program counter. Chip Cl, a TALS107, is a dual JK master-slave flip-flop, that produces the upper 2 address bits. Chip C2. another 74LS107, produces the lower 2 address bits. Chip C3 is a 74LS126, a quad three-state normally open switch; gives the program counter 2 three-state oulpit At the start of a computer run, a low CLR resets the program counter to 0000. During the T, state, a high E> places the address on the W bus. During the 7: state, a high Cp is applied to the program counter: midway through this state, the negative CLK edge (equivalent to positive CLK edge) increments the program counter. ‘The program counter is inactive during the to T, states Active MAR Chip C4, a 74.8173, is a 4-bit buffer register; it serves as the MAR. Notice that pins 1 and 2 are grounded; this Converts the three-state output to a two-state output, In other words, the output of the MAR is not connected 10 the W bus, and so there's no need to use the three-state output 2-to-1 Multiplexer Chip C5 is a 74LS157, a 2-0-1 nibble multiplexer, The left nibble (pins 14, 11, 5, 2) comes from the address switeh register (S;,). The right nibble (pins 13, 10, 6, 3) comes from the MAR. The RUN-PROG switch (S,) selects the nibble to reach to the output of C5. When S; is in the PROG position, the nibble out of the address switch register is selected. On the other hand, when Sis the RUN position, the output of the MAR is selected 16 x 8RAM Chips C6 and C7 are 74189s. Each chip isa 16 % 4 static RAM. Together, they give us a 16 % 8 read-write memory Sy is the data switch register (8 bits), and Sis the read- ‘rite switch (a push-button switch). To program the mem- ‘ry, S2is putin the PRoG position; this takes the CE input Jow (pin 2). The address and data switches are then set to the correct address and data words. A momentary push of the read-write switch takes WE low (pin 3) and loads the memory After the program and data are in memory, the RUN- 0G switch (S.) is putin the RUN postion in preparation for the computer run Instruction Register Chips C8 and C9 are 74LS173s. Each chip is a 4-bitthree- state buffer register, The two chips are the insruction register. Grounding pins 1 and 2 of C8 converts the three- state output to a two-state outpot, Ill. This nibble goes tothe instruction decoder in the controller sequencer, Signal E, controls the output of C9, the lower nibble in the instruction register. When Fis low, this nibble is placed on the W bus Chapter 10 sap1 153sists | [er Li ca 1 ¥a4Nn09 wvuDoud 154 Digitat computer Electronicssowifa1 wonnnsul pub “Aiouour soqunos wmRexd VS THOT “BH 18 of slo} uausio3y NOLLONWASNI cuswe oo Chapter 10. SAP-1 aay vycose ts wr © eifarforfo} sf oy eft om cust bio eifafof 6 voLwinwnoov a19 ozistee uouovaLens jaaaav guises existe | 019 L224 eis apap Digital Computer Electronics 156pun “onoengns-s9ppe “io)H804 UE V EL OL I b I 0 157 w79 Chapter 10 SAP-1 cuistee ez uaisiozu indino existe suistee 0x0 uaisioay gAccumulator Chips C10 and C11, 74LS173s, are the accumulator (see Fig. 10-13), Pins 1 and 2 are grounded on both chips to produce a two-state output for the adder-subtracter. Chips C12 and C13 are 74LS126s; these three-state switches place the accumulator contents on the W bus when E, is high. Adder-subtracter Chips C14 and CIS are 74L886s. These EXCLUSIVE-OR gates are a controlled inverter. When Sy is low, the contents of the B register are transmitted. When S, is high, the I's complement is transmitted and a 1 is added to the LSB to form the 2's complement, Chips C16 and C17 are 74L883s. These 4-bit full adders combine to produce an 8-bit sum or difference. Chips C18 and C19, which are T4LS126s, convert this 8-bit answer into a three-state output for driving the W bus. B Register and Output Register Chips C20 and C21, which are 74L8173s, form the B register. It contains the data to be added or subtracted from the accumulator. Grounding pins 1 and 2 of both chips produces a two-state output for the adder-subtracter. Chips C22 and C23 are 74LS173s and form the output register. It drives the binary display and lets us see the processed data Clear-Start Debouncer In Fig. 10-14, the clear-start debouncer produces two ‘outputs: CLR for the instruction register and CER for the program counter and ring counter. CLR also goes to C29, the clock-start flip-flop. Sis a push-button switch. When depressed, it goes tothe CLEAR positon, generating @ high CLR and a low CLR, When 8, is released, it returns tothe START position, producing a low CLR and a high CLR. Notice thathalf of C24 i used forthe clear-start debouncer and the other half for the single-step debouncer. Chip C24 is a 7400, « quad 2-input NAND gate Single-Step Debouncer SAP-I can run in either of two modes, manual or automatic. In the manual mode, you press and release S, to generate cone clock pulse. When S, is depressed, CLK is high; when released, CLK is low. In other words, the single-step debouncer of Fig. 10-14 generates the T states one at @ time as you press and release the button. This allows you to step through the different 7 states while troubleshooting ‘of debugging. (Debugging means looking for errors in your program. You troubleshoot hardware and debug software.) 158 Digital computer Electronics Manual-Auto Debouncer ‘Switch S, is a single-pole double-throw (SPDT) switch that ccan remain in either the MANUAL position or the AUTO position. When in MANUAL, the single-step button is active. When in AUTO, the computer runs automatically. Two of the NAND gates in C26 are used to debounce the MANUAL~ {AUTO switch, The other two NAND C26 gates ure part of a [NAND-NAND network that steers the single-step clock or the ‘automatic clock to the final CLK and CLR outputs. Clock Buffers The output of pin 11, C26, drives the clock buffers. As you see in Fig. 10-14, two inverters are used to produce the final CLK output and one inverter to produce the CLK output. Unlike most of the other chips, C27 is standard TTTL rather than a low-power Schottky (see SAP-1 Parts List, Appendix 5). Standard TTL is used because it can drive 20 low-power Schottky TTL loads, as indicated in Table 4-5, If you check the data sheets of the 74LS107 and 7418173, for input currents, you will be able to count the following low-power Schottky (LS) TTL loads on the clock and clear signals CLK = 19 LS toads CLK = 2LS loads CLR = 1LS load CLR = 20S loads This means that the CLK and CLR signals out of C27 (standard TTL) are adequate to drive the low-power Schotky TIL loads. Also, the CLR and CLR signals out of C24 (standard TTL) can drive their loads Clock Circuits and Power Supply Chip C28 is a 535 timer. This IC produces a rectangular 2-kHz output with a 75 percent duty cycle. As previously discussed, a start-the-clock flip-flop (C29) divides the signal down to | KHz and at the same time produces a 50 percent duty cyele. The power supply consists of a full-wave bridge rectifier ‘working into a capacitor-input filter. The de voltage across the 1,000-F capacitor is approximately 20 V. Chip C30, an LM340T-5, is a voltage regulator that produces a stable output of +5 V. Instruction Decoder Chip C31, a hex inverter, produces complements of the op-code bits, Iryly (see Fig. 10-15). Then chips C32, €33, and C34 decode the op code to produce five output signals: LDA, ADD, SUB, OUT, and HLT. Remember:cueany ee fee = ; oo : Sy Je MANUAL oe a. 18kD 6] NESS | e ow t of | 10-14 Power supply, clock, and clear circuits only one of these is active at a time. (HET is active low; all the others are active high.) When the HLT instruction is in the instruction register, bits Ingls are 1111 and HT is low. This signal returns to C25 (single-step clock) and C29 (automatic clock). In either MANUAL oF AUTO mode, the clock stops and the computer run ends, Ring Counter ‘The ring counter, sometimes called a state counter, consists of three chips, C36, C37, and C38. Each of these chips is a T4LS107, a dual JK master-slave flip-flop. This counter is reset when the clear-start button (S,) is pressed. The Qy flip-flop is inverted so that its Q output (pin 6, C38) drives Chapter 10 sap1 159papas pes HAT | ee omfg] spa] ep HT |S Hy on srr] YT | Let ova STH] Pa | levee ours] Joya] era | fe xIuww TOBLNOD ‘WaLNn0o ON ‘xuew yonve> pur “ssiuno> Buus “sapos9p uoNMasuy ST-OT “BA [ee NOLaAwISNt reel 69 160 Digitat computer Electronicsthe J input of the Q, Aip-flop (pin 1. C38). Because of this, the 7, output is initially high. ‘The CLK signal drives an active low input. This means that the negative edge of the CLK signal initiates each T state. Half a cycle later, the positive edge of the CLK signal produces register loading, as previously described. Control Matrix The LDA, ADD, SUB, snd OUT signal rom te instruction decoder drive the control mauri, C39 to C48, At the same time, the ringcounter signals, T; t0 To, are driving the mati (a cireuit receiving two groups of bits from different sources). The matrix produces CON, a 12-bit microinstrve- tin that tls the rest of the computer what to do. In Fig. 10-18, 7, goes high then 7, then 7, and so on Analyze the control matrix and here is what you wl find A high T, produces a high Ey and a low Ly (address sat) avbigh T results ina high Cy Ginerement state); and a high T, produces a low CE and a low L, (memory state). The fst three states, therefore, are always the fetch cycle in SAP-I. In chunked notation. the CON words fr the fetch cycle are State ON _Active Bits th SEH Ep, Lu Tr BE3H tr 263H During the execution states. 7, through 7; go high in succession. At the same time, only one of the decoded signals (LDA through OUT) is high. Because of this, the matrix automatically sters active bits tothe corect output contol lines. For instance, when LDA is high, the only enabled 2- input NAND gates are the ist, fourth, seventh, and tenth When 7, is high, it activates the fist and seventh NAND ates, resulting in low Ey and low F; (load MAR with address field). When 7; is high, it activates the fourth and tenth NAND Bates, producing a low CE and a low L, (oad RAM data into accumulator). When T, goes high, none of the conteo bts are active (nop) You should analyze the action of the contol matrix during the execution slates of the remaining possibilities: high ADD, high SUB, and high OUT. Then you will agree the control matrix ean generate the ADD, SUB, and OUT microinstrctions shown in Table 10-5 (SAP-1 micropro- ram) Operation Before cach computer run, the operator enters the program and data into the SAP-1 memory, With the program in low memory and the data in high memory, the operator presses and releases the clear button. The CLK and CLK signals drive the registers and counters, The microinstruction out of the controller-sequencer determines what happens on each positive CLK edge Each SAP-1 machine cycle begins with a fetch cycle. T, is the address state, 7; is the increment state, and T; is the memory state. AC the end of the fetch cycle, the instruction is stored in the instruction register. After the instruction field has been decoded, the control matrix automatically {enerates the correct execution routine, Upon completion of the execution cycle, the ring counter resets and the next ‘machine cycle begins. ‘The data processing ends when a HLT instruction is loaded into the instruction register 10-8 MICROPROGRAMMING ‘The control matrix of Fig. 10-15 is one way to generate the microinstructions needed for each execution eyele, With larger instruction sets, the control matrix becomes very complicated and requires hundreds or even thousands of gates. This is why hardivired control (matrix gates soldered together) forced designers to look for an alternative way to produce the control words that run a computer. Microprogramming is the alternative, ‘The basic idea is to store mictoinstructions in a ROM rather than produce them with a control matrix. This approach simplifies the problem of building a controller-sequencer. Storing the Microprogram By assigning addresses and including the fetch routine, we cean come up with the SAP-1 microinstructions shown in Table 10-6. These microinstructions can be stored in a control ROM with the fetch routine at addresses OH to 2H. the LDA routine at addresses 3H to SH, the ADD routine at 6H to 8H, the SUB routine at 9H to BH, and the OUT routine at CH to FH To access any routine, we need to supply the comrect addresses. For instance, to get the ADD routine, we need to supply addresses GH, 7H, and 8H. To get the OUT routine, we supply addresses CH, DH, and EH. Therefore, accessing any routine requires three steps: 1. Knowing the starting address of the routine 2. Stepping through the routine addresses 3. Applying the addresses to the control ROM. Address ROM Figure 10-16 shows how to microprogram the SAP-1 computer. It has an address ROM, a presettable counter, and a control ROM. The address ROM contains the starting addresses of each routine in Table 10-6, In other words, Chapter 10 sap1 161TABLE 10-6. SAP-1 CONTROL ROM ‘TABLE 10-7. ADDRESS ROM Address _Contentst_ Routine Active oH SESH Fetch 1H BESH 2H 2631 3H IASH LDA 4H 203 SH SESH oH 1A3H ADD 7H 2EIH 8H 3C7H oH 1A3H suB AH 2E1H BH 3CFH cH BPH our DH 3E3H EH 3E3H FH Xx x FOON = GELCE TELE, SEdslo. Adress Row 1x4 Presta sounter = Ccontot Row 16x12 ernst Fig. 10-16 Microprogrammed control of SAP-1 the address ROM contains the data listed in Table 10-7 AAs shown, the starting address of the LDA routine is 0011, the starting address of the ADD routine is 0110, and so on. ‘When the op-code bits Iodls drive the address ROM, the starting address is gonerated. For instance, if the ADD 162 Digital computer Electronics Address Contents Routine 0000 001 LDA 001 o110 ADD 0010 L001 SUB O01 XXXX None 0100 XXXX None o1o1 XXXX None o110 XXXX None our XXXX None 1000 XXXX None 1001 XXXX None 1010 XXXX None lol XXXX None 1100 XXXX None not XXXX None 1110 1100 out mi XXXX None instruction is being executed, Isl, is OOO. This is the input to the address ROM; the output of this ROM is 0110, Presettable Counter ‘When 7) is high, the load input ofthe presettable counter is high and the counter loads the starting address from the address ROM. During the otherT states, the counter counts Initially, a high CLR signal from the clear-start debouncer is differentiated to get a narrow positive spike. This resets the counter. When the computer run begins, the counter ‘output is 0000 during the ; state, 0001 during the 7; state, aund 0010 during the T; state. Every fetch eycle isthe same because 0000, 0001, and O00 come out of the counter during siates T,, Ts, and Ty The op code in the instruction register controls the execution cycle. If an ADD instruction has been fetched the Ida, bits are 0001. These op-code bits drive the address ROM, producing an output of 0110 (Table 10-7), ‘This starting address isthe input tothe presettable counter. When 7, is high, the next negative clock edge loads 0110 into the presettable counter. The counter is now preset, and counting can resume at the starting address of the ADD routine. The counter output is 0110 during the 7, state, O11 during the T; state, and 1000 during the 7, state When the 7; state begins, the leading edge of the T; signal is differentiated to produce a narrow positive spike Which resets the counter to 0000, the starting address of the fetch routine, A new machine eyele then begins.Control ROM The control ROM stores the SAP-1 microinstructions. During the fetch cycle, it receives addresses 0000, 0001, and 0010, Therefore, its outputs are SESH BESH 263H ‘These microinstructions, listed in Table 10-6, produce the address state, increment state, and memory state. If an ADD instruction is being executed, the control ROM receives addresses 0110, O111, and 1000 during the execution cycle. Its outputs a 1A3H 2E1H 3C7H ‘These microinstructions carry out the addition as previously discussed For another example, suppose the OUT instruction is being executed. Then the op code is 1110 and the starting address is 1100 (Table 10-7). During the execution cycle, the counter output is 1100, 1101, and 1110. The output of the control ROM is 3F2H, 3E3H, and 3E3H (Table 10-6). This routine transfers the accumulator contents to the output port Variable Machine Cycle The microinstruction 3E3H in Table 10-6 is a nop. It occurs once in the LDA routine and twice in the OUT routine ‘These nops are used in SAP-I to get a fted machine cycle for all instructions. In other words, each machine cycle takes exactly six T states, no matter what the instruction In some computers a fixed machine cycle is an advantage But when speed is important, the nops are a waste of time and can be eliminated ‘One way to speed up the operation of SAP-I isto skip any T state with a nop. By redesigning the circuit of Fig 10-16 we can eliminate the nop states. This will shorten the machine cycle of the LDA instruction to five states (7, Tp, Ty, Ty, and T.). also shortens the machine eycle of the OUT instruction to four states (Ty, Ty Ts. and T.) Figure 10-17 shows one way to get a variable machine cycle. With an LDA instruction, the action isthe same as before during the T; to 7; states. When the Ty state begins, the control ROM produces an output of 3E3H (the nop microinstruction), The NAND gate detects this nop instantly and produces a low output signal NOP. NOP is fed back to the ring counter through an aND gate, as shown in Fig 10-18. This resets the ring counter to the T, state, and a new machine eycle begins. This reduces the machine eycle of the LDA instruction from six states to five, ROW wx OG Presettable a —) > Contat Rol Mieronsrution Fig, 10-17 Variable machine cycle. —a Fig. 10-18, With the OUT instruction, the first nop occurs in the Ts slate. In this case, just after the 7; state begins, the control ROM produces an output of 3E3H, which is detected by the NAND gate. The low NOP signal then resets the ring counter to the 7, state. In this way, we have reduced the machine cycle of the OUT instruction from six states to four. Chapter 10 sap-1 163Variable machine cycles are commonly used with micro- processors. In the 8085, for example, the machine cycles take from two to six T states because all unwanted nop states are ignored, Advantages One advantage of microprogramming is the elimination of the instruction decoder and control matrix; both of these become very complicated for larger instruction sets. In other words, it's @ lot easier to store microinstructions in a ROM than it is to wire an instruction decoder and control matrix Furthermore, once you wire an instruction decoder and control matrix, the only way you can change the instruction set is by disconnecting and rewiring. This is not necessary ‘with microprogrammed control: all you have to do is change the control ROM and the starting-address ROM. This is a big advantage if you are trying to upgrade equipment sold earlier. Summary In conclusion, most moder microprocessors use micropro- ‘grammed control instead of hardwired control. The micro- programming tables and circuits are more complicated than those for SAP-1, but the idea is the same. Microinstruetions are stored in a control ROM and accessed by applying the address of the desired microinstruction, GLOSSARY address state The T, state. During this state, the address in the program counter is transferred to the MAR. ‘accumulator ‘The place where answers to arithmetic and logic operations are accumulated. Sometimes called the A register assembly language program, B register An auxiliary register that stores the data to be added or subtracted from the accumulator. {fetch cycle The first part of the instruction cycle, During the fetch cycle, the address is sent to the memory, the program counter is incremented, and the instruction is transferred from the memory to the instruction register. increment state The T, state. During this state, the pro- gram counter is incremented, instruction cycle All the states needed to fetch and execute an instruction instruction register The register that receives the instruc tion from the memory. instruction set The instructions a computer responds to. LDA. Mnemonic for load the accumulator. ‘machine cycle All the states generated by the ring counter. machine language ‘The strings of Os and Is used in a program, ‘macroinstruction One of the instructions in the instruction set The mnemonics used in writing @ MAR Memory address register. This register receives the address of the data to be accessed in memory. The MAR supplies this address to the memory. ‘memory-reference instruction An instruction that calls for a second memory operation to access data. memory state The T, state, During this state, the instruc- tion in the memory is transferred (o the instruction register microinstruction A control word out of the controller~ sequencer. The smallest step in the data processing. nop No operation. A state during which nothing happens. ‘output register The register that receives processed data from the accumulator and drives the output display of SAP- 1. Also called an output por. object program — program written in machine language. ‘opcode Operation code. That part of the instruction which tells the computer what operation to perform. program counter A register that counts in binary. Its contents are the address of the next instruction to be fetched from the memory. RAM Random-access memory. A better name is read- write memory. The RAM stores the program and data needed for a computer run. source program A program written in mnemonics SELF-TESTING REVIEW Read each of the following and provide the missing words, Answers appear at the beginning of the next question, 1. The counter, which is part of the con- trol unit, counts from 0000 to 1111. It sends to the memory the of the next instruction. 164 digital Computer Electronics 2. (program, address) The MAR, or —___— reg- ister, latches the address from the program counter. AA Dit later, the MAR applies this address to the —___, where read operation is performed. (memory-address, RAM) The instruction register ispart of the control unit. The contents of the register are split into two nibbles. The upper nibble goes to the instruction, controlter-sequencer) The controller- sequencer produces a 12-bit word that controls the rest of the computer. The 12 wires carrying this word are called the control (control, bus) The is a buffer register 10. that stores sums or differences, Its two-state output goes to the adder-subtracter. The pro- duces the sum when Sis low and the difference ‘when Sy is high. The output register is sometimes called an output (op. Assembly, Machine) SAP-1 has T states, periods during which register contents change. The ring counter, or counter, produces these T states, These six states represent ‘one machine cycle. In SAP-I the instruction cycle has only one machine cycle. In microprocessors like the 8080 and the 8085, the eycle may have from one to five machine cycles. (six, state, instruction) The controller-sequencer sends out control words, one during each T state or clock cycle. Each control word is called a Instructions like LDA, ADD, SUB, etc, are called Each SAP-1 macroin- siruetion is made up of three ee LisLDA, ADD, SUB, OUT, and ton) With larger srt st the snl HUE UDA, ADD. and SUB ae calea tix becomes very complstad. This why hand instctions because they use data sored ine wri coma eg reac by The pa Sock en to sore te ream Cnsacton. memory reference Te 8080 was the Row Hist widely wed micerecessor The" is 12. trorogramming,microinaracons) SAP- wes tnethanced version of the 8080 wih escataly he S fac machine ei oral stetos eter (3085) LDA. ADD. SUB, OUT, and HLT ae Sst Miropcesr te the BORS fave vale coved a 41 seingy of Gand la This cole i mathine eye Seer al ween np sates a ‘Sted the ee = ed toes macs cg Tyee poe ene mas PROBLEMS 10-1. Write a SAP- program sing mnemonics (sim fencbnebneeneben tn Jar to Example 10-1) that will display the result 1 + ae lg al : TAA. ote eipmbe ee Use adresses DH, EH, and FH forthe data Cig eae 10-2, Comenthe suenbly lnpuage of Pt, 10 poi | jo SAP machine language, Show We answer eee in inary form and in evade for Ta 10-3. Write an assembly-language program that per # iTrLiy a ee ia : tt B+4-345-2 oft é iy Tt Use adesses BH FH forthe dats, i 10-4, Conver the program and data of Prob, 1023 into a LT machine language. Express he esl in bth | binary and hexadecimal form. f 1 10-5. Figure 10-19 shows the timing diagram for the i ADD instruction. Draw the timing diagram for be H Chapter 10 sap.1 165axa TalL IAW ore csiswe 9 By pny a waiNnoo . wv'Doue = soso coi’s sifesforf ef of of ef © cust 119 wovinwnoow solovuians raaaay szistwe cuistee 0199 existe euswe zo eistee zz euistee 00 uausioay “unaLno uaisiogu ecuean/ START STEP MANUAL! AUTO cLock circurt Power SUPPLY Fig. 10.22 Sr manual, ke oe ho exo aga 170 Digital Computer Electronics x0 unaios +8xieLy¥ TOELNCD WaLNNOD ONE vl 300030 NOLLOMBLSNI econ H,106. 10-7. 10-8. 10-9, ‘Suppose an 8085 uses a clock frequency of 3 MHz, The ADD instruction of an 8085 takes four T states to fetch and execute. How long is this? ‘What are the SAP-1 microinstructions for the LDA routine? For the SUB routine? Express the answers in binary and hexadecimal form. ‘Suppose we want to transfer the contents of the accumulator to the B register. This requires a new microinstruction. What is this microinstruc- tion? Express your answer in hexadecimal and binary form. Look at Fig, 10-20 and answer the following ‘questions: a, Are the contents of the program counter changed on the positive or negative edge of the CER signal? At this instant, is the CLK signal on its rising or falling edge” b. To increment the program counter, does Cy have to be low or high? cc. To clear the program counter, does CLR have to be low or high? 4. To place the contents of the program counter on the W bus, should £, be low or high? 172 digitat computer Electronics 10-10. 10-11. 10-12, Refer to Fig. 10-21: a. IfZais high, what happens to the accumulator contents on the next positive clock edge? b. IFA = 0010 1100 and B = 1100 1110, what is on the W bus if Es high? ¢. IFA = 0000 1111, B= 0000 0001, and Sy = 1, what is on the W bus when Ey is high? Answer the following questions for Fig. 10-22: a. With $5 in the CLEAR position, is the CLR output low or high? b. With Sin the Low position, isthe output low ot high for pin 11, C24? ¢. Tohave a clock signal at pin 3 of C2: HLT be tow or high? Refer to Fig. 10-23 to answer the following 4. fale = 1110, only one ofthe output pins in C35 is high. Which pin is this? (Disregard pins 10 and 12.) b. CER goes low. Which is the timing signa (7, 10 Ts) that goes high? ©. LDA and T, are high. Is the voltage low or high at pin 6, C45? 4. ADD and T, ate high. Is the signal low or high at pin 12, C43? should