Course code: ET/PC/B/T/316
Analog CMOS Design &
Technology
Part-13
Sep 2023
Dr. Joydeep Basu, Assistant Professor
Dept. of Electronics & Telecommunication Engg., Jadavpur University
https://jadavpuruniversity.in/faculty-profile/joydeep-basu
Op-amp Noise
All devices within the opamp generate noise (thermal, 1/f, etc.)
Net noise current at the o/p:
𝑖𝑛,𝑜𝑢𝑡 = 𝑖𝑛,1 − 𝑖𝑛,2 + 𝑖𝑛,3 − 𝑖𝑛,4
Uncorrelated from each other
in3 in4
Thus, o/p current noise spectrum:
16
𝑆𝑖𝑛,𝑂𝑈𝑇 = 𝑆𝑖𝑛,1 + 𝑆𝑖𝑛,2 + 𝑆𝑖𝑛,3 + 𝑆𝑖𝑛,4 = 𝑘𝑇(𝑔𝑚1 +𝑔𝑚3 )
3 in1 in2
in0
J. Basu Image: B Razavi, Design of Analog CMOS Integrated Circuits 2
Op-amp Noise
Can be represented as an input-referred equivalent voltage source (just like offset)
called “input-referred noise”
Determines the minimum signal level that can be processed with reasonable quality
16 1 𝑔𝑚3
I/p referred noise voltage: 𝑆𝑣𝑛,𝐼𝑁 = 3
𝑘𝑇
𝑔𝑚1
+ 2
𝑔𝑚1
in3 in4
in1 in2
in0
J. Basu Image: B Razavi, Design of Analog CMOS Integrated Circuits 3
Op-amp Slew-Rate
Slew-rate (SR) is the max. possible rate of change of the o/p: (𝑑𝑉𝑜𝑢𝑡 Τ𝑑𝑡)max
Large-signal o/p may be limited by SR due to limited current available to charge and
discharge the dominant capacitor (CL)
Slewing is a nonlinear phenomenon
E.g., with step i/p to a unity-gain buffer: response is exponential for small inputs;
whereas a linear ramp (with a constant slope) for large input steps
creates o/p distortion
J. Basu Image: B Razavi, Design of Analog CMOS Integrated Circuits 4
Op-amp Slew-Rate
For the OTA – with large enough input swing, either M1 or M2 turns off:
𝐼𝑆𝑆
𝑆𝑅+ = = 𝑆𝑅−
𝐶𝐿
J. Basu Image: R. Baker, CMOS Circuit Design, Layout, and Simulation 5
Op-amp Noise
Exercise-1:
I/p-referred-noise voltage (say, 𝑣𝑛 ) of each transistor of the 5T OTA is 1 𝑛𝑉/√𝐻𝑧.
(a) Find the i/p-referred-noise voltage for this amplifier if (W/L)1,2 = 2 um/1 um, (W/L)3,4
= 1 um/1 um, CL = 10 pF and I0 = 50 uA.
Given μnCox= 100 μA/V2 = 2μpCox.
(b) Find the equivalent output noise current.
(c) What is the slew-rate under these conditions?
2
2 2 2
𝑔𝑚3 2 2
𝑣𝑛,𝑖𝑛 = 𝑣𝑛,1 + 𝑣𝑛,2 + 𝑣𝑛,3 + 𝑣𝑛,4
𝑔𝑚1
ANS: 𝑔𝑚3
2
2 2
= 2 ∙ 𝑣𝑛,1 ∙ 1+ = 2.5 ∙ 𝑣𝑛,1
𝑔𝑚1
Here, 𝑣𝑛,1 = 1 𝑛𝑉/√𝐻𝑧, thus 𝑣𝑛,𝑖𝑛 = 1.58 𝑛𝑉/√𝐻𝑧
J. Basu Image: B Razavi, Design of Analog CMOS Integrated Circuits 6
Op-amp Specs
To design an opamp in an IC for some specific application - need to meet a lot of
specifications (called “specs”):
dc gain
3-dB bandwidth (or, GBW)
Power consumption
Slew rate
ICMR
Output swing
CMRR
Noise
Offset
Harmonic distortion … etc.
J. Basu 7
Op-amp Specs
General design approach for an analog circuit:
Start with given specs
Get rough design (MOSFET W/L, current, etc.) using hand calculations
Feed these into simulator and check performance
Tune various design parameters in simulator
Again check performance
Iterate… till desired performance is achieved!
J. Basu 8
Op-amp Circuit Design Example
Design a single-stage opamp with the following specs:
dc gain ≥ 35 dB
Unity-gain freq ≥ 5 MHz (CL = 10 pF)
Power consumption ≤ 100 μW
Slew rate = 5 V/ μs
Input common-mode range (ICMR)
ICMR+ = 1.6V
ICMR- = 0.8V
Assume following process-specific parameters (from 180nm):
Vdd = 1.8 V, μnCox ~ 300 μA/V2, μpCox ~ 60 μA/V2, Vthn ~ 0.5 V ~ Vthp, λn ~ 70e-3, λp ~ 20e-3
Take L=0.5 μm for all MOSFETs (can increase if required)
J. Basu Image: B Razavi, Design of Analog CMOS Integrated Circuits 9
Op-amp Design Example (Hand Calculations)
Step-1: From SR and power I0
Step-2: From UGF (W/L)1,2
Step-3: From ICMR- (W/L)5
Step-4: From ICMR+ (W/L)3,4
Step-5: Calculate rds dc gain
Step-6: Might have to tune if some specs are Use a
not met current-
mirror in tail
E.g., refer to Allen &
Holberg – Ch 5
J. Basu Image: B Razavi, Design of Analog CMOS Integrated Circuits 10
Op-amp Design Example (in Simulator)
Home Assignment:
1. Use Cadence Virtuoso simulation tool and 180nm GPDK
2. Compose the schematic (with earlier designed values) in Virtuoso
3. Simulate and check different performance parameters
DC (operating point) analysis
AC analysis
Transient analysis
Parametric analysis
4. Tune the op-amp design within the simulator to meet the desired specs
(Numerous online tutorials available on the usage of Cadence Virtuoso)
J. Basu 11
Higher Gain Single-stage Op-amp
Telescopic cascode opamp topology
To have high gain from a single-stage OTA:
Drawback: less output swing
J. Basu Image: B Razavi, Design of Analog CMOS Integrated Circuits 12
Two-stage Op-amp
To get higher gain without sacrificing o/p swing
Miller-compensated 2-stage opamp is a very popular topology in IC design
Stage-1 can be any of the discussed topologies
Stage-2 is usually a common-source stage
J. Basu Images: B Razavi, Design of Analog CMOS Integrated Circuits 13
Two-stage Op-amp
Miller-compensated 2-stage opamp
Stage-1 is the 5T OTA
Stage-2 is a CS stage
Compensation
cap
Thus, total gain: 𝐴𝑣0 = 𝐴𝑣1 ∙ 𝐴𝑣2
VSS is Gnd or
-ve supply
There are poles at the o/p of each stage
voltage
Cc is used for compensation of the opamp (discussed in next slides)
J. Basu Images: P. Allen and D. Holberg, CMOS Analog Circuit Design 14
Op-amp Stability
Opamp/OTA are generally used in negative f/b systems (as discussed earlier)
Have a looping path with -ve gain, through which signal flows
X(s) + H(s) Y(s) 𝑌(𝑠) 𝐻(𝑠)
‒
=
𝑋(𝑠) 1 + 𝛽𝐻(𝑠)
Opamp
β loop−gain = −𝛽𝐻(𝑠)
If 𝛽𝐻(𝑠) = -1 at certain s=jω1, the closed-loop gain tends to infinity circuit can amplify its
own noise, until it eventually begins to oscillate at a freq. of ω1
i.e., |𝛽𝐻(𝑗𝜔1 )| = 1 and
Barkhausen
∠𝛽𝐻(𝑗𝜔1 ) = −180°
criteria
J. Basu 15
Op-amp Stability
Checking if |𝛽𝐻(𝑗𝜔1 )| = 1 and ∠𝛽𝐻(𝑗𝜔1 ) = −180°
In a stable system, the gain crossover must occur well before the phase crossover, e.g.,
Gain crossover
Phase crossover
J. Basu Image: B Razavi, Design of Analog CMOS Integrated Circuits 16
Op-amp Stability
Phase margin (ΦM): a measure of stability – value of phase when the magnitude is
unity (0 dB), or equivalently the margin left from reaching a phase-shift of -180°
Desirable PM ~ 45° to 60°
J. Basu Image: P. Allen and D. Holberg, CMOS Analog Circuit Design 17
Op-amp Stability
Importance of adequate phase margin is also evident from time-domain response
of the closed-loop system (e.g., second-order)
Larger phase margins result in
less “ringing” of the output signal
J. Basu Image: P. Allen and D. Holberg, CMOS Analog Circuit Design 18
Two-stage Op-amp Stability
Single pole cannot contribute a phase shift greater than 90° unconditionally stable
In systems with 2 poles, e.g., 2-stage opamp:
Each stage produces one dominant pole
Can become unstable in closed loop
Needs to be
“compensated”
J. Basu Image: B Razavi, Design of Analog CMOS Integrated Circuits 19
Two-stage Op-amp Stability
For uncompensated 2-stage op-amp
Each stage produces one “dominant” pole:
1 1
𝑝1′ = 𝑝2′ =
𝑅𝐼 𝐶𝐼 𝑅𝐼𝐼 𝐶𝐼𝐼
For –ve f/b loop using this op-amp and
f/b factor 𝛽 = 1 (worst case for stability
considerations):
One of the dominant poles must be
moved toward the origin PM is quite
< 45°
J. Basu Image: P. Allen and D. Holberg, CMOS Analog Circuit Design 20
Miller Effect
Home Exercise:
Using Miller effect, what are the effective capacitances at the nodes E and A due to
the capacitor Cc?
J. Basu 21
Frequency Compensation
For stability of closed-loop systems having 2-stage opamp:
Miller compensation is commonly applied
CC is the cap added in the 2-stage op-amp
Creates a large cap at node E
E A
Compensation
cap
Images: B Razavi, Design of Analog CMOS Integrated Circuits
J. Basu P. Allen and D. Holberg, CMOS Analog Circuit Design 22
Frequency Compensation
Miller compensation of 2-stage opamp
Transfer function:
zero (𝑧1 )
two poles (𝑝1 , 𝑝2 )
J. Basu Images: P. Allen and D. Holberg, CMOS Analog Circuit Design 23
Frequency Compensation
Miller compensation of 2-stage opamp
Due to increased 𝐶𝐼 𝑝1′ moves to a lower frequency 𝑝1
1
𝑝1 ≃
𝑅𝐼 𝑔𝑚𝐼𝐼 𝑅𝐼𝐼 𝐶𝑐
Due to reduced 𝑅𝐼𝐼 𝑝2′ moves to a higher
frequency 𝑝2
𝑔𝑚𝐼𝐼 we try to
𝑝2 ≃ keep 𝑝2 near
𝐶𝐼𝐼 or > GBW
Widely spaced poles called “pole splitting”
Improved PM
J. Basu 24
Two-stage Op-amp GBW
For 2-stage opamp:
Assuming the dominant pole (𝑝1 ) is much smaller than the output pole (𝑝2 )
GBW frequency is smaller than the output pole
Op-amp transfer function approximated by a single dominant pole:
𝑔𝑚𝐼 𝑔𝑚1
𝐺𝐵𝑊 = =
𝐶𝑐 𝐶𝑐
J. Basu 25
