nas une — | PLD Architectures > | and Applicationg ——— 3.1: Introduction + Eel te chests of PA rommmae Lge fans UA (ropummae tage ayy Hwan PLA cs nt rt a aS See Aecoder oF does not generate all the minterms ke ROME = SE n the PLA the decoder i rephaont BY a group of AND sehbtervinverters each of which cane page senerate some prt teins of input vanable aku are essential Ro realize the outptt Ametions, The AND ant OR gates inside the PLA ave inital’ ane with the fusible links among them The segue! Beate functions are implementat sum of the pais See opening the approprate lake and euinng Be eee #80. the PLA consists of to programmable planes AND ant ce planes, The AND plane sonst ot PROS? rate Haece along with AND gatec The OR plane gost of page Ses ane ttergonnest along sith OR ypu fo the PLA ast fe Seren 1 Bath oF the inpuae can Be soetmasta the cabo pas ant howsental jot PED Archiecrres nd Appice vist penignand Tecmology 3-2 __ PED Are connected, but configuring the PLA * Ser points together fein this view he AND Tris view is BY convention. i inputs (vertical lines) can be connected « Genera! sinacrere of a PLA S sho ate seen woth 2 angie ne 39 oe TS ree 7 As losie fancoone can be TORN gaeee whuch seeds a set of Sa Songer 2 ote ae was down the Fig O21 rough a ae of belies Sok + AND plane producesedmelogy 3-3 PLD Architectures end Aptction ‘VLSI Design an “Touch of tse terms can be conigred fo implement any ay fanction of X= Xn’ the inputs oan OR plane eTheproduct termsserveasthe input plane, which odes the oops Fy fy Each output canbe configured tg Pree any sum of Py~Py and hence any sumo produce ‘Seen of he PLA inp GHA is efidet in tems of the et needed for ty implementation on an integrated circuit chip. For this reason Plas are often included as part of larger chips, such ag cups tin dee of 4 PEL Ke sled B ier ope, fu, umber of product terms, and the number of outputs. The Tanber of sim terms is equal othe number of oxtpas, 22 Wit the help of suitable schematic, compare PROM, PLA and schitecares. Whet Is the need of CPLD ae 1 [SPU : May-15, Has 7) Ans: a No PROM. PLA PAL 1. AND amay is fced | Both AND and OR | OR aray is fixed and AND array ie programmable, 2 Conoedions are | PLAsakind of | PAL is an ‘sed and bumed programmable logic | combinational PLD ‘nthe eld with a device used to that was developed to | PROM ‘implement overcome certain | programmer cembinationa logic | disadvantage of PLA. sircut thas | PLA shows longer Programmable AND | delay due to Gate linked with | additional fusible links Programmable OR | which results from Gate using two | programmable array and increase circuit comple 1 Ge for Engnering Sinden YSIDesign end Technology 3-4 PLD Architectures and Applications Nood of CPLD 1. ACPLD comprises multiple circuit blocks on a single chip, with internal wiring resources to connect the circuit blocks. Each circuit block is similar to @ PLA or a PAL, 2. The characteristic of non-volatility makes the CPLD the device of choice in modem digital designs to perform ‘boot loader functions before handing over control to other devices not having this capability. A good example is where a CPLD is used ‘to load configuration date for an FPGA from non-volatile memory. 3. CPLDs offer a single-chip solution with fast pin-to-pin delays, ‘even for wide input functions. Use CPLDs for small designs, ‘where ‘instant-on’ fast and wide decoding, ultra-low idle power consumption, and design security are important (eg, in battery-operated equipment). Q3 What are the limitation of PLD architectures ? ES (SPPU : Maya, Mar 4] ‘Ans.: 1. Because the need is to be programmable, PLDs must ‘include extra circuitry in addition to -vhat is required to perform a specific function, 2 This results in increased die sizes. 3. Higher manufacturing cost per unit 4. As compared to ASIC, performance is poor. 3.2 : Design Flow 24 Explain PLD targeted design flow in detail (SPP: May 10. tnd Sem, Mk 7 Ot In Se, ark 6) A Gale for Enpnering SuterLp Arehitectares and Application, resign flow. FPGA eee Et ey on design flow? Explain tn deta, neat by ste eps age, Un Sem, Mae 5) op Eales on What design are a8 follows mate tan decomposition and functional simulation this stage is a document which futectare, suuctural LIOUkS, thet sans: Steps i 4, Architect 1s, probl " fable), The output of Of spare yr avira fanetons an ners. 2 HDL design entry The Hardware Description Langu HDLs are VHDL and Verilog. est environment design : This stage involves writing of test we emmens and behavioral models (when applicable). They seiner used to ensue thatthe HDL description of a device is comet. ‘4 Behavioral simulation : Ths is an important stage that checks HDL comecness by comparing outputs of the IDL model and the behavioral mode (being putin the same conditions). 5 Synthesis : This stage involves conversion of an HDL ‘description to a so-called netlist which is basically a formally ‘wien digital rout schematic. Synthesis is performed by a special software called synthesizer. For an HDL code that is corecly writen and simulated, synthesis shouldn't be any problem. However, synthesis can reveal some problems and Potential erors that cant be found using behavioral simulation, 5, a design engineer should pay attention to wamings ‘Produced by the synthesizer. 6 Implementation : A synthesizer-generated netlist is mapped ‘nto particular device's intemal structure. The main, phase of the Paap stage is place and route or layout, which 'A resources (Such as logic cells and connection se “A Gude for Enncering Ses device is described in a formal yge (HDL). The most common Vist Design and Tecnology 3 7. Timing analysi 6 PLD Architectures an Applications wires), Then these configuration data are written to a special file by a program called bitstream generator. During the timing analysis special software checks whether the implemented design satisfies timing constraints (such as clock frequency) specified by the user. Roquicements 1 ‘archecture ‘sion Test esign HOL design ony | | Beavoual ‘imulaton Syethesis Implementation Timing analyse Bisa Fig. @.4.1 Stops in PLD design ‘A Guide for Engncrng Sens‘PLD Architectures and Application, jecture, Features, cpu Archit 33: CPD rons, Applications ‘specifications, _ vi an Sb, ve of CPLD in detall. Explain cell tetas fees, clocki og Explore cis inter connect resources, clocking blocks, Int 1 [SPPU :Dec13, Hark Frp-ops, VO ety of devices Marke Ye) footprint compat tectre of CPLD in detail. (OR Explore the architects ey: wecnB5, 18, Hay39, nd Sem, Marks 7 {in dotall, Explain in brief (OR Draw CPLD orchitectne 19 OM sp: Oct-16, In Sem, Marks 5} ‘eplotn the detail architecture of CPLD. oe 6 (SPP Mp2, Mak, Deco Marks 8 aL cos of mulipl rat Backs on singe cp aS ng ures comet the cel lok, ES] 10 PAL PAL ec bio book Ieroomection wes | Tie tl x Pa PAL 10 Heck | Book ‘ook boc Fig, Q5.4 Structure of CPLO * The architectural building blocks of CPLD 1. PAL blocks (also called an function blocks) 2 Interconnect matrix 4 Inpet foutput (U0) blocks, “A Gude or Engnering Suns 1st Design and Technology 3 PLD Architectures and Applications + Fig. Q51 shows generic CPLD architecture. T ‘Mirooas Programmatic | Product [ Fom —e} AND tem |} ———}- ow ot array, alcalar matic i i 1) Function block + AND plane can accept inputs from the I/O blocks, other function blocks or feedback from the same function block. The terms are then ORed together using a fixed number of OR gatos, and terms are selected via a large muliplexer. ‘+ The output of the MUX can then be sent straight out of the block or through a clocked flip-Bop. Bach function is comprised of microcells each capable of implementing a combinational or registered function, +The FB generates outputs that drive the fast connect switch matsix * Logic within FB is implemented using a sum-of-product form. 2} Interconnect matrix ‘The interconnect matrix connects signals to FB inputs, all 1OB outputs and all 0. FB outputs drive the fast connect matrix. Any of these may be selected to drive each FB with a tniform delay. 3] YO block : ‘The I/O Block interfaces between the internal logic and the device uses 1/0 pins ee Soot 1 Gude for Engineering Sensjog PuDAncitactires end Appian, am input butler, output driver, oy sre and ser programmable grt ass oeagn ed Tene des “pach UO Blok inci Each TA jection suliple with § V TIL 33 V CMOS ang igred to provide fast switching wig, "Al output driver in the device may aie fr ding ether 93 V CMOS level des wser programmable ground pin capably, 8 eo ke gd atl pon, pins. + Bach 108 also that is active during valid provides for bushold circuitry (aso called Keeper) user operation. 3.41 FPGA Architecture, Features, ‘Specifications, Applications 46 Draw the architecutre of FPGA in detall. Explore LUTs, routing 2 ras memory blocks and clock management methods ee hye, aks 6; O28, In Sem, Dec, End Sem, Marks 4 (OR Draw FPGA. architecute in resources, Fipflops, U0 bloc Clock management etc. Give specifications of FPGA. TEE (SPP Doco36, Marks 16; May-19, End Sem, Marks 7) (OR Explore the architecture of FPGA in detail, 1 SPPU : Aug, Yn Sem, Marks 5) OR With the help of suitable dlagram of architectural details expan the typleal specications of FPGA. 1 [SPPU Aug, Marks 51 (OR Draw and explain the detall architecture of FPGA. 1 [SPPU May 18, Marks 6; Dec-18, Maks 7] “Tne for Englcering Se st Design and Tecmology 3-10 PLD Avcitectures and Applications ‘Ans. 1 Field Programmable Gate Array (FPGA): A FPGA is a programmable logic device which supports implementations of relatively large logic circuit. «# The building blocks of FPGA are 1. Logie eels (LCs) grouped into configurable logic blocks (CLBS) 2.10 blocs 3, Programmable interconnects. Tem Gauge) © [emtonaoe] [coma Se oe a wis) | | vectter | [_bosktcie a Trecpet rate g 8 8 Taayaae] © [emiginse] — [emiguane ae ae woe ortie) | | vestcis) | [_veckiies eee Fig. Q.6.1 Architecture of FPGA 4. Logle Cells : « Each logic block is an FPGA typically has a smaller number of inputs and outputs. A variety of FPGA products are on the market, featuring different types of logic blocks. ‘The most commonly used logic block is a lookup table (LUT), which contains storage cells that are used to implement a small log function. + Bach cell is capable of holding a single logic value, either 0 oF 1 ‘The stored value is produced as the output of the storage cell. ———— “Ane for Engincrng Staten ee aencmiay 2H _ MAIC gy ‘vist Design are spines where the size j Ts of various sze5 mY be crated i tg pp the mumber of MPU Two baat the structure ofa stall LUT: Tt has ting, eg. Q62 Sows all ‘Ae and one output neers ing any logic function of two v, spake of implementing any 13 i 7 oe Thoovanable truth table has four rows, this yp es, tomo a Soho eee ot xe o 0 o4 a0) 1 1] ORR oa (©) Storage cell contents inthe LUT Fg. 62 Circuit for a two-nput LUT +The put variables x and xp are used as the select inputs of ‘Ses ulspleurs, which depending on the valuation of x, and 2a select the content of one uf the four stor as the cuptut of the LUT. a a “A Guide for Enpnerng Sues? ree, VLSIDesign and Technology 3-12 __ PLD Architectures and Applications To see how a logic function can be realized in the two-input LUT, consider the truth table shown in Fig. Q62 (b). The function f; ftom this table can be stored in the LUT as illustrated in Fig. Q62 (0. ‘The arrangement of multiplexers in the LUT correctly realizes the function f,. When x, = x, = 0, the output of the LUT is driven by the top storage cell, which represents the entry in the truth table for xX; * 00. «Similarly, for all valuations of x, and x,, the logic value stored in the storage cell corresponding to the entry in the truth table chosen by the paticular valuation appears on the LUT output «+ Providing access to the contents of storage calls is only one way in which multiplexers can be used to implement logic functions ‘Three input LUT ‘Fig. Q63 shows a three input LUT. It has eight storage cells because 2 three-variabe truth table has eight rows ee ——— | on a uw wi of oF a a Fig. 6.3 A three Input LUT S—S— ecoess A Guide for Engineering Students{ee J sonny _ 1 pss tng pose nb TO ‘ein commercial 16 and 52 storaBe® inpots ea enc, besides @ LUT, in each ally have Os a peop may be inchuded in have either four or fiyg eFpca log Hoc Select Fstop J lp [ou lock —} Fg, G64 Inclusion of fps In an FPGA foie block « Fora loge cit tobe realized in an FPGA, each logic function rene art must be small enough to fit within a single logic block In pacc, a uses rut i automatically translated into the eequred frm by using CAD tools. «When a cuit is implemented in an FPGA, the logic blocks are programmed to realize the necessary functions and the routing channels ae programmed fo make the required interconnections between logic Blocks. 2.0 Blocks: + Each bank canbe configured individually to support @ particular WO standard. ‘Allows the FPGA to work with device using m Ales ing multiple 1/0 FPGA can actually be ly be used to inter ae face between different YO ‘A Guid for Engeering Suerte spstDesigané Tecnology 3-14 PLD Architectures and Apreniont sustDesgnantTechnlory 9-1 I a ‘Modern FPGA output signals with fast edge rates requires termination to prevent reflections and maintain signal integrity High pin count ° package cannot accommodate extemal termination registers. «Thus a digitally controlled impedance (DCI) is employed. ‘sDCI eliminates the need for extemal register and improves signal integrity +, Programmable Interconnect : ‘A programmable switch matrix form the heart of interconnect in J EPGA. The actual switching matrix employed a structure of six pass transistors per ross point, Thus connectivity can Pe RStablshed by controlling the transistors and various type of connections 1) Single lines : Used to connect a CLB to another CLB is one hop away” These wires have to go through a programmable switch hence add delay 1) Double lines : These sites travel past two CLB before hitting the switch, hence they provide shorter delays for longer connections. 3) Long lines : Wires in long grovps do not go through any programmable switch at all instead they travel all the way cross or down a row or column and are driven by tri-state drivers. 4) Global clock lines : These lines are optimized for case as clock inputs to the CLB, providing short delay and minimal skew. 7 How does logic get implement in CPLD and FPGA ? What Is conceptual diference ? (SPU : Auget5, In Sem, Nak 5] ‘Ans. : CPLD for logic implementation : *CPLDs can be thought of as multiple PLDs (plus some programmable interconnect) in a single chip. The larger size of a PLD allows implementing either more logic equations or a more ‘complicated design. A block diagram of « hypothetical CPLD is, shown in Fig. Q7.1 exco0ss 1 Ge for Engnering Sens15 _ PLD Architectures nd Application ———— 3-16 PLD Architectures and Applications srs Tet ‘uEst Design and Technology f " “| sat by coniguration lag | Lage tie U7 Besveem Logie block 1 y ee | i nk ' / a4 oie : — ae ee ae i a 074 i the four logic lacs shown there i the equivalent of ong Hib Howey, inan actual CPLD there may be more (or ls) TA four lagi blocks. These logic Blocks are themselves tompied of macrocels and interconnect wiing, just tke an crdnary PLD. FPGA for Loge implementation ‘Basc structure of an FPGA includes logic elements, rogammable interconnects and memory. Arrangement of these bods is specific to particular manufacturer, On the basis of intemal arangement of blocks FPGAS can be divided into three classes 1. Symnetsical arrays 2. Row based architecture 3, Hierarchical PLO ‘+ Look up table is used to implement any number of different fuxctionality. The input lines go into the input and enable of lookup table, The output of the lookup table gives the result of ‘he logic function that it implements, Lookup table is implemented using SRAM, ‘+A neinput LUT based logic block can be implemented in number of ferent ways with tadeo deny "27 Mh tadeott between performance and Topic Bach of SS 4 tapinin with dlagam SRAM and. antfuse programming Oe acd in PCR Tas cet re Ans, ; SRAM antisfuse programming technique : » Devices based on antifuse technology are one time programmable. An antifuse ritialy provides insulation between two conductors, but when Sudficient programming voltage is applied across it, conducting sath forma. It is one time programmable, once an antifuse is blown * can not be removed. + There exists two classes of antifuse technology. 1. Poly-diffusion antifuse 2, Metal-metal antifuse 1. Poly-dffusion antifuse : * An oxide nitride dielectric normally prevents current from flowing between diffusion and poly-silicon layers. + When programming pulse is applied the dielectric melts and a circuit formed between the diffusion and poly-silicon. 2. Motalmetal antituse : The link is an alloy of tungsten titanium and silicon. Usually the conductive link is formed at the comer or at via where the electric field is highest during programming, "1 Gul fr Boghnaaring Sedonaasi nt temcoy _ 90 ro se designs are verified by using a simulaty, sage Be gr bat neste fay ng of creat es Fac snd Fete TDP) allow eg ig * caeia that will be used during device layout. analyzer is usually part of the vendors aware. Tt provides timing information about einen ge Ts informa is wery arte and cn be ate Oe eet way, 5h s paying al pas in sen ann thm om lenges 1 shott delay ss ening analy is pefoed by dealt on he design pips faze of CDs is he determining a «fed dey xis per macroce Timing Report i able to give the exact propagation delays eup ies and clckto-ut times. 10 What is need of FPGA ? List typical of FPGA. EF SPPU Dec5, May39, End Sem, Maks 7] PLD Architectures and Application, eA static timing implementation 50! (OR Give typical features end specifications of FPGA. 1 [SPU : Oct-26, In Ser, Marks 5} ‘Ans. : Need of FPGA : 4. FPGA and CDLD retain the advantages and overcome the disadvantages of PALs and PLAS. 2. FPGA and CPLD are reprogrammable logic devices. 3. Designers use software to develop any digital cireuit and program the chip to perform the function. 4 Performance- FPGAs and CPLDs are very fast compared to microcontrollers 5. FPGA are more reliable and has less maintenance. —S— __ Guconrs ‘A Guliic for Hantvesrina Suds VLSI Design and Technology 3-20 PLD Architectures and Applications specifications of Altra Cyclone Ill FPGA Cyclone Il development board + Cyclone I EP3C120F780 FPGA. + Embedded USB-Blaster™ circuitry (includes an Altera MAX® II CPLD) allowing download of FPGA configuration files via the flash device or the host computer. Memory + 256 megabytes (MB) of dual-channel DDR2 SDRAM with error correction code (ECQ) ‘+ 8 MB of synchronous SRAM «+64 MB of flash memory ‘communication ports + 10/100/1000 Ethernet + USB 20 Power and analog devices from Linear Technology « Switching power supply LTMA601 «Switching and step-down regulators LTI931, LTS48t and LTC34I8 + Analog-o-digital converter LTC2402 + LDO regulators LT1963 and LTI761 Clocking 4 50-MHz and 125-MHz on-board oscillators + SMA inputs/outputs 11/08 for the two HSMC connectors + Various buttons switches and indicators Display 1128 x 64 graphics LCD «Dine x 16character LCD i eid for Ergicering SensVLSIDesign and Tecnology 3-22 PLD Architectures and Applications jot PLDAreitecturs and Applicat stein and Tce i vist Deion Connectors «Two HSMCS a UsB ope Debug tools se Throe HSM debug a ‘cables and powerlanalog 414 to 20-V DC input 1s (wo loop-back and a debug heades) «+ On-boand power measurement circuit 1 108 W per HSMC interface 211 With the help of suitable diagram of architectural deta iain the typical specifications of FPGA. ee [[SPPU: Auge, In Se, Maks 5) Ans. : FPGA Architecture : Refer Q6. FPGA Specifications: Refer Q10. (012 Compare CPLD wr. FPGA. 5 [SPPU:AugotS, In Sem, Nas 5} (OR Compare CPLD and FPGA architectures in brief 1 SSPU : Auget7, Marks 81 (OR What factors are considered to make a choice in between FPGA and CPLD ? a [SPP Dee, Hake) Ans. cru FPGA CLD provide highest FPGAs ae offered ina wide Desformance, but they also | density range, from few ‘contain fewer registers than | thousand gates to several LGAs million gates PLDs are ideal for complex | FPGA architecture is more blocks with a lange number of | granular compared to CPLD, | nyu ‘making it suitable for designs With large numberof simple blocks with few numbers of inputs PLDs can implement large | FPGAs cant implement large functions in one pass theoigh | functions in one pass through logic area. the loge area. CCPLD's resources are FPGAs contain arays of logic partiond int ogc bac celis and ae less parttoned | imposing restrictions on how | than CPLDs [they may be used, | 3 [A numberof inputouiput | A number of input-output pin olered by CPLD se | pin offered onthe FPGA are significantly higher. | less than CPLD. 6 | ny deign can tino» | Se design reque 130 TOOK gate CPLD, le space | gate FPGA ve space mquced repr on alicon tas. | ensilem is more CPLD based design needs es | FPGA bused design ands board spce, bord layout | increased bord spec board comply cst and bil of | layout comple ext and tateal (20M) than FPCA. | bilo material BOND) CCPLD dosnt requ any | FPGA invariably rege one ‘memory store configuration or more configuration PROM, | program dapending onthe ze o FPGA use (CPD with hi coursegiain | Due to granular achecture Srchesuy and dedetcd | and sgueted vung of routing ofthe vantage of) FPGA sei predic predicble timing and | the speed perormance of 2 | Enderae design ul it aged in | the stare 12. | CPLD ansume more power | FPGA comes is power than FPGA devies than CHD. TH [ Proc cnologes are | Proes ecnologies ae EPROM EEPROM and) | SRAM, ant-fuse and FLASH EEPROM! rm ati ai Applications of CPLD bus | FPGA applications Interfaces, complex state machines, fast memory interfaces, wide detectors, PAL | device integration Logic consolidation, board integeatin, replace absolute vices, simple state machines, comple contrlleesfinterface. Ata fo Logesing Ses, "Gnade for Engnering Sens3, €ot8 Wha lor panning? Extn 4 ys, was “ans. +« Foogplanng is an essential design step for hirarchicay tpullding module design methodology on tearlaming i the process of placing Blockshmacos in the Supreoe arthereby determining the routing areas Between them, «+ Foorplanning provides ealy feedback that evaluates architectura, Soper ap am andi hy ag estimates ¢hif congestion caused BY ‘wing As technology advances, design Comply is increasing and the creuit size is getting larger 1 Two popular approaches to loorplanning are: 1. Simulated annealing and 2. Analytical formulation +4 good foorplanring should mest the following constraints 1 Minimize the total chip area, 2 Make routing phase easy (outable) 5 Improve the performance by reducing signal delays Foorlanning Functions + Florpanning includes following functions 1, Define the sizeof your chp/lock and aspect rato, 2 Detinng the core area and 1O core spacing, 3, Defining ports specified by tp level engineer 4 Design a floor plan and power network with horizontal metal layer such thatthe total IR drop must be less than 5 % of VDD to operate within the power budget 5:10 placement pacetea 6, Alloctes power routing resources. 7. Place the hard macros (fyline analysis) and reserve space for standard calls, (Refer rules for placing hard macros). 8. Defining placement and routing blockages 9 If we have multi height cells in the reference library separate Ficement rows have to be provided for two different unit = ‘ide for Engincering Ser VLSI Design and Technology 3-24 PLD Architectures and Applications 10. Creating VO rings. 11, Creating the pad ring forthe chp. 12. Creating VO pin rings for blocks Floorplanning Concepts 1. Abutment : Establishing connections between cells by putting them direcly next to each other, without the necessity of routing. 2 Leaf cell: A cell atthe lowest evel of the hierarchy; it does not contain any other cell ‘Composite cell: A cell that is composed of either leaf cells or composite ces. The whole chip is the highest-evel composite cell 4. Resttiction : All leaf cells and composite cells are supposed to be rectangular. Floorplanning control parameters ‘+ Floorplanning control parameters are aspect ratio and core utilization. « Aspect ratio and core utlization are defined as follows Aspect Ratio = Horizontal Routing Resources / Vertical Routing Resources Core Utilization = Standard Cell Area / (Row Area + Channel Area) Floorplanning Model ‘+ Hloorplans can be classified into two categories 1) Slicing floorplans 2) Non-sicing floorplans. #4 slicing Aoorplan can be obtained by repetitively cutting the ‘lorplan horizontally or vertically, whereas a nos-slicing floorplan cannot. The given dimension of each hard module must be kept. All modules are free of rotation; if a module is rotated, its width and height are exchanged. * Slicing floorplans can be represented by a slicing tee. END. “A Gude for Exner SudensFores | Digital Cc JL [sme a4 Eaplain MOS structure with the help of energy band diagram of prpe acon substrate. ‘onside a simple two terminal MOS structure having three an ners 8 1 Metal gt electrode layer. 2. Insulating oxide (SiO,) layer. '3 Pype bulk semiconductor (Si) oF substrate. « under eullrum the mobile cris in semiconductor obeys the mass actin a. ape at where » represents electron concentration p represents hole concetaton represents inns cazier concentration of silicon (1.45x10" em? at T = 300 K) fetes Fig. Q.1.1 Two terminal MOS structure eee an ~~ VES! Desig aud Techuology ‘©The equiblbrium electron and hole concentrations in P-type substrate are approximated by = ye # XE Ppo = Na where, Ny represents acceptor concentration typically 10'° to 10! cm”. «The energy band diagram of pAype substrate i shown in Fig. Q12. «For silicon the band gap between conduction band and valance band is approximately 1.1 eV. The equilibrium Fermi level Ey within the band gap is determined ty doping type and concentration in silicon substrate. The Fermi potential oy is given by equation - Ep te = For ptype semiconductor Kr), ML where, k is Boltzmann constant 4 unit charge on electron Vjq) between gate and source will give rise to the formation of p-type channel between the source and drain terminal, ‘If the drain is made negative with respect to source current can flow through channel. Here the current is carried by holes rather than electrons. ‘©The hole mobility (i.,) compared to electron mobility (H,) is about 25 times less, Therefore, pMOS devices are inherentiy slower than MOS. Tut fo EngieringSadensDigit CMOS Chey —~ pMos ss) AMOS No. ] device is slower than 1 | The mobility of electrons rie (carers in n-channel device is | wo times greater than Roles | (Carrs of pMOSY thas MOS || device is faster than device i _ ‘igh sac power dissipation. _| Low static power dissipation T GMOS is used for pulldown | pMOS i used for pullup eae network “| Fabinon proses is short and | Large steps of fabrication is ay. requited. | nMOS devices have low nase | pMOS devices show high noise — fnmurity. 2 Lit advantages and dandvantages of CMOS. ‘Ana: Advantage of CMOS : 1. Low power dissipation 2 High packing density 3. Bidirectional capabty 4 Low input impedance 5. Low delay senstvity to oad Disadvantages of CMOS : 1, CMOS devices ote lack the current drive capability. 2 More noise is generated compared to BJTs. CMOS has an advantage in its law level at shot noise but its 1/F noise is 3 Mich in GMCS devs see hgh Ths aft he ‘reliability of the system, indi SS — A Gude for Engineering Sets VISIDesign and Technology 4 8 Digital CMOS Cteits QS Desive the expression fr Ing In non-saluated region for nMOS transistor. = a Ama When device is operated in non-sturtedrepon, the IR drop in the channel is same thoughout the channel and can be tke as average vate a whee Vos 18 voltage difference between gate and channel assuming substrate connected to channel + In norvsaturated region, the effective gate voltage V, is given by - Vg = Vos-Vy 0 where, Veis threshold voltage needed to invert the charge under the {gate and to establish the channel «The charge gets induced into the channel due to gate voltage and if , is the average electric field from gate to chanel ‘The charge per unit area = Ey inp ° where, fing is relative permitivty of insulation between gate and ‘channel (=4for silicon oxide) £0 is permitivity of free space (885%10" F/ em) ‘The total induced charge forthe area of WL is given by, = Byte 0 Now, [-vo-"] B= 5 ~ 4) whe, Dis ove hiresDigital CMOS Citey rasmus ot a « Pating the expression M ce UWE | 6 Drain current can be expressed 38 Vos . extol Ww Wives“) ‘bs 6 sine M des te pomtiy of te deve end cn te combined with factor Kt give w Bek Bl Vos ~VelVs 6 ‘The capacitance formed by gate and channel has a parallel plate geometry. + Saat ra 0) Then in terms of Cy oy K= WC ay ve 8S bos = AO [vv e A Gade for Engineering Soden. VLSI Design and Technology 4-0 Digital CMOS Cireits «Gate capactance per uni are Go Cis defined as Gs ee Therefore Ips can be written as - |= Gut [tt « 8 Derive the expression for Ios in saturated reglon for nMOS sransistor. Ans.:+ The device enters into saturation when Ves=Vos-V,. because at this point the IR drop in the channel equals the effective gate to channel voltage. The current through the channel remains fairly constant for any further increase in Vp, a (2) 8) o ‘* The expression for Ips hold for both, the depletion and enhancement mode devices. However, the threshold voltage for ‘nMOS depletion mode device is negative and denoted by Vy. ‘Typical characteristics nMOS transistors are shown in Fig, Q61 MOS transistor characteristics are similar with suitable reversal of polarity. 1 Gu for Enginering SuesGe Digital CMOS Citeuig st Desig and Technol ° 05¥p0 Yoo Saturation (Vos? Vos) os #050 ‘ ° 05%e9 oo (b) Enhancement mode device Fig. 06.1 « Following expression summarizes current in three regions. Vcg Vayar Saturation. (A Ge for Englceing Ser LSI Design and Technology 2 Digital CMOS Ciresits 4.3 : MOSFET Parasitic Q7 Draw ac equivalent circuit of MOSFET & explain various capacitances involved. 1 SPP: May 16, Marks 9] ‘Ans. : MOSFET equivalent circuit : Fig. 74 Capacitance Model : + There is inter-eletrode capacitance between the terminals of MOS. The capacitances are nonlinear and dependent on voltage. These capacitances can be approximated as simple capacitance models. The models are used for estimating delay and power consumption of transistors + Different MOS capacitance sels are - 1. Simple MOS capacitance models. 2. Detailed MOS gate capacitance model. 3, Detailed MOS diffusion capacitance model 1. Simple MOS Capacitance Model : + The gate terminal of MOS transistor offers a considerable capacitance also its capacitance is necessary to attract charge to invert the channel. A high gate ‘capacitance is desirable to obtain high log ‘The gate capacitance is a parallel plate capacitance with a gate on top and channel on bottom and thin oxide dielectric is between the plates. The gate capacitance is given as - C= GWE ‘© The parasitic capacitance arise from reverse bised p-n junction and are called as diffusion capacitance. The size of these junction are dependent on - ess “A Gale for Enniseee “ Digital CMOS Cireit, nd Tecnois¥ oe paar an in afsion Area and perimeter of 8 + The depth of difsion = The doping levels = Voltage applied : + Various parasitic Seas ce ‘represents gate 10 sou Sy ca cc epee att ran capac Cay represents source to substrate capacitance yay represents drain to subse capac «Fig. Q72 shows these capactances 18 nt Cy and Cy mt now 38 junction oF diffusion capacitance ~Substote arses from the depletion charge between the source and oppositely doped substrate. Similarly, between drain and Cw substrate The Fig. 072 capacitance varies with source or drain voltage. «The total capacitance seen from gate terminal of CMOS transistor Gye Cee + Gp + Cys 2. Detailed MOS Gate Capacitance Model : + The MOS gate sits above the channel overlapping, the source and drain diffusion sareas. Hence gate capacitance has two components i) Intvinsic capacitance (over the channel) i) Overlap capacitance (to the souree, drain and body). +The intrinsic capacitance is approximated as simple parallel plate capacitance and overlap (bottom plate) capacitance depends on ‘mode of operation (cutof linear and saturation) of transistor. = ees “ile for Enghering des ‘VLSI Design and Technology ‘ 4 Digital CMOS Cireits 4. Cutoff: + When transistor is OFF ie, Vos = 0, the charge on the gate is matched with opposite charge from the body (as channel is not inverted), this is called gate-to-body capacitance (C,). When Ves is below threshold, a depletion region forms at the surface. Because of this bottom plate moves downward from oxide and reduces the capacitance 2, Linear: + When Ves > V;, the channel inverts and agun serves as a good conductive bottom plate. But the chanel i connected to the source and drain rather than he body. Fr lw vate ofthe cel charge is shared between source sin dain Se. Cy, = Cys = SP. When Vo. is increased, the region near drain becomes less inverted, therefore more faction of capacitance is attributed to source compared to drain 3, Saturation : + When Vps> (Vox ~ W),the transistor saturates and channel pinches off. All capacitance is attributed to source. Due to pinch of, capacitance reduces 10 Cy, = 2Cy ‘The intrinsic MOS gate capacitances in these three regions are summarized in Table Q7.1 ‘Parameter | Cut-off region) Linear. ‘Saturation & co 0 0 . 0 Co x e | % % Ge 7 oi 0 [ ft 2 GGG |G G . Table 74 Intrinsic MOS gate capacitance Overtap capacitance : + The gate overlaps the source and drain partially. This causes added overlap capacitance and is proportional to the width of transistor. Fig. Q73 shows this overlap capacitance The overlap capacitance becomes relatively more important for shorter channel transistor. The effective gate capacitance vat Gul or Egiewring SuesPiel MOS Cy, nse — ast Design sed Te and source. The 5 of drain ret 7 7 wotage. For delay calculation, ted by following ex can be approxima Pretin py fas units of capactanclaes at Cpe has writs of capacianceflength 1s Since the depletion region thickness depends on reverse bias, parasitics are nonlinear, My Gon 1) where, is junction capacitance at zer0 bias. Mis junction grading coefficient between (0.5 to 033) vo is builtin potential Vo = vpn 2 where, (ermal voltage) «E25 mV at room temperate) Na/No are doping levels of body and source ditfusion region. ris intrinsic carer concentration in undoped slcon- (usually 145 x 10* fom? at 300 4) «The sidewall capacitance term is of a similar form but uses different coefficients. ae (ra¥e Some * Cin) -@) Considering. all the facts on MOS transistor can be viewed as a fourterminal device with ‘capacitances between each Fig, @.7.5 Capacitances of MOS ‘wansistor Fé. 7, Diftusion region geometry 5 terminal pair as shown in Aree AS = W vee PS = 2020 Bears Teal 28 Explain device ‘and thelr limitation on the ‘are parasitic capacitance is given by - performance of CMOS circuits 1 (SPP : Deeb, Marks 8) Ce + 7 AS Con * FS Chany Ans. : Refer Q7 A Gilde for Engineering Sens GOBES “A Ged for Engnerng Senspeer Ae Digital MOS Cia, ! — eigen Tel = Nonideal -V Effects 44e velcty stration ey ean ant vlaty md Dance SES {ag oso Hy, re ee ld Ey) PEWEED sou ag say eae “elocy rolls off due to carr sca cay saat of Yr A BE OF AEE VAIOGY very and eventually ect field is shown in Fig. O91 ay ass Ese a Fig. 9.4 Carter velocity versus electric field Ey is determined by expression, Vat 7H Bat For electrons = 6-10/108em / sec For holes sat * 4-81108 cm/sec This results in'Sturation field for nMOS transistors, VISE Design and Technology 18 Digital CMOS Circuits ‘elf transistor is completely velocity saturated ie. vag then saturation current expression is modified to - Ths = Co W(Ves-Ve) sat Here the drain current is quadratically dependent on voltage without velocity saturation and linearly dependent when fully velocity saturated. For moderate supply voltages, transistors operate in region where Velocity no longer increases linearly with field. Not completely saturated. «This behavior is approximated by c-power law model. «is called velocity modulation index determined by curve fitting measured LV data. The model is based on three parameters: c, BP, and P,. [ 0 — VosVsar Saturation where, BR a Vast = 3 (Vos - Vo) Vasa = Pe Wos-V? ‘The low-field mobility of holes is much lower than that of electrons, so pMOS transistors experience less velocity saturation than nMOS for given Vip, Therefore value of «is larger for 'PMOS than nMOS transistors, 2.40 What is body effect ? What are its impact on performance of (CMOS elreuit ?, [SPPU : Maya, marks 8) eco 4 Gude for Engineering Suen“8 Digel MOS Cie, vist Dignan Tene “CMOS devies are cons effec and its effet Os normaly equal ‘Ans. Bol oe ‘The substrate bias level equi onnen 5 : fe of subse iS er as easton comes Yea aig + Conse shown in Fig. 101 po Fig, 104 «The source to substrate voltage Vy as observed vertically upward O and Vjy2 # 0. It means that Vyg and Vagy_ are not te. Vay © same This vation of Vy ase variation in threshold voltages te. Vjp and Vy Since Vy > Vy therefore, Vip > Vi). This ‘variation of threshold voltage due to source to substrate voltage 's referred as body effec. In complex logic circuit body effect is signtcanly important The body effect (change in threshold voltage) is. because of ‘aration in depletion charge region under oxide as a result of VEST Design end Technology +0 Digital CMOS Citeits Fig. Q.10.2 n-channel MOSFET ——_——_—_——_ Va = Yn W285 + Vay ~ 261 where, yp is body effect coeficient depends on gate oxide thickness and substiate doping, : «Typical value for yy is in the range of 04 to 1.2. 11 Explain the following : Velocity saturation 1DBody effect L)Hot electron effect i) Channel length modulation 1 SPU: May, De-16,19, Marks 8] ‘Ans, 1) Velocity saturation : + Ideally carier drift velocity and hence current increases linearly with the lateral electric field (E,.) between source and drain. But in practice drift velocity rolls off ddue to carrier scattering and eventually saturates of vy. A plot of cartier velocity versus electric field is shown in Fig. Q.111 ‘Eis determined by expression, source substrate voltage as shown in Fig, Q.102 Yaar = Eat * Change in threshold voltage AV), is given by = et eee vg « IN Fa Z “ ; avy PNAES grup — Jom) orbes y= AB cm/sec = Auld for Engineering Sntens —— CREDRS. Ace ie ache eyi Digital 08 Cry, ast Desgean Tce t cara an ‘sea ran aI East se Esa Em Fig. 114 Carer velocity versus oleic flld ‘This results in saturation field for nlMOS transistors, uy 22x 10 Vl. ‘if transistor is completely velodty saturated Le. V = Vy then saturation curet expression i modified to ~ pg = Cy W(Ves-Vi)¥eat Here the drain current is quadratically dependent on voltage without velodty saturation and linearly dependent when fully Velocity saturated. - ‘For moderate supply voltages, transistors operate in region where . ~ Velocity no longer increases linearly with il. ~ Not completely saturate, * Ts behavior i approximated by ocpower law model. ais called Tog Maltin Inde deterined by curve tng measured ‘model is based on thre parameters; o, 6 Pe and A Gale forEngineting Stes 151 Design an Technology 2 Digital CMOS Cieuits é 0 Veg<¥, Cut-off y, Tos = {lust Go Vos Yaa Satoraton whee, Br i.) Fae * FE Wos-Wo Vast = Pe (Vos -V)? ‘©The low-field mobility of holes is much lower than that of electrons, so pMOS transistors experience less velocity saturation than nMOS for given Vop. Therefore value of a is larger for MOS than nMOS transistors. i) Body effect : Refer Q.10 I) Hot electron effect : + Hot Electron Effect is when a high lectric field intensity developed across the channel causes an avalanche of electronic charge to break the insulation barrier. As a result high speed electrons are directed towards the (floating) gate. «This is caused because the device dimensions have been scaled down, but power supply and the operating voltages have not scaled accordingly. This causes the increase of electrical field strength and the velocity of electrons + Electrons trapped in oxide change the threshold voltage, typically increasing the threshold of NMOS, decreasing the threshold of PMOs. The hotelectron phenomenon can lead to a long-term reliability problem. To keep the hot-arrier effect under control, specially ‘engineered drain and source regions are used to keep the electrical fields in bound |v) Channel length modulation : + For a transistor in saturation ideally Ip, is independent of Vos, this makes transistor a perfect current source A Ge for Eouinering SanDigital CMOS Cle, = son between dain and ody fom reverse bias PUTT “y nat increases with reverse seh gion effectively SHOMENS thy biased voltage: channel length to tag Esher cent incre, length res na Ing) ° Ys sa Fig, 1121-V characters (for nMOS) wth channel length modtion sin satuation regan sven by expression (Vos -V,)? Jog = BUBW a r¥%55) wher, 1. channel length modulation factor ‘As the channel length gets shorter, the effect of channel length ‘modulation becomes more significant. The 2 is inversely ‘Proportional to channel length. The channel length modulation ‘model is useful for conceptual understanding of device. ‘The channel length modulation is an is is an important parameter for svalog designer as it grety affects gain of amplifier. — A Galo Exgerig Sader VLSI Design and Technology 4m Digital CMOS Cireuits {212 Explain the following : 1) Chennel length modulation 10) Body effect. 1 SPP: Hay, Mars 4} ‘Ans. 14) Refer QU(iv) ii) Refer Q10 13 Write a note on MOS models. Ans, : Different MOS models are developed to predict more accurately the performance of MOS devices. sotto Fig, 13.4 Smal signal model for MOS transistor ‘The MOS transistor can be represented by simplified (Vg, = 0) small signal equivalent model an shown in Fig. Q.131 where, fm is transconductance Bas i8 output conductance. +The MOS transistor is modeled as voltage controlled current source (gj,) and the inter electrode capacitances. ‘The output conductance is expressed as - Bas * BU gs -Ve)-2 Vag] * The channel resistance is approximated by, i R, (linear) = BY, -V) 4 The trans-conductance is expressed as - aly, 8m 7 ay "el vg. = constant 1 Ghd forEngnering Stadetn near region niet) = Bas In sanaation region [45 : Technology Seal i 1? What are types ? Explain each in 44 Wat i techno sai rs faa hes 3) and explain any one type of scaling. oe say ome OE SSP: May, Mass 6] (OR Which lambds rules are used for CMOS layout ? Give its ‘Sigaificance. 1 (SPP: Dect, Maks 8] (OR What is technology scaling ? What are its effect ? 1 [SPP De-t78, Mars 6) Ans : VLSI fabrication proossses are being aimid at achieving scallz Ine widths and size (cheap area) for higher packing ders This scaling-down must also improve ccuit performance Sever indicators of micro drei technology ae, Count of gates on chip sizeof device 18) Power dissipation 5) Maximum frequency of operation %) Die size * Scaling improves the igure of merit by shrinking the dimensions of transistors and interconnection between themn. "7 eb bed den pty ey des of Stem res ofa parte whch i sbseuetyasiaed such thet the features resulting out ees Supported by the fabrication proces: ‘the value of lambda ae vale, of the design are technology used decide “Gite fr Ege ing Stade ISI Desi and Technology 426 Digital CMOS Cireits wie SS ee ‘Lambda is defined a5 the maximum distance by which a geometrical feature can stray from another feature with a suitable safety factor. Lambda is maximum misalignment of 2 feature from its intended position chip. «Defining Lambda makes design independent of process therefore chip can be sealed to any ratio that means today's design remain cuseble when line widths are reduced (ie. the value assigned to. js reduced) by advances in future technology. There are three models of scaling - 1. Constant field (constant E) scaling 2. Constant voltage (constant V) scaling 3, Lateral scaling, » Constant field scaling says that the charactoristics of devices can be maintained and the basic operational characteristics preserved if citical parameters of a device are scaled in accordance to a siven criteria «The scaled device is obtained by applying a dimensionless factor x to dimensions, device voltages concentration densities. ‘Tn constant voltage scaling, voltage Vpp is kept constant and the process is scaled. When device is scaled down by dimension + its current density increases by x? whereas gate shrink increases the current density by x? ‘In lateral scaling only gate length is scaled called gate shrink Lateral scaling is easy to implement, The package density increases many fold. Two scaling factors 1/< and 1/@ are used in Fig. Q161 in order to cater fr all the three scaling models. “A Gn for Engng SeDig CMOS Cie, Vist Design and Technology 151 Design and Teco _ Fig, 0144 045 Explain merits and demerits of technology sealing. ‘Ans. : Moris: 1. creased chip density Le. more mumber of gate counts on single chip. Improved chip pesiormance ie. increased speed and reduced power consumption. 3. Improved devie characteristics, Reduced parasitic capacitance Reduced interconnect delays between devices. 6 Chip cs ees ose. Denes of eng 1 Ereoagh oveal power consumption rics but power trsunpion je ult ea Incense due To seling, Hoe evs ed op ng is operon 2 Beto eng dwn, carer moiy reduces wl ‘reduces gain of device. 7 — —— ‘cet —<—<$<——= ust Deigrand Technology 4-28 Digital CMOS Cireits 43. Reduced conductor size decreases current carrying cacy. 4 High package density increases heat generated which is to be dissipated by forced cooling, 4.6 + CMOS Inverters ‘9.16 Explain transfer characteristics of CMOS inverter. (OR Explain CMOS inverter and its transfer_characteritics In etal. How to achieve symmetry in the characteristics [PP M1, Dee, 18, Mts 8) ‘ans. In CMOS, both p and n-channel transistors are used. The dreut is fabricated on an n-type silicon substrate in which 2 piype ‘well or "hb" is crested by difusion. The mchanel transistors are created in the powell region. The p-channel devices are made in the nsubstate under an jon-implanted layer called the Frlaye. Similar to the depleton-mode implantation used for MOS. In this p-vell process, special ‘p-plugs" are used to connect the powell substrate and the source of the channel wansistor f0 gqound. Simlazly, an “plug” comes the r-ubstrate and the crave of the ptype transistor t0 Vpp, the postive supply voltage. «A schematic circuit representation ofthe CMOS invert i shown in Fig. Q164 alongwith its transfer characteristics. «The operation ofthe cteuit on an inverter can be explained a5 follows. All voltages aze referenced with respect t0 Vs: the ground potential. When the input vallage Vi zr, the gt of the phannel transistor i at Vpp blow the source potent is, oe Vpp. This tums on this transistor, feng valence patho load capactance C which wil be chars eb to Typ. No cuent flows though the channel ans ‘hich is tamed off since Vos =0 for this transistor. in