Accepted Manuscript

An improved approach for robust control of dynamic voltage restorer and

power quality enhancement using grasshopper optimization algorithm

Ahmed I. Omar, Shady H.E. Abdel Aleem, Essam E.A. El-Zahab,

Mostafa Algablawy, Ziad M. Ali

PII: S0019-0578(19)30210-1
DOI: https://doi.org/10.1016/j.isatra.2019.05.001
Reference: ISATRA 3196

To appear in: ISA Transactions

Received date : 12 January 2019

Revised date : 3 May 2019
Accepted date : 3 May 2019

Please cite this article as: A.I. Omar, S.H.E. Abdel Aleem, E.E.A. El-Zahab et al., An improved
approach for robust control of dynamic voltage restorer and power quality enhancement using
grasshopper optimization algorithm. ISA Transactions (2019),
https://doi.org/10.1016/j.isatra.2019.05.001

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*Title page showing Author Details

An Improved Approach for Robust Control of Dynamic Voltage

Restorer and Power Quality Enhancement Using Grasshopper
Optimization Algorithm

Ahmed I. Omar1*, Shady H. E. Abdel Aleem2, Essam E. A. El-Zahab3, and Mostafa Algablawy4,
and Ziad M. Ali5

1
Electrical Power and Machines, The Higher Institute of Engineering at El-Shorouk City, Cairo,
Egypt
2
15th of May Higher Institute of Engineering, Mathematical and Physical Sciences, Cairo,
Egypt
3
Electrical Power and Machines Engineering, Cairo University, Giza, Egypt
4
Pyramids Higher Institute for Engineering and Technology, Giza, Egypt
5
Electrical Engineering Department, College of Engineering at Wadi Addawaser, Prince Sattam
bin Abdulaziz University, Saudi Arabi, 11991. Electrical Engineering Department, Aswan
faculty of Engineering, Aswan University, Egypt, 81542 (On leave)
*
Correspondence author: Ahmed I. Omar (email: a.omar@sha.edu.eg)
*Highlights (for review)

Highlights
 We present a low complexity voltage control scheme for effective control of a dynamic
voltage restorer
 The control scheme utilizes an error-driven PID controller
 The scheme maintains the load voltage close to or equal to the nominal value in terms of
various voltage disturbances
 A fractional order PID controller and active disturbance rejection controllers are
presented and compared with the proposed controller
 The performance of the optimal PID using grasshopper optimization algorithm
outperforms the performance of the other controllers
*Blinded Manuscript - without Author Details
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An Improved Approach for Robust Control of Dynamic Voltage Restorer and

Power Quality Enhancement Using Grasshopper Optimization Algorithm

Abstract—This paper presents a novel contribution of a low complexity control scheme for voltage control
of a dynamic voltage restorer (DVR). The scheme proposed utilizes an error-driven proportional-integral-
derivative (PID) controller to guarantee better power quality performance in terms of voltage enhancement
and stabilization of the buses, energy efficient utilization, and harmonic distortion reduction in a distribution
network. This method maintains the load voltage close to or equal to the nominal value in terms of various
voltage disturbances such as balanced and unbalanced sag/swell, voltage imbalance, notching, different fault
conditions as well as power system harmonic distortion. A grasshopper optimization algorithm (GOA) is
used to tune the gain values of the PID controller. In order to validate the effectiveness of the proposed DVR
controller, first, a fractional order PID controller was presented and compared with the proposed one.
Further, a comparative performance evaluation of four optimization techniques, namely Cuckoo search
(CSA), GOA, Flower pollination (FBA), and Grey wolf optimizer (GWO), is presented to compare between
the PID and FOPID performance in terms of fault conditions in order to achieve a global minimum error and
fast dynamic response of the proposed controller. Second, a comparative analysis of simulation results
obtained using the proposed controller and those obtained using an active disturbance rejection controller
(ADRC) is presented, and it was found that the performance of the optimal PID is better than the
performance of the conventional ADRC. Finally, the effectiveness of the presented DVR with the controller
proposed has been assessed by time-domain simulations in the MATLAB/Simulink platform.

Keywords: Disturbance rejection; dynamic voltage restorer; PID controller; FOPID controller; power
quality; harmonic distortion; stochastic optimization.
List of abbreviations

ADRC Active disturbance rejection controller

ALO Ant-lion optimizer
ANN An artificial neural network
CBEMA Computer and Business Equipment Manufacturers Association
CSA Cuckoo search algorithm
D-FACTS Distributed flexible AC transmission systems
DVR Dynamic voltage restorer
ES Energy storage
EVS Voltage sag energy
FACTS Flexible AC transmission systems
FBA Flower pollination algorithm
FOPID Fractional order proportional integral derivative
FRT Fault ride-through
GA Genetic algorithm
GOA Grasshopper optimization algorithm
GWO Grey wolf optimization
IGBT Insulated gate bipolar transistor
IM Induction motor
ITAE Integral time absolute error
KVL Kirchhoff's voltage law
MOSFET Metal oxide semiconductor field effect transistor
MVO Multi verse optimization
PID Proportional integral derivative
PLL Phase-locked loop
PQ Power quality
PSO Particle swarm optimization
PWM Pulse width modulation
QN Quasi Newton
SS Detroit Edison sag score
THD Total harmonic distortion
VSI Voltage source inverter
VSLEI Voltage sag lost energy index

Nomenclature
Cs Series capacitor of the DVR
Transfer function for the fractional order PID controller
, Maximum and minimum numbers of decreasing factor
Unit vector between the two grasshoppers
et1 Signal error of the DVR
A unity vector in the direction of the center of the earth
A unity vector towards the direction of the wind
An indicator for intensity of attraction
Gi Impact of gravity
g Gravitational constant
Ji Objective function of the ith error
Attractive length
Is Supply current in amperes
ISfault Supply fault current
I1, I2 Current flowing through feeders 1 and 2, respectively
Kp, Ki, Kd Proportional, integral and derivative gains of the DVR
k Constant drift
L Maximum number of iterations
Lower bounds in mth dimension
λ Fractional power of integral control
µ Fractional power of differential control
N Number of grasshoppers
Rs Series resistance of the DVR
Si Social factor of grasshopper
Upper bounds in mth dimension
Vc1(t) Control signals of the PWM for the DVR
VD Injected voltage in volts
VPre-sag Pre-sag voltage in volts
Vref Reference voltage in volts
VSag Voltage during sag in volts
Vs, VL AC voltage at buses “s” and “L”, respectively
Wi Wind horizontal impact
grasshopper position
ZL1, ZL2 Load impedances at feeder 1 and 2, respectively
Ztot Magnitude of total feeder reactance
 1. Introduction
Due to the growth of electronic equipment and nonlinear loads in the distribution network, several impacts
are emerging that change the electrical waveforms. To overcome these circumstances, it is essential to meet
the power demand needs and also to enhance power quality (PQ) performance in distribution systems. PQ has
a key role in feeding the loads in the case of uninterrupted power supply services. There are various PQ
problems that can manifest in numerous aspects like voltage sag/swell, harmonics, interruption, etc. [1], [2]. In
this regard, voltage sag and swell are the most common PQ issues in distribution systems. In the literature,
voltage sag (either amplitude or phase) is a decrement in the rms voltage value in between 10% to 90% of the
nominal voltage at fundamental frequency for half a cycle to one minute [3]. One of the reasons of voltage sag
is the start-up of large-power motors like elevators, pumps, and air conditioning devices. Voltage swell is the
rise in rms voltage value in between 110% to 180% of the nominal voltage at fundamental frequency for half a
cycle to one minute. It normally happens with a switching of the large capacitive load. In general, sags and
swells of voltage are counted as disturbances but not interruptions or failures [4]. As a result of voltage sag
and swell, there may be an unexpected drop-out of relays, malfunction of the adjustable speed drive,
maloperation on drives power converters and failure of other sensitive electronic devices [5].

In the literature, different intelligent control schemes for dynamic voltage restorers (DVR) have been
presented in many studies of electrical power systems. The topologies of the DVR have been applied as an
active series filter in order to enhance voltage stability, mitigate harmonics, compensate any reactive power
shortage, and promote energy sustainability. Due to load voltage excursion, a DVR was utilized to enhance
these voltage drifts [6]. In order to enhance the voltage correction for different types of sag, a DVR was
presented and simulated in [7]. For enhancing most PQ disturbances, a new control technique of coupling
proportional and sequence-decouple resonant controllers was presented in [8]. In addition, a DVR was
equipped with a grid-tied transformer for limiting fault currents [9]. A grid-connected with a photovoltaic
interface was introduced in [10], for enhancing the PQ problems in distribution networks under
symmetrical/asymmetrical grid faults and voltage sags using a self-supported DVR scheme. In [11], a hybrid
intelligent control strategy was utilized with a DVR to improve the fault ride-through (FRT) capability of a
wind system. In [12], a DVR scheme controlled by an artificial neural network (ANN) with ant-lion
optimization technique was presented to improve voltage drifts with nonlinear loads connected. Also, a fuzzy
logic-based DVR was utilized with a PI controller for compensation of voltage sag/swell in [13]. In [14], in
the case of unbalanced, swell and sag voltage modes of the grid, an optimization technique with a PI controller
was equipped with the DVR control scheme for PQ improvement. Anti-parallel electronic switches were
applied to compensate voltage fluctuations with limiting capability of fault current in [15]. A Quasi-Newton
(QN) filter provided by PI control strategy was introduced to the DVR scheme to estimate fundamental
frequency, mitigate harmonics, and enhance voltage disturbances in [16]. In [17], the DVR was controlled
using an optimized sliding mode control strategy to keep the voltage within the allowable limits, exhibits fast
response and mitigate harmonic distortion. A dual P-Q theory with energy optimized technique was presented
in [18] to compensate voltage, control of power flow and mitigate harmonics. The performance of several
distributed FACTS devices was comparatively evaluated in a particular case study in [19] and it was revealed
that the dynamic responses are better with the existence of a PI controller that has optimized controller gains
using evolutionary metaheuristic techniques [19]. Using DVR, there are many research works offered on
various power quality events with different control strategies. Table 1 summarizes the recent works on DVR
applications in terms of controller type and number, optimization technique used, studied power quality
issues, and findings.

One can see from Table 1 that the controller not only has many circuits such as sags/swells detector
circuit, positive/negative sequence analyzer circuits for current and voltage controllers but also, each
controller circuit has PI controller, which takes a long time to minimize the errors and enhance the voltage
drifts. Also, many of these works did not consider finding optimal controller gains using evolutionary
metaheuristic techniques although of their impact on the dynamic response of the controller. As well,
effectiveness of DVR with a fractional order PID or active disturbance rejection controller is not investigated
in these works. In addition, the results are not sufficient to address most of the common power quality issues.
Accordingly, in this study, a new contribution of a DVR control scheme is endorsed as a low-cost dynamic
voltage stabilization scheme, providing low complexity with a fast-dynamic response for enhanced
power/energy utilization with better power quality performance in terms of harmonics reduction and voltage
stabilization. The dynamic control strategy is proposed using an error-driven proportional-integral-derivative
(PID) controller to control the compensator. Also, a fractional order PID (FOPID) controller is presented and
compared with the proposed method to reflect the effectiveness of the introduced DVR controller scheme.
Further, a comparative performance evaluation of the four optimization strategies, Cuckoo search (CSA),
Flower pollination (FBA), Grasshopper optimization algorithm (GOA), and Grey wolf optimizer (GWO)
techniques, was implemented between the PID and FOPID in terms of fault conditions in order to get the
global minimum error and a fast-dynamic response of the proposed control method. Further, a comparative
analysis between the results obtained using the proposed controller and those obtained using an active
disturbance rejection controller (ADRC) is presented. The DVR with the proposed controller has been
assessed by time-domain simulations in the MATLAB/Simulink platform.
 Table 1
Summary of the reviewed DVR research works and applications
Controller Optimal design
Power quality issues*
Ref. Year Comparative ADRC Comments
Type Number Technique
analysis
1 2 3 4 5 6 7 8 9 10 11 12
 Two PID controllers were used without using any
✗ ✗ ✗ ✗ ✗ ✗ ✗ ✓ ✓ ✓ ✗ ✗ ✗ ✗ ✗  Few power quality issues were investigated.
optimization techniques
[7] 2015 PI 2
 No comparative analysis.
 Two PID controllers with 18 IGBT switches and 2
PWM generators used to drive VSI, which have
[10] 2015 PI 2 ✗ ✗ ✗ ✓ ✗ ✓ ✗ ✓ ✗ ✗ ✗ ✗ ✗ ✗ ✗ high switching losses and long response time.
 No optimization technique was used.
 Few power quality issues were investigated.
 Optimization technique was not clarified.
✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗
 No comparative analysis with other techniques was
✓ ✓ ✓
Sliding Not
[17] 2016 1
mode clarified introduced to verify results.
 Most of the PQ issues were not investigated.
 Three PID controllers with 6 gains designed
[6] 2017 PI 3 ✗ ✗ ✗ ✓ ✓ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ without any optimization technique.
 Only two power quality issues were investigated.
 The DVR controller was obtained from AC/DC
✗ ✗ ✗ ✓ ✓ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗
converter without any isolation between AC and
[9] 2017 PI 1
DC systems.
 No optimization technique was used.
 No comparative analysis.
✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗
 It took long time to get minimum value of the
[13] 2017 PI 1 Fuzzy ✗ ✗ ✓ ✓
global error.
 Only two power quality issues were investigated.
 The controller used is so complicated due to it has
more circuits such as +ve, -ve and zero sequence
[8] 2018 PI 2 ✗ ✗ ✗ ✓ ✓ ✓ ✓ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✓ analyzers circuits.
 It takes long time to detect the fault and to respond
 No optimization techniques used.
 Complicated controller due to use of modified
✗ ✓ ✓ ✗ ✗ ✗ ✗ ✗ ✓ ✗ ✗ ✗ ✗
enhanced phase locked loop.
[14] 2018 PI 2 PSO AGPSO
 Most of the PQ issues were not investigated.
 No comparative analysis.
 Table 1 (Continued)
Summary of the reviewed DVR research works and applications
Controller Optimal design
Power quality issues*
Ref. Year Comparative ADRC Comments
Type Number Technique
analysis 1 2 3 4 5 6 7 8 9 10 11 12
 Two ANN were employed with GA, which
✗ ✗ ✓ ✓ ✓ ✓ ✓ ✗ ✗ ✗ ✗ ✗ ✗ ✓
ANN- took long time for learning and training
[11] 2018 2 GA
based process.
 No comparative analysis.
 Optimization technique was not clarified.
✗ ✗ ✓ ✓ ✓ ✓ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✓
P-Q Not
[18] 2018 2
based clarified  No comparative analysis.
 No comparative analysis with other controller
✗ ✓ ✓ ✓ ✓ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗  Most of the PQ issues are not investigated.
ANN- to verify results.
[12] 2019 1 ALO PSO
based
 Comparative analysis with PSO.
 No optimization technique used.
[15] 2019 PI 1 ✗ ✗ ✗ ✓ ✗ ✗ ✗ ✓ ✗ ✗ ✗ ✗ ✗ ✗ ✗  No comparative analysis.
 Few power quality issues are investigated.
 Few power quality issues were investigated.
[16] 2019 QN-PI 1 MVO ✗ ✗ ✓ ✗ ✗ ✗ ✗ ✗ ✗ ✓ ✗ ✗ ✗ ✓
 No comparative analysis.
 The controller circuit has very simple
configuration because of using only one PID
controller.
 Fast dynamic response.
 Comparative analysis between the proposed
PID controller with two other controller such as
fractional order PID and active disturbance
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
GWO, CSA
Proposed PID 1 GOA rejection controllers.
and FBA
 Four Optimization Techniques are compared to
verify results.
 Most of PQ issues are investigated to ensure
the proposed controller scheme.
 It has a low-cost control method of DVR
because the structure diagram of the controller
has only one control loop system.
*
1 denotes balanced sag, 2 denotes balanced swell, 3 denotes unbalanced sag, 4 denotes unbalanced swell, 5 denotes three phase short circuit, 6 denotes double line to
ground fault, 7 denotes single line to ground fault, 8 denotes voltage imbalance, 9 denotes voltage notching, 10 denotes impulsive transient, 11 denotes oscillatory
transient, and 12 denotes harmonics.
 The rest of the paper is prepared as follows: The system under study and models of its components are
presented and discussed in Section 2. In Section 3, details of the compensator proposed and its operating
principle are introduced. Further, design procedure of the proposed PID controller and modeling of the DVR
are presented and discussed in Section 4. Formulation of the optimization problem, the fitness function, and
detailed procedure of the optimization technique algorithm are discussed in Section 5. Verification of the
performance of the presented method, built in offline time-domain simulations, and a comparative analysis of
the different controllers with the four optimization techniques are introduced and discussed in Section 6.
Further, a comparative analysis of the proposed PID controller and ADRC results is introduced and discussed.
Finally, conclusions and possible work extensions are given in Section 7.

2. Configuration of the system under study

Figure 1 depicts the sample study of a distribution system comprising a 66 kV, 50 Hz AC utility connected
in series with a three-phase three-winding transformer 66/22/22 kV, 10 MVA. There are two feeders
connected with the secondary windings of the transformer. The first feeder is connected through a feeder
length of 3 km and a two-winding transformer 22/0.38 kV, 500 kVA that feeds non-sensitive loads. The other
feeder is also connected through the feeder and a two-winding transformer 22/0.38 kV, 2 MVA that feeds
hybrid loads. The AC hybrid loads consist primarily of linear and nonlinear loads, then other industrial
loads/blocks are added to the main loads in order to study each case separately, including the induction motors
(IMs), lightning strokes, inserting high voltage capacitor banks, as well as the nonlinear load with pulse-
controlled three-phase rectifiers. All the numerical parameters of the system under study, illustrated in Table
2, are taken from [20], [21].

Fig. 1. Three-phase representation of the system under study

 Table 2
Detailed specification of the system components
Utility (AC grid) 66 kV, 50 Hz AC hybrid loads
Transformers Load 1 Linear load: 10 kVA, 0.8 lag power factor
T1 10 MVA, 66/22/22 kV Hybrid Nonlinear load: 50 kVA
T2 500 kVA, 22/0.38 kV Load 2 Resistive load: 5 kW
T3 2 MVA, 22/0.38 kV Nonlinear load Inductive load: 0.5 kVA
Feeder 1,2 Firing angle of AC-DC converter: 10 degrees
Feeder resistance 1Ω Load 3 Resistive load: 10 kW
Feeder inductance 5 mH Motor IM: 15 kW, 400 V, 1460 rpm
Non-sensitive load 0.5 kW, 0.5 kVAr HV capacitor 5 kVAr, 22 kV, 50 Hz

3. The proposed compensator

The presented DVR structure is inserted between the Vg bus and the load bus VL, and it operates
simultaneously as a PQ conditioner to enhance voltage, compensate reactive power and minimize harmonic
distortion. The proposed DVR, shown in Fig. 2, is constructed from a series capacitor (Cs) connected on the
AC side of the three single-phase boosting transformers. A series resistance (Rs) is equipped in series with a
capacitor bank to control the flow of power [22]. The detailed parameters of the DVR scheme are illustrated
in Table 3.

(a) (b)

Fig. 2. Functional model of the DVR scheme: (a) schematic diagram of DVR and (b) block diagram of the
filter circuit
 Table 3
Detailed specification of the DVR scheme
Part Value Part Value
VDC 7000V Filter shunt resistance 60 Ω
R 0.1 Ω Filter shunt capacitance 6 µF
f 50 Hz Filter series inductance 80 mH
Voltage source inverter 3 arms, 6 pulses Filter series resistance 0.1 Ω
Carrier frequency 5000 Hz Boosting transformer ratio 1:1

The proposed DVR, shown in Fig. 2, comprises the following components:

(i) Energy storage (ES) unit: Its main function is to supply the DVR with the desired real power
during compensation. It can be represented as a battery, or supercapacitors can be inserted as a
storage element which has a fast response [23].
(ii) Universal bridge unit: It is a power electronic device represented as a voltage source inverter
(VSI) which is utilized to convert voltage from the DC battery to AC for injecting the transformer
with the desired voltage magnitude, phase, and frequency.
(iii) Boosting transformer unit: It transfers the voltage from the universal bridge to the distribution
network which is required for compensation. The primary winding is connected in series with the
power system and the secondary winding is coupled with the universal bridge unit.
(iv) Harmonic filter: It consists of an RLC circuit in order to mitigate the harmonic distortion of the
generated waveform produced by VSI.
(v) Error-driven PID controller: It represents the supervisor for controlling the load voltage. In other
words, it takes the signal voltage of the load bus and compares it with the reference voltage for
driving the PID controller.
(vi) Bypass switch: It protects the DVR circuit during periods of high currents.

3.1 Operating principle of the proposed DVR

Figure 3(a) depicts a Thevenin circuit of the system under study denoted by its equivalent voltage source
VS and source impedance ZS [24]. It feeds two loads represented by their impedances ZL1 and ZL2 through
two feeders VF and Vg, where Ztot represents the feeder impedance. During normal operation, the pre-sag
voltage (VPre-sag) at the common bus and the line current (Is) are determined by applying Kirchhoff's voltage
law (KVL) for a typical DVR as presented in Eqs. (1) and (2):
(1)

(2)
 A high current (ISfault) passes through the first feeder when a fault occurs (F) on it. Hence, the voltage at
the common bus during sag (Vsag) will be given by Eqs. (3) and (4):
(3)

(4)

Therefore, the phasor diagram as clarified in Fig. 3(b) illustrates the injected voltage (VD) during the sag
condition. Both magnitude and angle of the injected voltage are determined by Eqs. (5) and (6):

(5)

(6)

It can be noted that the main task of the series compensation is to suppress a fraction of the line reactance
of the feeders for the sake of load voltage enhancement.

(a) (b)
Fig. 3. (a) Thevenin equivalent circuit of DVR scheme, (b) Phasor diagram of DVR principle of operation

3.2 Voltage sag indices

To assess the voltage quality of the system, three sag indices are employed to indicate the DVR
compensation capability. These indices should be easy to assess and be sensitive to any disturbance to give
precise evaluation of the system performance. These indices can be expressed as follows:
3.2.1 Voltage sag lost energy index (VSLEI):
This index expresses the lost energy through a sag condition [7] and is given by Eq. (7)

W=T (7)
where V is the per unit phase voltage, Vnom is the nominal voltage, and T is the time duration of the sag in
milliseconds. It can be noted that the factor α is derived from the power acceptability curve for computer
business equipment and is equal to 3.14 as per the CBEMA curve [8].
3.2.2 Detroit Edison sag score (SS):
The Detroit Edison sag score (SS) [7], given by Eq. (8), is defined as
SS = (8)

where VA, VB, and VC represent the rms phase voltages.

3.2.3 Voltage sag energy (EVS):
The voltage sag energy [7], given by Eq. (9), is defined as

EVS= dt (9)

where V(t) represents the magnitude of the voltage at time t and T is the time duration of the sag.
4. The proposed control scheme of the DVR
Generally, there are five steps for controlling the proposed DVR as given below.

1. The voltage disturbances that occur are detected in the system.

2. VL is compared with a reference voltage as shown in Fig. 4.
3. The controller is synchronized with the supply voltage.
4. The controller scheme is introduced.
5. The gate pulses are produced to drive the voltage source inverter (VSI) as an output of the DVR
voltages which absorbs in increasing voltage and compensates in decreasing voltage.

First step: The type of voltage disturbance has a very important role for detecting the duration time (start
and end points), depth and phase jump. Different methods utilized for detecting the voltage disturbances are
illustrated in [25]. In this study, the three-phase load voltages VL,abc and reference voltages Vref,abc are
transformed into vectorized dq0 voltage components VL,dq0 and Vref,dq0 by using Park transformation. The
reference voltage of the three phases is calculated as follows:

(10)

Then it is transformed from three-phase abc-to-dq0 components using Park transformation, which is given as
follows:
 (11)

Second step: After transforming the load voltage and reference voltage to the dq0 frame, they will be
compared to get the error signal et as a voltage magnitude and phase shift.

(12)

For any voltage disturbance in magnitude and phase shift, this will lead to a change in the dq0
components. The introduced control detects the change in the state of the supply with a fast response.

Third step: For sufficient control of the presented DVR, synchronization to the supply voltage is a
significant step as introduced in [26]. It maintains an output signal of the controller synchronized with a
reference input signal in frequency and phase alike. Hence, a phase-locked loop (PLL) is utilized in this work
as a synchronization tool.

Fourth step: The low complexity of the presented DVR control is based on an error-driven PID
controller. The function of the controller is to adjust error signal to be minimized on the distribution grid as
shown in Fig. 4. Further, in the time domain, Vc is the contribution signal in the dq0 frame of the PWM of the
DVR for the PID controller, given as follows:

(13)

Fifth step: Finally, the output of the PID controller comes back to the three-phase abc frame to control the
PWM for generating the gating pulses to drive the VSI, given as follows:

(14)

5. Formulation of the optimization problem

5.1 Fitness function
To fine-tune the proposed DVR-PID controllers’ gains (Kp, Ki and Kd), the fitness function, given by Eq.
(15), is defined as:
 (15)

where J is the total error of the controller of the proposed DVR and ITAE is the integral time absolute error.
The ITAE performance index is mathematically expressed as given in Eq. (16):

(16)

where represents the error signal between the reference and load voltages in the dq0 components. The
optimization problem is subject to the following constraints.

Fig. 4. Scheme of proposed control strategy

5.2 Constraints
 The voltage level at the second feeder is constrained between its minimum and maximum values,
given by Eq. (17), thus
(17)

 The THD of the voltage (THDv) of the second feeder, given by Eq. (18), should be below its
maximum value ( ) reported in IEEE Standard 519 [27], [28] thus

(18)

(19)
  The THD of the current (THDi), given by Eq. (20), should be below its maximum value ( )
reported in IEEE Standard 519 [27], [28] thus

(20)

(21)

5.3 Grasshopper optimization algorithm (GOA)

A lot of optimization algorithms have been inspired by the behavior of animals, birds, or insects, and this
algorithm has been inspired by the grasshopper. In this algorithm [29], [30], the author emulates grasshopper
behavior when searching for food. This process is divided into two main processes: diversification and
intensification. In diversification, the search agents make an unexpected motion (local search), whereas they
move locally during intensification (global search). The search for the target of those two functions can be
modeled as in Eq. (22), where there are many factors that influence the food searching process, such as
social interaction, gravity, and the horizontal impact of the wind.

(22)

where is the grasshopper position, denotes the social factor, denotes the impact of gravity, and
denotes the wind’s horizontal impact. Equation (23) is considered the randomized version of Eq. (22),
where, , , and are random factors and they are in the range of [0,1].
(23)

The social interaction can be described as in Eq. (24), where the function measures the intensity of social
interaction.
(24)

is the distance between two grasshoppers, the and , and is calculated as in Eq. (25), while is
the unit vector between the two grasshoppers, also illustrated in Eq. (25).

and (25)

The interactions between grasshoppers and the comfort zone is demonstrated in Eq. (26) using s.

(26)

where is considered as an indicator of the intensity of attraction, while measures the attractive length.
 Although the function s divides the space between two grasshoppers into a repulsion zone, comfort zone,
and attraction zone as shown in Fig. 5, s returns values close to zero with distances greater than 10. Thus,
this function cannot put on strong forces between grasshoppers with large distances between them. To
resolve this problem, the distance of the grasshoppers must be in the interval of [1,4].

Fig. 5. Behavior of grasshoppers

The G and W components in Eq. (27) are calculated as follows:
, (27)
where g denotes the gravitational constant, represents a unity vector towards the center of the earth, k
represents a constant drift, and is a unit vector towards the wind direction. Therefore, Eq. (28) expresses
the grasshopper position as follows:

(28)

where indicates the intensity function and N is the number of grasshoppers. The
position can be modified for the next iteration as illustrated in Eq. (29):

(29)

where represent the upper and lower bounds in the mth dimension respectively, is the m-
dimensional location of the best solution, and C is the decreasing coefficient, given by Eq. (30), to lessen the
comfort zone (repulsion and attraction zone) which is proportional to the number of iterations and can be
calculated as follows:
(30)

where are the maximum and minimum numbers, respectively. l is the current iteration. L is
the maximum number of iterations. In this work, they were taken as 1 and 0.00004 for
respectively.
 5.4 Implementation of GOA technique
The GOA is used to tune the controller gains to control DVR to guarantee better power quality
performance in terms of various voltage profile issues such as balanced and unbalanced sag/swell, voltage
imbalance, notching, different fault conditions as well as power system harmonic distortion mitigation. The
optimized controller maximizes the presence region of DVR and enhances the dynamic response due to the
value and effect of self-tuning PID controller in DVR performance, in which the dq0 components of VL are
compared with the Vref and the error signal enters the PID controller and hence the controller computes the
proportional, integral and derivative gains of this error signal. The selected gains minimize the error signal
to be stable and well responses to the different disturbances. Further, the outputs of the controller are
transformed into the Vabc frame to be forwarded to PWM generator. Hence, the fitness function is chosen to
enhance the overall performance by minimizing the error. For this purpose, detailed steps for obtaining the
optimal solution is shown in Fig. 6.

During the fault conditions, the error signal is occurred due to the disturbance, the VSI switched on after
completing the optimization loops and getting the optimal solution, hence the storage element will inject the
required voltage and phase angle after converting from DC to AC through VSI to the boosting transformer
to ensure better power quality performance in terms of voltage enhancement and stabilization of the buses,
energy efficient utilization, and harmonic distortion reduction in the system under study.

During the healthy condition, the error signal will be almost zero, the VSI will be switched off, and
hence the storage element will not inject any voltage through VSI to the boosting transformer.

The following GOA parameters are used for verifying the performance of the GOA–PID controllers in
searching for the PID controller gains and finding the global minimum error:
 (a)

(b)

Fig. 6. (a) Implementation of the proposed method, (b) Detailed search procedure
 Initialization
 The controller parameters are Kp, Ki, Kd;
 The maximum iteration (L)= 300;
 The search agents’ size (N)= 50;
 The lower boundary (lb)= 0;
 The upper boundary (ub)= 5;
 Number of variables (dim) = 3;
 The maximum and minimum numbers of the decreasing factor Cmax = 1; Cmin= 0.0004.
Calculate the objective function value from (ITAE) for each solution - value (J)
Get the best solution of controller parameters with minimum objective function
While (l < max. iteration) i.e. the main loop begins
Update the decreasing coefficient as given by Eq. (29)
for (j < search agent) i.e. to get the new solution of controller parameters
Get the normalized distance between grasshoppers
Update the position
j=j+1
end for loop
Replace the solution with the new one if the objective function is less than J
l=l+1
end

The proposed implementation of the GOA procedure for determining the controller parameters and finding
the global minimum error is illustrated in Fig. 7. For more information about GOA, readers may refer to
[30].
 Fig. 7. Proposed implementation of GOA procedure for determining controller parameter

The simulation model is tested in eleven modes of operation; balanced and unbalanced sag, balanced and
unbalanced swell, three types of fault conditions, imbalance, notching, and impulsive and oscillatory
transients. The detailed parameters of the optimized PID controllers’ gains are reported in Table 4.
Table 4
Optimal controller parameters of the PID using GOA technique
PI controller Computation Objective fn.
Operating conditions
Kp Ki Kd time (J)
Case I: Balanced voltage sag 3.2394 1.928 0.1662 83.474 1.623
Case II: Unbalanced voltage sag 3.4344 0.2640 1.9765 80.846 1.487
Case III: Balanced voltage swell 2.1433 1.8362 1.1854 81.011 1.668
Case IV: Unbalanced voltage swell 4.261 0.3357 1.1401 86.282 1.689
Case V: Three phase short circuit 1.3909 1.6157 1.3959 153.505 1.312
Case VI: Double line to ground fault 4.9931 0.4528 0.0704 205.134 1.335
Case VII: Single line to ground fault 3.9573 1.1788 0.5753 83.12 1.519
Case VIII: Voltage imbalance 3.1744 1.9788 1.5766 80.049 1.557
Case IX: Voltage notching 2.5437 0.6076 0.8431 82.323 1.736
Case X: Impulsive transient 2.544 0.0882 0.3235 83.584 0.07725
Case X: Oscillatory transient 3.3777 1.3025 1.6846 81.557 1.534
 6. Results and Discussion
6.1 Modeling and simulation
The presented DVR is investigated in the MATLAB/Simulink platform in terms of enhancing balanced
and unbalanced voltages sag and swell, and different fault circumstances, voltage notching, voltage imbalance
as well as transients’ conditions for the power system illustrated in Fig. 8.

Fig. 8. MATLAB simulation model of the system under study

Two criteria to test the control schemes are presented, namely different operation conditions and
harmonics analysis. The results are provided for the load side, where the simulations are provided with and
without the proposed DVR. In addition, using the best solution of the error-driven PID controllers’ gains from
the optimal DVR performance of the technique used is also compared. Ten cases of faults are simulated using
the MATLAB Simulink platform. These cases under study can be outlined as given below:
 6.1.1 Case I: Three-phase balanced voltage sag
A three-phase overload is applied at the time interval t=0.1 s and t=0.15 s. In addition, the starting of a
three-phase induction motor is applied at the time interval t=0.185 s and t=0.2 s. As a result of that, a balanced
voltage sag mode occurs. The voltage sag at the load point is almost 70% and 50% with respect to the
reference voltage, respectively. When the DVR is presented during this event, it is observed from Fig. 9 that
the DVR injects the necessary voltage on the three phases and then enhances the load voltage profile of the
system under study.

(a)

(b)

(c)
Fig. 9. Simulated results for case I: Sag mode by using DVR: (a) uncompensated load voltage in volts,
(b) compensated load voltage in volts, and (c) injected voltage in volts
 6.1.2 Case II: Unbalanced voltage sag

In this case, an overload occurs from 0.2 s to 0.3 s in phase A, and the voltage at VL bus is reduced to
70% and to 92% in phase B with respect to the reference voltage. It is noted that the DVR rapidly detects
this sag condition in different phases and injects the required magnitude and phase angle of voltage to keep
VL in balance. Figure 10 depicts the load voltage profile before and after compensation as well as the
necessary injected voltage.

(a)

(b)

(c)
Fig. 10. Simulated results for case II: Unbalanced sag mode by using DVR: (a) uncompensated load voltage
in volts, (b) compensated load voltage in volts, and (c) injected voltage in volts
 6.1.3 Case III: Three-phase balanced voltage swell

A swell mode occurs because different heavy loads are switched off in the three phases. Accordingly, for
this test, it was assumed that swell mode is applied at t=0.1 s to t=0.2 s. The voltage swell on the three phases
at the load point is almost 140% with respect to Vref. The simulation results illustrate the voltage profile at the
load voltage bus at the three phases during this event. Figure 11 depicts the load voltage before and after
compensation by using DVR.

(a)

(b)

(c)
Fig. 11. Simulated results for case III: Balanced swell mode by using DVR: (a) uncompensated load voltage
in volts, (b) compensated load voltage in volts, and (c) injected voltage in volts
 6.1.4 Case IV: Unbalanced voltage swell

In this case, an unbalanced voltage swell occurs from 0.2 s to 0.3 s in the system in phase A, and the
voltage at VL bus increases to 140%, to 115% in phase B and to 110% in phase C with respect to the
reference voltage, respectively. It can be observed that the DVR rapidly detects this case in the different
phases and injects the necessary magnitude and phase angle of voltage to keep VL in balance. Figure 12
depicts the load voltage profile before and after compensation as well as the necessary injected voltage.

(a)

(b)

(c)
Fig. 12. Simulated results for case IV: Unbalanced swell mode by using DVR: (a) uncompensated load
voltage in volts, (b) compensated load voltage in volts, and (c) injected voltage in volts
 6.1.5 Case V: Three-phase short circuit (TLG)
A three-phase short circuit is applied at first feeder voltage VF1 in the time interval from t=0.05 s to t= 0.18
s. The voltage during this event is equal in the three phases (balanced fault). Figure 13 depicts the voltage
profile at VL before and after compensation.

(a)

(b)

(c)

(d)
Fig. 13. Simulated results for case V: Three-phase short circuit using DVR: (a) faulty feeder voltage in
volts, (b) uncompensated load voltage in volts, (c) compensated load voltage in volts, and (d) injected
voltage in volts
 6.1.6 Case VI: Double line to ground fault (DLG)

A double line to ground fault (between phase A and B) occurs at the first feeder in the time interval from
t=0.1 s to t= 0.2 s. The DVR rapidly injects the required voltage during this fault condition. Figure 14 depicts
the voltage profile at VL before and after compensation as well as the injected voltage.

(a)

(b)

(c)

(d)
Fig. 14. Simulated results for case VI: Double line to ground fault using DVR: (a) faulty feeder in volts, (b)
uncompensated load voltage in volts, (c) compensated load voltage in volts, and (d) injected voltage in volts
 6.1.7 Case VII: Single line to ground fault (SLG)

A single line to ground fault (phase C is faulted) occurs at the first feeder in the time interval from t=0.05 s
to t= 0.18 s. The voltage during this event is equal in the three phases (balanced fault). Figure 15 depicts the
voltage profile at VL before and after compensation.

(a)

(b)

(c)

(d)
Fig. 15. Simulated results for case VII: Single line to ground fault using DVR: (a) faulty feeder in volts, (b)
uncompensated load voltage in volts, (c) compensated load voltage in volts, and (d) injected voltage in volts
 Table 5 presents the voltage sag indices calculation during different sag conditions. The voltage sag
indices calculation developed in MATLAB is made available by the author at Mathworks official MATLAB
central file exchange in [31].
Table 5
Voltage sag indices before and after compensation

Indices VSLEI SS EVS

Uncomp. Comp. Uncomp. Comp. Uncomp. Comp.

Fault type (pu) (pu) (pu) (pu) (pu) (pu)

Balanced voltage sag 3.4218 0.0019 0.7 0.9733 0.0135 1.1000×10-4

Unbalanced voltage sag 2.3171 0.0013 0.8733 0.9803 0.0096 1.1610×10-4
Three-phase short circuit 45.94 7.99×10-3 0.5 0.968 0.4047 0.40381
Double line to ground fault 17.2 3.22×10-4 235 307.7 0.3645 0.3398
Single line to ground fault 0.010026 2.1953×10-5 304.34 308.67 0.34115 0.33941

6.1.8 Case VIII: Voltage imbalance

In this case study, from 0.05 s to 0.185 s, an unbalanced voltage (the magnitudes of each phase are
different) occurs in the system, the voltage at VL in phase A decreases to 70%, to 50% in phase B and to
80% in phase C with respect to the reference voltage, respectively. It can be observed that the DVR rapidly
detects this case in different phases and injects the required phasor voltage to keep VL in balance.
According to IEC 61000-3-13 [32], the imbalance factor, given by Eq. (31), can be defined as the ratio
negative sequence (V-) voltage to the positive sequence voltage (V+). It must not exceed 2%.

(31)

In this case study, the imbalance factor before compensation is 13.23% and after compensation is
reduced to almost zero. Figure 16 depicts the load voltage profile before and after compensation as well as
the necessary injected voltage.
 (a)

(b)

(c)
Fig. 16. Simulated results for case VIII: Voltage imbalance using DVR: (a) uncompensated load voltage in
volts, (b) compensated load voltage in volts, and (c) injected voltage in volts

6.1.9 Case IX: Voltage notching

Notching is a periodic transient caused by the commutation process in power electronic converters. This
nonlinear load model is utilized to present voltage notches and harmonics investigated by a 6-pulse three-
phase rectifier. The nonlinear model comprises 5 kW resistive and 0.5 kVA inductive loads. To control the 6-
pulse rectifier, a PLL is utilized to synchronize the pulse generator for producing the necessary pulses. The
firing angle is set to 10 degrees to control the pulses width of the AC–DC converter. Voltage notches are
described by their depth and area at the point where the notches start.

According to IEEE Std. 519 [24], the limits on commutation notches are 20% of notch depth and 22800
volt-microsecond notch area in the general system. The presented DVR detects the notching periods and
injects the necessary magnitude and phase angle voltage at each phase where the voltage notching occurs. The
simulation results in Fig. 17 show that the load voltage profile is enhanced and the total harmonic distortion is
mitigated. The voltage notching calculation is made available by the author to confirm and download at
Mathworks official MATLAB central file exchange in [33].

(a)

(b)

(c)

(d)
Fig. 17. Simulated results for Case IX: Voltage notching: (a) uncompensated load voltage in volts, (b)
injected voltage in volts, (c) compensated load voltage in volts, and (d) 22 kV bus instantaneous waveform
 It can be noted that the voltage notches through each phase are clearly visible in the sinusoidal waveform
at the 0.38 kV bus as shown in Fig. 17(a), but the voltage notches significantly vanish after it propagates
upstream to the 22 kV bus through the transformer as shown in Fig. 17(d). Table 6 describes the commutation
notches, harmonic analysis and the load voltage and current of the system under study before and after
compensation.
Table 6
Notching and THD analysis before and after compensation
Notch depth Notch area THDv THDi Load voltage Load
(%) (V.µs) (%) (%) magnitude (V) current (A)

Uncompensated voltage 26.87 23.28 1.58 22.54 219.2 54.24

Compensated voltage 12.29 0.0827 0.708 10.78 219.4 18.64
.

6.1.10 Case X: Transients

Another PQ index when the magnitude of voltage is very large with nonpower frequency change for a
very short period of time is transients or spikes, and can be categorized into two impulsive and oscillatory
transients.

A lightning strike is the first event that introduces the type of impulsive transient shown in Fig. 19. This is
described in IEEE 1159 [34] as when the magnitude of the voltage suddenly rises or falls for a very short
period (fewer than 50 ns). The lightning model is investigated in MATLAB Simulink as shown in Fig. 18. The
load comprises 10 kW resistive and 10 kVAr inductive loads. At the time 0.05 s, the lightning strike is
produced and the proposed DVR detects and injects the required voltage.

The high voltage capacitor bank model developed in Simulink is the second event that presents the other
type of oscillatory voltage transient. The capacitor bank model is inserted on the 22kV transmission line, 5
kVAr, 50 Hz. At the time 0.05 s, the capacitor bank is energized through three-phase breakers at the 22kV
feeder line, which produces voltage transients at 0.38kV and 22kV. The presented DVR detects and also
injects the necessary voltage during this event.

6.1.11 Analysis of harmonic distortions

Total harmonic distortion (THD) is an important measure to quantify the level of harmonic distortion in
voltage or current waveforms [35]. Hence, THD values of the voltage and current at the source and load
buses, with the proposed DVR, are investigated.
 (a) (d)

(b) (e)

(c) (f)
Fig. 18. Simulated results for case X: Transients: (i) Impulsive transient (a) uncompensated load voltage in
volts, (b) injected voltage in volts, and (c) compensated load voltage in volts. (ii) Oscillatory transient (d)
uncompensated load voltage in volts, (e) injected voltage in volts, and (f) compensated load voltage in volts

Figure 19 depicts the measured THD of voltages and currents at the load bus VL before and after
compensation during some different operating conditions to verify the effectiveness of the proposed DVR
scheme. It is clearly seen that the THD of the voltage and current values are significantly reduced to be within
the allowable limits stated in IEEE 519 [27].
 (a) (b) (c) (d)

(e) (f) (g) (h)

(i) (j) (k) (l)

Fig. 19. FFT analysis of the voltages and currents at load bus: (a) THDv at VL without DVR during sag
mode, (b) THDv at VL with DVR during sag mode, (c) THDi without DVR during sag mode, (d) THDi
with DVR during sag mode, (e) THDv without DVR during swell mode, (f) THDv with DVR during
swell mode, (g) THDi without DVR during swell mode, (h) THDi with DVR during swell mode, (i) THDv
without DVR during imbalance mode, (j) THDv with DVR during imbalance mode, (k) THDi without
DVR during imbalance mode, (l) THDi with DVR during imbalance mode.
 6.2 Comparative performance evaluation of optimal PID with FOPID controller
FOPID is the integer order PID controller [36]. The FOPID controller is utilized for improving the
stability and robustness of the system. The transfer function CFOPID for the controller is represented by Eq.
(32):
(32)

where the FOPID controller variables are (Kp, Ki, Kd, λ and μ). The factors λ and μ denote the fractional power
of integral and differential control respectively. Further, in the time domain, Vc is the contribution signal
produced by the FOPID controller in the dq0 frame to the PWM of the DVR, given by Eq. (33), as follows:

(33)

For simulation operation, the facilities offered by the FOMCON available in the MATLAB package can
be used and the four optimization techniques are applied based on the minimization of the performance
index ITAE.
A comparative performance evaluation of the optimization strategies used, Cuckoo search (CSA) [37],
Flower pollination (FBA) [38], Grey wolf optimizer (GWO) [39], and GOA techniques, is implemented
between the PID and FOPID to reflect the performance of the proposed DVR scheme. Tables 7 to 9 show
the comparative analysis of the four algorithms in terms of fault conditions such as TLG, SLG, and DLG to
reflect the performance of the proposed scheme.
 Table 7
Comparative analysis of the PID controller with the FOPID during TLG by using different optimization techniques
Controller type PID FOPID
Optimization techniques CSA FBA GWO GOA CSA FBA GWO GOA
No. of iterations 300 300 300 300 300 300 300 300
No. of population 50 50 50 50 50 50 50 50
is linearly is linearly
decreased decreased
Cmax=1; Cmax=1;
Control parameters from 2 to 0 from 2 to 0,
Cmin=0.00004 Cmin=0.00004
r1& r2 r1& r2
rand in [0,1] rand in [0,1]
J (ITAE) 1.328 1.57 1.567 1.312* 5.388 63.64 3.159 6.77
Computation time (s) 394.403 174.349 158.564 153.505 58.313 22.995 87.761 120.695
Kp 0.7566 0.0500 2.1261 1.3909 4.584759 4.08477 2.5171 3.8856
Ki 2.8998 0.7237 1.9391 1.6157 2 1.53476 3.9161 4.561
Kd 0.3355 0.0500 0.0912 1.3959 0.517449 0.65003 0.44038 0.31623
λ NA** 1.668153 1.74496 1.6698 1.5803
μ NA 0.132331 0.29766 0.5104 0.55988
*
The value in bold face represents the best value achieved by the proposed algorithm
**
NA: Not applicable
 Table 8
Comparative analysis of the PID controller with the FOPID during DLG by using different optimization techniques

Controller type PID FOPID

Optimization techniques CSA FBA GWO GOA CSA FBA GWO GOA
No. of iterations 300 300 300 300 300 300 300 300
No. of population 50 50 50 50 50 50 50 50
is linearly is linearly
decreased decreased
; Cmax=1; Cmax=1;
Control parameters from 2 to 0 from 2 to 0
Cmin=0.00004 Cmin=0.00004
r1& r2 r1& r2
rand in [0,1] rand in [0,1]
J (ITAE) 1.667 1.69 1.392 1.335 4.485 53.87 84.92 44.49
Computation time (s) 130.161 209.86 207.397 205.134 62.352 35.086 88.171 124.545
Kp 3.604885 0.4898 4.2499 4.9931 3.852802 3.3778 4.1032 4.5866
Ki 1.338188 1.223 2.4161 0.45287 2.641333 2 2.679 2
Kd 2.817189 1.6609 0.31686 0.070466 0.534244 0.5489 0.30023 0.33465
λ NA 1.380642 1.4311 1.2032 1.0339
μ NA 0.127785 0.3048 0.36912 0.29532
 Table 9
Comparative analysis of the PID controller with the FOPID during SLG by using different optimization techniques

Controller type PID FOPID

Optimization techniques CSA FBA GWO GOA CSA FBA GWO GOA
No. of iterations 300 300 300 300 300 300 300 300
No. of population 50 50 50 50 50 50 50 50
is linearly is linearly
decreased decreased
; Cmax=1; Cmax=1;
Control parameters from 2 to 0 from 2 to 0
Cmin=0.00004 Cmin=0.00004
r1& r2 r1& r2
rand in [0,1] rand in [0,1]
J (ITAE) 1.695 1.634 1.687 1.519 5.699 103 51.6 19.7
Computation time (s) 463.999 71.12 158.231 83.12 174.678 24.323 100.77 127.805
Kp 0.279418 1.252896 0.18236 3.9573 2.073489 3.00988 4.3584 3.7425
Ki 1.336834 0.950109 0.86781 1.1788 2.537421 3.33505 2.2923 2.3444
Kd 3.7536 0.05 4.8355 0.57532 0.684986 0.48601 0.45652 0.71705
λ NA 1.357246 1.66987 1.3688 1.0023
μ NA 0.497719 0.39779 0.64604 0.39878
 From the results obtained in the three studied cases, one can note that the optimal values of the PID
controller obtained from the GOA technique achieves the global minimum error compared to the optimal
values of the FOPID controller obtained using the same technique. As seen from Table 7, during TLG, one
can note that:
 From the perspective of the optimization techniques used, the proposed PID controller with GOA
technique achieved minimum error (ITAEGOA = 1.312) whereas the error obtained by the other three
mentioned optimization techniques was greater than that obtained using the proposed method i.e.
(ITAECSA=1.328, ITAEFBA=1.57 and ITAEGWO=1.567).
 From the perspective of the controller used, the global error obtained by the proposed method with the
optimal PID controller was less than that obtained by the FOPID controller i.e. (for the FOPID
controller: ITAECSA=5.388, ITAEFBA=63.64, ITAEGWO=3.159 and ITAEGOA=6.77).
 From the perspective of the computation time used, the computation time of the proposed method
(PID-GOA) was 153.505s, which has fast dynamic response in extracting the optimum values of
controller parameters and minimum error compared with the three mentioned optimization techniques
(i.e. tCSA=394.403 s, tFBA=174.349 s and tGWO=158.564 s).
Also, during DLG, as seen from Table 8, one can note that PID controller proposed with GOA technique
achieved minimum error (ITAEGOA = 1.335) whereas the error obtained by the other three optimization
techniques was greater than that obtained using the proposed method i.e. (ITAECSA=1.667, ITAEFBA=1.69 and
ITAEGWO=1.392). In addition, in comparison with FOPID controller, the global error obtained from the
proposed method with PID controller was less than that obtained from FOPID controller i.e. (for the FOPID
controller: ITAECSA=4.485, ITAEFBA=53.87, ITAEGWO=84.92 and ITAEGOA=44.49). As well, during SLG, as
seen from Table 9, one can note that PID controller proposed with GOA technique achieved minimum error
(ITAEGOA = 1.519) whereas the error obtained by the other three optimization techniques was greater than the
proposed method i.e. (ITAECSA=1.695, ITAEFBA=1.634 and ITAEGWO=1.687).
To sum up, the proposed approach using GOA successfully achieves the global minimum error in all the
studied cases compared to the other optimization techniques. Also, in a comparison of the optimal PID and
FOPID controllers, the proposed DVR scheme with PID is effective, fast, robust, and superior to the presented
DVR with FOPID controller. From the author’s point of view, it can be noted from the above-mentioned
results that the DVR with the proposed control is a low-cost control method of DVR which has a very simple
circuit configuration. It provides a highly dynamic response and highly efficient utilization of energy
(sustainability). The total harmonic distortion (THD) is reduced considerably. It provides a higher X/R ratio,
which is more effective for compensating reactive power in distribution networks. However, it can
compensate any voltage disturbance but with changes in the energy storage element.
6.3 Impact of using disturbance rejection controller on the system performance

An active disturbance rejection controller (ADRC) can be placed instead of the highly dominating PID
controller as presented in [40], [41]. It combines the PID controller and a partially modelled-based modern
controller [42]. It drives e(t) from the PID controller and a state observer (SO) [43]. The main objective of
using ADRC is to detect the disturbances and compensate the necessary voltage in the system to keep the load
voltage within the allowable limits. These are performed by utilizing an extended SO. Then the output value
of an extended SO is given to the controller as presented in [40].
The performance evaluated during using a conventional PID, proposed optimal PID and ADRC controllers
are compared during balanced voltage sags, in which a balanced three-phase voltage sag occurs in the time
interval from t=0.2 s to t= 0.3 s. The voltage drops by 30%. Fig. 20 depicts the performance of DVR control
scheme with ADRC and the conventional PID, while Fig. 21 shows the performance of DVR control scheme
with ADRC and the proposed optimal PID with GOA technique. From these figures, one can see that the
performance of the model using the optimal PID controller is more effective than the performance attained
using the ADRC based model, in which the ITAE measured values were 1.325 and 0.813 respectively, using
ADRC and the optimal PID controller that restores the voltage to 99%. However, this was not the case using
the conventional (unoptimized) PID controller that restores the voltage to 90% with respect to the reference
value.
 Fig. 20. Performance of DVR with ADRC and conventional PID controllers

Fig. 21. Performance of DVR with ADRC and optimal PID controllers during balanced
sag
 Also, the performance evaluated during using proposed optimal PID and ADRC controllers are compared
during the imbalance condition illustrated in Fig. 22. It can be noted from Fig. 23 that the magnitude of
voltage at each phase with the optimal PID controller is higher compared to the one with the ADRC
controller. Additionally, the overshoot (OS) at the beginning and the end of the imbalance disturbance mode
(2.6%) and the ITAE value (1.114) are lower with the optimal PID controller than those obtained with the
ADRC controller (4.7% for the OS and 2.154 for the ITAE) for phase C. Similar values are obtained for the
other phases. Therefore, we can conclude that the response of the optimal PID controller to compensate
voltage imbalance is faster compared to the ADRC controller.

Fig. 22. Rms voltage during imbalance condition

(a)

(b)
 (c)

Fig. 23. DVR performance with ADRC and optimal PID controllers: (a) phase A, (b) phase B, (c) phase C

7. Conclusions and extensions

The paper presents a novel contribution of low-cost voltage control by using a dynamic voltage restorer
scheme as a series compensation device to cope with power quality issues of hybrid industrial loads connected
with a distribution network, while ensuring energy-efficient operation and minimal impact on the grid
systems. The DVR scheme controlled by an optimal PID regulation controller is employed for driving the
switching signal of a voltage source inverter to identify the optimum fitness value for minimization of the total
error-driven loop to guarantee a fast-dynamic response for the sake of efficient energy utilization. A fractional
order PID is presented and compared with a conventional PID to verify the proposed method. Further, a
comparative performance evaluation of the four optimization strategies, CSA, FBA, GOA, and GWO
techniques, was implemented between the PID and FOPID in terms of fault conditions, and the results
obtained revealed the superior effectiveness and robustness of the optimal PID compared with the FOPID
controller. Also, a comparative analysis of the results obtained using the proposed controller and those
obtained using ADRC is presented, and it is found that the performance of the optimal PID is better than the
performance of the conventional ADRC.
 The same device will be extended in future work using a variable structure-sliding mode-Bang Bang and
multi-stage recently optimized metaheuristic-based controller to be utilized for smart systems using hybrid
fuel cell/PV/supercapacitors. In addition, new topologies of DVR inter-coupled AC/DC compensation systems
will be developed.

Acknowledgements

The authors thank the editor and reviewers for their constructive comments.
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*Conflict of Interest

Declaration of interests

☒ The authors declare that they have no known competing financial interests or personal relationships
that could have appeared to influence the work reported in this paper.

☒The authors declare no financial interests/personal relationships which may be considered as potential
competing interests.

Ahmed I. Omar
a.omar@sha.edu.eg