ESMT AD52060

2x20W Stereo Class-D Audio Amplifier with Power Limit

Features  TV audio
 Boom-Box
 Single supply voltage  Powered speaker
8V ~ 26V for loudspeaker driver  Monitors
Built-in LDO output 5V for others  Consumer Audio Equipment
 Loudspeaker power from 24V supply
BTL Mode: 20W/CH into 8 @<1% THD+N
PBTL Mode: 40W/CH into 4 @<10% THD+N
Description
 Loudspeaker power from 12V supply The AD52060 is a high efficiency stereo class-D
BTL Mode: 10W/CH into 8 @10% THD+N audio amplifier with adjustable power limit function.
 88% efficient Class-D operation eliminates need The loudspeaker driver operates from 8V~26V
for heat sink supply voltage. It can deliver 20W/CH output power
 Differential inputs into 8 loudspeaker within 1% THD+N at 24V
 Four selectable, fixed gain settings supply voltage and without external heat sink when
 Internal oscillator playing music.
 Short-Circuit protection with auto recovery option
AD52060 provides parallel BTL (Mono)
 Under-Voltage detection
application, and it can deliver 40W into 4
 Over-Voltage protection
loudspeaker at 24V supply voltage. The adjustable
 Pop noise and click noise reduction
power limit function allows user to set a voltage rail
 Adjustable power limit function for speaker
lower than half of 5V to limit the amount of current
protection
through the speaker.
 Output DC detection for speaker protection
 Filter-Free operation Output DC detection prevents speaker damage
 Over temperature protection with auto recovery from long-time current stress. AD52060 provides
 Superior EMC performance superior EMC performance for filter-free application.
The output short circuit and over temperature
Applications protection include auto-recovery feature.

Simplified Application Circuit

Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018

Revision: 1.5 1/23
ESMT AD52060
Pin Assignments
E-TSSOP-28L
(TOP VIEW)

SD 1 28 PVCCL
FAULT 2 27 PVCCL
LINP 3 26 BSPL
LINN 4 25 OUTPL
GAIN0 5 24 PGND
GAIN1 6 23 OUTNL
AVCC 7 22 BSNL
AGND 8 21 BSNR
GVDD 9 20 OUTNR
PLIM 10 19 PGND
RINN 11 18 OUTPR
RINP 12 17 BSPR
TEST 13 16 PVCCR
PBTL 14 15 PVCCR

Pin Description
E-TSSOP
NAME TYP DESCRIPTION
-28L
Shutdown signal for IC (low = disabled, high = operational). Voltage compliance
SD 1 I
to AVCC.

Open drain output used to display short circuit or dc detect fault. Voltage

compliant to AVCC. Short circuit faults can be set to auto-recovery by

FAULT 2 O
connecting FAULTB pin to SD pin. Otherwise, both short circuit faults and dc
detect faults must be reset by cycling AVCC.

LINP 3 I Positive audio input for left channel. Biased at 2.5V.

LINN 4 I Negative audio input for left channel. Biased at 2.5V.

GAIN0 5 I Gain select least significant bit. Voltage compliance to AVCC.

GAIN1 6 I Gain select most significant bit. Voltage compliance to AVCC.

AVCC 7 P Analog supply.

AGND 8 P Analog signal ground. Connect to the thermal pad.

GVDD 9 O 5V regulated output, also used as supply for PLIMIT function.

Power limit level adjustment. Connect a resistor divider from GVDD to GND to

PLIMIT 10 I set power limit. Give V(PLIMIT) <2.4V to set power limit level. Connect to GVDD

(>2.4V) or GND to disable power limit function.

RINN 11 I Negative audio input for right channel. Biased at 2.5V.

RINP 12 I Positive audio input for right channel. Biased at 2.5V.

TEST 13 I Test mode pin.

Parallel BTL mode switch, high for parallel BTL output. Voltage compliance to
PBTL 14 I
AVCC.

Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018

Revision: 1.5 2/23
ESMT AD52060
High-voltage power supply for right-channel. Right channel and left channel
PVCCR 15,16 P
power supply inputs are connect internal.

BSPR 17 I Bootstrap I/O for right channel, positive high side FET.

OUTPR 18 O Class-D H-bridge positive output for right channel.

PGND 19 P Power ground for the H-bridges.

OUTNR 20 O Class-D H-bridge negative output for right channel.

BSNR 21 I Bootstrap I/O for right channel, negative high side FET.

BSNL 22 I Bootstrap I/O for left channel, negative high side FET.

OUTNL 23 O Class-D H-bridge negative output for left channel.

PGND 24 P Power ground for the H-bridges.

OUTPL 25 O Class-D H-bridge positive output for left channel.

BSPL 26 I Bootstrap I/O for left channel, positive high side FET.

High-voltage power supply for right-channel. Right channel and left channel
PVCCL 27,28 P
power supply inputs are connect internal.

Thermal Pad P Must be soldered to PCB’s ground plane.

Ordering Information

Product ID Package Packing / MPQ Comments

50 Units / Tube
AD52060-QG28NRT E-TSSOP 28L Green
100 Tubes / Small Box

2500 Units / Reel

AD52060-QG28NRR E-TSSOP 28L Green
2500 Units / Small Box

Available Package
Package Type Device No. θJA(℃/W) θ JT(℃/W) Ψ JT(℃/W) Exposed Thermal Pad

E-TSSOP 28L AD52060 28 27.1 1.33 Yes (Note 1)

Note 1.1: The thermal pad is located at the bottom of the package. To optimize thermal
performance, soldering the thermal pad to the PCB’s ground plane is necessary.
Note 1.2: θ JA is simulated on a room temperature (TA=25℃), natural convection environment test
board, which is constructed with a thermally efficient, 4-layers PCB (2S2P). The
measurement is simulated using the JEDEC51-5 thermal measurement standard.
Note 1.3: θ JT represents the thermal resistance for the heat flow between the chip junction and the
package’s top surface. It’s extracted from the simulation data with obtaining a cold
plate on the package top.
Note 1.4: Ψ JT represents the thermal parameter for the heat flow between the chip junction
and the package’s top surface center. It’s extracted from the simulation data for
obtainingθ JA, using a procedure described in JESD51-5.

Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018

Revision: 1.5 3/23
ESMT AD52060
Marking Information
AD52060
ESMT
● Marking Information
AD52060
Line 1：LOGO Tracking Code
Line 2：Product No
Line 3：Tracking Code PIN1 DOT

Absolute Maximum Ratings

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.
SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT
PVCC Supply voltage PVCCL, PVCCR -0.3 30 V
SD, GAIN0, GAIN1, PBTL, FAULT, -0.3 30
VI Interface pin voltage V
PLIMIT -0.3 5.5
o
TA Operating free-air temperature range -40 85 C
o
TJ Operating junction temperature range -40 150 C
o
Tstg Storage temperature range -65 150 C
BTL: PVCC ＞ 13V 4.8 
RL Minimum Load Resistance BTL: PVCC ≦ 13V 3.2 
PBTL 3.2 
Human Body Model ±2k
ESD V
Charged Device Model ±500

Recommended Operating Conditions

SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT
PVCC Supply voltage AVCC, PVCCL, PVCCR 8 26 V
VIH High-level input voltage SD, GAIN0, GAIN1, PBTL 2 V
VIL Low-level input voltage SD, GAIN0, GAIN1, PBTL 0.8 V
VOL Low-level output voltage FAULT, RPULL-UP=100k, VCC=16V 0.8 V
SD, GAIN0, GAIN1, PBTL, VI=2V,
IIH High-level input current 50 uA
VCC=18V

SD, GAIN0, GAIN1, PBTL, VI=0.8V,

IIL Low-level input current 5 uA
VCC=18V
IOH High-level output current VI=2V, VCC=18V 50 
IOL Low-level output current VI=0.8V, VCC=18V 50 
o
TA Operating free-air -40 85 C
temperature

Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018

Revision: 1.5 4/23
ESMT AD52060
General Electrical Characteristics
 PVCC=24V, RL=8TA=25°C (unless otherwise noted)

SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT

SD=2V, no load,
ICC(q) Quiescent supply current 20 35 mA
PVCC=12V
Quiescent supply current SD=0.8V, no load,
ICC(SD) < 12 25 uA
in shutdown mode PVCC=12V
Drain-source on-state
resistance-High side 220 m
NMOS PVCC=12V, Id=500mA,
RDS(on) o
Drain-source on-state TJ=25 C
resistance-Low side 220 m
NMOS
Class-D output offset
|VOS| voltage (measured PVCC=12V VI=0V, mV
1.5 15
Gain=36dB
differential)
tON Turn-on time SD=2V 90 ms

tOFF Turn-off time SD=0.8V 2 s

GVDD Regulator output IGVDD=0.1mA 4.75 5 5.25 V

GAIN1 GAIN0=0.8V 18 20 22
=0.8V GAIN0=2V 24 26 28
G Gain dB
GAIN1 GAIN0=0.8V 30 32 34
=2V GAIN0=2V 34 36 38

Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018

Revision: 1.5 5/23
ESMT AD52060
Electrical Characteristics and Specifications of Loudspeaker Driver
 PVCC=24V, RL=8TA=25°C (unless otherwise noted)
SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT
THD+N=0.03%, f=1kHz, PVCC=24V 20
PO Output power W
THD+N=10%, f=1kHz, PVCC=12V 10
PVCC=24V, RL=8f=1kHz, PO=10W
0.02
Total harmonic distortion (half-power)
THD+N %
plus noise PVCC=12V, RL=8f=1kHz, PO=5W
0.03
(half-power)
Maximum output at THD+N<1%, f=1kHz,
SNR Signal to noise ratio 103 dB
Gain=20dB, a-weighted
F=20Hz ~ 20kHz, Gain=20dB, a-weighted
Vn Output integrated noise 80 V
filter, RL=8

Power Supply Rejection Vripple=200mVpp at 1kHz, Gain=20dB, inputs

KSVR -70 dB
Ratio ac-grounded

Crosstalk Crosstalk F=1kHz, VO=1Vrms, Gain=20dB -103 dB

fOSC Oscillator frequency 250 310 370 kHz

o
Thermal trip point 150 C
TSENSOR o
Thermal hysteresis 25 C

THD + N (%) v.s. Output power (8ohm load)

20
T
10
Gain=20dB
5
Load=8ohm+66uH 12V 18V 24V

0.5
%

0.2

0.1

0.05

0.02

0.01
10m 20m 50m 100m 200m 500m 1 2 5 10 20 60
W

Sweep Trace Color Line Style Thick Data Axis Comment

1 1 Red Solid 3 Anlr.THD+N Ratio Left 24V

2 1 Blue Solid 3 Anlr.THD+N Ratio Left 18V
3 1 THD + N (%) v.s. Output power (6ohm load)
Magenta Solid 3 Anlr.THD+N Ratio Left 12V

Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018

Revision: 1.5 6/23
ESMT AD52060

20
T
10
Gain=20dB
5
12V 18V 24V
Load=6ohm+47uH
2

0.5
%

0.2

0.1

0.05

0.02

0.01
10m 20m 50m 100m 200m 500m 1 2 5 10 20 60
W

Sweep Trace Color Line Style Thick Data Axis Comment

1 1 Red Solid 3 Anlr.THD+N Ratio Left 24V

2 1 Blue Solid 3 Anlr.THD+N Ratio Left 18V
3 1 Magenta Solid 3 Anlr.THD+N Ratio Left 12V

THD + N (%) v.s. Output power (4ohm load)

20
T
10

5 Gain=20dB 12V 18V

Load=4ohm+33uH
2

0.5
%

0.2

0.1

0.05

0.02

0.01
10m 20m 50m 100m 200m 500m 1 2 5 10 20 60
W

Sweep Trace Color Line Style Thick Data Axis Comment

1 1 Blue Solid 3 Anlr.THD+N Ratio Left 18V

2 1 Magenta Solid 3 Anlr.THD+N Ratio Left 12V

Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018

Revision: 1.5 7/23
ESMT AD52060
AD52060_8ohm stereo

35

30

25
Output Power (W

20

15
THD+N=10%
10 THD+N=1%
5

0
4 6 8 10 12 14 16 18 20 22 24 26

PVCC (V)
Note: Dashed Line represent thermally limited regions.

AD52060_6ohm stereo

35

30

25
Output Power (W)

20

15
THD+N=10%
10 THD+N=1%
5

0
4 6 8 10 12 14 16 18 20 22 24 26

PVCC (V)
Note: Dashed Line represent thermally limited regions.

Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018

Revision: 1.5 8/23
ESMT AD52060
AD52060_4ohm Mono

50
45
40
Output Power (W)

35
30
25
20
15 THD+N=10%
THD+N=1%
10
5
0
4 6 8 10 12 14 16 18 20 22 24 26

PVCC (V)
Note: Dashed Line represent thermally limited regions.

THD + N (%) v.s. Frequency (24V 8ohm load)

10
T TT
5

2
Gain=20dB
1 Load=8ohm+66uH
0.5

0.2 10W
% 0.1
0.05 20W

0.02
0.01
5W
0.005

0.002

0.001
20 50 100 200 500 1k 2k 5k 10k 20k
Hz

Sweep Trace Color Line Style Thick Data Axis Comment

1 1 Red Solid 3 Anlr.THD+N Ratio Left 24V 20W LCH

3 1 Blue Solid 3 Anlr.THD+N Ratio Left 10W LCH
4 1 Magenta Solid 3 Anlr.THD+N Ratio Left 5W LCH

Noise (8ohm load)

Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018
Revision: 1.5 9/23
ESMT AD52060

120u
110u
100u

90u
80u
70u

V 60u 12V 18V 24V

Gain=20dB
50u
Load=8ohm+66uH
40u
30u

20u
10u

0
20 50 100 200 500 1k 2k 5k 10k 20k
Hz

Efficiency (Stereo 8ohm load) / 2ch

100

90

80

70

60
Efficiency (%)

50

40

30
PVDD=24V
20
PVDD=18V
10 PVDD=12V

0
0 10 20 30 40 50 60 70 80

Output Pow er (W)*2CH

Efficiency (Mono 4ohm load) / 2ch

Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018

Revision: 1.5 10/23
ESMT AD52060

100

90

80

70

60
Efficiency (%)

50

40

30 PVDD=24V

20 PVDD=18V

10 PVDD=12V

0
0 10 20 30 40 50 60 70 80

Output Pow er (W)

Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018

Revision: 1.5 11/23
ESMT AD52060
Functional Block Diagram

PVCCL
BSPL
LINP Power OUTPL
Gain Control PLIMIT PWM
Modulator Stage
LINN Amplifier Logic OUTNL
N/N
BSNL
PGND

DC Short-Circuit
∆-wave Protection
Detect

PVCCR
BSPR
RINP Power OUTPR
Gain Control PWM Stage
PLIMIT Modulator
RINN Amplifier Logic OUTNR
N/N
BSNR
PGND
GAIN0
Gain Select
GAIN1
Thermal
PLIMIT
PLIMIT Detect
Reference Bias
SD Control Logic And
Reference Under-Voltage
AGND Protection
Regulator

PVCC GVDD

Short Circuit Error FAULT

DC Detect Error Logic FAULT

Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018

Revision: 1.5 12/23
ESMT AD52060
Operation Descriptions

 Gain settings
The gain of the AD52060 is set by two input pins, GAIN0 and GAIN1. By varying input
resistance in AD52060, the various volume gains are achieved. The respective volume
gain and input resistance are listed in Table 1. However, there is 20% variation in input
resistance from production variation.

Table 1. Volume gain and input impedance

GAIN1 GAIN0 Volume Gain (dB) Input Resistance, Rin (k)
0 0 20 60
0 1 26 30
1 0 32 15
1 1 36 9

 Shutdown ( SD ) control
Pulling SD pin low will let AD52060 operate in low-current state for power conservation.
The AD52060 outputs will enter mute once SD pin is pulled low, and regulator will also
disable to save power. If let SD pin floating, the chip will enter shutdown mode because
of the internal pull low resistor. For the best power-off performance, place the chip in the
shutdown mode in advance of removing the power supply.

 DC detection
AD52060 has dc detection circuit to protect the speakers from DC current which might
be occurred as input capacitor defect or inputs short on printed circuit board. The
detection circuit detects first volume amplifier stage output, when both differential
outputs’ voltage become higher than a determined voltage or lower than a determined
voltage for more than 420ms, the dc detect error will occur and report to FAULT pin. At
the same time, loudspeaker drivers of right/left channel will disable and enter Hi-Z. This
fault can not be cleared by cycling SD , it is necessary to cycle the PVCC supply.

The minimum differential input voltages required to trigger the DC detect function are
shown in table2. The input voltage must keep above the voltage listed in the table for
more than 420msec to trigger the DC detect fault. The equivalent class-D output duty of
the DC detect threshold is listed in table3.

Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018

Revision: 1.5 13/23
ESMT AD52060

Table 2. DC Detect Threshold

AV (dB) Vin (mV, differential)
20 250
26 125
32 63
36 35

Table 3. Output DC Detect Duty (for Either Channel)

PVCC (V) Output Duty Exceeds
8 20.8%
12 20.8%
16 20.8%

 Thermal protection
If the internal junction temperature is higher than 150oC, the outputs of loudspeaker
drivers will be disabled and at low state. The temperature for AD52060 returning to
normal operation is about 125oC. The variation of protected temperature is about 10%.
Thermal protection faults are NOT reported on the FAULT pin.

 Short-circuit protection
To protect loudspeaker drivers from over-current damage, AD52060 has built-in
short-circuit protection circuit. When the wires connected to loudspeakers are shorted to
each other or shorted to VSS or to PVCC, overload detectors may activate. Once one of
right and left channel overload detectors are active, the amplifier outputs will enter a
Hi-Z state and the protection latch is engaged. The short protection fault is reported on
FAULT pin as a low state. The latch can be cleared by reset SD or power supply
cycling.

The short circuit protection latch can have auto-recovery function by connect the FAULT
pin directly to SD pin. The latch state will be released after 420msec, and the short
protection latch will re-cycle if output overload is detected again.

 Under-voltage detection
When the GVDD voltage is lower than 2.8V or the PVDD voltage is lower than 4V,
loudspeaker drivers of right/left channel will be disabled and kept at low state. Otherwise,
AD52060 return to normal operation.

Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018

Revision: 1.5 14/23
ESMT AD52060
 Over-voltage protection
When the PVCC voltage is higher than 29.5V, loudspeaker will be disabled kept at low
state. The protection status will be released as PVCC lower than 29V.

 Power limit function

 The voltage at PLIMIT pin can used to limit the power of first gain control amplifier
output. Add a resistor divider from GVDD to ground to set the voltage V PLIMIT at the
PLIMIT pin. The voltage VPLIMIT sets a limit on the output peak-to-peak voltage.
PLIMIT is adjustable from 1.33V~2.5V.

For normal BTL operation (Stereo) and PBTL (Mono) operation:

2
 2.5V  PLIMIT 
  2  PVDD  1.23  0.0076  PVDD 
 2.1V  0.81  PLIMIT 
Po @ 1% 
2  RL

Po @10%  ( Po @1%)  1.2  0.02  PVDD 

Connect PLIMIT pin to ground or GVDD to disable power limit function. The output
variation during power limit feature enable may have +-20% variation due to process
window.

Table 4. PLIMIT Typical OperationⅠ

VPLIMIT (V) @
Test Conditions Output PO (W)
THD+N=10%
5 1.99
8 1.872
PVCC=24V
10 1.808
RL=8
12 1.752
15 1.678

Table 4.1 PLIMIT Typical OperationⅡ

VPLIMIT (V) @
Test Conditions Output PO (W)
THD+N=10%
3 1.756
PVCC=12V 5 1.578
RL=8 8 1.388
9 1.336

 PBTL (Mono) function

Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018
Revision: 1.5 15/23
ESMT AD52060
AD52060 provides the application of parallel BTL operation with two outputs of each
channel connected directly. If the PBTL pin is tied high, the positive and negative
outputs of left and right channel are synchronized and in phase. Apply the input signal to
the RIGHT channel input in PBTL mode and let the LEFT channel input grounded, and
place the speaker between the LEFT and RIGHT outputs. The output swing is doubled
of that in normal mode. See the application circuit example for PBTL (Mono) mode
operation. For normal BTL (Stereo) operation, connect the PBTL pin to ground.

Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018

Revision: 1.5 16/23
ESMT AD52060
Application information

 Input capacitors (Cin)

The performance at low frequency (bass) is affected by the corner frequency (fc) of the
high-pass filter composed of input resistor (Rin) and input capacitor (Cin), determined in
equation (2). Typically, a 0.1F or 1F ceramic capacitor is suggested for Cin. The
resistance of input resistors is different at different gain setting. The respective gain and
input resistance are listed in Table 1 (shown at GAIN SETTING). However, there is 20%
variation in input resistance from production variation.

-3 dB
fc 
1
Hz  2
2π R in Cin

fC
 Ferrite Bead selection
If the traces from the AD52060 to speaker are short, the ferrite bead filters can reduce
the high frequency emissions to meet FCC requirements. A ferrite bead that has very
low impedance at low frequency and high impedance at high frequency (above 1MHz)
is recommended. The impedance of the ferrite bead can be used along with a small
capacitor with a value around 1000pF to reduce the frequency spectrum of the signal to
an acceptable level.

FB
OUTP
1000pF

1000pF
FB
OUTN

Figure 2. Typical Ferrite Bead Filter

 Output LC Filter
If the traces from the AD52060 to speaker are not short, it is recommended to add the
output LC filter to eliminate the high frequency emissions. Figure 3 shows the typical
output filter for 8 speaker with a cut-off frequency of 27 kHz and Figure 4 shows the
typical output filter for 4 speaker with a cut-off frequency of 27 kHz.

Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018

Revision: 1.5 17/23
ESMT AD52060

33H
OUTP
L1 C1 1uF
8
C2 1uF
33H
OUTN
L2

Figure 3. Typical LC Output Filter for 8 Speaker

15H
OUTP
L1 C1 2.2uF
4
C2 2.2uF
15H
OUTN
L2

Figure 4. Typical LC Output Filter for 4 Speaker

 Power supply decoupling capacitor (Cs)

Because of the power loss on the trace between the device and decoupling capacitor,
the decoupling capacitor should be placed close to PVCC and PGND to reduce any
parasitic resistor or inductor. A low ESR ceramic capacitor, typically 1000pF, is
suggested for high frequency noise rejection. For mid-frequency noise filtering, place a
capacitor typically 0.1F or 1F as close as possible to the device PVCC leads works
best. For low frequency noise filtering, a 100F or greater capacitor (tantalum or
electrolytic type) is suggested.

PVCC Power Supply

1000pF 0.1uF 100uF

Figure 5. Recommended Power Supply Decoupling Capacitors.

Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018

Revision: 1.5 18/23
ESMT AD52060
Application Circuit Example
 Application circuit for BTL (Stereo) mode configuration and Singe-Ended Input
PVCC

100k
1k
Shutdown
1 28
Control SD PVCCL PVCC
2 27
PVCCL 0.1uF 100uF
FAULT
Note 2 3 26
1uF
L-ch
Input LINP BSPL
1k 4 25 0.22uF
1uF FB
LINN OUTPL
5 24 1000pF
GAIN0 PGND
10
6 23 FB
1000pF

PVCC GAIN1 OUTNL

7 22 0.22uF
AVCC BSNL
1uF
8 AD52060 21
AGND BSNR
1uF 0.22uF
9 20 FB
1uF
RPL2 GVDD OUTNR
RPL1 10 19 1000pF
PLIM PGND
Note 2 11 18 FB
1000pF
1uF
RINN OUTPR
1k 12 17 0.22uF
R-ch 1uF
Input
RINP BSPR
13 16
TEST PVCCR PVCC
14 15
PBTL PVCCR 0.1uF 100uF

Note 2: These resistances must be connected to ground, resistance=1Kohm

Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018

Revision: 1.5 19/23
ESMT AD52060
Application Circuit Example
 Application circuit for parallel BTL (Mono) mode configuration and Singe-Ended Input
PVCC

100k
1k
Shutdown
1 28
Control SD PVCCL PVCC
2 27
PVCCL 0.1uF 100uF
FAULT
3 26
LINP BSPL
4 25 0.47uF
LINN OUTPL
5 24
GAIN0 PGND
10
6 23 FB
PVCC GAIN1 OUTNL
7 22
AVCC 1000pF
BSNL
1uF
8 AD52060 21
AGND BSNR
1uF FB 1000pF
9 20
1uF
RPL2 GVDD OUTNR
RPL1 10 19
PLIM PGND
Note 2 11 18
1uF
RINN OUTPR
1k 12 17 0.47uF
R-ch 1uF
Input
RINP BSPR
13 16
TEST PVCCR PVCC
14 15
PVCC PBTL PVCCR 0.1uF 100uF

Note 2: These resistances must be connected to ground, resistance=1Kohm.

Note 3: Be noted that input should be applied on R-channel only for Mono application.

Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018

Revision: 1.5 20/23
ESMT AD52060
Package Dimensions
 E-TSSOP 28L

28 15

D2

E2 E E1 DETAIL A
PIN#1
MARK 1 14
c
TOP VIEW
D

A
A1
1 14
b e
L
SIDE VIEW

Dimension in mm Exposed pad

Symbol
Min Max Dimension in mm
A -- 1.20 Option 1 Min Max
A1 0.05 0.15 D2 4.25 5.75
b 0.19 0.30 E2 2.35 3.18
c 0.09 0.20
D 9.60 9.80
E 4.30 4.50
E1 6.30 6.50
e 0.65 BSC
L 0.45 0.75

Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018

Revision: 1.5 21/23
ESMT AD52060
Revision History

Revision Date Description

0.1 2016.04.18 Original.
0.2 2016.10.07 Add Tape/Reel information
1.0 2016.11.15 Modified version to 1.0, removed preliminary.
1.1 2016.12.15 Modified Package Dimensions information
1.2 2017.01.05 Modified Exposed PAD information
1.3 2017.04.19 Added performance data.
1.4 2018.01.22 Modify ESD data
1.Modify simplified application circuit
1.5 2018.03.05
2.Modify MOQ for AD52060-QG28NRR

Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018

Revision: 1.5 22/23
ESMT AD52060

Important Notice
All rights reserved.

No part of this document may be reproduced or duplicated in any form or by

any means without the prior permission of ESMT.

The contents contained in this document are believed to be accurate at the

time of publication. ESMT assumes no responsibility for any error in this
document, and reserves the right to change the products or specification in
this document without notice.

The information contained herein is presented only as a guide or examples for

the application of our products. No responsibility is assumed by ESMT for any
infringement of patents, copyrights, or other intellectual property rights of third
parties which may result from its use. No license, either express, implied or
otherwise, is granted under any patents, copyrights or other intellectual
property rights of ESMT or others.

Any semiconductor devices may have inherently a certain rate of failure. To

minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure, should
be provided by the customer when making application designs.

ESMT's products are not authorized for use in critical applications such as,
but not limited to, life support devices or system, where failure or abnormal
operation may directly affect human lives or cause physical injury or property
damage. If products described here are to be used for such kinds of
application, purchaser must do its own quality assurance testing appropriate
to such applications.

Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2018

Revision: 1.5 23/23