See discussions, stats, and author profiles for this publication at: https://www.researchgate.

net/publication/318910440

Full Adder Circuit Using CNTFET

Technical Report · May 2015

DOI: 10.13140/RG.2.2.30809.42082

CITATIONS READS
2 3,541

All content following this page was uploaded by Yashwanth Popuri on 04 August 2017.

The user has requested enhancement of the downloaded file.

 .

Spring 2015

ECE-5310, Dr. Tooraj Nikoubin

Full Adder Circuit Using CNTFET

By:

Yashwanth Popuri

Gopala Krishna Reddy Yarram

1
Abstract:

Full Adder is one of the critical parts of logical and arithmetic units. So, presenting a low
power full adder cell reduces the power consumption of the entire circuit. Also, using Nano-scale
transistors, because of their unique characteristics will save energy consumption and decrease the
chip area. In this paper we presented a low power full adder cell by using carbon nanotube field
effect transistors (CNTFETs). Simulation results were carried out using HSPICE based on the
CNTFET model in 32 nanometer technology in Different values of VDD at room temperature.

2
Table of contents:

Abstract 2

List of figures 5

List of tables 6

1. Introduction 7

1.1 MOSFET 8

1.2 FinFET 9

1.3 CNTFET & Carbon nanotube 10

1.4 Comparison 13

2. Device Fabrication 14

3. Types of CNTFET 15

3.1 Based on fabrication 15

3.2 Based on working 17

4. Theoretical behavior of CNTFET 18

4.1 Size of CNFET 19

4.2 CNTFET threshold voltage 19

4.3 Transconductance 20

4.4 Subthreshold Slope 20

4.5 Gate Delay 20

4.6 Dynamic Energy 21

5. Optimization of CNFET device parameters 21

5.1 Choice of number of carbon tubes 21

5.2 Choice of diameter of carbon nanotube 22

5.3 Choice of inter nanotube spacing 22

3
6. Simulation of FULL ADDER in HSPICE 23

6.1 INVERTER 23

6.2 AND 25

6.3 OR 26

6.4 XOR 28

6.5 FULL ADDER 29

7. RESULTS 33

8. CONCLUSION 35

9. FUTURE SCOPE 36

REFERENCES 37

4
List of figures:

1. Moore's Law 7

2. MOSFET 8

3. FINFET 9

4. Unrolled graphite sheet and the rolled carbon nanotube lattice structure. 11

5. CNTFET 12

6. Device Fabrication 14

7. Back gated CNTFET 15

8. Top gated CNTFET 16

9. Wrap around gate CNTFET 16

10. Suspended CNTFET 17

11. SCFET AND MCNFET 18

12. CNT pitch vs PDP 23

13. Full adder circuit 23

14. INVERTER 24

15. Output for INVERTER 25

16. AND gate 25

17. Output for AND 26

18. OR gate 26

19. Output for OR 27

20. XOR gate 28

21. Output for XOR 29

22. Full adder circuit 29

23. Output for full adder 30

24. Graph for full adder 31

5
List of tables:

1. Truth table for AND gate 25

2. Truth table for OR gate 27
3. Truth table for XOR gate 28
4. Truth table for FULL ADDER gate 30
5. PDP, Time delay and Average power of Full-Adder comparison 31
6. Default values of the parameters 32
7. Comparison of CNFET, CMOS and FINFET 34

6
1. INTRODUCTION

According to Moore's law, the dimensions of individual devices in an integrated circuit have
been decreased by a factor of approximately two every two years. This scaling down of devices
has been the driving force in technological advances since late 20th century.

Fig 1. Moore's law

However, as noted by ITRS 2009 edition, further scaling down has faced serious limits
related to fabrication technology and device performances as the critical dimension shrunk down
to sub-22 nm range. The limits involve electron tunneling through short channels and thin
insulator films, the associated leakage currents, passive power dissipation, short channel effects,
and variations in device structure and doping. These limits can be overcome to some extent and
facilitate further scaling down of device dimensions by modifying the channel material in the
traditional bulk MOSFET structure with a single carbon nanotube or an array of carbon
nanotubes.

Silicon-based technology has experienced phenomenal growth in the last few decades. A large
part of the success of the MOS transistor is due to the fact that it can be scaled to increasingly
smaller dimensions, which results in higher performance. Though this trend still continues, bulk
MOSFET will soon reach its limiting size. For this reason, the semiconductor industry is looking
for different materials and devices to integrate with the current silicon-based technology and in
the long run, possibly replace it. The carbon nanotube field effect transistor is one among the
most promising alternatives due to its superior electrical properties.

7
 Carbon nanotubes (CNTs) are at the forefront of these new materials because of the
unique mechanical and electronic properties. Carbon nanotube field effect transistor
(CNFET) is the most promising technology to extend or complement traditional silicon
technology due to three reasons: First, the operation principle and the device structure are
similar to CMOS devices; we can reuse the established CMOS design infrastructure.
Second, we can reuse CMOS fabrication process. And the most important reason is that
CNFET has the best experimentally demonstrated device current carrying ability to date.

1.1 MOSFET

The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS

FET) is a type of transistor used for amplifying or switching electronic signals.
Although the MOSFET is a four-terminal device with source (S), gate (G), drain (D), and
body (B) terminals, the body (or substrate) of the MOSFET is often connected to the source
terminal, making it a three-terminal device like other field-effect transistors. Because these two
terminals are normally connected to each other (short-circuited) internally, only three terminals
appear in electrical diagrams. The MOSFET is by far the most common transistor in
both digital and analog circuits, though the bipolar junction transistor was at one time much more
common.
The main advantage of a MOSFET over a regular transistor is that it requires very little current
to turn on (less than 1mA), while delivering a much higher current to a load (10 to 50A or more).
However, the MOSFET requires a higher gate voltage (3-4V) to turn on.

Fig 2. MOSFET

8
1.2 FINFET

The distinguishing characteristic of the FinFET is that the conducting channel is wrapped
by a thin silicon "fin", which forms the body of the device. The thickness of the fin (measured in
the direction from source to drain) determines the effective channel length of the device. The
Wrap-around gate structure provides a better electrical control over the channel and thus helps in
reducing the leakage current and overcoming other short-channel effects.

Fig 3. FINFET

9
1.3 CNTFET

As one of the promising new devices, CNFET avoid most of the fundamental limitations
for traditional silicon devices. All the carbon atoms in CNT are bonded to each other with sp2
hybridization and there is no dangling bond which enables the integration with high-k dielectric
materials. In the next section, we will introduce the basic properties of CNFET, and will describe
the problem to be modeled. A carbon nanotube field-effect transistor (CNTFET) refers to
a field-effect transistor that utilizes a single carbon nanotube or an array of carbon nanotubes as
the channel material instead of bulk silicon in the traditional MOSFET structure. First
demonstrated in 1998, there have been major developments in CNTFETs.

Carbon Nanotube:

Carbon atom has an electron configuration of 1s22s22p2 in its ground state. In graphene, sp2
hybridization occurs through covalent bonding of the two outermost shells. A carbon atom in
graphene assembles in a single-sheet hexagonal lattice. The inter-carbon-atom distance within
the hexagonal lattice (d) is approximately 1.44 Å, and the angle between carbon-carbon bonds
(σ-bond) is 120 degrees. The lattice constant (a) is given by 3d = 2.49 Å. The 2p electrons from
all the atoms on a lattice form a delocalized π-orbital between the two adjacent sheets. The inter-
layer spacing between the multiple sheets in graphene is about 3.35 Å. The weak electrostatic
interactions between the sheets make it possible to assume the electrical characteristics of the
graphite sheets are independent each other. The dispersion relation for graphene, obtained by the
Slater-Koster tight-binding scheme, considering only the π-orbital, is given by,

Where (kx, ky) are wavevectors, Vπ is the transfer integral (or the nearest-neighbour
parameters). Figure 1.4 illustrates the band structure calculated with the above equation.
The high-symmetry points are indicated by capital letters. K-points are degenerate,
indicating the zero-bandgap (semi-metallic+) characteristic of graphene sheet.

10
 Fig 4. Carbon nanotubes

A single-walled carbon nanotube (SWCNT) can be visualized as a sheet of graphite, which is

rolled up and joined together along a wrapping vector Ch = n1.ā1 + n2.ā2, where [ā1, ā2] are
lattice unit vectors as shown by Figure 1.5, and the indices (n1, n2) are positive integers that
specify the chirality of the tube . The length of Ch is thus the Circumference of the CNT, which
is given by,

Single-walled CNTs are classified into one of their groups (Figure 1.5(a)), depends on the chiral
number (n1, n2): (1) armchair (n1 = n2), (2) zigzag (n1 = 0 or n2 = 0), and (3) chiral (all other
indices).

The diameter of the CNT is given by the formula DCNT = Ch /π. The typical diameters of
CNTs are about several nanometers. Due to the small diameter of CNT, the quantization of wave
vector in the circumferential direction occurs. A general analytic E-k dispersion relation for CNT
is obtained by applying periodic boundary conditions in the circumferential direction to the 2D
graphite sheet E-k dispersion relation.

CNTFET

The operation principle of carbon nanotube field-effect transistor (CNFET) is similar to that of
traditional silicon devices. This three (or four) terminal device consists of a semiconducting
nanotube, acting as conducting channel, bridging the source and drain contacts. The device is
turned on or off electrostatically via the gate. The quasi-1D device structure provides better gate
electrostatic control over the channel region than 3D device (e.g. bulk CMOS) and 2D device
(e.g. fully depleted SOI) structures.

11
 Fig 5. CNTFET

The first fabricated CNFET devices with Au or Pt source/drain metal contacts were
reported in 1998. The gate dielectric material was a thick SiO2 layer. A highly doped Si back
gate was used to control the conductivity. The Al2O3 gate dielectric was introduced to improve
the gate controllability over the channel region. The front gate device structure, by placing the
gate electrode over the thin gate oxide that covers CNT, was used to further improve the channel
electrostatics. Better gate electrostatics was achieved by using high-k, e.g. HfO2, gate dielectric
material. The source/drain contacts using a variety of metals (Ti, Ni, Al, Pd, …) were fabricated
to study the effect of the work function difference between the metal contacts and CNT on
device conductivity. Ti source/drain metallization was reported to be efficient on reducing the
contact resistance. The device fabricated with Pd source/drain metal contact, Al gate electrode,
and HfO2 gate dielectric was reported to achieve excellent dc characteristics.

While the CNT synthesis / fabrication technique and the performance of CNFET devices
and circuits have been significantly improved since the first fabricated device in 1998, CNFETs
is still premature for very large scale integrated (VLSI) circuits design and commercial use. In
order for CNFET to develop into a technology, first, we need tools to enable circuit design and
performance benchmarking.

Efforts have been made in recent years on modeling semiconducting CNFET for digital
logic applications and CNT for interconnects in order to evaluate the potential performance at the
device level. This thesis will mostly focus on the device applications of CNT. A numerical
model was reported in to evaluate the dc current of SB-CNFET. The model reported in predicts
the dc performance of short channel SB-CNFET. Though good dc current can be achieved by
SB-CNFET with the self-aligned structure, its ac performance is going to be poor due to the
proximity of the gate electrode to the source/drain metal. The ambipolar behavior of SBCNFET
also makes it undesirable for complementary logic design. Considering both the fabrication
feasibility and superior device performance of MOSFET-like CNFET as compared to SB-
CNFET, we will focus on MOSFET-like CNFETs. To evaluate the device/circuit performance as
well as the performance dependence on device/geometry parameters, the requirements for a good
device model include:
(1) Good scalability.
(2) Physics-based, or at least semi-physics based.
(3) Reasonable accuracy for both large signal and small signal analysis.

12
(4) Acceptable run time.

1.4 Comparison:

• There is FINFET which is better than MOSFET but still why we are opting this nano tube
FET? Expect the speed of the circuit operations. Using this technology it is far better than
MOSFET.
• Apart from speed? Yes, even the current we get is very good compared to MOSFET and
FINFET.(10µA/nm)
• When designing more smaller circuits in nanoscale using the MOSFET technology there
exists a non – idealities with gate length and related circuit issues.
• There is a problem of high doping to reduce the channel effects in FINFET.
• Mechanical and electrical properties of CNT are even better.
• Unlike FINFET the design of CNTFET is not complex and is just similar to MOSFET.
• CNT diameter determines the threshold voltage of CNTFET.
• While scaling down the size of CMOS structure power dissipation and leakage currents
have become a major concern in modern VLSI designs.
• By decreasing the size of MOSFET, higher sub threshold conduction occurs.
• Current in CNTFET can be controlled by number of CNTs used.

13
2. Device Fabrication

Si wafer with 1 μm thermal oxide served as the starting substrate. A photolithography

step followed by reactive ion etch (RIE) removed 250 nm SiO2 to define trenches for the poly-Si
gates. Before the poly-Si deposition, a thin nitride liner (~200 Å, RTCVD) was inserted to
prevent the loss of gate dopants into the surrounding SiO2. 500 nm LPCVD poly-Si was then
deposited, and the wafer was sent for chemical-mechanical polishing (CMP). Smooth poly
surface (average roughness < 5 Å from atomic force microscope) was achieved in CMP to ensure
a high quality dielectric deposition. Because our gate process reversed the conventional top-gate
scheme, an ultra low energy ion implantation with high doses was used to form heavily
degenerated n- and p-type doping near the surface. To reduce the gate resistivity, a second
implantation with higher energy was performed. A flat profile in As-doped gate is observed due
to the higher annealing temperature (1050 °C vs. 950 °C for BF2 gate). The resistivities of n- and
p-gate are measured to be 2 and 16 m_-cm, respectively. Since there are no thermal budget and
dopant penetration concerns in our process flow, the gate resistance can be further improved by
the optimization of RTA/implant conditions. Pure metal gates (with proper gate work functions)
can also be used to provide better gate resistance, however, the material compatibility issue to
current CMOS process equipments needs be solved.

After native oxide removal, 44 Å CVD HfO2 was then deposited at 500 °C. The method
we used to prepare carbon nanotube array on substrates. Aligned CNT arrays grown on single-
crystal quartz were transferred to our wafer, forming single- or multi-CNT channels per device
for high current output. Finally, contact metals of 5Å Ti/300Å Pd/200Å Au were formed to
complete the CNFETs.

Fig 6. Device fabrication

14
3. Types of CNTFET:

There are many types of CNTFET devices; a general survey of the most common geometries is
covered below.

3.1 Types of CNTFET based on fabrication

Back Gated CNTFETs

The earliest techniques for fabricating carbon nanotube (CNT) field-effect transistors
involved pre-patterning parallel strips of metal across a silicon dioxide substrate, and then
depositing the CNTs on top in a random pattern.

Fig 7. Back Gated CNTFET

The semiconducting CNTs that happened to fall across two metal strips meet all the requirements
necessary for a rudimentary field-effect transistor. One metal strip is the "source" contact while
the other is the "drain" contact. The silicon oxide substrate can be used as the gate oxide and
adding a metal contact on the back makes the semiconducting CNT gateable.

This technique suffered from several drawbacks, which made for non-optimized
transistors. The first was the metal contact, which actually had very little contact to the CNT,
since the nanotube just lay on top of it and the contact area was therefore very small. Also, due to
the semiconducting nature of the CNT, a Schottky barrier forms at the metal-semiconductor
interface, increasing the contact resistance. The second drawback was due to the back-gate
device geometry. Its thickness made it difficult to switch the devices on and off using low
voltages, and the fabrication process led to poor contact between the gate dielectric and CNT.

Top- gated CNTFETs

Eventually, researchers migrated from the back-gate approach to a more advanced top-
gate fabrication process.[11] In the first step, single-walled carbon nanotubes are solution
deposited onto a silicon oxide substrate. Individual nanotubes are then located via atomic force
microscope or scanning electron microscope. After an individual tube is isolated, source and
drain contacts are defined and patterned using high resolution electron beam lithography. A high
temperature anneal step reduces the contact resistance by improving adhesion between the

15
contacts and CNT A thin top-gate dielectric is then deposited on top of the nanotube, either via
evaporation or atomic layer deposition. Finally, the top gate contact is deposited on the gate
dielectric, completing the process.

Fig 8. Top Gated CNTFET

Arrays of top-gated CNTFETs can be fabricated on the same wafer, since the gate
contacts are electrically isolated from each other, unlike in the back-gated case. Also, due to the
thinness of the gate dielectric, a larger electric field can be generated with respect to the
nanotube using a lower gate voltage. These advantages mean top-gated devices are generally
preferred over back-gated CNTFETs, despite their more complex fabrication process.
Wrap-around gate CNTFETs
Wrap-around gate CNTFETs, also known as gate-all-around CNTFETs were developed
in 2008,[12] and are a further improvement upon the top-gate device geometry. In this device,
instead of gating just the part of the CNT that is closer to the metal gate contact, the entire
circumference of the nanotube is gated. This should ideally improve the electrical performance
of the CNTFET, reducing leakage current and improving the device on/off ratio.

Fig 9. Wrap around gate CNTFET

16
 Device fabrication begins by first wrapping CNTs in a gate dielectric and gate contact via
atomic layer deposition These wrapped nanotubes are then solution-deposited on an insulating
substrate, where the wrappings are partially etched off, exposing the ends of the nanotube. The
source, drain, and gate contacts are then deposited onto the CNT ends and the metallic outer gate
wrapping.

Suspended CNTFETs
Yet another CNTFET device geometry involves suspending the nanotube over a trench to
reduce contact with the substrate and gate oxide. This technique has the advantage of reduced
scattering at the CNT-substrate interface, improving device performance. There are many
methods used to fabricate suspended CNTFETs, ranging from growing them over trenches using
catalyst particles, transferring them onto a substrate and then under-etching the dielectric
beneath,[16] and transfer-printing onto a trenched substrate.

Fig 10. Suspended CNTFET

The main problem suffered by suspended CNTFETs is that they have very limited material
options for use as a gate dielectric (generally air or vacuum), and applying a gate bias has the
effect of pulling the nanotube closer to the gate, which places an upper limit on how much the
nanotube can be gated. This technique will also only work for shorter nanotubes, as longer tubes
will flex in the middle and droop towards the gate, possibly making touching the metal contact
and shorting the device. In general, suspended CNTFETs are not practical for commercial
applications, but they can be useful for studying the intrinsic properties of clean nanotubes.

3.2 Types of CNTFET based on working:

There are two types of carbon-nanotube transistors that are being extensively studied in the
literature. The first one is a tunneling device, shown in Fig. 1(a), which works on the principle of
direct tunneling through a Schottky barrier (SB) at the source–channel junction. The barrier
width is modulated by application of the gate voltage so that the transconductance of the device
is dependent on the gate voltage. The main disadvantage of this technology is that the energy
barrier at SB actually restricts the transconductanceŒ1214• of the CNFET in the ON state and

17
reduces the current delivery capability, which is a significant metric to the speed of a device. SB-
CNFETs demonstrate strong ambipolar characteristics that restrict the usage of these devices in
CMOS-like logic families. This type of CNFET is appropriate for moderating high-performance
applications. To overcome the mentioned drawback associated with SB CNTFETs, there have
been attempts to develop CNTFETs that behave like normal MOSFETs but with a higher
performance.

Fig 11. SCNTFET and MCNTFET

Therefore, the Potassium doped source and drain CNT regions have been fabricated and unipolar
characteristics and the field-effect behavior have been reached. This type of CNFET is called a
MOSFET-like CNFET, shown in Fig 11. It operates on the principle of barrier height modulation
by application of the gate potential. Recently published experiment resultsŒ19• demonstrated
that, MOSFET like CNFETs devices are air-stable outside a vacuum or an inert environment and
also with much higher on/off ratios (Ion/Ioff/ (compared to the SBCNFETs). Further, SB-
CNFETs exhibit strong ambipolar characteristics and this constrains the use of these transistors
in conventional CMOS logic families. As a result, MOSFET-like CNFETs are very suitable for
ultra-high-performance digital applications.
Based on the mentioned advantage of the MOSFET-like CNFETs and also due to the further
resemblance with MOSFETs in terms of operation and characteristics, this type of CNFET is
utilized for designing proposed logic families. In this paper, we will consider the non-SB
MOSFET-like unipolar CNFET with ballistic transport as our device of interest. Hereafter, in
this paper, the word CNFET will be used to mean such a MOSFET-like device, unless otherwise
mentioned.
4. THEORETICAL BEHAVIOR OF CNTFET:
In this section, we discuss the theoretical background necessary for analyzing the effect of
variations of the CNFET technology parameters on important device and circuit performance
metrics, like the size of CNTFET (width of gate), threshold voltage (Vth), ON–OFF current ratio
(Ion/Ioff), transconductance, subthreshold slope (S), gate delay (td) and switching energy.

18
4.1 Size of CNTFET:
Figure 1(a) shows the schematic of a typical CNFET device. The distance between the centers of
two adjoining SWCNTs under the same gate of a CNFET is called the pitch, which directly
impacts the width of the gate and contacts of the device. The total size of the CNFET is
determined by the width of the gate. The gate width can be determined by the pitch. By setting
the minimum gate width Wmin and the number of tubes N, the gate width can be approximated
as

where Wmin is the minimum width of the gate and N is the number of nanotubes under the gate.
4.2 CNTFET threshold voltage:
To design a circuit with the best performance based on an average power consumption and
speed, it is very important to determine the threshold voltage because this affects the switching
speed, the current and leakage power. Similar to a MOSFET device, a CNFET also has a
threshold voltage which is the voltage required for turning ON the device electrostatically
through the gate. A great advantage of CNFET is that its threshold voltage can be adjusted by
changing the diameter of its CNTs. This practical characteristic makes CNFET more flexible
than MOSFET for designing digital circuits and makes it very suitable for designing multi-
threshold circuits. The threshold voltage of a CNFET is almost considered as the half band gap
and can be calculated by

= 1.506 nm
where a = 2.49 Å is the lattice constant. Since the band gap of semiconducting CNTs is
proportional to the diameter, then the threshold voltage of the intrinsic CNT channel can be
approximated to the first order as the half band gap (which is inversely proportional to the
diameter). By adjusting the diameter, the threshold voltage can be controlled and is given by

= 0.2788 V

19
4.3 Transconductance:
Transconductance (gm) is defined as the change in drain– source current with respect to the
corresponding change in gate–source voltage, as illustrated in below equation. It is a function of
the geometry of the device as well as of the carrier mobility and threshold voltage.

The transconductance of the CNFETs are calculated from the simulation work. The parameters
used are 2.0 nm insulator thickness, 1 nm CNT diameter and a temperature of 300 K, shows a
value of 5 105 S/m, which is much higher than the one presented by the 20 nm N-MOSFET.

4.4 Subthreshold Slope (SS):

The subthreshold slope (SS) is another important device design metric that determines the
relationship between the subthreshold leakage current and the gate voltage. It is defined as the
amount of Vgs required to change the subthreshold current by an order of magnitude. A small SS
is preferred for a higher ON current for a given OFF current value. From the definition of inverse
subthreshold slope, it can be expressed as

The value of S, which is theoretically limited to 60 mV/dec at T D 300 K, should be as small as

possible to ensure the steepest subthreshold characteristics.
4.5 Gate Delay:
The gate delay is translated as the amount of time starting from when the input to a logic gate
becomes stable and valid, to the time that the output of that logic gate is stable and valid. Often
this refers to the time required for the output to reach 50% of its final output level when the input
changes. In other words, the gate delay shows the speed of a device. It can be determined by
using the following equation. The delay of a CMOS gate may be expressed as

20
4.6 Dynamic Energy:
The energy delay product (EDP) shows the relationship between the total power consumption
and the speed of a device, which means that the lower EDP shows the better performance. The
EDP can be calculated by

5. OPTIMIZATION OF CNTFET DEVICE PARAMETERS:

The proposed CNTFET logic circuits are designed in terms of optimum structural device
parameters. The power dissipation and speed of CNFET devices are mainly governed by the
number of tubes in the channel (n), the diameter of the carbon nanotube (DCNT), and uniform
inter-nanotube spacing (Pitch, S). Hence, there is a need to explore the best possible values of
DCNT, the number of tubes in the channel (n) and the pitch (S) for better device and circuit
performance for a given tube diameter.

5.1 Choice of number of carbon tubes (N):

It is important to determine the number of CNTs to be used in an array in order to ensure a
sufficient current supply for driving fixed capacitive loads as a single nanotube based transistor
does not provide competitive performance over traditional silicon devicesŒ21; 22•. Therefore,
we need to choose the optimum value of „N‟ for a better current driving capability of CNFET
with reduced output resistance, thereby allowing a greater fan-out factor. From the analytical
results, it can be inferred that, the logic gate power delay product (PDP) value changes, which
occurs corresponding to the increase in the „N‟ value, as shown in Fig. 5(a). It is important to
investigate the problem associated with a large number of tubes in addition to the geometrical
constraints. Here, the current per tube IPERTUBE is constant owing to the non-varying „S‟ but
laying of more tubes increases the net width „W ‟ and the on-current approximately given by
below equation. This is due to the significant increase in transconductance with the increase in
the number of nanotubes. The increase in transconductance further increase the parasitic of the
devices. Hence, we chose an optimum value of „N‟ for each logic gate used, which is determined
by the minimum PDP value.

21
5.2 Choice of carbon nanotube diameter (DCNT):
CNFET circuit performance and electrical behavior directly depends on the CNT diameter. The
diameter is the main parameter that affects the on-current proportionally in a CNFET, apart from
the barrier height at the S/D contact (or RS/D), chirality and oxide thickness but for larger
diameters, current tends to saturate due to the large screening and scattering effects. From the
Analytical results, it can be inferred that, the logic gate PDP value changes occur corresponding
to an increase in the diameter of the nanotube. This is because the transconductance goes up with
the increase in diameter of the nanotubes. The logic gate PDP reduces with the diameter due to
the fact that the lowering of output resistance with the diameter is more than the increase in its
transconductance. The logic gate PDP is also affected severely with the increase in load
capacitance. Hence, for low loads such as 1 fF in deep sub-micron is better with unaltered PDP
performance. Therefore, we have chosen the optimum value of the diameter, with respect to the
low power application to be around chiral vector (19, 0) i.e. diameter of 1.5 nm. Moreover, a
slight shift could also be observed when choosing the optimize parameter over the other, such as
a chiral vector (22, 0) (i.e. a diameter of 2.0 nm) is best for high power applications.

5.3 Choice of inter nanotube spacing (S):

It is clear from below graph that with the increase in inter-tube spacing „S‟ (i.e. pitch), the logic
PDP values are almost constant. With larger spacing, the number of current carrying CNTs
decreases, thereby, reducing the universal density of states (DOS). This indirectly affects the
transconductance. From the plots of the graph, we inferred that the optimum inter-tube spacing
for each logic gate is around 12 nm. Beyond this value, one can increase the parasitic without
improving the ION current.

22
 Fig 12. CNT pitch vs PDP

6. SIMULATION OF FULL ADDER CIRCUIT IN HSPICE:

Fig 13. Full adder circuit

In this simulation the full-adder circuit used consists of Inverter, Xor gate, And gate and OR
gate. The circuit is designed in a similar way of CMOS technology so that Power, Delay and
PDP can be compared.

6.1 INVERTER:
In the inverter we have used four CNTs for P-type CNTFET and two CNTs for N-type CNTFET.

23
 Fig 14. INVERTER circuit
In fig.14, we can observe that there are no glitches and the output is perfect for the inverter for
both 1 to 0 and 0 to 1 transitions.

Fig 15. Output for INVERTER

24
6.2 AND gate:
For AND gate the above inverter along with the CMOS type NAND gate structure is used. The
number of CNTs used for all transistors except the inverter part is four.

Fig 16. AND gate

For and gate the output will be high or the capacitor at the output will be charge when all the
inputs are high.

Input A Input B Output

0 0 0

0 1 0

1 0 0

1 1 1

Table 1. Truth table for AND gate

It is observed that the output transitions are perfect without noise switching between 1 to 0 and 0
to 1 and also for either of the inputs both A and B.

25
 Fig 17. OUTPUT for AND

6.3 OR gate:
This gate is implemented using NOR gate and the Inerter. For P-CNTFET the number of CNT
used are four, and for that of N-CNTFET they are two.

Fig 18. OR gate

For OR gate the output will be high or the capacitor at the output will be charge when any of the
inputs are high.

26
 Input A Input B Output

0 0 0

0 1 1

1 0 1

1 1 1

Table 2. Truth table for OR gate

Fig 19. OUTPUT for OR

It is observed that the output transitions are perfect without noise switching between 1 to 0 and 0
to 1 and also for either of the inputs both A and B.

27
6.4 XOR gate:
We have used four CNTs for P-type CNTFET and two CNTs for N-type CNTFET and total of
just 8 transistors are used.

Fig 20. XOR gate

For XOR gate the output will be high or the capacitor at the output will be charge when any of
the inputs are high and not when all are high or low.

Input A Input B Output

0 0 0

0 1 1

1 0 1

1 1 0

Table 3. Truth table for XOR gate

28
 Fig 21. Output for XOR
It is observed that glitches are occuring only when all the inputs are either switching from 0 to 1
or from 1 to 0.
6.5 FULL ADDER CIRCUIT:

Fig 22. Full adder

The full adder circuit is a combination of two half adders made of XOR gate, OR gate and AND
gate.

29
 Input A Input B Carry _in Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Table 4 . Truth table for Full Adder

Fig 23. Output for full adder

From the table 5, it is observed that CNTFET can also work at 0.3V as the threshold
Voltage Vth is approximately 0.27V. It is also observed that at 0.3 V the power consumption is
very less for CNTFET and also it does not affect the current due to voltage. Thus it does not
affect the Fan-Out.

30
 Vdd = 0.3V Vdd = 0.5V Vdd = 0.9V

Time Average Time Average Time Average

PDP PDP PDP
delay power delay power delay power
(e-22) (e-22) (e-22)
(e-12) (e-11) (e-12) (e-11) (e-12) (e-11)

INVERTE
2.2115 4.3806 5.0483 3.0147 2.6364 11.435 28.06 2.328 120.53
R

AND 41.372 18.676 22.152 36.659 6.5202 41.372 131.78 3.4644 380.37

OR 32.561 16.45 19.680 36.737 6.232 58.946 98.277 3.356 292.84

XOR 79.706 17.264 46.169 66.113 6.582 100.44 389.57 4.1212 945.28

FULL
994.28 54.97 180.86 996.97 16.083 619.90 3435.6 9.5996 3578.9
ADDER

Table 5. PDP, Time delay and Average power comparison

The below graph shows the PDP average power and time delay of the full adder circuit for
different voltages at room temperature.

31
The assigned values shown in the code above are the default values (or global parameter value)
for the parameters.

Device
Description Default Value
Parameter
32.0nm (Set by global
Lch Physical channel length1.
parameter L_channel)
200.0nm (Set by
The mean free path in the intrinsic CNT channel
Lgeff global parameter
region due to non-ideal elastic scattering.
Lceff)
The length of doped CNT source-side extension 32.0nm (Set by global
Lss
region. parameter L_sd)
The length of doped CNT drain-side extension 32.0nm (Set by global
Ldd
region. parameter L_sd)
0.6 eV (Set by global
Efi The Fermi level of the doped S/D tube.
parameter Efo)
The dielectric constant of high-k top gate 16.0 (Set by global
Kgate
dielectric material (planer gate). parameter Kox)
The thickness of high-k top gate dielectric
Tox 4.0nm
material (planer gate).
The coupling capacitance between the channel 20.0pF/m (for a 10μm
Csub
region and the substrate (backgate effect). thick SiO2)
The coupling capacitance between channel region 0.0pF/m (Set by global
Ccsd
and source/drain region. parameter Ccsd)
The percentage of Ccsd that corresponds to the 0.0 (Set by global
CoupleRatio coupling capacitance between the channel and parameter
drain. CoupleRatio)
Flatband voltage for n-CNFET and p-CNFET,
Vfbn, Vfbp 0.0eV, 0.0eV
respectively.
The property of the drain-side output:
0: the drain output is connected to metal contact,
Dout 0
1: the drain output is connected to another CNFET
directly.
The property of the source-side output:
Sout 0: the source output is connected to metal contact, 0
1: the source output is connected to another

32
 CNFET directly.
The distance between the centers of two adjacent
Pitch 20.0nm
CNTs within the same device2.
6.4nm (set by global
Wgate The width of metal gate3.
parameter sub_pitch)
The position of CNT under the gate (only for
Uniform Models):
0: the tube is in the middle and sees two adjacent
CNTPos 1
neighbors,
1: the tube is at edge of the device and sees only 1
neighboring CNT.
(n1, n2) The chirality of tube4. (19, 0)
tubes The number of tubes in the device. 1
Table 6. Default values of the parameters

7. Results
Power (in E-11 watt), delay(in ps), and PDP (in E -22 watt-sec) are measured and
compared in 32nm for three different FET technologies i.e for CNTFET, CMOS and FINFET. It
is observed that FINFET has good characteristics compared to CMOS. But CNTFET has better
characteristics than FINFET. If compared with inverter the CNTFET(25.06) has PDP is 45 times
less than CMOS(1220), similarly for AND, OR, XOR. Finally for FULL- ADDER also the
CNTFET has power consumption 25 times less than CMOS and 3 times less than FINFET.
When delay is compared it also varies in a similar way. The main factor PDP is of great
advantage for large circuits using full adder as the CNTFET has 50 times less than CMOS and 5
times less than FINFET.

33
 power(E- delay pdp (E- power delay pdp (E- power delay Pdp (E
11) (ps) 22) (E-11) (ps) 22) (E-11) (ps) -22)
Cntfet cmos Finfet
inverter 120.53 2.328 28.06 7370 1.65 1220 641 2.81 181
and 380.37 3.4644 131.78 24100 59100 14200 1769 7.13 1260
or 292.84 3.356 98.277 14100 9.41 13300 1914 7.97 1520
xor 945.28 4.1212 389.57 37500 17.8 66800 2679 5.7 1520
Full
10827 15.47 16700
Adder 3578.9 9.5996 3435.6 88500 1970 174000

Table 7. Comparison of CNFET CMOS and FINFET

34
8. CONCLUSION:

In this paper we have compared the CNFET-based logic gates with the CMOS-based
logic gates, both simulated in 32-nm technology in HSPICE software using Stanford
University‟s CNFET HSPICE Model and BSIM PTM Model respectively. The simulations are
carried out at room temperature for different values of supply voltages i.e. 0.9V, 0.5V and 0.3V,
and performances are studied in terms of power, delay and PDP. The CNFET-based logic gates
show far better results as compared to those of CMOS-based logic gates.

35
9. FUTURE SCOPE :

Apart from gate level models of any circuits, transistor level circuits are observed to have
better performance and thus one of the proposed energy efficient Full Adder circuit is as follows.

36
 REFERENCES

1.Ali Ghorbani and Ghazaleh Ghorbani, Energy Efficient Full Adder cell design withusing
CNTFET in 32nm technology, International journal of VLSI design and comunication systems,
vol. 5, no. 5, October 2014.

2.K.Navi, M.Rashtian, A. Khatir, P.Keshavarzian and O. Hashemipour, Springer, Nanoscale

Res.Lett. 5, 859(2010). http://dx.doi.org/10.1007/s11671-010-9575-4

3.H.S. Philip Wong, Jie Deng, Arash, Hazeghi, Tejas krishna mohan, Gordon C.Wan, Centre for
intregated systems and Department of Electrical Enineering at Stanford
University(ICCAD,2006).

4.Jie Deng, H.S. Philip Wong, A Compact SPICE Model for CNTFETs including nonidealities
and its application-Part I: Model of intrinsic channel region. IEEE transactions on electron
devices , vol 54, no.12, DEC-2007.

5.Jie Deng, H.S. Philip Wong, A Compact SPICE Model for CNTFETs including nonidealities
and its application-Part II: Full device model and circuit performance benchmarking. IEEE
transactions on electron devices , vol 54, no.12, December 2007.

6.Raychowdhury A, Roy K. Carbon Nanotube Electronics: Design of High-Performance and

Low-Power Digital Circuits. Circuits and Systems I: Regular Papers, IEEE Transactions, Nov
2007; 54,11:2391-2401.

7.Raychowdhury A, Roy K. Carbon-Nanotube-Based Voltage-Mode Multiple-Valued Logic

Design.IEEE Trans. Nanotechnology, March 2005; 4, 2:168-179.

8.Navi K, Sharifi Rad R, Moaiyeri M H, Momeni A. A Low-Voltage and Energy-efficient Full

Adder Cell Based on Carbon Nanotube Technology. Nano Micro Letters, 2010; 2,2:114-120.

9.Navi K, Mohammad Hossein Moaiyeri, Mona Moradi and Reza Faghih Mirzaee. “An
Applicable High-Efficient CNTFET - Based Full Adder Cell for Practical Environments”. CSI
International Symposium on Computer Architecture and Digital Systems, 2012.

10. Sonal Shreya and Rajeevan Chandel. “Performance analysis of cntfet based digital logic
circuits”,IEEE-2014

11. B. Srinivasu and K. Sridharan. “Reliability analysis of full adder in Schottkey barrier
CNTFET technology”, International conference on nano technology, IEEE-2014

37

View publication stats