+

Chapter 3  A Top-Level View of Computer

 Function and Interconnection

William Stallings, Computer Organization and Architecture,9th Edition

+ Objectives
 What are main components of a computer?
 How are they connected?
 After studying this chapter, you should be able to:
 Understand the basic elements of an instruction cycle and
the role of interrupts.
 Describe the concept of interconnection within a computer
system.
 Understand the difference between synchronous and
asynchronous bus timing.
 Explain the need for multiple buses arranged in a
hierarchy.
 Assess the relative advantages of point-to-point
interconnection compared to bus interconnection.
+
Contents
 3.1- Computer Components
 3.2- Computer Function
 3.3- Interconnection Structures
 3.4- Bus Interconnection
+
3.1- Computer Components

 Contemporary (nowaday) computer designs are based on

concepts developed by John von Neumann at the Institute for
Advanced Studies, Princeton

 Referred to as the von Neumann architecture and is based

on three key concepts:
 Data and instructions are stored in a single read-write memory
 The contents of this memory are addressable by location,
without regard to the type of data contained there
 Execution occurs in a sequential fashion (unless explicitly
modified) from one instruction to the next

 Hardwired program
 The result of the process of connecting the various components in
the desired configuration
+
Hardware
and Software
Approaches
Software
• A sequence of codes or instructions Software
• Part of the hardware interprets each instruction and
generates control signals
• Provide a new sequence of codes for each new
program instead of rewiring the hardware

Major components: I/O

• CPU Components
• Instruction interpreter
• Module of general-purpose arithmetic and logic
functions
• I/O Components
+
• Input module
• Contains basic components for accepting data
and instructions and converting them into an
internal form of signals usable by the system
• Output module
• Means of reporting results
 Memory Memory buffer MEMORY
address register (MBR)
register (MAR) • Contains the data
• Specifies the to be written into
address in memory memory or
for the next read or receives the data
write read from memory

MAR

I/O address I/O buffer

register (I/OAR) register (I/OBR)
• Specifies a • Used for the
+ particular I/O exchange of data
device between an I/O
module and the
CPU MBR
 Computer
Components:
Top Level
View
+
3.2- Computer Function

Basic Instruction Cycle

+
Fetch Cycle
 At the beginning of each instruction cycle the processor
fetches an instruction from memory

 The program counter (PC) holds the address of the

instruction to be fetched next

 The processor increments the PC after each instruction

fetch so that it will fetch the next instruction in sequence

 The fetched instruction is loaded into the instruction

register (IR)

 The processor interprets the instruction and performs the

required action
+
Execute Cycle
 The CPU decodes and performs the corresponding actions
response specified in the instruction code (Opcode)

 These actions fall into four categories:

 Processor-memory

 Processor-I/O

 Data processing

 Control
 Action Categories

• Data transferred • Data transferred to or

from processor to from a peripheral
memory or from device by
memory to transferring between
processor the processor and an
I/O module
Processor- Processor-
memory I/O

Data
Control
processing

• An instruction may • The processor may

specify that the perform some
sequence of arithmetic or logic
execution be altered operation on data
+ Instruction structure:

Opcode 4 bits  16 actions

Máy giả định

 + Example
of
Program
Execution

1940(h)
1: 0001  Load AC from memory
940(h)  Data address
5941(h)
5: 0101  Add to AC from memory
941(h)
2: 0010Store AC to memory
 Add 2 memory cell at addresses
940, 941. The result is stored at 941
+
Instruction Cycle State Diagram

begin
+ Classes of Interrupts
Virtually all computers provide a mechanism by which other
modules (I/O, memory) may interrupt the normal processing
of the processor. An interrupt can be caused by:
Program Flow Control
+ Transfer of Control via Interrupts
+ Instruction Cycle With Interrupts
+

Program
Timing:
Short I/O
Wait
+

Program
Timing:
Long I/O
Wait
Instruction Cycle State Diagram
With Interrupts
 Transfer of
Control

Multiple
Interrupts

+
+ Time Sequence of E me
x p
Multiple Interrupts a l
+
I/O Function
 I/O module can exchange data directly with the processor

 Processor can read data from or write data to an I/O module

 Processor identifies a specific device that is controlled by a
particular I/O module
 I/O instructions rather than memory referencing instructions

 In some cases it is desirable to allow I/O exchanges to occur

directly with memory
 The processor grants to an I/O module the authority to read from
or write to memory so that the I/O memory transfer can occur
without tying up the processor
 The I/O module issues read or write commands to memory
relieving (làm giảm nhẹ) the processor of responsibility for the
exchange
 This operation is known as direct memory access (DMA)
+ 3.3-
Interconne_
ction
Structures
The interconnection structure must support the
following types of transfers:

Memory Processor I/O to or

I/O to Processor
to to from
processor to I/O
processor memory memory

An I/O
module is
allowed to
exchange
data
Processor Processor
directly
reads an Processor reads data Processor
with
instruction writes a from an I/O sends data
memory
or a unit of unit of data device via to the I/O
without
data from to memory an I/O device
going
memory module
through the
processor
using direct
memory
access
A communication pathway Signals transmitted by any
connecting two or more one device are available for
devices
• Key characteristic is that it is a
reception by all other
devices attached to the bus 3.4-
shared transmission medium • If two devices transmit during the
same time period their signals will
overlap and become garbled
Bus
Inter-
Typically consists of multiple
conne
communication lines Computer systems contain a
• Each line is capable of
transmitting signals representing
number of different buses
that provide pathways ction
binary 1 and binary 0 between components at
various levels of the
computer system hierarchy

System bus
• A bus that connects major The most common computer
computer components (processor,
memory, I/O) interconnection structures
are based on the use of one
or more system buses
Data Bus
 Data lines that provide a path for moving data among system
modules

 May consist of 32, 64, 128, or more separate lines

 The number of lines is referred to as the width of the data bus

 The number of lines determines how many bits can be

transferred at a time

 The width of the data bus

is a key factor in
determining overall
system performance
+ Address Bus Control Bus

 Used to designate the source or  Used to control the accessand the use of
destination of the data on the the data and address lines
data bus
 If the processor wishes to
read a word of data from  Because the data and address lines are
memory it puts the address of shared by all components there must be
the desired word on the a means of controlling their use
address lines
 Control signals transmit both command
 Width determines the maximum
possible memory capacity of the and timing information among system
system modules

 Also used to address I/O ports  Timing signals indicate the validity of
 The higher order bits are data and address information
used to select a particular
module on the bus and the  Command signals specify operations to
lower order bits select a
memory location or I/O port be performed
within the module
Bus Interconnection Scheme
Fig. 3.17- Example Bus Configuration
Fig. 3.17- Example Bus Configuration
+ Elements of Bus Design

Dedicated: chuyên dụng, multiplex: đa thành phần

Synchronous- đồng bộ- At a time, only one device can uses the bus. The others must
wait until the bus is idle.
Arbitration: phân xử, quản lý
Asynchronous- không đồng bộ- At a time, some devices can use the bus concurrently
 Timing of
Synchronous
Bus
Operations
 Timing of
Asynchronous
Bus
Operations
+
Questions
(Write answers to your notebook)

 3.1 What general categories of functions are specified by

computer instructions?

 3.2 List and briefly define the possible states that define an
instruction execution.

 3.3 List and briefly define two approaches to dealing with

multiple interrupts.

 3.4 What types of transfers must a computer’s interconnection

structure (e.g., bus) support?

 3.5 What is the benefit of using a multiple-bus architecture

compared to a single-bus architecture?
+
Read by yourself

 3.5- Point-to-Point Interconnect

 3.6- PCI Express

+ Summary A Top-Level View of
Computer Function
and Interconnection
Chapter 3

 Computer components
 Computer function
 Instruction fetch and
execute
 Interrupts
 I/O function
 Interconnection structures
 Bus interconnection
 Bus structure
 Multiple bus hierarchies
 Elements of bus design