Embedded Low-Power
Embedded System
Application
4190.303C
Laboratory
2010 Spring Semester
ROMs, Non-volatile and Flash Memories
ELPL
Naehyuck Chang
Dept. of EECS/CSE
Seoul National University
naehyuck@snu.ac.kr
Revisit Previous Issues
DRAM Bitlines
Bitline (BL) is driven by the cell
Bitline inversion (BLB) is not driven (reference)
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Types of Memory Arrays
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Magnetic Core Memory
Non-volatile main memory
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Diode ROM
Wang 144-T Scientific Calculator
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Read-Only Memory Cells
BL BL BL
VDD
WL
1 WL WL
BL BL BL
WL WL
0 WL
GND
Diode ROM MOS ROM 1 MOS ROM 2
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MOS OR ROM
Pulling up with NMOS transistors is not a good idea
BL [0] BL [1] BL[2] BL [3]
WL[0]
VDD
WL [1]
WL [2]
VDD
WL [3]
Vbias
Pull-down loads
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MOS NOR ROM
Default wordline value is low
Pseudo NOS setup with PMOS pull-ups
V
DD
Pull-up devices
WL[0]
GND
WL[1]
WL[2]
GND
WL[3]
BL [0] BL [1] BL [2] BL [3]
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MOS NOR ROM
Equivalent Transient Model for a MOS NOR ROM
Word line parasitics
Wire capacitance and gate capacitance
Wire resistance (polysilicon)
Bit line parasitics
Resistance is not dominant (metal)
Drain and gate-drain capacitance
VDD
BL
Rword
WL Cbit
Cword
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MOS NOR ROM
MOS NOR ROM Layout
Programming using the active layer only
Cell (9.5λ x 7λ)
Polysilicon
Metal1
Diffusion
Metal1 on diffusion
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MOS NOR ROM
MOS NOR ROM Layout
Programming using the contact layer only
Cell (11λ x 7λ)
Polysilicon
Metal 1
Diffusion
Metal1 on diffusion
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MOS NAND ROM
All word lines high by default with exception of selected row
V DD
Pull-up devices
BL [0] BL [1] BL [2] BL [3]
WL [0]
WL [1]
WL [2]
WL [3]
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MOS NAND ROM
Equivalent Transient Model for MOS NAND ROM
Word line parasitics
Similar to NOR ROM
Bit line parasitics
Resistance of cascaded transistors dominates
Drain/source and complete gate capacitance
V DD
BL
CL
Rbit
Rword Cbit
WL
Cword
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MOS NAND ROM
MOS NAND ROM Layout
Programming using the metal1 layer only
Cell (8λ x 7λ)
No contact to VDD or GND necessary;
drastically reduced cell size
Loss in performance compared to NOR ROM
Polysilicon
Diffusion
Metal1 on Diffusion
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MOS NAND ROM
MOS NAND ROM Layout
Programming using implants only
Cell (5λ x 6λ)
Polysilicon
Threshold-altering
implant
Metal1 on Diffusion
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Precharged MOS NOR ROM
PMOS precharge device can be made as large as necessary, but clock driver becomes
harder to design
f V DD
pre
Precharge devices
WL [0]
GND
WL [1]
WL [2]
GND
WL [3]
BL [0] BL [1] BL [2] BL [3]
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Non-Volatile Memory History
MRAM, Phase
Change, Polymer
2000’s
Ferro-electric
1988
Nitride
Storage
2002
MLC NOR Flash
1995
NOR Flash
1988
AND, DiNOR Flash
1990’s
EPROM
1971
MLC NAND Flash
1996
NAND Flash
1985
EEPROM
Bipolar ROMS/PROMS
1980
Late 60’s
1970 1980 1990 2000
MLC = Multi-Level Cell
ELPL
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Floating Gate Transistor
D
POLY2
Tunnel Oxide CONTROL GATE
FG
POLY1
FLOATING GATE CG
N+ SOURCE N+ DRAIN
P-WELL
Deep N-Well
P-Substrate
S
Stacked gate NMOS transistor
Poly1 floating gate for charge storage
Poly2 control gate for accessing the transistor
Tunnel-oxide for gate oxide
Oxide-nitride-oxide (ONO) for the inter poly dielectric
Source/drain junctions optimized for program/erase/leakage
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Floating Gate Transistor
Programming = Electrons Stored on the FG = High Vt
Erasing = Remove electrons from the FG = Low Vt
Threshold Voltage shift = ΔQFG/CCG
Stored
Electrons
“1” “0”
Ids
Erased
“1” Programmed
“0”
Vcg
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UV EPROM
Programming flowchart
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UV EPROM
UV version and OTP version
Package and window difference
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UV EPROM
To erase a chip, it is removed from its socket on the system board and placed in EPROM
erasure equipment to expose it to UV radiation for 15 - 20 minutes
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Hot Electron Effect
NOR flash programming
Channel hot electron programming - gate voltage inverts channel; drain voltage accelerates
electrons towards drain; gate voltage pulls them to the floating gate
In lucky electron model, electron crosses channel without collision, gaining > 3.2eV, hits Si atom,
bounces over barrier
Program Time ~ 0.5 - 1 ms
Program current ~ 50 mA/cell
10V “Lucky” Electron
Ec Vgate = 10V
9
Ev 8
0V 5V Substrate 7 Vd=3.0V
6 Vd=3.25V
Vt (V)
5 Vd=3.5V
NN++ NN+ + 4 Vd=3.75V
Ec
Channel
3 Vd=4.0V
P-Well Ev 2
Floating
1
Gate
Program 1.E-07 1.E-06 1.E-05 1.E-04
0V Time (s)
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Fowler Nordheim Tunneling (FN-t)
NAND flash programming
Tunnel programming from channel by biasing the top gate positive with respect to the ground
Program Time ~ 300 µs
Program current ~ displacement plus tunneling current
Low current allows large parallelism
20V
Ec
0V 0V
Ev
Floating
Channel Gate
N+ N+
P-well
Ec
“0”-Program Ev
Y. S. Yim, et al. IEDM 2003
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Characteristics of NVM Devices
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Comparison with NAND and NOR Flash
NOR and NAND operations
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Comparison with NAND and NOR Flash
Cell array architecture
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Comparison with NAND and NOR Flash
Basic program operation of a NOR flash
Basic read operation of a NOR flash
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Comparison with NAND and NOR Flash
NOR
Direct access to bitline little parasitic resistance
Cell current directly discharges bitline capacitance
Fast initial random read access
NAND
Indirect access to bitline parasitic resistance from neighbor cells
Cell current indirectly discharges bitline capacitance through large resistor
Slow initial access
Both have wide read
Page access
NOR: fast transistor = high read performance
NAND: architected for lowest cost = slow transistors = low read performance
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Comparison with NAND and NOR Flash
Cell size
NAND ~5λ2
NOR ~10λ2
Both capable of multi-level cells
NOR read latency = 10’s of nSec
NAND read latency = 1-10’s of µSec
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Comparison with NAND and NOR Flash
Applications
Data storage for digital cameras, MP3 players, USB drive, etc.)
Code storage for PDA, cell phones, etc.
Pros and cons
NOR XIP (execution-in-place) and high price
NAND low price and shadow RAM requirement
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Comparison with NAND and NOR Flash
Required pinouts
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Comparison with NAND and NOR Flash
Performance comparison
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Comparison with NAND and NOR Flash
Summary of characteristics
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More About NAND Flash
Market size
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More About NAND Flash
Market share by products
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More About NAND Flash
NAND flash architecture
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More About NAND Flash
Command cycle
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More About NAND Flash
Command and address cycles
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More About NAND Flash
Erase cycle
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More About NAND Flash
Program command
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Multi-Level-Cell (MLC) Flash
Same cell holds digital information of
more than one bit
Use sophisticated circuit to store a
“11” “01” “00” “10”
controlled amount of charge Ids
Use complex sensing mechanism to sense
four levels of Vth
Noise immunity reduced
Vcg
Scalability reduced
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Multi-Level-Cell (MLC) Flash
SLC Take advantage of the threshold voltage
difference between the erased and
programmed states of the single-level-cell
case
Two levels = 1 bit/cell
Four levels = 2 bits/cell
In general: n bits/cell = log2 (#levels)
Need additional reference cells for program/
read
One read reference cell for 1 bit/cell
Three read reference cells for 2bits/cell
N-1 reference cells for n bits/cell
Corresponding reference cells for program
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Multi-Level-Cell (MLC) Flash
SLC Take advantage of the threshold voltage
difference between the erased and
programmed states of the single-level-cell
case
Two levels = 1 bit/cell
Four levels = 2 bits/cell
In general: n bits/cell = log2 (#levels)
Need additional reference cells for program/
read
One read reference cell for 1 bit/cell
MLC Three read reference cells for 2bits/cell
N-1 reference cells for n bits/cell
Corresponding reference cells for program
Count
11 10 01 00
R1 P1 R2 P2 R3 P3
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Multi-Level-Cell (MLC) Flash
Why do MLC?
Cost
Effectively cuts cell area per bit in half
Provides the same cost improvement from an array area perspective as a litho generation
Three key MLC considerations
Precise charge placement (Programming)
Cell programming must be accurately controlled, which requires a detailed understanding of cell physics,
voltage control and timing
Precision voltage generation for stable wordline and drain voltage
Precise charge sensing (Read)
MLC read operation is an analog to digital conversion of the charge stored in the cell
Device and capacitance matching, collapsing sources of variation, precision wordline and drain voltage
generation, Low current sensing
Stable charge storage
Leakage rate needs to be less than one electron per day
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Multi-Level-Cell (MLC) Flash
SLC and MLC performance difference
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OneNAND
Architecture
Add three SRAM blocks instead of data registers
Add SRAM interface for the random access to the SRAM blocks
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OneNAND
Buffer RAM
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OneNAND
Applications
Aiming at elimination of a NOR flash for booting
Necessary boot code is provided by the buffer RAM with XIP
Preserving the shadowing scheme
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FTL (Flash Translation Layer)
A software layer emulating standard block device interface Read/Write
Features
Sector mapping
Garbage collection
Power-off recovery
Bad block management
Wear-leveling
Error correction code (ECC)
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FTL (Flash Translation Layer)
Garbage collection is performed when a virtual block is full, or the number of free pages in
the whole device is lower than a specified threshold value
The virtual blocks meeting the conditions are selected for erasure
The valid physical pages are copied into a free area
The selected physical blocks are erased
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FTL (Flash Translation Layer)
Wear leveling
Expected NAND flash lifetime
If the application writes at 3 Kbyte/s
Wear Leveling extends the lifetime of NAND flash devices because it ensures that even if an
application writes to the same virtual blocks over and over again, the program/erase cycles will be
distributed evenly over the NAND flash memory
Block Aging Table (BAT) to remember which blocks have been erased in a selected period of time
Dynamic Wear Leveling
Static Wear Leveling
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FTL (Flash Translation Layer)
Wear leveling
Dynamic Wear Leveling
New data is programmed to the free blocks, among the ones used to store user data, that have had the fewest
write/erase cycles
Static Wear Leveling
Storing long-lived data (for example, code) are involved and their content is copied to another block so that the
original block can be used for more frequently-changed data
Triggered when the difference between the maximum and the minimum number of write/erase cycles per block
reaches a specific threshold
With this particular technique, the mean age of physical NAND blocks is maintained constant
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FTL (Flash Translation Layer)
Bad block management (BBM)
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FTL (Flash Translation Layer)
Bad block management (BBM)
Skip block method
Creates the Bad Block Table and when the target address corresponds to a Bad Block address, the data is
stored in the next good block, skipping the Bad Block
Reserved block method
Replaced by good blocks by “re-directing” the Flash Translation Layer to a known good block
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Modern Nonvolatile Memory Devices
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Modern Nonvolatile Memory Devices
MRAM and FRAM technology forecast
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Modern Nonvolatile Memory Devices
FRAM (Ferroelectric RAM)
FRAM is a random access memory similar in construction to DRAM
Uses a ferroelectric layer instead of a dielectric layer to achieve non-volatility
B GND
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Modern Nonvolatile Memory Devices
FRAM hysteresis curve
Binary state 0
Positive electric field
Positive polarization
Binary state 1
Negative electric field
Negative polarization
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Modern Nonvolatile Memory Devices
PRAM (Phase Change RAM)
PRAM uses the unique behavior of chalcogenide glass
Chalcogenide glass can be “switched” between two states, crystalline and amorphous, wit the
application of heat
GND
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Modern Nonvolatile Memory Devices
Chalcogenide material
Chalcogenide is the general class of switching media in CD-RW and DVD-RW
Laser beam energy is used to control the switching between crystalline and amorphous phase
Low energy laser beam to read
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Modern Nonvolatile Memory Devices
MRAM (Magnetoresistive RAM)
Data is not stored as electric
charge or current flows, but by
magnetic storage elements
The elements are formed from
two ferromagnetic plates
Each of plates can hold a
magnetic filed, separated by a
thin insulating layer
GND
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Modern Nonvolatile Memory Devices
MRAM (Magnetoresistive RAM)
Parallel magnetization
→ Low R
Ferromagnetic film
Anti-parallel magnetization
→ High R Thin insulator
Ferromagnetic film
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Modern Nonvolatile Memory Devices
Comparisons of major silicon memories
DRAM SRAM NAND NOR FRAM PRAM
Cell size 2 6 1 4 5 2
Latency 2 1 6 5 2 4
Data rate 2 1 4 5 2 6
Low Vcc 2 1 6 5 2 3
Non-volatility X X O O O O
Endurance 1 1 6 6 2 3
High density 2 6 1 3 6 2
1 ← best worst → 6
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NV Memory Future
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NV Memory Future
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