Clocks and Timers-Sources & Controls-2
Clocks and Timers-Sources & Controls-2
Introduction
Timers are often thought of as the heartbeat of an embedded system. Whether you need a
periodic wake-up call, a one-time delay, or need a means to verify that the system is running
without failure, Timers are the solution.
MSP430’s TIMER_A module. Not only does it provide rudimentary counting/timing features,
but provides sophisticated capture and compare features that allow a variety of complex
waveforms – or interrupts – to be generated. In fact, this timer can even generate PWM (pulse
width modulation) signals.
Timers of MSP430
MSP430 series chips have two types of Timers known as Timer_A and Timer_B. Both of them
are 16 bit timers with several capture compare channels and selectable clock sources.
Timer_B is slightly complex than Timer_A and offers more extensive interrupt capabilities and
capture compare channels.
MSP430Gxxx series chips that ship with Launchpad development board usually have two
Timer_A modules named as Timer0_A3 and Timer1_A3.Here A3 indicates the number of
Capture Compare registers (here 3 registers) available in each timer.Timer A is a 16 bit
Timer/Counter with 3 capture compare registers.
SMCLK is an internal clock generally taken from DCO (Digitally Controlled Oscillator) and is in
the Megahertz range. The DCO clock is temperature dependent and may change depending
upon temperature.
ACLK is an internal clock taken either from VLO or an external 32KHz clock crystal connected
to the MSP430.ACLK when taken from an external clock crystal is usually stable and do not
change with temperature. The ACLK frequency is usually in Kilo hertz range (32KHz).
TACLK and INCLK are external clocks that can be connected to MSP430 through external pins.
TASSELx bits are used to select the required clock to the 16 bit Timer register and IDx bits are
used to select clock divider which are present in the TACTL register.
The 16 bit Timer A register(TAR) starts counting on the positive edge of the clock. TAR can be
cleared by setting the TACLR bit to 1.
Timer A Operating Modes
Timer_A has 4 operating modes selected by the MCx bits in TACTL register.
Up Mode
User has to load count in TA0CCR0 register. The timer register TAR starts incrementing from
0 after each clock cycle and compares its value continuously with value of TACCR0 register.
When the TAR register value equals TACCR0, the TAR register rolls back to 0 and the timer
restarts counting from zero. The TAIFG interrupt flag is set when the TAR count is roll back to
zero. This process is repeated continuously.
Continuous Mode
The timer register TAR starts increments from 0 after each clock cycle and compares its value
continuously with FFFF H. When the TAR register value equals to FFFF H, the TAR register roll
back to value 0 and the timer restarts counting from zero. The TAIFG interrupt flag is set when
the TAR count is roll back to zero. This process is repeated continuously. When TACCR0 is
modified while running, the timer counts up to the new period and if the new period is less
than the current count value.
Up/Down Mode
User has to load count in TA0CCR0 register. The timer repeatedly counts up to the value of
compare register TACCR0 and back down to zero. The period is twice the value in TACCR0.
The TACCR0 CCIFG interrupt flag and the TAIFG interrupt flag are set only once during a
period, separated by 1/2 the timer period. The TACCR0 CCIFG interrupt flag is set when the
timer counts from TACCR0−1 to TACCR0, and TAIFG is set when the timer completes counting
down from 0001h to 0000h
Timer_A Registers
TACTL Register
IDx (Bits 7-6): Input divider. These bits select the divider for the input clock.
• 00 /1
• 01 /2
• 10 /4
• 11 /8
Timer A Interrupts
Two interrupt vectors are associated with the 16-bit Timer_A module one for TACCR0 and the
other for rest of the channels as well as the Timer overflow (TAIFG):
TACCR0 interrupt vector for TACCR0 CCIFG
TAIV interrupt vector for all other CCIFG flags and TAIFG
In capture mode any CCIFG flag is set when a timer value is captured in the associated TACCRx
register.
The register TACCR0 has a separate vector location which has a higher priority compared to
the other timer interrupts.
Rest of the capture compare channels (CCR1 and CCR2) along with the Timer overflow (TAIFG)
are given separate vector location. Since all of them are combined together the interrupt
vector register TAIV is used to determine which flag requested an interrupt.
In compare mode, any CCIFG flag is set if TAR counts to the associated TACCRx value. Software
may also set or clear any CCIFG flag. All CCIFG flags request an interrupt when their
corresponding CCIE bit and the GIE bit are set.
Example Code to to blink an LED connected to P1.0 of MSP430G2553 (Launchpad board)
whenever TAR overflows
#include "msp430g2553.h"
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop the WDT
// Port Configuration
P1DIR |= BIT0; // P1.0 output
P1OUT &= ~BIT0; // P1.0 = 0
// Timer 0 Configuration
TACTL |= MC_0; // Stop Timer0_A3
TACTL = TASSEL_1 + ID_2 + TAIE;// ACLK,ACLK/4,enable TAR interrupt
TACTL |= MC_2; // Start Timer0 in Continuous Mode
When the Timer register counts and reaches the value 10000, CCR0 interrupt is triggered and
the program control goes to the CCR0 interrupt routine of Timer 0. You can then lit up an LED
or do something.
#pragma vector = TIMER0_A0_VECTOR //CCR0 interrupt vector
__interrupt void CCR0_Interrupt(void)
{
P1OUT ^= BIT0; //toggle an LED
}
When TAR reaches the count = 30000 the CCR1 interrupt is triggered, CCR2 interrupt is
triggered at 40000 and finally the timer overflow (TAIFG) is triggered as TAR rolls over.