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DM7473 Dual Master-Slave J-K Flip-Flops With Clear and Complementary Outputs

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Abhishek Vishwakarma

Device contains two independent positive pulse triggered J-K flip-flops. Logic states of The J and K inputs must not change while the clock is HIGH. A LOW logic level on the clear input will reset the outputs.

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DM7473 Dual Master-Slave J-K Flip-Flops With Clear and Complementary Outputs

Uploaded by

Abhishek Vishwakarma
51 views4 pages
Device contains two independent positive pulse triggered J-K flip-flops. Logic states of The J and K inputs must not change while the clock is HIGH. A LOW logic level on the clear input will reset the outputs.

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DM7473

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© Attribution Non-Commercial (BY-NC)

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Device contains two independent positive pulse triggered J-K flip-flops. Logic states of The J and K inputs must not change while the clock is HIGH. A LOW logic level on the clear input will reset the outputs.

Copyright:

Attribution Non-Commercial (BY-NC)
Download as PDF, TXT or read online from Scribd
Download as pdf or txt
51 views4 pages

DM7473 Dual Master-Slave J-K Flip-Flops With Clear and Complementary Outputs

Uploaded by

Abhishek Vishwakarma
Device contains two independent positive pulse triggered J-K flip-flops. Logic states of The J and K inputs must not change while the clock is HIGH. A LOW logic level on the clear input will reset the outputs.

Copyright:

Attribution Non-Commercial (BY-NC)
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DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

September 1986 Revised July 2001

DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
General Description
This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops after a complete clock pulse. While the clock is LOW the slave is isolated from the master. On the positive transition of the clock, the data from the J and K inputs is transferred to the master. While the clock is HIGH the J and K inputs are disabled. On the negative transition of the clock, the data from the master is transferred to the slave. The logic states of the J and K inputs must not be allowed to change while the clock is HIGH. Data transfers to the outputs on the falling edge of the clock pulse. A LOW logic level on the clear input will reset the outputs regardless of the logic states of the other inputs.

Ordering Code:
Order Number DM7473N Package Number N14A Package Description 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Connection Diagram

Function Table
Inputs CLR L H H H H CLK J X L H L H K X L L H H Q L Q0 H L Toggle Outputs Q H Q0 L H

H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level = Positive pulse data. the J and K inputs must be held constant while the clock is HIGH. Data is transferred to the outputs on the falling edge of the clock pulse. Q0 = The output logic level before the indicated input conditions were established. Toggle = Each output changes to the complement of its previous level on each HIGH level clock pulse.

2001 Fairchild Semiconductor Corporation

DS006525

www.fairchildsemi.com

DM7473

Absolute Maximum Ratings(Note 1)


Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 5.5V 0C to +70C
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.

65C to +150C

Recommended Operating Conditions


Symbol VCC VIH VIL IOH IOL fCLK tW Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency (Note 3) Pulse Width (Note 3) tSU tH TA Clock HIGH Clock LOW Clear LOW Input Setup Time (Note 2)(Note 3) Input Hold Time (Note 2)(Note 3) Free Air Operating Temperature 0 20 47 25 0 0 0 70 ns ns ns Min 4.75 2 0.8 Nom 5 Max 5.25 Units V V V mA mA MHz

0.4
16 15

Note 2: The symbol (, ) indicates the edge of the clock pulse is used for reference: () for rising edge, () for falling edge. Note 3: TA = 25C and V CC = 5V.

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI VOH VOL II IIH Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage HIGH Level Input Current IIL LOW Level Input Current IOS ICC Short Circuit Output Current Supply Current VCC = Min, II = 12 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIH = Min, VIL = Max VCC = Max VI = 2.4V VCC = Max VI = 0.4V VCC = Max (Note 5) VCC = Max, (Note 6) J, K Clock Clear J, K Clock Clear 18 18 2.4 3.4 0.2 0.4 1 40 80 80 1.6 3.2 3.2 55 34 mA mA mA A Min Typ (Note 4) Max 1.5 Units V V V mA

Input Current @ Max Input Voltage VCC = Max, VI = 5.5V

Note 4: All typicals are at VCC = 5V, TA = 25C. Note 5: Not more than one output should be shorted at a time. Note 6: With all outputs OPEN, ICC is measured with the Q and Q outputs HIGH in turn. At the time of measurement the clock input grounded.

Switching Characteristics
Symbol fMAX tPHL tPLH tPHL tPLH Parameter Maximum Clock Frequency

at VCC = 5V and TA = 25C


From (Input) To (Output) RL = 400, CL = 15 pF Min 15 Clear to Q Clear to Q Clock to Q or Q Clock to Q or Q 40 25 40 25 Max MHz ns ns ns ns Units

Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output

www.fairchildsemi.com

DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 3 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

www.fairchildsemi.com

This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.

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