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Combinational Logic-Part2

This document discusses multi-bit buses and their usage in hardware description languages. It explains how arrays of bits can be manipulated together as buses. Addition of two 16-bit numbers is provided as an example, where the bitwise additions are done in parallel but the carry propagation is sequential. Various gates and adders are implemented using buses, including 16-bit NOT, AND, and OR gates as well as a 16-bit parallel adder. The benefits and drawbacks of ripple carry adders are also covered.

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21 views19 pages

Combinational Logic-Part2

This document discusses multi-bit buses and their usage in hardware description languages. It explains how arrays of bits can be manipulated together as buses. Addition of two 16-bit numbers is provided as an example, where the bitwise additions are done in parallel but the carry propagation is sequential. Various gates and adders are implemented using buses, including 16-bit NOT, AND, and OR gates as well as a 16-bit parallel adder. The benefits and drawbacks of ripple carry adders are also covered.

Uploaded by

sarangoudsai
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Elements of Computing Systems-1

Combinational Logic (Part 2)

Dr. Jyothish Lal G, Assistant Professor (Sr. Gr)


Department of AI / Center for Computational Engineering and Networking (CEN)
Amrita School of AI, Coimbatore
Acknowledgment: Prof. Noam Nisan, Prof. Shimon Schocken
Multi-bit Buses

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 2


Arrays of bits
• Manipulate array of bits together
• We conceptually think such groups as a single entity, termed bus
• HDL has a convenient notion for representing bus

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 3


Example : Addition of two 16 bit numbers

• The bitwise additions are done in parallel


• The carry propagation is sequential

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 4


Buses in HDL

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 5


Using buses in HDL

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 6


Using buses in HDL

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 7


Working with bits in buses: Example 1

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 8


Working with bits in buses: Example 2

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 9


Relevant bus tips

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 10


Relevant bus tips

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 11


Hack exercises
• Implement 16 bit variants of
– NOT gate (chip name chip name in project folder : Not16)
16-bit bitwise NOT
– AND gate (chip name chip name in project folder : And16)
16-bit bitwise AND
– OR gate (chip name chip name in project folder : Or16)
16-bit bitwise OR
• Implement multi-way variant
– Or8way (ie, OR together all 8 bits of the input)

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 12


Parallel Adder Design
• Various designs of n-bit parallel adder
– Ripple carry adder
– Carry look-ahead adder

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 13


Ripple carry adder
• Cascade n full adders to create a n-bit parallel adder
• Carry output from ith stage propagates as carry input to (i+1)th
stage

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 14


Important note :
4 bit binary parallel adder can be constructed
✓By using 4 full adders with input carry for LSB full adder as zero
Or
✓By using 3 full adders and one half adder

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 15


4 bit Parallel Adder :HDL code

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 16


Hack exercise
• Implement 4-bit parallel adder
• Implement 16-bit parallel adder (chip name in
project folder: Add16)

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 17


Drawback of Ripple carry adder
• The main bottleneck is the carry, which
propagates sequentially from one stage to the
next
• How this can be overcome ?
– Generate all the carry bits in parallel before the
addition starts
– All the addition can be done parallel

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 18


Thank You

|EOC-1|B.TECH CSE (AI)|CEN|Dr. Jyothish 19

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