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Sequential Logic Circuits Guide

This document contains 9 questions about sequential logic circuits including flip flops, counters, and their applications. Question 1 covers NAND latches and their operation. Question 2 covers D flip flops and their truth tables and output waveforms. Question 3 covers JK flip flops, their truth tables, and output waveforms. The remaining questions cover applications of JK and D flip flops in counters including asynchronous and synchronous up/down counters with various counting sequences and state diagrams.

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Wan Aleeya
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67 views2 pages

Sequential Logic Circuits Guide

This document contains 9 questions about sequential logic circuits including flip flops, counters, and their applications. Question 1 covers NAND latches and their operation. Question 2 covers D flip flops and their truth tables and output waveforms. Question 3 covers JK flip flops, their truth tables, and output waveforms. The remaining questions cover applications of JK and D flip flops in counters including asynchronous and synchronous up/down counters with various counting sequences and state diagrams.

Uploaded by

Wan Aleeya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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DBV30023

SEQUENTIAL LOGIC CIRCUITS 1


Q4. Determine the output waveform Q and Q in figure 3 from the JK Flip Flop
Q1. Latches is the basic flip flop circuit that can be constructed from two NAND circuit in figure 4 (Assume J=K=1 and Q initial =1)
Gates
(a) Draw the NAND Latch Circuit
(b) Explain NAND Latch Operation
(c) Construct NAND Latch Truth Table

Q2. Referring to the figure 1,


(a) Write the truth table for D Flip Flop
(b) Draw the output waveform Q of the given D flip flop Below

CLK
Figure 3

D
‘

Q
Figure 1

Q3. Referring to the figure 2,


(a) Write the truth table for J-K flip flop
(b) Draw the output waveform Q of the given J-K flip flop below
CLK
Figure 4

Q5. Classify the difference between synchronous counter and asynchronous


counter circuit
J
Q6. A 3-bit synchronous down counter is triggered by NGT input clock signal
(a) State the state transition diagram for this counter
(b) Produce the state transition table by using D Flip Flop
K
Q7. Design MOD 4 Asynchronous Up Counter using JK flip flop triggered by NGT
clock. In your design
(a) Determine the number of flip flop to be used
(b) Sketch the state transition diagram
Q (c) Draw the circuit diagram
Figure 2 (d) Sketch the output waveform for Q0, Q1

1
DBV30023

Q8. Design MOD 6 synchronous counter using JK flip flop by answering the
following questions.

(a) Determine the number of flip flop to be used


(b) Sketch the state transition diagram
(c) Construct a truth table based on Present state and Next state
(d) Determine the J and K inputs of each flip flop by using Karnaugh Map
method
(e) Draw the circuit diagram

Q9. Design a synchronous counter that count from the following sequence:
5,4,7,6,2,3,1by using JK Flip Flop and then repeat again. From your design,
(a) Determine how many flip flop will be used
(b) Sketch the state transition diagram
(c) Construct a truth table based on Present state and Next state
(d) Draw the Karnaugh Map and simplify the Boolean expression
(e) Draw the circuit diagram
(f) Sketch the output waveform for Q0, Q1 and Q2

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