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Sequential Logic Design Tasks

This document contains 8 questions about sequential logic design and finite state machines (FSMs). Question 1 and 2 ask to sketch the output of an SR latch, D latch, and D flip-flop given input waveforms. Question 3 asks if a circuit is combinational or sequential logic. Questions 4-6 are about designing logic gates to create a D flip-flop and analyzing FSM states. Questions 7-8 analyze the state transition diagram and timing of an FSM circuit.

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Sushant R Naik
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81 views2 pages

Sequential Logic Design Tasks

This document contains 8 questions about sequential logic design and finite state machines (FSMs). Question 1 and 2 ask to sketch the output of an SR latch, D latch, and D flip-flop given input waveforms. Question 3 asks if a circuit is combinational or sequential logic. Questions 4-6 are about designing logic gates to create a D flip-flop and analyzing FSM states. Questions 7-8 analyze the state transition diagram and timing of an FSM circuit.

Uploaded by

Sushant R Naik
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Computer Aided Digital Design

Unit 2: Sequential Logic Design


Assignment-2
1 Given the input waveforms shown in Figure, sketch the output, Q, of an SR latch.

2 Given the input waveforms shown in Figure, sketch the output, Q, of a D latch and D
flip-flop

3 Is the circuit in Figure combinational logic or sequential logic? Explain in a simple


fashion what the relationship is between the inputs and outputs. What would you call this
circuit?

4 Design an asynchronously resettable D flip-flop using logic gates

5 Which of the circuits in Figure are synchronous sequential circuits? Explain

6 You are designing an FSM to keep track of the mood of four students working in the
digital design lab. Each student’s mood is either HAPPY (the circuit works), SAD (the
circuit blew up), BUSY (working on the circuit), CLUELESS (confused about the circuit),
or ASLEEP (face down on the circuit board). How many states does the FSM have? What
is the minimum number of bits necessary to represent these states?
7 Analyze the FSM shown in Figure. Write the state transition and output tables and sketch
the state transition diagram. Describe in words what the FSM does.

8 Ben Bitdiddle has designed the circuit in Figure to compute a registered four-input XOR
function. Each two-input XOR gate has a propagation delay of 100 ps and a contamination
delay of 55 ps. Each flip-flop has a setup time of 60 ps, a hold time of 20 ps, a clock-to-Q
maximum delay of 70 ps, and a clock-to-Q minimum delay of 50 ps. what is the maximum
operating frequency of the circuit?

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