T 7.2.1.1 Multiplicación de Frecuencia
T 7.2.1.1 Multiplicación de Frecuencia
T 7.2.1.1 Multiplicación de Frecuencia
Frequency Multiplication
by K. Breidenbach
October 1998
The sensitive electronics of the equipment contained in the present experiment litera-
ture can be impaired due to the discharge of static electricity. Consequently, electro-
static build up should be avoided (particularly by utilizing appropriate rooms) or
eliminated by discharging (e.g. at the panel frames or similar).
TPS 7.2.1.1 Table of Contents
Measurement Procedures
1 Practical Information on the Experiments ............................................................... 5
1.1 The Oscilloscope ....................................................................................................... 5
1.2 The Spectrum Analyzer ............................................................................................ 7
1.3 Measurement Assembly ........................................................................................... 9
Solutions .................................................................................................................. 25
Appendix ................................................................................................................. 37
3
TPS 7.2.1.1 Measurement Procedures 1.1
5
TPS 7.2.1.1 Measurement Procedures 1.1
a bandwidth of 20 MHz. All the experiments have examples. The experiments can, however, to a
been carried out using such a device (LD Cat. No. great extent, be carried out using only a purely
575 29) and produced the results given here in the real-time oscilloscope.
6
TPS 7.2.1.1 Measurement Procedures 1.2
The Spectrum Analyzer spondingly shifted along with it. The principle of
Signals can be equally validly described in terms the operation of the spectrum analyzer is shown in
of their spectrum as well as in terms of their Fig. 1.2-2. Its assembly is shown in Fig. 1.2-1.
behaviour with respect to time. Spectrum or fre-
quency analyzers are used in measurement tech- The Time Rule of Electrical Telecommunications
nology for the recording of signal spectra. These Technology
analyzers operate either in digital mode using When using analyzers according to the sweep fil-
mathematical algorithms such as e.g. the fast Fou- ter principle, one of the most fundamental laws of
rier transformation (FFT) or in analog as filter electrical engineering must be taken into consid-
banks or sweep analyzers. The latter principle is eration. According to the time rule of telecommu-
realised in the spectrum analyzer, training panel nications technology, the transient response of a
726 94 and should, thus, be investigated more low-pass filter system to a voltage jump becomes
closely. all the longer, the smaller its bandwidth b is. This
The analyzer is made up of a signal path (ampli- is also true for band pass filters. If pulses of very
tude component) A, an oscillator component B short duration are to be transmitted via a low-pass
and an indicating unit C (see Fig. 1.2-1). The har- filter (LP) then the output signal of the LP needs
monic signal supplied by the VCO is fed into the more time to reach the pulse amplitude, the
mixer together with the input signal. Depending smaller the bandwidth b of the filter is. The time
on the spectral quality of the input signal and the law of electrical telecommunications technology
oscillator frequency, an IF signal which lies ex- is similar to the uncertainty principle in atomic
actly in the pass range of the band filter appears at physics. It states that it is impossible to decrease
the mixer output . The AC voltage signal at the the duration of a signal as well as the bandwidth
output of the band filter is produced for various of the transmission channel for that signal at the
spectral components in the input signal at corre- same time. When tuning the VCO, the mixer out-
spondingly different frequencies of the VCO. If put signal is all the longer in the pass range of the
the VCO frequency is linearly dependent on its following band pass filter (BP), the slower the
control voltage, then it can be used for the X de-
flection of a cathode ray tube (or an XY-recorder).
In this way, the X axis also receives a linear fre-
quency division. The desired frequency-depen-
dent amplitude representation of the input signal
is displayed on the monitor when the VCO varies,
if, after rectification and corresponding amplifica-
tion, the output voltage of the band filter is con-
nected to the Y deflection of the beam tube (or
XY-recorder). Therefore, the spectrum analyzer
represents a process of the well-known super-
heterodyne principle used in radio technology,
whereby the band filter can be regarded as a spec-
tral window. The position of this window within
the frequency range is determined by the VCO
frequency. The width of the window is deter- Fig. 1.2-2: The principle of the spectrum analyzer
mined by the selected bandwidth of the band pass A: Amplitude transfer function of the bandpass
filter. (spectral window) with bandwidth b.
The centre frequency of the BP shifts
When the VCO sweeps the set frequency span, the with V = SPAN/T.
center position of the spectral window is corre- B: Arbitrary signal spectrum
7
TPS 7.2.1.1 Measurement Procedures 1.2
8
TPS 7.2.1.1 Measurement Procedures 1.3
9
TPS 7.2.1.1 Measurement Procedures 1.3
sponding control. Then, the upper frequency limit set parameters must be changed, this is only pos-
is set in SCAN-MODE fmax. The frequencies can sible in SCAN-MODE STOP. In this mode, the
be read from the connected counter. Here, locking of the RESET function is cancelled. In ad-
SPAN = fmax fmin holds true. dition, the analyzer can be operated manually in
this setting by means of a toggle switch. The setting
Starting the analyzer UP of the toggle switch makes the VCO run in the
In SCAN-MODE RUN, the VCO will now sweep direction fmax, while the button setting DOWN re-
the set frequency range once. An LED indicates duces the frequency. When fmax has been reached,
when the upper frequency limit has been reached. the analyzer carries out an automatic zero balance
The VCO stops at fmax, so that an inadvertent over- (Auto-Zero). During the Auto-Zero phase, the in-
writing of the spectrum is avoided when the XY put signal is switched off internally.
recorder is used. For the same reason, a premature
reset of the VCO to fmin during the sweep cycle is Note:
also not possible. Reset in RUN-mode is, therefore, Since the XY recorder cannot be used for a sweep
only possible after fmax has been reached. However, period T = 1/25 s (see C), the set frequency span
should one desire to interrupt the spectrum record- is here repeatedly swept in RUN-MODE. This
ing during the sweep cycle, which can last up to makes it possible to use the spectrum analyzer
160 s, because e.g. one notices at an early stage that also as a sweep generator.
10
TPS 7.2.1.1 Measurement Procedures 1.3
11
TPS 7.2.1.1 Measurement Procedures 1.3
12
TPS 7.2.1.1 Frequency Multiplication 1
Fig. 1-1: The 4-quadrant characteristics field Fig. 1-2: Transistor amplifier in common emitter
13
TPS 7.2.1.1 Frequency Multiplication 1
U u1
= I B 0 exp. B 1 + Eq. 1-3
UT uT
14
TPS 7.2.1.1 Frequency Multiplication 1
When the frequency multiplier is in operation, For the arrangement of the voltages in the fre-
the oscillating circuit is fixed to the frequency quency multiplier, see Fig. 1-4. Here:
f0 = 100 kHz. The selection of the desired har- U1 : Input voltage
monics is carried out by changing the frequency UE : Voltage across the emitter resistor
f1 of the input signal. UC : Voltage between collector and ground
Example: U2 : Output voltage
Harmonics with frequencies: Due to unavoidable characteristics dispersion,
fn = nf1 n = 1, 2, 3.. amplitude measurements using different devices
can be expected for f1 = 10 kHz when a suitable may vary. This is unimportant and does not affect
choice of the OP and the amplitude of the input the students ability to understand the experiment.
signal is made.
Thus, the oscillating circuit tuned to
f10 = 10 f1 = 100 kHz selects the 10th harmonic.
15
TPS 7.2.1.1 Frequency Multiplication 1
16
TPS 7.2.1.1 Frequency Multiplication 1
17
TPS 7.2.1.1 Frequency Multiplication 1
18
TPS 7.2.1.1 Frequency Multiplication 2
19
TPS 7.2.1.1 Frequency Multiplication 2
Thus, the VCO is frequency-modulated by the AC cally, i.e. uncontrolled. The mean phase position,
voltage. The changing frequency of the VCO is however, remains constant. Noise superposi-
immediately recognized by the phase detector PD. tioned on the wanted signal thus does not influ-
If we are lucky, the VCO generates the right ence the PLL in the first approximation.
frequency f1 for a brief moment. This causes a DC
voltage to appear at the PD output. This too is led Dynamic behavior of the PLL
to the VCO via the loop filter, where it causes the Up to now we have examined the PLL in steady-
VCO to generate a fixed oscillation of the input state operation only. The reference signal has the
signal with the frequency f1. The VCO thus locks constant frequency f1, and the PLL was fortu-
into the frequency of the input signal. The con- nately able to lock into this frequency. In this
trol-circuit design of the PLL obviously ensures case, its task was to control minor disturbances. In
that each deviation of the VCO frequency from examining the dynamic behavior, we are inter-
the input signal frequency results in an automatic ested in the ability of the PLL to lock into the ref-
resetting of the VCO. The controller adjusts the erence signal at all, which, under certain
VCO until the VCO frequency again matches the circumstances, can differ greatly in terms of fre-
input frequency. The controlled loop exhibits in- quency when the unit is switched on. It is obvious
tegral behavior. For this reason even the smallest that it cannot accomplish this for every frequency.
of frequency differences leads in time to consider- The frequency range in which the frequency f1 of
able phase shifts which control the VCO. The the input signal (reference signal) must lie if the
phase shift Φ causes a voltage UΦ after the PD. PLL is to lock into it is called the capture range
This is led to the input of the loop filter. The phase of the PLL. The size of the capture range depends
shift Φ thus directly influences the DC control on the time constant TI and the gain Ap of the loop
voltage Uf of the VCO. There is normally a linear filter (controller). If the PLL has already locked
relationship between Φ and the output voltage of in, the VCO frequency f2 will follow the
the PD: frequency f1 of the input signal across a particular
UΦ = kΦΦ Eq. 2-1 range. The frequency range in which f1 may
change without the PLL reaching its tracking
Noise behavior of the PLL limit is called the hold range. The hold range is
In its locked state, the phase detector determines larger than, or at least as large as, the capture
the phase difference Φ between the VCO and the range. It depends on the loop gain and the control
reference signal. If the reference signal contains characteristic of the VCO.
noise, the phase difference will change stochasti-
20
TPS 7.2.1.1 Frequency Multiplication 2
21
TPS 7.2.1.1 Frequency Multiplication 2
Thus, using this relationship, any quartz-stabi- Connect the VCO output directly to the
lized, rational frequency ratios can be derived lower input of the PD using a bridging
from a reference oscillation with the frequency f1. plug.
Display the signal at the VCO output on
The PLL frequency multiplier your oscilloscope. Use the corresponding
The training panel contains the following mod- control to adjust the loop filter so that the
ules: PLL locks in.
1. Clock oscillator, square-wave output signal, The PLL is locked in when the VCO out-
τ = 50%, f1 = 100 kHz, unipolar 0/+10 V. put signal has a symmetrical duty cycle
2. Phase detector constructed as sample-and- and has approximately stationary slopes.
hold element. Measure the VCO frequency using the
3. Loop filter with PI characteristic (lowpass). counter (toggle switch in position: ANA-
The P component is adjustable. LOG). Connect the multimeter to the VCO
4. VCO input and set the range to 3 V DC. Note
5. Adjustable frequency divider with each value for the VCO frequency f2 and
N2 = 2...10 control voltage Uf in Table 1. You must
vary the frequency f1 of the input signal in
Advance questions the range from 20 kHz...200 kHz in steps
1. Draw the function circuit diagram of a PLL. of approx. 20 kHz..
What functions do the individual elements Note: The equation f1 = f2 is valid only when the
have? VCO is constantly locked in. Sketch the
2. Name some possible ways of realizing a graph of the control characteristic, i.e. f1
VCO and a phase detector. versus Uf.
3. Describe the lock-in process. What is meant What happens when you disconnect the
by capture range and hold range? function generator?
4. How must the PLL circuit be expanded in
order to be able to use it for frequency syn- 2. Investigate the tracking behavior of the
thesis? PLL. You can vary the input frequency,
5. Where else are PLL circuits used? among other means, by switching the fre-
quency decade on the function generator.
Experiment procedure Observe whether the locked-in PLL loses its
Set up the experiment according to plug-in dia- synchronization; in other words, draw your
gram 2-1. conclusions regarding the hold range.
1. Record the control characteristic of the VCO Test whether the PLL is able to lock into the
Apply an external square-wave signal to respective input frequency. In doing so, you
input 1 of the PD from the function genera- are investigating the capture range of the
tor with f1 = 100 kHz and 20 Vpp. PLL. To do this, it is necessary to briefly
22
TPS 7.2.1.1 Frequency Multiplication 2
break the connection between the function ponent. Once again, display the signal
generator and the PD. Vary the input fre- curves at the VCO input and output on your
quency as much as is necessary or possible. oscilloscope, but this time with a greater
Note: time resolution (TB: 1 ms/Div.). Draw the
You may need to adjust the loop. signals in a diagram. Compare your results
3. Replace the function generator with the here with those obtained in Point 4 and in-
clock generator of the training panel. Using terpret them.
the oscilloscope, display the signals at the 6. Assemble a frequency synthesizer. To do
two inputs of the PD: Y1,2: 0.5 V/Div., this, connect the adjustable frequency di-
TB: 2 ms/Div. Adjust the PLL again until it vider in the feedback line from the VCO
locks in. Measure the frequency f1 of the output to the PD input. Set the divider ratio
quartz oscillator. Draw the input signal and from N = 2 to N = 10 in consecutive order.
the VCO output signal (the two oscilloscope Display the signal at the VCO output on the
signals) in a diagram. What do you observe? oscilloscope and, if necessary, adjust the
4. Use your oscilloscope to display the curves loop filter so that the PLL remains locked-
of the signals at the VCO input and VCO in. Measure the frequency of the oscillator
output. Draw these signals in a diagram. using the counter (gate time: 1 s). Measure
5. Investigate the PLL in its unlocked state. To the frequency of the VCO output signal with
do this, start from the settings given in Point the counter for all nine divider settings using
3 and move the adjuster control of the loop the same time resolution of the counter.
filter very slightly to the left. Take another Record your results in Table 2. Display the
look at Fig. 2-2. The adjuster control of the signals at the inputs of the PD for all divider
loop filter acts on resistor R2. When the con- settings, i.e. the reference oscillation and the
trol is at its right limit, then R2 = min. Ac- output signal of the frequency divider.
cording to Eq. 2-3, the gain of the P What do you observe?
component is also a minimum. Correspond-
ingly, when the control is at its left limit, Note
R2 = max., i.e., maximum gain of the P com- The tables can be found in the appendix.
Plug-in diagram 2
23
TPS 7.2.1.1 Frequency Multiplication 2
24
TPS 7.2.1.1 Solutions MP
Measurement set-up
Results
1. 2.1 Table 1:
Spectrum of a symmetrical square-wave signal
Signal: Analyzer:
AR = 5 V V1 = 1
fP = 2,0 kHz b = 500 Hz
fr = 20 kHz
T = 20 s
Measurement Theory
f S(n) SR(n) SR(n)
Curve of a square-wave signal with respect to time n V2
Parameters: AR = 5.0 V kHz V V V
fR = 2.0 kHz 1 2 6.6 1 6.6 6.37
25
TPS 7.2.1.1 Solutions MP
2.2
26
TPS 7.2.1.1 Solutions 1
I0 A12 A12
ID ≈ − 2 + 2 cos( 2 π 2 f1 t ) +
U P2
A1 A2 cos[ 2 π ( f1 + f 2 ) t ] +
A1 A2 cos[ 2 π ( f1 − f 2 ) t ] +
A22 A22
+ cos( 2 π 2 f 2 t )
4. Due to the bent input characteristic curve, 2 2
distortions in the base current occur for high
control voltage at the base. With corre- 1. DC voltages proportional to
sponding gain, these cause a distorted col-
lector current. The collector current flows A12 A22
,
across the load resistor RL; thus, the ampli- 2 2
fied non-linearly distorted output voltage 2. Spectral components with twice the signal
can be taken from this resistor. frequencies 2 f1 and 2 f2:
5. The distortions are dependent on the curve
of the input characteristic, the degree of con- A12 A22
trol and the selection of the operating point cos( 2 π 2 f1 t ),cos( 2 π 2 f 2 t )
2 2
(OP). For example, if the operating point is
3. Spectral components with the sum and dif-
fixed at 0 V, the transistor blocks com-
ference frequencies f1 + f2, f1 f2:
pletely for negative input signals! If we ad-
ditionally select a high control level, i.e. A1A2 cos[2π(f1 + f2)t], A1A2 cos[2π(f1 f2)t]
input voltage, many higher-order terms of The pn-FET can be used for frequency dou-
the power series according to Eq. 1-2 must bling because of 2, and for modulation be-
be taken into consideration. This in turn re- cause of 3.
sults in stronger distortions.
27
TPS 7.2.1.1 Solutions 1
Experiment results
1. Table 1:
Y1 : ~ 10 V Y2 : ~ 60 mV
U1 = (50...100) mVss, SINE
OP : right limit
f1 U1 f2 U2
kHz mVss kHz Vss
32.9 50 __ 0.1
25.0 50 __ __
Adjustment of the frequency multiplier
10 . 0
VURES = = 200 s.Table 1.
0 . 05
28
TPS 7.2.1.1 Solutions 1
Table 2:
U1 = (500...800)mVss, SINE
OP : center position
f1 U1 f2 U2
kHz mVss kHz Vss
Output voltage U2
Input voltage U1 ≈ 1200 mVpp, f1 = 20.0 kHz
Note:
OP left limit When measuring with f1 = 11.1 kHz and
f1 = 10.0 kHz, the counter only responds to the
signal components with amplitudes greater
than the sensitivity limit of the analog input.
For f1 = 11.1 kHz, it has apparently over-
looked one oscillation: instead of
9 · 11.1 kHz = 99.9 kHz, it has only counted
8 · 11.1 kHz = 88.8 kHz. For f1 = 10.0 kHz, it
has only counted 1 oscillation out of 10.
29
TPS 7.2.1.1 Solutions 1
Output voltage U2 subjected to load by the spectrum Output signal U2 not subjected to load by the spectrum
analyzer. analyzer.
Input signal with f1 = 20.2 kHz, the fundamental period is Same input signal as on the left.
the high peak. Output signal frequency f2 = 101.2 kHz
The value of the input resistance Ri of the spec- circuit affects the spectrum of the collector volt-
trum analyzer is 10 kΩ. The output transformer of age UC. Thus the use of the spectrum analyzer
the frequency multiplier converts RE with the leads to two significant error sources:
square of its transformation ratio n2 into the 1. When the analyzer is connected to the out-
antiresonant circuit. The additional damping due put of the frequency multiplier, the input
to the spectrum analyzer causes a reduction in the spectrum before the oscillating circuit (at
quality of the circuit. This lowers the selectivity the collector) changes.
of the oscillating circuit. Under certain circum- 2. The bandwidth of the oscillating circuit be-
stances, the output signal U2 can now contain in- comes wider, i.e. it permits more spectral
terfering spectral components which would have components to reach the output.
been filtered out if the selectivity had been In spite of this, the spectra allow us to draw the
greater. At the same time, the damped oscillating following qualitative conclusions:
30
TPS 7.2.1.1 Solutions 1
When a non-linear characteristic is control- lective enough. For this reason, the output
led, harmonics are formed from a harmonic signal U2 contains more than just the desired
input signal U1 (the single line at f = f1 in the spectral component, and the resulting curve
spectrum SU1) at f = nf1, n = 1,2,3,... of the output signal with respect to time is
The desired harmonics can be selected distorted.
through the use of a filter with a high-qual- The oscillation with the fundamental fre-
ity selection device. quency f1 is the highest peak in each case. It
3. is followed by n1 oscillations with decreas-
The frequency of the output signal f2 is al- ing amplitude.
ways 100 kHz in spite of excitation by a low Example:
frequency input signal. f1 = 20 kHz
At a high control level and in the absence of f2 = 100 kHz
a base bias voltage, many harmonics are n = 100/20 = 5
formed. At low frequencies of the input sig- In this case, there are four oscillations of de-
nal U1 these harmonics are so close together creasing amplitude.
that the antiresonant circuit is no longer se-
31
TPS 7.2.1.1 Solutions 1
32
Solutions
TPS 7.2.1.1 2
Frequency Multiplication
33
Solutions
TPS 7.2.1.1 2
Frequency Multiplication
Experiment results
1. If the connection from the PD to the function 2. The capture and hold ranges are approxi-
generator is interrupted, the PLL can no mately equal. We can determine only the
longer lock in. The output signal of the VCO lower cut-off frequency, as the function gen-
causes a slightly superpositioned AC voltage erator with fmax = 200 kHz is not sufficient to
at the loop filter output. This in turn causes a determine the upper cut-off frequency limit.
continuing frequency modulation of the VCO. The PLL can be pulled from f1 ≈ 2 kHz to at
least f1 ≥ 200 kHz without losing its “hold”. It
Table 1:
can also synchronize to an external frequency
The control charac- within the same frequency range.
teristic of the VCO
3. The signals are in phase. The oscillator fre-
f2 Uf quency is:
kHz V fosc = f1 = 99.990 kHz
99.1 2.18
80.4 2.12
60.2 2.06
0
40.3 1.96
19.0 1.87
120.7 2.25 0
139.8 2.31
Reference signal and VCO output signal
160.5 2.37
4. The control voltage Uf is essentially a DC
180.8 2.43
voltage of approx. 2.2 V.
200.3 2.50
34
Solutions
TPS 7.2.1.1 2
Frequency Multiplication
6. Table 2:
Frequency synthesis
Frequency of clock oscillator
f1 : 99.990 kHz
Gate time of counter: 1 s
f2 f2
N
kHz N
2 199.980 99.99
3 299.970 99.99
4 399.960 99.99
5 499.950 99.99
6 599.940 99.99
7 699.930 99.99
8 799.919 99.99
9 899.910 99.99
10 999.899 99.99
35
Solutions
TPS 7.2.1.1 2
Frequency Multiplication
36
TPS 7.2.1.1 Appendix 1
Worksheet Table 2:
The 4-quadrant characteristics field
U1 = mVss, SINE
AP :
f1 U1 f2 U2
kHz mVss kHz Vss
Table 1: Table 3:
37
TPS 7.2.1.1 Appendix 1
To chapter 2:
38
TPS 7.2.1.1 Appendix 1
Table 1: Table 2:
39
TPS 7.2.1.1 Key Words
Appendix 1
40