Adm 1278

Hot Swap Controller and Digital Power and
Energy Monitor with PMBus Interface

Data Sheet ADM1278
FEATURES TYPICAL APPLICATION CIRCUIT
4.5V TO 20V RSENSE Q1
±0.3% accurate, 12-bit ADC for IOUT, VIN, VOUT, and temperature
320 ns response time to short circuit
Shutdown on detection of FET health fault HS+ MO+ MO– HS–
Constant power foldback for tighter FET SOA protection VCC ADM1278-1
+ –
×50 CHARGE
VCAP
Remote temperature sensing with programmable warning LDO
ISENSE PUMP
VCP
and shutdown thresholds UV
+
1.0V GATE
Resistor-programmable 5 mV to 25 mV VSENSE current limit – DRIVE/ GATE
OV LOGIC
– TEMP
Programmable start-up current limit 1.0V + TIMEOUT
+ PWGIN
1% accurate UV, OV, and PWRGD thresholds ISET REF – +
SELECT –
Split hot swap and power monitor inputs to allow additional PSET
1.0V
1.0V
CURRENT-
external ADC filtering ISTART HS–
LIMIT
CONTROL VOUT
Reports power and energy consumption over time VCBOS
Peak detect registers for current, voltage, and power PWRGD
IOUT
PROCHOT power throttling capability TIMER
TIMER TIMEOUT
FAULT
ENABLE
PMBus fast mode compliant interface HS+
LOGIC GPO2/ALERT2
ISENSE AND GPO1/ALERT1/CONV
12-BIT PMBus
5 mm × 5 mm, 32-lead LFCSP VOUT ADC SCL
TEMP SDA
RETRY ADR1
APPLICATIONS ADR2
ANALOG CSOUT
Servers VOUT
12198-001
Power monitoring and control/power budgeting PGND GND
Telecommunication and data communication equipment

Figure 1.
GENERAL DESCRIPTION
The ADM1278 is a hot swap controller that allows a circuit In case of a short-circuit event, a fast internal overcurrent
board to be removed from or inserted into a live backplane. It also detector responds within 320 ns and signals the gate to shut
features current, voltage, power, and temperature readback via an down. A 1500 mA pull-down device ensures a fast FET response.
integrated 12-bit analog-to-digital converter (ADC), accessed The ADM1278 features overvoltage (OV) and undervoltage (UV)
using a PMBus™ interface. The load current is measured using an protection, programmed using external resistor dividers on the
internal current sense amplifier that measures the voltage across UV and OV pins. A PWRGD signal can be used to detect when the
a sense resistor in the power path via the HS+ and HS− pins. A output supply is valid, using the PWGIN pin to accurately
default current limit of 20 mV is set, but this limit can be monitor the output.
adjusted, if required.
The ADM1278 is available in a 32-lead LFCSP with a RETRY pin
The ADM1278 limits the current through the sense resistor by
that can be configured for automatic retry or latch-off when an
controlling the gate voltage of an external N-channel FET in the
overcurrent fault occurs.
power path, via the GATE pin. The sense voltage, and therefore
the load current, is maintained below the preset maximum. The Table 1. Model Options
ADM1278 protects the external FET by limiting the time that Model ADC Accuracy SPI Interface Enable Pin1
the FET remains on while the current is at its maximum value. ADM1278-1AA ±0.3% No Active high
This current-limit time is set by the choice of capacitor connected ADM1278-1A ±0.7% No Active high
to the TIMER pin. In addition, a constant power foldback scheme ADM1278-1B ±1.0% No Active high
is used to control the power dissipation in the MOSFET during ADM1278-2A ±0.7% Yes Active high
power-up and fault conditions. The level of this power, along ADM1278-3A ±0.7% No Active low
with the TIMER regulation time, can be set to ensure that the
MOSFET remains within safe operating area (SOA) limits. 1
Active high relates to the ENABLE pin, and active low relates to the ENABLE pin.
Rev. C Document Feedback

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ADM1278 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 SMBus Protocol Usage .............................................................. 34
Applications ...................................................................................... 1 Packet Error Checking .............................................................. 34
Typical Application Circuit ............................................................ 1 Partial Transactions on I2C Bus ............................................... 35
General Description ......................................................................... 1 SMBus Message Formats .......................................................... 35
Revision History ............................................................................... 3 Group Commands ..................................................................... 37
Specifications .................................................................................... 4 Hot Swap Control Commands ................................................. 37
Power Monitoring Accuracy Specifications ............................. 8 ADM1278 Information Commands ....................................... 37
Serial Bus Timing Characteristics .............................................. 8 Status Commands ...................................................................... 38
SPI Timing Characteristics (ADM1278-2) ............................... 9 GPO and Alert Pin Setup Commands .................................... 38
Absolute Maximum Ratings ......................................................... 10 Power Monitor Commands ...................................................... 39
Thermal Characteristics ............................................................ 10 Warning Limit Setup Commands ........................................... 40
ESD Caution................................................................................ 10 PMBus Direct Format Conversion .......................................... 40
Pin Configurations and Function Descriptions ......................... 11 Voltage and Current Conversion Using LSB Values ............ 41
Typical Performance Characteristics ........................................... 17 Alert Pin Behavior .......................................................................... 42
Theory of Operation ...................................................................... 24 Faults and Warnings .................................................................. 42
Powering the ADM1278............................................................ 24 Generating an Alert ................................................................... 42
Hot Swap Current Sense Inputs ............................................... 24 Handling/Clearing an Alert ...................................................... 42
Power Monitor Current Sense Inputs ..................................... 25 SMBus Alert Response Address ............................................... 43
Current-Limit Reference ........................................................... 25 Example Use of SMBus ARA.................................................... 43
Setting the Current Limit (ISET) ............................................. 26 Digital Comparator Mode ........................................................ 43
Setting a Linear Output Voltage Ramp at Power-Up ........... 26 Typical Application Circuits .................................................... 43
Start-Up Current Limit ............................................................. 27 PMBus Command Reference ....................................................... 45
Constant Power Foldback ......................................................... 28 Register Details ............................................................................... 46
Timer ............................................................................................ 28 Operation Register ..................................................................... 46
Hot Swap Retry ........................................................................... 29 Clear Faults Register .................................................................. 46
FET Gate Drive Clamps ............................................................ 29 PMBus Capability Register ....................................................... 46
Fast Response to Severe Overcurrent ...................................... 29 VOUT OV Warning Limit Register ............................................ 46
Undervoltage and Overvoltage................................................. 29 VOUT UV Warning Limit Register ............................................ 47
Power Good ................................................................................ 29 IOUT OC Warning Limit Register.............................................. 47
FAULT Pin .................................................................................. 29 OT Fault Limit Register............................................................. 47
ENABLE/ENABLE Input .......................................................... 30 OT Warning Limit Register ...................................................... 47
Current Sense Output (CSOUT) ............................................. 30 VIN OV Warning Limit Register .............................................. 47
Remote Temperature Sensing .................................................. 30 VIN UV Warning Limit Register .............................................. 48
SPI Interface ................................................................................ 31 PIN OP Warning Limit Register ................................................ 48
VOUT Measurement ..................................................................... 32 Status Byte Register .................................................................... 48
FET Health .................................................................................. 32 Status Word Register ................................................................. 49
Power Throttling ........................................................................ 32 VOUT Status Register ................................................................... 50
Power Monitor ........................................................................... 32 IOUT Status Register ..................................................................... 50
PMBus Interface ............................................................................. 34 Input Status Register .................................................................. 50
Device Addressing...................................................................... 34 Temperature Status Register .................................................... 51
Rev. C | Page 2 of 61
Data Sheet ADM1278
Manufacturer Specific Status Register .....................................51 Power Monitor Configuration Register................................... 55
Read EIN Register .........................................................................52 Alert 1 Configuration Register.................................................. 56
Read VIN Register ........................................................................52 Alert 2 Configuration Register.................................................. 57
Read VOUT Register ......................................................................53 Peak Temperature Register ....................................................... 57
Read IOUT Register .......................................................................53 Device Configuration Register .................................................. 57
Read Temperature 1 Register ....................................................53 Power Cycle Register .................................................................. 58
Read PIN Register .........................................................................53 Peak PIN Register ......................................................................... 59
PMBus Revision Register ...........................................................53 Read PIN (Extended) Register .................................................... 59
Manufacturer ID Register ..........................................................54 Read EIN (Extended) Register .................................................... 59
Manufacturer Model Register ...................................................54 Hysteresis Low Level Register ................................................... 59
Manufacturer Revision Register ...............................................54 Hysteresis High Level Register.................................................. 59
Manufacturer Date Register ......................................................54 Hysteresis Status Register .......................................................... 60
Peak IOUT Register ........................................................................54 Start-Up IOUT Limit Register ...................................................... 60
Peak VIN Register .........................................................................55 Outline Dimensions ....................................................................... 61
Peak VOUT Register ......................................................................55 Ordering Guide ........................................................................... 61
Power Monitor Control Register ..............................................55
REVISION HISTORY
3/2020—Rev. B to Rev. C
Change to Endnote 1, Table 6 .......................................................10 12/2014—Rev. 0 to Rev. A
Changes to Figure 27 ......................................................................20 Changes to Features Section, General Description Section,
Changes to Figure 62 ......................................................................35 and Applications Section ................................................................. 1
Changes to Table 12 ........................................................................41 Added Table 1, Renumbered Sequentially .................................... 1
Added Endnote 1, Table 13 ...........................................................45 Changes to POWER_CYCLE Command Section ...................... 37
Changes to Table 57 ........................................................................60 Change to Power Cycle Register Section ..................................... 58
10/2018—Rev. A to Rev. B 6/2014—Revision 0: Initial Version

Changes to Figure 4 and Figure 5 .................................................11
Changes to Figure 6 ........................................................................14
Updated Outline Dimensions .......................................................61
Changes to Ordering Guide...........................................................61
ADM1278 Data Sheet
SPECIFICATIONS
VCC = 4.5 V to 20 V, VCC ≥ VHS+ and VMO+, VHS+ = 2 V to 20 V, VSENSE_HS = (VHS+ − VHS−) = 0 V, TA = −40°C to +85°C, unless otherwise
noted.
Table 2.
Parameter1 Symbol Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY
Operating Voltage Range VCC 4.5 20 V
Undervoltage Lockout UVLO 2.4 2.7 V VCC rising
Undervoltage Hysteresis 90 120 mV
Quiescent Current ICC 5.5 mA GATE on and power monitor running
UV PIN
Input Current IUV 50 nA UV ≤ 3.6 V
UV Threshold UVTH
A Grade and AA Grade 0.99 1.0 1.01 V UV falling
B Grade Only 0.97 1.0 1.03 V UV falling
UV Threshold Hysteresis UVHYST 45 60 75 mV
UV Glitch Filter UVGF 2 7 μs 50 mV overdrive
UV Propagation Delay UVPD 5 8 μs UV low to GATE pull-down active
OV PIN
Input Current IOV 50 nA OV ≤ 3.6 V
OV Threshold OVTH
A Grade and AA Grade 0.99 1.0 1.01 V OV rising
B Grade Only 0.97 1.0 1.03 V OV rising
OV Threshold Hysteresis OVHYST 45 60 75 mV
OV Glitch Filter OVGF 1.5 3.5 μs 50 mV overdrive
OV Propagation Delay OVPD 3.0 4.0 μs OV high to GATE pull-down active
HS+ AND HS− PINS
Input Current ISENSEx 150 μA Per individual pin; VHS+, VHS− = 20 V
Input Imbalance IΔSENSE 5 μA IΔSENSE = (I+ − I−)
MO+ AND MO− PINS
Input Current IMO± 25 nA Per individual pin; VMO+, VMO− = 20 V
VCAP PIN
Internally Regulated Voltage VVCAP
A Grade and AA Grade 2.68 2.7 2.72 V 0 μA ≤ IVCAP ≤ 100 μA; CVCAP = 1 μF
B Grade Only 2.66 2.7 2.74 V 0 μA ≤ IVCAP ≤ 100 μA; CVCAP = 1 μF
ISET PIN
Reference Select Threshold VISETRSTH 1.35 1.5 1.65 V If VISET > VISETRSTH, an internal 1 V reference (VCLREF) is used
Internal Reference VCLREF 1 V Accuracies included in total sense voltage accuracies
Gain of Current Sense AVCSAMP 50 V/V Accuracies included in total sense voltage accuracies
Amplifier
Recommended Maximum VISET 0.25 1.25 V 5 mV to 25 mV VSENSE current limit
Operating Range
Input Current IISET 100 nA VISET ≤ VVCAP
GATE PIN Maximum voltage on the gate is always clamped to ≤31 V
GATE Drive Voltage ΔVGATE ΔVGATE = VGATE − VOUT
10 12 14 V 20 V ≥ VCC ≥ 8 V; IGATE ≤ 5 μA
8 10 V VHS+ = VCC = 5 V; IGATE ≤ 5 μA
7 9 V VHS+ = VCC = 4.5 V; IGATE ≤ 1 μA
GATE Pull-Up Current IGATEUP −20 −30 μA VGATE = 0 V
GATE Pull-Down Current IGATEDN
Regulation IGATEDN_REG 45 60 75 μA VGATE ≥ 2 V; VISET = 1.0 V; (VHS+ − VHS−) = 30 mV
Slow IGATEDN_SLOW 5 10 15 mA VGATE ≥ 2 V
Fast IGATEDN_FAST 750 1500 2250 mA VGATE ≥ 12 V; VCC ≥ 12 V
Data Sheet ADM1278
GATE Holdoff Resistance 20 Ω VCC = 0 V, VGATE = 2 V
HOT SWAP SENSE VOLTAGE
Hot Swap Sense Voltage VSENSECL
Current Limit
A Grade and AA Grade 19.75 20 20.25 mV VISET > 1.65 V; VGATE = (VHS+ + 3 V); IGATE = 0 μA
B Grade Only 19.6 20 20.4 mV VISET > 1.65 V; VGATE = (VHS+ + 3 V); IGATE = 0 μA
Constant Power Inactive VGATE = (VHS+ + 3 V); IGATE = 0 μA; VDS = (HS−) − VOUT
A Grade and AA Grade 24.75 25 25.25 mV VISET = 1.25 V; VDS < 2 V
19.75 20 20.25 mV VISET = 1.0 V; VDS < 2 V
14.75 15 15.25 mV VISET = 0.75 V; VDS < 2 V
B Grade Only 24.6 25 25.4 mV VISET = 1.25 V; VDS < 2 V
19.6 20 20.4 mV VISET = 1.0 V; VDS < 2 V
14.6 15 15.4 mV VISET = 0.75 V; VDS < 2V
Constant Power Active FET power limit = (VPSET × 8)/(50 × RSENSE); constant power
active when VDS > (VPSET × 8)/ISET
A Grade and AA Grade 9.25 10 10.75 mV VISET > 1.65 V; VPSET = 0.25 V; VDS = 4 V
4.65 5 5.35 mV VISET > 1.65 V; VPSET = 0.25 V; VDS = 8 V
B Grade Only 9 10 11 mV VISET > 1.65 V; VPSET = 0.25 V; VDS = 4 V
Start-Up Current Limit VISTARTCL
A Grade and AA Grade 4.7 5 5.3 mV STRT_UP_IOUT_LIM = 3; VISET > 1.65 V
3.7 4 4.3 mV VISTART = 0.2 V
B Grade Only 4.5 5 5.5 mV STRT_UP_IOUT_LIM = 3; VISET > 1.65 V
3.5 4 4.5 mV VISTART = 0.2 V
Start-Up Current-Limit Clamp VISTARTCL_CLAMP
A Grade and AA Grade 1.6 2 2.4 mV VISTART = 0 V or STRT_UP_IOUT_LIM = 0
B Grade Only 1.4 2 2.6 mV VISTART = 0 V or STRT_UP_IOUT_LIM = 0
Circuit Breaker Offset VCBOS 0.6 0.88 1.12 mV Circuit breaker trip voltage, VCB = VSENSECL − VCBOS
SEVERE OVERCURRENT
Voltage Threshold VSENSEOC
A Grade and AA Grade 23 25 27 mV VISET > 1.65 V; VPSET > 1.1 V; optional select PMBus (125%)
28 30 32 mV VISET > 1.65 V; VPSET > 1.1 V; optional select PMBus (150%)
43 45 47 mV VISET > 1.65 V; VPSET > 1.1 V; default at power-up (225%)
B Grade Only 20 25 30 mV VISET > 1.65 V; VPSET > 1.1 V; optional select PMBus (125%)
40 45 50 mV VISET > 1.65 V; VPSET > 1.1 V; default at power-up (225%)
Short Glitch Filter Duration 100 220 ns VSENSE_HS step = 18 mV to (2 mV above VSENSEOC_MAX)
Long Glitch Filter Duration 530 900 ns VSENSE_HS step = 18 mV to (2 mV above VSENSEOC_MAX)
(Default)
Response Time
Short Glitch Filter 200 320 ns VSENSE_HS step = 18 mV to (2 mV above VSENSEOC_MAX)
Long Glitch Filter 630 1000 ns VSENSE_HS step = 18 mV to (2 mV above VSENSEOC_MAX)
ISTART PIN
Active Range 0.1 1.25 V Tie ISTART to VCAP to disable start-up current limit
Gain of Current Sense Amplifier AVCSAMP 50 V/V Accuracies included in total sense voltage accuracies
Input Current IISTART 100 nA VISTART ≤ VVCAP
TIMER PIN
TIMER Pull-Up Current
Power-On Reset (POR) ITIMERUPPOR −2 −3 −4 μA Initial power-on reset; VTIMER = 0.5 V
Overcurrent (OC) Fault ITIMERUPFLT −57 −60 −63 μA Overcurrent fault; 0.2 V ≤ VTIMER ≤ 1 V
ADM1278 Data Sheet
TIMER Pull-Down Current
Retry ITIMERDNRT 1.7 2 2.3 μA After fault when GATE is off; VTIMER = 0.5 V
Hold ITIMERDNHOLD 100 μA Holds TIMER at 0 V when inactive; VTIMER = 0.5 V
TIMER High Threshold VTIMERH 0.98 1.0 1.02 V
TIMER Low Threshold VTIMERL 0.18 0.2 0.22 V
TIMER Glitch Filter TIMERGF 10 μs
Minimum POR Duration 27 ms Minimum initial insertion delay regardless of CTIMER value
PSET PIN FET power limit = (VPSET × 8)/(50 × RSENSE)
Reference Select Threshold VPSETRSTH 1.35 1.5 1.65 V If VPSET > VPSETRSTH, constant power is disabled
Gain of Current Sense Amplifier AVCSAMP 50 V/V Accuracies included in total sense voltage accuracies
Input Current IPSET 100 nA VPSET ≤ VVCAP
VOUT PIN
Input Current 40 μA VOUT = 20 V
FAULT PIN
Output Low Voltage VOL_LATCH 0.4 V IFAULT = 1 mA
1.5 V IFAULT = 5 mA
Leakage Current 100 nA VFAULT ≤ 2 V; FAULT output high-Z
1 μA VFAULT = 20 V; FAULT output high-Z
ENABLE PIN
Input High Voltage VIH 1.1 V
Input Low Voltage VIL 0.8 V
Glitch Filter 1 μs
RETRY PIN
Input High Voltage VIH 1.1 V Latch off when high; internal pull-up sets this as default
Input Low Voltage VIL 0.8 V 10 second automatic retry when pin pulled low
Glitch Filter 1 μs
Internal Pull-Up Current 8 μA
CSOUT PIN
CSOUT Gain 350 V/V CSOUT = VSENSE_HS × 350; VCC > CSOUT + 2 V
Total Output Error −1.6 +1.6 % VSENSE_HS = 20 mV; ICSOUT ≤ 1 mA; CCSOUT = 1 nF
−3.0 +3.0 % VSENSE_HS = 10 mV; ICSOUT ≤ 1 mA; CCSOUT = 1 nF
Output Swing to GND 40 mV
Current Limiting 5 mA CSOUT short-circuit current
GPO1/ALERT1/CONV PIN
Output Low Voltage VOL_GPO1 0.4 V IGPO1 = 1 mA
1.5 V IGPO1 = 5 mA
Leakage Current 100 nA VGPO1 ≤ 2 V; GPO1 output high-Z
1 μA VGPO1 = 20 V; GPO1 output high-Z
Input High Voltage VIH 1.1 V Configured as CONV
Input Low Voltage VIL 0.8 V Configured as CONV
Glitch Filter 1 μs Configured as CONV
GPO2/ALERT2 PIN
Output Low Voltage VOL_GPO2 0.4 V IGPO2 = 1 mA
1.5 V IGPO2 = 5 mA
Leakage Current 100 nA VGPO2 ≤ 2 V; GPO2 output high-Z
1 μA VGPO2 = 20 V; GPO2 output high-Z
PWRGD PIN
Output Low Voltage VOL_PWRGD 0.4 V IPWRGD = 1 mA
1.5 V IPWRGD = 5 mA
VCC That Guarantees Valid 1 V ISINK = 100 μA; VOL_PWRGD = 0.4 V
Output
Leakage Current 100 nA VPWRGD ≤ 2 V; PWRGD output high-Z
1 μA VPWRGD = 20 V; PWRGD output high-Z
Data Sheet ADM1278
PWGIN PIN
Input Current IPWGIN 50 nA PWGIN ≤ 3.6 V
PWGIN Threshold PWGINTH
A Grade and AA Grade 0.99 1.0 1.01 V PWGIN falling
B Grade Only 0.97 1.0 1.03 V PWGIN falling
PWGIN Threshold Hysteresis PWGINHYST 50 60 70 mV
Glitch Filter 1 μs Asserting and deasserting of PWRGD pin
CURRENT AND VOLTAGE See Table 3 for power monitor accuracy specifications
MONITORING
ADC Conversion Time Includes time for power multiplication
144 165 μs One sample of IOUT; from command received to valid data
in register
64 73 μs One sample of VIN; from command received to valid data
in register
64 73 μs One sample of VOUT; from command received to valid
data in register
ADRx PINS
Address Set to 00 0 0.8 V Connect to GND
Input Current for Address Set −40 −22 μA VADRx = 0 V to 0.8 V
to 00
Address Set to 01 135 150 165 kΩ Resistor to GND
Address Set to 10 −1 +1 μA No connect state; maximum leakage current allowed
Address Set to 11 2 V Connect to VCAP
Input Current for Address Set 3 10 μA VADRx = 2.0 V to VCAP; must not exceed the maximum
to 11 allowable current draw from VCAP
TEMP PIN External transistor is 2N3904
Operating Range −55 +150 °C Limited by external diode
Accuracy ±1 ±10 °C TA = TDIODE = −40°C to +85°C
Resolution 0.25 °C LSB size
Output Current Source2
Low Level 5 μA
Medium Level 30 μA
High Level 105 μA
Maximum Series Resistance RS 100 Ω For <±0.5°C additional error, CP = 0 F
for External Diode2
Maximum Parallel CP 1 nF RS = 0 Ω
Capacitance for External
Diode2
SPI DIGITAL INPUTS (SPI_SS, Compatible with SPI Mode 0; MDAT is the output data
MCLK, MDAT) pin; output is high impedance when not transmitting
Output Low Voltage VOL 0.4 V IOL = 4 mA
Leakage Current 1 μA
Data Rate 1 MHz
SERIAL BUS DIGITAL INPUTS
(SDA, SCL)
Output Low Voltage VOL 0.4 V IOL = 4 mA
Input Leakage ILEAK-PIN −10 +10 μA
−5 +5 μA Device is not powered
ADM1278 Data Sheet
Nominal Bus Voltage VDD 2.7 5.5 V 3 V to 5 V ± 10%
Capacitance for SDA, SCL Pins CPIN 5 pF
Input Glitch Filter tSP 0 50 ns
1
Dual function pin names are referenced by the relevant function only (see the Pin Configurations and Function Descriptions section for full pin mnemonics and
descriptions).
2
Sampled during initial release to ensure compliance, but not subject to production testing.
POWER MONITORING ACCURACY SPECIFICATIONS

Table 3.
AA Grade A Grade B Grade
Parameter Min Typ Max Min Typ Max Min Typ Max Unit Test Conditions/Comments
CURRENT AND
VOLTAGE
MONITORING
Current Sense VCC = 4.5 V to 15 V; VMO+ = 2 V to 15 V,
Absolute Error 128-sample averaging (unless otherwise
noted)
±0.25 ±0.7 ±1.0 % VSENSE_MO = 25 mV
±0.04 ±0.3 ±0.04 ±0.7 ±1.0 % VSENSE_MO = 20 mV
±0.5 ±1.0 ±1.5 % VSENSE_MO = 20 mV; 16-sample averaging
±1.5 ±2.8 ±4.0 % VSENSE_MO = 20 mV; one-sample averaging
±0.3 ±0.8 ±1.1 % VSENSE_MO = 15 mV
±0.4 ±1.1 ±1.5 % VSENSE_MO = 10 mV
±0.75 ±2.0 ±3.0 % VSENSE_MO = 5 mV
±1.6 ±4.3 ±6.2 % VSENSE_MO = 2.5 mV
HS+/VOUT ±0.35 ±1.0 ±1.5 % VHS+, VOUT = 10 V to 20 V
Absolute Error
±0.5 ±1.0 ±1.5 % VHS+, VOUT = 5 V
Power Absolute ±0.65 ±1.7 ±2.5 % VSENSE_MO = 20 mV, VHS+ = 12 V
Error
SERIAL BUS TIMING CHARACTERISTICS

Table 4.
Parameter Description Min Typ Max Unit
fSCLK Clock frequency 400 kHz
tBUF Bus free time 1.3 μs
tHD;STA Start hold time 0.6 μs
tSU;STA Start setup time 0.6 μs
tSU;STO Stop setup time 0.6 μs
tHD;DAT SDA hold time 300 900 ns
tSU;DAT SDA setup time 100 ns
tLOW SCL low time 1.3 μs
tHIGH SCL high time 0.6 μs
tR1 SCL, SDA rise time 20 300 ns
t F1 SCL, SDA fall time 20 300 ns
1
tR = (VIL(MAX) − 0.15) to (VIH3V3 + 0.15) and tF = 0.9 VDD to (VIL(MAX) − 0.15); where VIH3V3 = 2.1 V, and VDD = 3.3 V. VIH3V3 is the input high voltage when VDD = 3.3 V.
Data Sheet ADM1278
tLOW
tR tF
VIH
SCL
VIL
tSU;STA tSU;STO
tHD;DAT tHIGH tSU;DAT
tHD;STA
VIH
SDA
VIL
12198-002
tBUF
P S S P
Figure 2. Serial Bus Timing Diagram
SPI TIMING CHARACTERISTICS (ADM1278-2)

Table 5.
Parameter Description Min Typ Max Unit Test Conditions/Comments
tS1 SPI_SS falling edge to MCLK 50 ns
rising edge setup time
tHIGH1 MCLK high time 180 ns
tLOW1 MCLK low time 180 ns
tCLK1 MCLK cycle time 1 μs
tH1 Hold time between SPI_SS 1 μs
and MCLK
tV Hold time between new data 110 260 ns Track capacitance = 120 pF; IOL = 4 mA
valid and MCLK falling edge
tON SPI_SS falling edge to MDAT 130 240 ns Track capacitance = 120 pF; IOL = 4 mA
active time
tOFF Bus relinquish time after 130 280 ns Track capacitance = 120 pF; IOL = 4 mA
SPI_SS rising edge
1
Guaranteed by design, but not production tested.
SPI_SS
tHIGH
tS tLOW tCLK tH
MCLK DON’T DON’T

CARE 1 2 3 78 79 CARE
tON
tV tOFF
12198-003
MDAT MSB LSB
Figure 3. SPI Timing Diagram
ADM1278 Data Sheet
ABSOLUTE MAXIMUM RATINGS

Table 6. Stresses at or above those listed under Absolute Maximum
Parameter Rating Ratings may cause permanent damage to the product. This is a
VCC Pin −0.3 V to +25 V stress rating only; functional operation of the product at these
UV Pin −0.3 V to +4 V or any other conditions above those indicated in the
OV Pin −0.3 V to +4 V operational section of this specification is not implied.
ISTART Pin −0.3 V to +4 V Operation beyond the maximum operating conditions for
TIMER Pin −0.3 V to VCAP + 0.3 V extended periods may affect product reliability.
TEMP Pin −0.3 V to VCAP + 0.3 V THERMAL CHARACTERISTICS
VCAP Pin −0.3 V to +4 V
θJA is specified for the worst-case conditions, that is, a device
ISET Pin −0.3 V to +4 V
soldered in a circuit board for surface-mount packages.
PSET Pin −0.3 V to +4 V
FAULT Pin −0.3 V to +25 V Table 7. Thermal Resistance
RETRY Pin −0.3 V to +4 V Package Type θJA Unit
PWGIN Pin −0.3 V to +4 V CP-32-13 32.5 °C/W
SCL Pin −0.3 V to +6.5 V
SDA Pin −0.3 V to +6.5 V
SPI_SS Pin −0.3 V to +4 V ESD CAUTION
MCLK Pin −0.3 V to +4 V
MDAT Pin −0.3 V to +4 V
ADR1 Pin −0.3 V to +6.5 V
ADR2 Pin −0.3 V to +6.5 V
ENABLE Pin −0.3 V to +25 V
GPO1/ALERT1/CONV Pin −0.3 V to +25 V
GPO2/ALERT2 Pin −0.3 V to +25 V
PWRGD Pin −0.3 V to +25 V
VOUT Pin −0.3 V to +25 V
GATE Pin (Internal Supply Only)1 −0.3 V to +36 V
HS+ Pin −0.3 V to +25 V
HS− Pin −0.3 V to +25 V
MO+ Pin −0.3 V to +25 V
MO− Pin −0.3 V to +25 V
PGND ±0.3 V
VSENSE_HS (VHS+ − VHS−) ±0.3 V
VSENSE_MO (VMO+ − VMO−) ±0.3 V
CSOUT Short-Circuit Duration Indefinite
Continuous Current into Any Pin ±10 mA
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature, Soldering (10 300°C
sec)
Junction Temperature 105°C
1
The GATE pin has internal clamping circuits to prevent the GATE pin voltage
from exceeding the maximum ratings of a MOSFET with gate to source voltage,
VGSMAX = 20 V, and internal process limits. Applying a voltage source to this
pin externally may cause irreversible damage.
Data Sheet ADM1278
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
TEMP
TEMP
MO+
MO–
MO+
MO–
VCC
VCC
HS+
HS–
HS+
HS–
OV
OV
UV
UV
PIN 1 PIN 1
INDICATOR
32
31
30
29
28
27
26
25
INDICATOR
32
31
30
29
28
27
26
25
PSET 1 24 GATE PSET 1 24 GATE
VCAP 2 23 PGND VCAP 2 23 PGND
ISET 3 22 GND ISET 3 22 GND
ISTART 4 ADM1278-1 21 PWGIN ISTART 4 ADM1278-2 21 PWGIN
TIMER 5 TOP VIEW 20 VOUT TIMER 5 TOP VIEW 20 VOUT
(Not to Scale) (Not to Scale)
FAULT 6 19 CSOUT FAULT 6 19 CSOUT
ADR1 7 18 PWRGD ADR1 7 18 PWRGD
ADR2 8 17 RETRY ADR2 8 17 RETRY
11
10
12
13
14
15
16
9
11
10
12
13
14
15
16
SDA
GPO2/ALERT2
NIC
NIC
NIC
SCL
GPO1/ALERT1/CONV
SDA
GPO2/ALERT2
ENABLE
GPO1/ALERT1/CONV
SCL
NIC
NIC
NIC
ENABLE
NOTES NOTES
1. NIC = NOT INTERNALLY CONNECTED. 1. NIC = NOT INTERNALLY CONNECTED.
2. SOLDER THE EXPOSED PAD TO THE BOARD 2. SOLDER THE EXPOSED PAD TO THE BOARD
12198-004
12198-106
TO IMPROVE THERMAL DISSIPATION. THE EXPOSED TO IMPROVE THERMAL DISSIPATION. THE EXPOSED
PAD CAN BE CONNECTED TO GROUND. PAD CAN BE CONNECTED TO GROUND.
Figure 4. ADM1278-1 Pin Configuration Figure 5. ADM1278-3 Pin Configuration
Table 8. ADM1278-1 and ADM1278-3 Pin Function Descriptions

Mnemonic
Pin No. ADM1278-1 ADM1278-3 Description
1 PSET PSET Power Limit. This pin allows the constant power limit to be programmed. The current limit is
dynamically adjusted to ensure that the maximum power dissipation in the FET never
exceeds this limit during any operating condition. The power limit can be adjusted to a user
defined value using a resistor divider from VCAP. An external reference can also be used. The
FET power is limited to (VPSET × 8)/(50 × RSENSE).
2 VCAP VCAP Internal Regulated Supply. Place a capacitor with a value of 1 μF or greater on this pin to
maintain accuracy. This pin can be used as a reference to program the ISET pin voltage.
3 ISET ISET Current Limit. This pin allows the current-limit threshold to be programmed. The default
limit is set when this pin is connected directly to VCAP. To achieve a user defined sense
voltage, the current limit can be adjusted using a resistor divider from VCAP. An external
reference can also be used.
4 ISTART ISTART Start-Up Current Limit. This pin allows a separate start-up current limit to be set for dv/dt
power-up mode. When powering up in dv/dt mode, the current charging the capacitor is
constant and is typically much smaller than the normal load current. The ISTART pin sets the
start-up current limit in a similar manner as ISET is used to set the normal current limit. The
start-up current limit is only active while PWRGD is low. The start-up current limit can also be
set over PMBus with the STRT_UP_IOUT_LIM register. Start-up current limit = VISET ×
(STRT_UP_IOUT_LIM/16). The lowest of all the active current limits always takes priority.
5 TIMER TIMER Timer. An external capacitor, CTIMER, sets an initial timing cycle delay and a fault delay. The
GATE pin is pulled low when the voltage on the TIMER pin exceeds the upper threshold.
6 FAULT FAULT Fault. This pin asserts low and latches after a fault has occurred. The faults that can trigger
this pin include an overcurrent fault resulting in the TIMER pin voltage exceeding the upper
threshold, an overtemperature fault, and an FET health fault. This is an open-drain output
pin.
7, 8 ADR1, ADR2 ADR1, ADR2 PMBus Address. These pins can be tied to GND, tied to VCAP, left floating, or tied low
through a resistor for a total of 16 unique PMBus device addresses (see the Device
Addressing section).
9, 10, 11 NIC NIC Not Internally Connected.
ADM1278 Data Sheet
Mnemonic
12 ENABLE ENABLE Enable. On the ADM1278-1, the ENABLE pin is an active high digital input pin. This input
must be high to allow the ADM1278-1 hot swap controller to begin a power-up sequence. If
the ENABLE pin is held low, the ADM1278-1 is prevented from initiating a hot swap attempt.
On the ADM1278-3, the ENABLE pin is an active low digital input pin. This input must be low
to allow the ADM1278-3 hot swap controller to begin a power-up sequence. If the ENABLE
pin is held high, the ADM1278-3 is prevented from initiating a hot swap attempt.
13 GPO1/ALERT1/ GPO1/ALERT1/ General-Purpose Digital Output (GPO1).
CONV CONV Alert (ALERT1).This pin can be configured to generate an alert signal when one or more fault
or warning conditions are detected.
Conversion (CONV). This pin can be used as an input signal to control when a power monitor
ADC sampling cycle begins.
The GPO1/ALERT1/CONV pin defaults to an alert output at power-up. This is an open-drain
output pin.
14 GPO2/ALERT2 GPO2/ALERT2 General-Purpose Digital Output (GPO2).
Alert (ALERT2). This pin can be configured to generate an alert signal when one or more fault
or warning conditions are detected.
The GPO2/ALERT2 pin defaults to an alert output at power-up. This is an open-drain output
pin.
15 SDA SDA Serial Data Input/Output. Open-drain input/output. Requires an external pull-up resistor. If
the I2C pins, SDA and SCL, are not used, tie them to GND or via a resistor pull-up to VCAP or
another supply. This avoids any glitches on the I2C pins being interpreted as I2C transactions.
16 SCL SCL Serial Clock. Open-drain input. Requires an external pull-up resistor. If the I2C pins, SDA and
SCL, are not used, tie them to GND or via a pull-up resistor to VCAP or another supply. This
avoids any glitches on the I2C pins being interpreted as I2C transactions.
17 RETRY RETRY Retry. The RETRY pin has an internal pull-up resistor; therefore, it can be left floating to
enable the default latch off mode after an overcurrent fault. This pin can be pulled low to
enable a 10 second autoretry following an overcurrent fault.
18 PWRGD PWRGD Power-Good Signal. This pin indicates that the supply is within tolerance (PWGIN input), no
faults have been detected, and the ADM1278-1 hot swap is enabled with the gate fully
enhanced. This is an open-drain output pin.
19 CSOUT CSOUT Current Sense Output. The VSENSE_HS voltage is amplified to give an output voltage
corresponding to the load current.
20 VOUT VOUT Output Voltage. VOUT is an input pin and is used to read back the output voltage using the
internal ADC. Insert a 1 kΩ resistor in series between the source of a FET and the VOUT pin.
This pin is also used along with HS− to calculate the drain to source voltage (VDS) of the FET for
constant power foldback operation.
21 PWGIN PWGIN Power-Good Input. This pin sets the power-good input threshold. The user can set an accurate
power-good threshold with a resistor divider from the source of the FET (VOUT). The PWRGD
output signal is not asserted high until the output voltage is above the threshold set by this
pin.
22 GND GND Ground. This pin is the ground connection for all of the sensitive analog nodes. Take care to
isolate this ground connection from the main high current path and any large transients. A
good technique for this is to create a ground island around the ADM1278-1 device and the
supporting small signal components. Connect this ground island to the main ground plane
at a single point as close to the ADM1278-1 GND pin as possible. See the ADM1278
evaluation board (EVAL-ADM1278EBZ) as an example.
23 PGND PGND Power Ground. This pin is the ground return path for the strong gate pull-down current. It is
also the ground return for the external transistor used for temperature measurements.
24 GATE GATE Gate Output. This pin is the high-side gate drive of an external N-channel FET. This pin is
driven by the FET drive controller, which uses a charge pump to provide a pull-up current to
charge the FET gate pin. The FET drive controller regulates to a maximum load current by
regulating the GATE pin. GATE is held low when the supply is below the undervoltage
lockout threshold (UVLO).
25 TEMP TEMP Temperature Input. An external NPN device can be placed close to the MOSFETs and
connected back to the TEMP pin to report temperature. The voltage at the TEMP pin is
measured by the internal ADC.
Data Sheet ADM1278
Mnemonic
26 MO− MO− Negative Power Monitor Input. A sense resistor between the MO+ pin and the MO− pin sets
the sense voltage that is used by the ADC internally to measure load current. Extra filtering
can be added between the MO+ and MO− pins if required.
27 HS− HS− Negative Current Sense Input. A sense resistor between the HS+ pin and the HS− pin sets the
analog current limit. The hot swap operation of the ADM1278-1 controls the external FET
gate to maintain the sense voltage (VHS+ − VHS−).
28 HS+ HS+ Positive Current Sense Input. This pin connects to the main supply input. A sense resistor
between the HS+ pin and the HS− pin sets the analog current limit. The hot swap operation
of the ADM1278-1 controls the external FET gate to maintain the sense voltage (VHS+ − VHS−).
This pin is also used to measure the supply input voltage using the ADC.
29 MO+ MO+ Positive Power Monitor Input. A sense resistor between the MO+ pin and the MO− pin sets
the sense voltage that is used by the ADC internally to measure load current. Extra filtering
can be added between the MO+ and MO− pins if required.
30 VCC VCC Positive Supply Input. A UVLO circuit resets the device when a low supply voltage is
detected. GATE is held low when the supply is below UVLO. During normal operation, it is
recommended that this pin be greater than or equal to HS+ and MO+ to ensure that
specifications are adhered to. No sequencing is required.
31 UV UV Undervoltage Input. An external resistor divider is configured from the input supply to this
pin to allow an internal comparator to detect whether the supply is below the UV limit.
32 OV OV Overvoltage Input. An external resistor divider is configured from the input supply to this pin
to allow an internal comparator to detect whether the supply is above the OV limit.
EPAD EPAD Exposed Pad. Solder the exposed pad to the board to improve thermal dissipation. The
exposed pad can be connected to ground.
ADM1278 Data Sheet
TEMP
MO+
MO–
VCC
HS+
HS–
OV
UV
PIN 1
INDICATOR
32
31
30
29
28
27
26
25
PSET 1 24 GATE
VCAP 2 23 PGND
ISET 3 22 GND
ISTART 4 ADM1278-2 21 PWGIN
TIMER 5 TOP VIEW 20 VOUT
(Not to Scale)
FAULT 6 19 CSOUT
ADR1 7 18 PWRGD
ADR2 8 17 RETRY
11
10
12
13
14
15
16
SDA
GPO2/ALERT2
SCL
MCLK
MDAT
SPI_SS
GPO1/ALERT1/CONV
ENABLE
NOTES
1. SOLDER THE EXPOSED PAD TO THE BOARD
12198-105
TO IMPROVE THERMAL DISSIPATION. THE EXPOSED
PAD CAN BE CONNECTED TO GROUND.
Figure 6. ADM1278-2 Pin Configuration
Table 9. ADM1278-2 Pin Function Descriptions

Pin No. Mnemonic Description
1 PSET Power Limit. This pin allows the constant power limit to be programmed. The current limit is
dynamically adjusted to ensure that the maximum power dissipation in the FET never exceeds this limit
during any operating condition. The power limit can be adjusted to a user defined value using a
resistor divider from VCAP. An external reference can also be used. The FET power is limited to (VPSET × 8)/(50
× RSENSE).
2 VCAP Internal Regulated Supply. Place a capacitor with a value of 1 μF or greater on this pin to maintain
accuracy. This pin can be used as a reference to program the ISET pin voltage.
3 ISET Current Limit. This pin allows the current-limit threshold to be programmed. The default limit is set
when this pin is connected directly to VCAP. To achieve a user defined sense voltage, the current limit
can be adjusted using a resistor divider from VCAP. An external reference can also be used.
4 ISTART Start-Up Current Limit. This pin allows a separate start-up current limit to be set for dv/dt power-up mode.
When powering up in dv/dt mode, the current charging the capacitor is constant and is typically much
smaller than the normal load current. The ISTART pin sets the start-up current limit in a similar manner as
ISET is used to set the normal current limit. The start-up current limit is only active while PWRGD is low.
The start-up current limit can also be set over PMBus with the STRT_UP_IOUT_LIM register. Start-up
current limit = VISET × (STRT_UP_IOUT_LIM/16). The lowest of all the active current limits always takes
priority.
5 TIMER Timer. An external capacitor, CTIMER, sets an initial timing cycle delay and a fault delay. The GATE pin is
pulled low when the voltage on the TIMER pin exceeds the upper threshold.
6 FAULT Fault. This pin asserts low and latches after a fault has occurred. The faults that can trigger this pin
include an overcurrent fault resulting in the TIMER pin voltage exceeding the upper threshold, an
overtemperature fault, and an FET health fault. This is an open-drain output pin.
7, 8 ADR1, ADR2 PMBus Address. These pins can be tied to GND, tied to VCAP, left floating, or tied low through a resistor
for a total of 16 unique PMBus device addresses (see the Device Addressing section).
9 SPI_SS Slave Select. When pulled low, this pin begins to transfer data on the MDAT line.
10 MCLK Master Clock. The MCLK signal outputs data on the MDAT line. This pin is clocked by an external device.
11 MDAT Master Data Output. Open-drain output. Requires an external pull-up resistor. The MDAT pin is an
output only pin and can be used to stream data from the ADC. There is a fixed format for the current,
voltage, and temperature data, and no header information is required. This pin is high impedance
when not transmitting data.
12 ENABLE Enable. This pin is an active high digital input pin. This input must be high to allow the ADM1278-2 hot
swap controller to begin a power-up sequence. If this pin is held low, the ADM1278-2 is prevented from
initiating a hot swap attempt.
Data Sheet ADM1278
13 GPO1/ALERT1/CONV General-Purpose Digital Output (GPO1).
Alert (ALERT1). This pin can be configured to generate an alert signal when one or more fault or
warning conditions are detected.
Conversion (CONV). This pin can be used as an input signal to control when a power monitor ADC
sampling cycle begins.
The GPO1/ALERT1/CONV pin defaults to an alert output at power-up. This is an open-drain output pin.
14 GPO2/ALERT2 General-Purpose Digital Output (GPO2).
Alert (ALERT2). This pin can be configured to generate an alert signal when one or more fault or
warning conditions are detected.
The GPO2/ALERT2 pin defaults to an alert output at power-up. This is an open-drain output pin.
15 SDA Serial Data Input/Output. Open-drain input/output. Requires an external pull-up resistor. If the I2C pins,
SDA and SCL, are not used, tie them to GND or via a resistor pull-up to VCAP or another supply. This
avoids any glitches on the I2C pins being interpreted as I2C transactions.
16 SCL Serial Clock. Open-drain input. Requires an external pull-up resistor. If the I2C pins, SDA and SCL, are not
used, tie them to GND or via a resistor pull-up to VCAP or another supply. This avoids any glitches on
the I2C pins being interpreted as I2C transactions.
17 RETRY Retry. The RETRY pin has an internal pull-up resistor; therefore, it can be left floating to enable the
default latch off mode after an overcurrent fault. This pin can be pulled low to enable a 10 second
autoretry following an overcurrent fault.
18 PWRGD Power-Good Signal. This pin indicates that the supply is within tolerance (PWGIN input), no faults have
been detected, and the ADM1278-2 hot swap is enabled with the gate fully enhanced. This is an open
drain output pin.
19 CSOUT Current Sense Output. The VSENSE_HS voltage is amplified to give an output voltage corresponding to the
load current.
20 VOUT Output Voltage. VOUT is an input pin and is used to read back the output voltage using the internal
ADC. Insert a 1 kΩ resistor in series between the source of a FET and the VOUT pin. This pin is also used
along with HS− to calculate the drain to source voltage (VDS) of the FET for constant power foldback
operation.
21 PWGIN Power-Good Input. This pin sets the power-good input threshold. The user can set an accurate power-
good threshold with a resistor divider from the source of the FET (VOUT). The PWRGD output signal is not
asserted high until the output voltage is above the threshold set by this pin.
22 GND Ground. This pin is the ground connection for all of the sensitive analog nodes. Take care to isolate this
ground connection from the main high current path and any large transients. A good technique for this
is to create a ground island around the ADM1278-2 device and the supporting small signal
components. Connect this ground island to the main ground plane at a single point as close to the
ADM1278-2 GND pin as possible. See the ADM1278 evaluation board (EVAL-ADM1278EBZ) as an
example.
23 PGND Power Ground. This is the ground return path for the strong gate pull-down current. It is also the
ground return for the external transistor used for temperature measurements.
24 GATE Gate Output. This pin is the high-side gate drive of an external N-channel FET. This pin is driven by the
FET drive controller, which uses a charge pump to provide a pull-up current to charge the FET gate pin.
The FET drive controller regulates to a maximum load current by regulating the GATE pin. GATE is held
low when the supply is below the UVLO threshold.
25 TEMP Temperature Input. An external NPN device can be placed close to the MOSFETs and connected back
to the TEMP pin to report temperature. The voltage at the TEMP pin is measured by the internal ADC.
26 MO− Negative Power Monitor Input. A sense resistor between the MO+ pin and the MO− pin sets the sense
voltage that is used by the ADC internally to measure load current. Extra filtering can be added
between the MO+ and MO− pins if required.
27 HS− Negative Current Sense Input. A sense resistor between the HS+ pin and the HS− pin sets the analog
current limit. The hot swap operation of the ADM1278-2 controls the external FET gate to maintain the
sense voltage (VHS+ − VHS−).
28 HS+ Positive Current Sense Input. This pin connects to the main supply input. A sense resistor between the
HS+ pin and the HS− pin sets the analog current limit. The hot swap operation of the ADM1278-2
controls the external FET gate to maintain the sense voltage (VHS+ − VHS−). This pin is also used to
measure the supply input voltage using the ADC.
29 MO+ Positive Power Monitor Input. A sense resistor between the MO+ pin and the MO− pin sets the sense
voltage that is used by the ADC internally to measure load current. Extra filtering can be added
between the MO+ and MO− pins if required.
ADM1278 Data Sheet
30 VCC Positive Supply Input. A UVLO circuit resets the device when a low supply voltage is detected. GATE is
held low when the supply is below UVLO. During normal operation, it is recommended that this pin be
greater than or equal to HS+ and MO+ to ensure that specifications are adhered to. No sequencing is
required.
31 UV Undervoltage Input. An external resistor divider is configured from the input supply to this pin to allow
an internal comparator to detect whether the supply is below the UV limit.
32 OV Overvoltage Input. An external resistor divider is configured from the input supply to this pin to allow
an internal comparator to detect whether the supply is above the OV limit.
EPAD Exposed Pad. Solder the exposed pad to the board to improve thermal dissipation. The exposed pad
can be connected to ground.
Data Sheet ADM1278
TYPICAL PERFORMANCE CHARACTERISTICS

5 80
70
4
60
IGATEDN_REG (µA)
50
3
ICC (mA)
40
2
30
20
1
10
0 0
12198-208
12198-207
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 7. Supply Current (ICC) vs. Temperature Figure 10. GATE Pull-Down Current (IGATEDN_REG) vs. Temperature
10 0
9
–5
8
7
–10
6
IGATEUP (µA)
ICC (mA)
5 –15
3 –20
2
–25
1
0 –30
12198-209
0 5 10 15 20
12198-211
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80
VCC (V) TEMPERATURE (°C)
Figure 8. Supply Current (ICC) vs. VCC Figure 11. GATE Pull-Up Current (IGATEUP) vs. Temperature
14 35
13 VCC = 20V
12 30
11
10 25
IGATEDN_SLOW (mA)
9
8 VCC = 8V
VGATE (V)
20
7
6 15 VCC = 5V
5
4 10
3
2 5
1
0 0
12198-210
12198-212
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80

Figure 9. GATE Pull-Down Current (IGATEDN_SLOW) vs. Temperature Figure 12. VGATE (5 μA Load ) vs. Temperature
ADM1278 Data Sheet
16 15
14
14 13
12
12 VCC = 20V 11
IGATEDN_SLOW (mA)
10
GATE DRIVE (V)
10 VCC = 8V
9
VCC = 5V
8
8
7
6
6
5
4
4
3
2 2
1
0 0
12198-213
12198-216
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 0 5 10 15 20 25
TEMPERATURE (°C) VCC (V)
Figure 13. GATE Drive (5 μA Load) vs. Temperature Figure 16. IGATEDN_SLOW vs. VCC
35 0
–1
30
–2
25 –3
ITIMERUPPOR (µA)
–4
VGATE (V)
20
–5
15
–6
10 –7
–8
5
–9
0 –10
12198-214
12198-217
0 5 10 15 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80
Figure 14. VGATE (5 μA Load) vs. VCC Figure 17. TIMER Pull-Up Current POR (ITIMERUPPOR) vs. Temperature
16 0
14 –10
12 –20
GATE DRIVE (V)
ITIMERUPFLT (µA)
10 –30
8 –40
6 –50
4 –60
2 –70
0 –80
12198-215
0 5 10 15 20
12198-218
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80

Figure 15. GATE Drive vs. VCC Figure 18. TIMER Pull-Up Current OC Fault (ITIMERUPFLT) vs. Temperature
Data Sheet ADM1278
0 100
–1 90
–2 80
–3 70
ITIMERDNHOLD (µA)
ITIMERUPPOR (µA)
–4 60
–5 50
–6 40
–7 30
–8 20
–9 10
–10 0
12198-221
12198-219
0 5 10 15 20 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80
Figure 19. TIMER Pull-Up Current POR (ITIMERUPPOR) vs. VCC Figure 22. TIMER Pull-Down Current Hold (ITMERDNHOLD) vs. Temperature
0 1000
900
–10
800
–20
700
ITIMERUPFLT (µA)
–30
VTIMERL (mV)
600
–40 500
400
–50
300
–60
200
–70
100
–80 0
12198-224
12198-223
0 5 10 15 20 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80

Figure 20. TIMER Pull-Up Current OC Fault (ITIMERUPFLT) vs. VCC Figure 23. TIMER Low Threshold (VTIMERL) vs. Temperature
4 1100
1000
900
3
800
ITIMERDNRT (µA)
700
VTIMERH (mV)
600
2
500
400
1 300
200
100
0 0
12198-220
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80

12198-226
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80

Figure 21. TIMER Pull-Down Current Retry (ITIMERDNRT) vs. Temperature Figure 24. TIMER High Threshold (VTIMERH) vs. Temperature
ADM1278 Data Sheet
1100 100
UV THRESHOLD LOW (mV)
UV THRESHOLD HIGH (mV)
90
80
1050
OV HYSTERESIS (mV)
70
UV THRESHOLD (mV)
60
1000 50
40
30
950
20
10
900 0
12198-227
12198-230
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80
Figure 25. UV Threshold vs. Temperature Figure 28. OV Hysteresis vs. Temperature
100 1100
PWGIN THRESHOLD LOW (mV)
90 PWGIN THRESHOLD HIGH (mV)
80
1050
70 PWGIN THRESHOLD (mV)
UV HYSTERESIS (mV)
60
50 1000
40
30
950
20
10
0 900
12198-228
12198-231
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80
Figure 26. UV Hysteresis vs. Temperature Figure 29. PWGIN Threshold vs. Temperature
1100 100
OV THRESHOLD LOW (mV)
OV THRESHOLD HIGH (mV) 90
80
1050
PWGIN HYSTERESIS (mV)
OV THRESH OLD (mV)
70
60
1000 50
40
30
950
20
10
900 0
12198-232
12198-229
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80

Figure 27. OV Threshold vs. Temperature Figure 30. PGIN Hysteresis vs. Temperature
Data Sheet ADM1278
16 5.0
4.5
4.0
14
3.5
3.0
MEASUREMENT ERROR (°C)

12 2.5
2.0
CSOUT VOLTAGE (V)
1.5
10
1.0
0.5
8 0
–0.5
–1.0
6
–1.5
–2.0
4 –2.5
–3.0
–3.5
2
–4.0
–4.5
0 –5.0
12198-235
12198-233
0 10 20 30 40 50 60 –60 –40 –20 0 20 40 60 80 100 120 140 160
VSENSE (mV) EXTERNAL TRANSISTOR TEMPERATURE (°C)
Figure 31. CSOUT Voltage vs. VSENSE Figure 34. Measurement Error vs. External Transistor Temperature
10
7
CSOUT ERROR (%)
2
2
1
12198-032
0
CH2 5.00V M5.00µs CH2 19.8V
12198-234
0 5 10 15 20 25 30
VSENSE (mV)
Figure 32. CSOUT Error vs. VSENSE Figure 35. VGATE Response to Severe Overcurrent Event
(GATE Fast Pull-Down)
150 0.8
×128
140 ×16
130 NO AVG
120
0.6
110
100
OCCURRENCE
90 VCC = 4.5V
VOL (V)
80 0.4
70
VCC = 12V
60
50
40 0.2
30
20
10
0 0
12198-033
0 1 2 3 4 5 6
2834
2836
2838
2840
2842
2844
2846
2848
2850
2852
2854
2856
2858
2860
2862
2864
12198-236
IOL (mA)
CODE
Figure 33. ADC Code Histogram (VSENSE = 10 mV, 200 Measurements) Figure 36. PWGD Pin, VOL vs. IOL
ADM1278 Data Sheet
25 250
200
20
VSENSECL 150
IMO+/ IMO– (nA)

VSENSE (mV)
15
VCB 100
10
50
5
0
0 –50
12198-034
0 2 4 6 8 10 12 14 16
12198-130
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
ISTART CODE (STRT_UP_IOUT_LIM) VMO+ = VMO– (V)
Figure 37. VSENSE vs. ISTART Code (STRT_UP_IOUT_LIM) Figure 40. IMO+/IMO− vs. VMO+/VMO− with VCC = 20 V
25 1.0
0.8
20
0.6
0.4
IMO+/ IMO– (nA)
VSENSE (mV)
15
VSENSECL 0.2
10
0
VCB
–0.2
5
–0.4
0 –0.6
12198-035
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
12198-131
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
ISTART VOLTAGE (V) VMO+ = VMO– (V)
Figure 38. VSENSE vs. ISTART Voltage Figure 41. IMO+/IMO− vs. VMO+/VMO− with VCC = VMO+ = VMO−
25 10
0
20
–10
VDS = 4V
VDS = 8V
VSENSECL (mV)
15 –20
IMO+ (nA)
–30
10
–40
VDS = 20V
–50
5
–60
0
–70
12198-036
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

12198-132
0 10 20 30 40 50 60 70 80 90 100
VPSET VSENSE (mV)
Figure 39. VSENSECL vs. VPSET Figure 42. IMO+ vs. VSENSE with VCC = VMO+ = 20 V
Data Sheet ADM1278
70 150
60
50
100
40
IHS+ /IHS− (µA)

IMO– (nA)
30
20
50
10
–10 0
12198-133
0 1 2 3 4 5 6 7 8 9 10 11 12
12198-134
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100
VSENSE (mV) VHS+ (V)
Figure 43. IMO− vs. VSENSE with VCC = VMO+ = 20 V Figure 44. IHS+/IHS− vs. VHS+
ADM1278 Data Sheet
THEORY OF OPERATION
When circuit boards are inserted into a live backplane,
discharged supply bypass capacitors draw large transient
currents from the backplane power bus as they charge. These
22Ω
transient currents can cause permanent damage to connector HS+ HS–
pins, as well as dips on the backplane supply that can reset other
boards in the system.
The ADM1278 is designed to control the powering on and off VCC GATE
ADM1278
of a system in a controlled manner, allowing a board to be
removed from, or inserted into, a live backplane by protecting it 330nF
from excess currents. The ADM1278 can reside on the
12198-006
backplane or on the removable board. GND
POWERING THE ADM1278 Figure 46. Transient Glitch Protection Using an RC Network
A supply voltage from 4.5 V to 20 V is required to power the HOT SWAP CURRENT SENSE INPUTS
ADM1278 via the VCC pin. The VCC pin provides the
The load current is monitored by measuring the voltage drop
majority of the bias current for the device; the remainder of the
across an external sense resistor, RSENSE (see Figure 47). An
current needed to control the gate drive and to best regulate the
internal current sense amplifier provides a gain of 50 to the
VGS voltage is supplied by the HS+ pin.
voltage drop detected across RSENSE. The result is compared to
To ensure correct operation of the ADM1278, the voltage on an internal reference and used by the hot swap control logic to
the VCC pin must be greater than or equal to the voltage on detect when an overcurrent condition occurs.
the HS+ and MO+ pins. No sequencing of the VCC and HS+ RSENSE Q1
rails is necessary. The HS+ pin can be as low as 2 V for normal
operation, provided that a voltage of at least 4.5 V is connected
to the VCC pin. In most applications, both the VCC and HS+ pins
are connected to the same voltage rail, but they are connected via HS+ HS–
separate traces to prevent accuracy loss in the sense voltage + –

×50
measurement (see Figure 45).
4.5V TO 20V RSENSE Q1 VCC OVER- GATE
+ CURRENT
REFERENCE –
ADM1278
12198-007
HS+ HS–
GND
Figure 47. Hot Swap Current Sense Amplifier

VCC
ADM1278 GATE The HS± inputs can be connected to multiple parallel sense
resistors, which can affect the voltage drop detected by the
ADM1278. The current flowing through the sense resistors
creates an offset, resulting in reduced accuracy.
12198-005
GND
To achieve better accuracy, averaging resistors can be used to sum
Figure 45. Powering the ADM1278 the current from the nodes of each sense resistor, as shown in
To protect the ADM1278 from unnecessary resets due to transient Figure 48. A typical value for the averaging resistors is 10 Ω.
supply glitches, an external resistor and capacitor can be added, as The input current to each sense pin is matched to within 5 μA.
shown in Figure 46. Choose the values of these components such This ensures that the same offset is observed by both sense
that a time constant is provided that can filter any expected inputs.
glitches. However, use a resistor that is small enough to keep
voltage drops caused by quiescent current to a minimum. Unless a
resistor is used to limit the inrush current, do not place a supply
decoupling capacitor on the rail before the FET.
Data Sheet ADM1278
2V
TO 20V Q1 CURRENT-LIMIT REFERENCE
The current-limit reference voltage determines the load current
level to which the ADM1278 limits the current during an over-
HS+ HS– current event. This reference voltage is compared to the amplified
current sense voltage to determine whether the limit is reached.
BIAS
CURRENT An internal current-limit reference selector block continuously
VCC GATE compares the ISET and PSET voltages to determine which voltage
12198-008
reference is the lowest at any given time; the lowest voltage is used
GND
as the current-limit reference. The ISTART pin is also
Figure 48. Connection of Multiple Sense Resistors to the HS± Pins monitored while PWRGD is inactive. This ensures that the
POWER MONITOR CURRENT SENSE INPUTS programmed current limit, ISET, is used in normal operation,
and that the start-up current limit and foldback features reduce
The internal ADC uses separate current sense input pins for the current limit when required during startup and/or fault
measuring the load current from those used by the hot swap conditions.
circuitry. This allows additional filtering on the power monitor
RSENSE Q1
pins without affecting the response time of the hot swap to an
overcurrent event. HS+ HS–
The same external sense resistor, RSENSE, is used for hot swap
VCC ×50
control and ADC measurements. If additional external filtering
is not required, the HS± and MO± pins can be tied together, OVER- GATE
ISET CURRENT
close to the device under test, as shown in Figure 49.
PSET
RSENSE ISTART
Q1 ADM1278
12198-011
GND
Figure 51. Current-Limit Reference Selection

MO+ HS+ HS– MO–
The foldback and start-up current-limit voltage inputs to the
internal comparator are clamped to minimum levels of 100 mV
(that is, VSENSECL = 2 mV) to prevent zero current flow caused by
VCC GATE the current limit being too low. Figure 52 provides an example
12198-009
of how the ISTART, PSET, and ISET voltages interact during

GND
startup as the ADM1278 is enhancing the FET and charging the
Figure 49. Power Monitor, No External Filtering output load capacitance.
If additional antialiasing filtering is required, filtering V
components can be added, as shown in Figure 50, without

PSET
affecting the hot swap performance.
RSENSE
1V ISET
CURRENT-LIMIT
HS+ MO+ MO– HS– REFERENCE
+ – ISTART
ADC
+ – 0.1V
VOUT
ADM1278 HS CONTROL
12198-010
12198-012
Figure 50. Power Monitor Current Sense Filtering PWRGD
Figure 52. Interaction of ISTART, PSET, and ISET Current Limits
ADM1278 Data Sheet
SETTING THE CURRENT LIMIT (ISET) The VCAP rail can also be used as the pull-up supply for the
The maximum current limit is partially determined by selecting resistor divider on the PSET and ISTART pins and for setting
a sense resistor to match the current sense voltage limit on the the I2C address. Do not use the VCAP pin for any other purpose.
controller for the desired load current. However, as currents To guarantee accuracy specifications, do not load the VCAP pin
become larger, the sense resistor requirements become smaller, by more than 100 μA.
and resolution can be difficult to achieve when selecting the SETTING A LINEAR OUTPUT VOLTAGE RAMP AT
appropriate sense resistor. The ADM1278 provides an adjustable POWER-UP
current sense voltage limit to manage this issue. The device The ADM1278 standard method of power-up in a server
allows the user to program the required current sense voltage application is to configure a single linear voltage ramp on the
limit from 5 mV to 25 mV. output, which allows a constant inrush current into the load
The default value of 20 mV is achieved by connecting the ISET capacitance. This method has the advantage of setting very low
pin directly to the VCAP pin. This connection configures the inrush currents where required by a combination of large
device to use an internal 1 V reference, which equates to 20 mV output capacitance and FET SOA limitations.
at the sense inputs (see Figure 53). The object of such a design is to allow a linear monotonic
VCAP power-up event without the restrictions of the system fault
timer. To achieve this, a power-up ramp is set such that the
C1
inrush is low enough not to reach the active circuit breaker
current limit. This allows the power-up to continue without the
ADM1278 timer running. When using this method, ensure that the power
ISET
in the MOSFET during this event meets the SOA requirements.
An extra component, CGATE, is required on the GATE pin as
shown in Figure 55.
12198-013
GND
HS+ HS–
Figure 53. Fixed 20 mV Current Sense Limit
To program the sense voltage from 5 mV to 25 mV, a resistor

VCC
divider is used to set a reference voltage on the ISET pin (see GATE
ADM1278
Figure 54). CGATE
VCAP
PGND
12198-015
GND
C1 R1
Figure 55. DV/DT Power-Up Configuration
ADM1278
ISET To ensure that the inrush current does not approach or exceed
the active current-limit level, the output voltage ramp can be set
by selecting the appropriate value for CGD as follows:
R2
CGATE = (IGATEUP/IINRUSH) × CLOAD
where IGATEUP is the gate pull-up current specified.
12198-014
GND
Add margin and tolerance as necessary to ensure a robust
Figure 54. Adjustable 5 mV to 25 mV Current Sense Limit design. Subtract any parasitic CGD of the MOSFETs from the
total to determine the additional external capacitance required.
The VCAP pin has a 2.7 V internal generated voltage that can
be used to set a voltage at the ISET pin. Assuming that VISET Next, the power-up ramp time can be approximated by
equals the voltage on the ISET pin, size the resistor divider to tRAMP = (VIN × CLOAD)/IINRUSH = (VIN × CGATE)/IGATEUP
set the ISET voltage as follows: Check the SOA of the MOSFET for conditions and the
VISET = VSENSECL × 50 duration of this power-up ramp. TIMER regulation period can
where VSENSECL is the current sense voltage limit. be minimized to provide a simple fault filtering solution.
The diagram in Figure 56 shows a typical hot swap power-up
with a gate capacitor configured for a linear output voltage
ramp.
Data Sheet ADM1278
VCC/ 12V
ENABLE
0V
1V
TIMER
0V
GATE
24V
GATE/ 16V
VOUT
VOUT
12V
0V
~3A TYP
IOUT
0A
12V
PWRGD
(PULL-UP
TO VCC)
0V
CL = ISET
(FOR EXAMPLE, 60A)
CURRENT CL = ISTART
LIMIT (FOR EXAMPLE, 10A)
12198-116
POR TIME SET BY OUTPUT VOLTAGE
TIMER CAPACITOR RAMP SET BY
(MIN 27ms) GATE CAPACITOR
Figure 56. Linear Voltage Ramp Power-Up
START-UP CURRENT LIMIT More importantly, the circuit breaker level can be calculated
When powering up in dv/dt mode, the inrush current is typically using the following equation:
configured to be in the order of <5 A. The other active current  VISTART  0.88 mV
limits (PSET and ISET) may be much higher than this. The start-  
Startup_ CB   
50
up current limit is intended as an extra level of protection during RSENSE
this initial power-up stage. It helps catch a resistive type fault that
causes the inrush to be higher than expected. To prevent the start-up current limit from being triggered
during a normal dv/dt power-up, set the circuit breaker level
The start-up current limit is only active during power-up. It is
above the maximum expected inrush current.
enabled while PWRGD is deasserted and is disabled when
PWRGD is asserted. The ISTART pin can be tied to VCAP to disable the start-up
current limit. The start-up current limit PMBus register is set to
The start-up current limit can be programmed via the ISTART pin
the maximum by default; therefore, it is effectively disabled by
or via the PMBus register, STRT_UP_IOUT_LIM (Register 0xF6).
default.
If both are configured, the lowest current limit is selected as the
active current limit. The clamp level in both cases is a 2 mV VSENSE If configuring the start-up current limit with the PMBus
current limit. register, the start-up current limit is set as a fraction of the ISET
current limit. There are four register bits so that the start-up
When configuring with the ISTART pin, the current limit is
current limit can be set from 1/16th to 16/16th of the normal
VISTART current limit. The effective ISTART voltage can be calculated as
Startup_ CL 
50  RSENSE
 STRT _ UP _ IOUT _ LIM   1 
VISTART  VISET   
 16 
ADM1278 Data Sheet
The start-up circuit breaker and current limits can then be reset. During this first short reset period, the GATE and
calculated from this effective ISTART voltage. TIMER pins are both held low.
CONSTANT POWER FOLDBACK The ADM1278 then goes through an initial timing cycle. The
Foldback is a method that actively reduces the current limit as TIMER pin is pulled high with 3 μA. When the TIMER pin
the voltage drop across the FET increases. It keeps the power reaches the VTIMERH threshold (1.0 V), the first portion of the
across the FET below the programmed value during power-up, initial timing cycle is complete. The initial timing cycle is a
overcurrent, or short-circuit events. This allows a smaller FET minimum of approximately 27 ms to allow FET health checks
to be used, resulting in board size savings and cost savings. The to be completed. If the initial TIMER cycle is set shorter than 27
foldback method used is a constant power foldback scheme, ms by the TIMER capacitor, the TIMER pin continues to be
meaning power in the FET is held constant, regardless of the pulled up to the VCAP voltage level until the 27 ms has expired.
VDS of the FET. This simplifies the task of ensuring that the FET The 100 μA current source then pulls down the TIMER pin until
is always operating within the SOA limits. it reaches VTIMERL (0.2 V). The initial timing cycle duration is
related to CTIMER by the following equation:
The ADM1278 detects the VDS voltage drop across the FET by
sensing the HS+ and VOUT pins. The foldback current limit VTIMERH  CTIMER (VTIMERH  VTIMERL )  CTIMER
t INITIAL  
dynamically changes as the VDS voltage changes to maintain a 3 μA 100 μA
constant power level in the MOSFET. For example, as VOUT where tINITIAL ≥ 27 ms, regardless of CTIMER value.
drops, the current-limit reference follows VPSET after it becomes
the lowest voltage input to the current-limit reference selector For example, a 100 nF capacitor results in an initial insertion
block. This results in a reduction of the current limit and, delay of approximately 34 ms. If the UV and OV inputs
therefore, the regulated load current. To prevent complete current indicate that the supply is within the defined window of operation
flow restriction, a clamp becomes active when the current-limit when the initial timing cycle terminates, the device is ready to start
reference reaches 100 mV. The current limit cannot drop below a hot swap operation.
this level. When the voltage across the sense resistor reaches the circuit
The maximum FET power level is configured with a resistor breaker trip voltage, VCB, the 60 μA TIMER pull-up current is
divider on the PSET pin activated, and the gate begins to regulate the current at the current
limit. This initiates a ramp-up on the TIMER pin. If the sense
FET Power Limit 
VPSET  8 voltage falls below this circuit breaker trip voltage before the
50  RSENSE  TIMER pin reaches VTIMERH, the 60 μA pull-up is disabled and
Therefore, after determining the desired FET power limit and the 2 μA pull-down is enabled.
RSENSE values, the required PSET voltage can be calculated. Set The circuit breaker trip voltage is not the same as the hot swap
this voltage with a resistor divider from the VCAP pin. sense voltage current limit. There is a small circuit breaker offset,
VCBOS, which means that the TIMER pin actually starts ramping
TIMER
a short time before the current reaches the defined current limit.
The TIMER pin handles several timing functions with an
However, if the overcurrent condition is continuous and the
external capacitor, CTIMER. The two comparator thresholds are
sense voltage remains above the circuit breaker trip voltage, the
VTIMERL (0.2 V) and VTIMERH (1 V). There are four timing current
60 μA pull-up current remains active and the FET remains in
sources: a 3 μA pull-up, a 60 μA pull-up, a 2 μA pull-down, and
regulation.
a 100 μA pull-down.
This allows the TIMER pin to reach VTIMERH and to initiate the
These current and voltage levels, together with the value of
CTIMER chosen by the user, determine the initial timing cycle GATE shutdown. On the ADM1278, the FAULT pin is pulled
time and the fault regulation time. The TIMER pin capacitor low immediately and PWRGD is deasserted.
value is determined using the following equation: In latch-off mode, the TIMER pin is switched to the 2 μA
CTIMER = (tON × 60 μA)/VTIMERH pull-down current when it reaches the VTIMERH threshold. While
the TIMER pin is being pulled down, the hot swap controller
where tON is the time that the FET is allowed to spend in remains off and cannot be turned back on.
regulation at the set current limit.
When the voltage on the TIMER pin goes below the VTIMERL
The choice of FET is based on matching this time with the SOA threshold, the hot swap controller can be reenabled by toggling
requirements of the FET. Foldback can be used to simplify the the UV pin or by using the PMBus OPERATION command to
selection. toggle the on bit from on to off and then on again.
When VCC is connected to the backplane supply, the internal
supply of the ADM1278 must be charged up. In a very short
time, the internal supply is fully charged up and, because the
UVLO voltage is exceeded at VCC, the device emerges from
Data Sheet ADM1278
HOT SWAP RETRY POWER GOOD
The RETRY pin is used to configure latch-off or autoretry The power-good (PWRGD) output can be used to indicate
mode. The RETRY pin has an internal pull-up current; therefore, whether the output voltage is above a user defined threshold
it can be left floating to enable latch-off mode after an and can, therefore, be considered good. A resistor divider on
overcurrent fault. The RETRY pin can be pulled low to enable a the PWGIN pin sets an accurate power-good threshold on the
10 second autoretry following an overcurrent fault. output voltage.
FET GATE DRIVE CLAMPS The PWRGD pin is an open-drain output that pulls low when
the voltage at the PWGIN pin is lower than 1.0 V (power bad).
The charge pump used on the GATE pin is capable of driving When the voltage at the PWGIN pin is above this threshold
the pin to VCC + (2 × VCC), but it is clamped to less than 14 V plus a fixed hysteresis of 60 mV, output power is considered to be
above the HS± pins and less than 31 V. These clamps ensure that good.
the maximum VGS rating of the FET is not exceeded.
However, PWRGD asserts only when the following conditions
FAST RESPONSE TO SEVERE OVERCURRENT are met:
The ADM1278 features a separate high bandwidth current
 PWGIN is above the rising threshold voltage.
sense amplifier that detects a severe overcurrent that is
 Hot swap is enabled, that is, the ENABLE pin is high
indicative of a short-circuit condition. A fast response time
(ENABLE pin is low), and UV and OV are within range.
allows the ADM1278 to handle events of this type that may
otherwise cause catastrophic damage if not detected and acted  There is no active fault condition, that is, the FAULTpin
on very quickly. The fast response circuit ensures that the has been cleared following any fault condition.
ADM1278 can detect an overcurrent event at approximately  The MOSFET is fully enhanced (gate voltage >
125% to 225% of the normal current limit (ISET) and can VMOSFET_DRAIN + 4 V).
respond to and control the current within 1 μs, in most cases. After all of these conditions are met, the open-drain pull-down
There are four severe overcurrent threshold options and two current is disabled, allowing PWRGD to be pulled high.
severe overcurrent glitch filter options selectable via the PMBus PWRGD is guaranteed to be in a valid state for VCC ≥ 1 V.
registers. If the gate voltage drops below VMOSFET_DRAIN + 4 V (that is, no
UNDERVOLTAGE AND OVERVOLTAGE longer meets MOSFET fully enhanced condition), PWRGD still
remains asserted for 100 ms. If the condition persists for longer
The ADM1278 monitors the supply voltage for undervoltage
than 100 ms, PWRGD is deasserted and an FET health fault is
(UV) and overvoltage (OV) conditions. The UV and OV pins
signaled.
are connected to the input of an internal voltage comparator,
and its voltage level is internally compared with a 1 V voltage If any of the other conditions for PWRGD are no longer met,
reference. PWRGD is deasserted immediately.
Figure 57 illustrates the voltage monitoring input connections. FAULT PIN
An external resistor network divides the supply voltage for moni- The FAULT pin asserts when one of the following faults causes
toring. An undervoltage event is detected when the voltage
the hot swap to shut down:
connected to the UV pin falls below 1 V, and the gate is shut
down using the 10 mA pull-down device. Similarly, when an  FET health fault
overvoltage event occurs and the voltage on the OV pin exceeds  Overcurrent fault
1 V, the gate is shut down using the 10 mA pull-down device.  Overtemperature fault
There is a fixed 60 mV hysteresis on the UV and OV pin
The FAULT pin is latched, and it can only be cleared by a rising
thresholds.
edge on the ENABLE pin (falling edge on the ENABLE pin), a
VIN RSENSE
Q1
PMBus OPERATION on command from the off state, or a
HS+ HS– POWER_CYCLE command, assuming no faults are still active.
VCC + – ADM1278 The fault registers are not cleared by the ENABLE/ENABLE pin
×50
or the POWER_CYCLE command; they can only be cleared by
IOUT a PMBus OPERATION off to on command or a
UV
+ CLEAR_FAULTS command.
1V – GATE
DRIVE GATE
OV
–
1V +
12198-016
GND
Figure 57. Undervoltage and Overvoltage Supply Monitoring
ADM1278 Data Sheet
RSENSE
controller can then monitor and respond to an elevated
MOSFET operating temperature. It is not possible to measure
temperature at more than one location on the board.
Place the transistor close to the MOSFET for best accuracy. If
HS+ HS– GATE
TEMP the transistor is placed on the opposite side of the PCB, use
FET
FAULT
multiple vias to ensure the optimum transfer of heat from the
HEALTH
MONTIOR MOSFET to the transistor.
ENABLE
OVER
CURRENT Temperature Measurement Method
FAULT
A simple method of measuring temperature is to exploit the
OVER
12198-017
TEMPERATURE negative temperature coefficient of a diode by measuring the
ADM1278 FAULT
base-emitter voltage (VBE) of a transistor operated at constant
Figure 58. FAULT Pin Operation current. However, this technique requires calibration to null
the effect of the absolute value of VBE, which varies from device
ENABLE/ENABLE INPUT
to device.
The ADM1278 provides a dedicated ENABLE/ENABLE digital
The technique used in the ADM1278 is to measure the change
input pin. The ADM1278-1 and ADM1278-2 have an active
in VBE when the device is operated at three different currents.
high ENABLE pin whereas the ADM1278-3 has an active low
The use of a third current allows automatic cancellation of
ENABLE pin. The ENABLE/ENABLE pin allows the ADM1278
resistances in series with the external temperature sensor.
to remain off by using a hardware signal, even when the voltage
on the UV pin is greater than 1.0 V and the voltage on the OV The temperature sensor takes control of the ADC for 64 μs
pin is less than 1.0 V. Although the UV pin can be used to (typical) every 6 ms. It takes 12 ms to obtain a new temperature
provide a digital enable signal, using the ENABLE/ENABLE pin measurement from the ADC.
for this purpose means that the ability to monitor for Remote Sensing Diode
undervoltage conditions is not lost. The ADM1278 is designed to work with discrete transistors.
In addition to the conditions for the UV and OV pins, the The transistor can be either a PNP or NPN connected as a
ADM1278 ENABLE/ENABLE input pin must be asserted for diode (base shorted to the collector). If an NPN transistor is
the device to begin a power-up sequence. used, the collector and base are connected to the TEMP pin and
the emitter to PGND. If a PNP transistor is used, the collector
CURRENT SENSE OUTPUT (CSOUT) and base are connected to PGND and the emitter to TEMP.
The ADM1278 provides a CSOUT pin voltage output that is
The best accuracy is obtained by choosing devices according to
proportional to the VSENSE_HS voltage.
the following criteria:
CSOUT = VSENSE_HS × 350
 Base-emitter voltage greater than 0.25 V at 6 μA, at the
The CSOUT voltage is an analog representation of the main highest operating temperature.
system current flowing through RSENSE. A resistor divider can be  Base-emitter voltage less than 0.95 V at 100 μA, at the
added to CSOUT to clamp the voltage output to any lowest operating temperature.
downstream devices, provided the maximum load conditions  Base resistance less than 100 Ω.
described in Table 2 are not exceeded.  Small variation in hFE (50 to 150) that indicates tight
The response time of the CSOUT pin to a change in VSENSE control of VBE characteristics.
voltage is very fast; therefore, it can be used when fast response
Transistors, such as the 2N3904, 2N3906, or equivalent in
time is required, for example, power throttling. The CSOUT
SOT-23 packages are suitable devices to use.
response time to a 10 mV step in VSENSE voltage is typically 10 μs.
Noise Filtering
REMOTE TEMPERATURE SENSING
For temperature sensors operating in noisy environments, the
The ADM1278 provides the capability to measure temperature
industry standard practice has been to place a capacitor across
at a remote location with a single discrete NPN or PNP
the temperature pins to mitigate the effects of noise. However,
transistor. The temperature measurements can be read back
large capacitances affect the accuracy of the temperature
over the PMBus interface. Warning and fault thresholds can
measurement, leading to a recommended maximum capacitor
also be set on the temperature measurement. Exceeding a fault
value of 1000 pF. Although this capacitor reduces the noise, it
threshold causes the controller to turn off the pass MOSFET,
does not eliminate it, making it difficult to use the sensor in a
deassert the PWRGD pin, and assert the FAULT pin. very noisy environment.
The external transistor is typically placed close to the main pass The ADM1278 has a major advantage over other devices for
MOSFETs to provide an additional level of protection. The eliminating the effects of noise on the external sensor. The
Data Sheet ADM1278
series resistance cancellation feature allows a filter to be con- 0), but it is also possible to launch and capture data on the same
structed between the external temperature sensor and the device. clock edge for extra timing margin if required.
The effect of any filter resistance seen in series with the remote The interface has the following characteristics:
sensor is automatically cancelled from the temperature result.
 MDAT is driven by the ADM1278 (master input, slave
The construction of a filter allows the ADM1278 and the
output). SPI_SS and MCLK are driven by the user, for
remote temperature sensor to operate in noisy environments.
example, a baseboard management controller (BMC).
Figure 59 shows a low-pass R-C-R filter with the following
 No header or ID information required. The 80-bit data
values: R = 100 Ω and C = 1 nF. This filtering reduces both
format is fixed regardless of ADC sampling selection (see
common-mode noise and differential noise.
Figure 60).
100Ω
TEMP  The falling edge of SPI_SS activates the serial interface, at
REMOTE
TEMPERATURE 1nF which point MCLK can be used to clock out data on
12198-018
SENSOR
100Ω
PGND MDAT. The time between SPI_SSfalling edges must be
Figure 59. Filter Between Remote Sensor and ADM1278 greater than or equal to the maximum ADC sampling time
to avoid duplicate data.
SPI INTERFACE
 Select single shot mode to allow the falling edge of SPI_SS
The serial peripheral interface (SPI) allows the user to output a to trigger ADC sampling (ADC convert start signal).
stream of raw data from the ADC as soon as new data is  Maximum clock speed (MCLK) is approximately 1 MHz.
available, removing the bandwidth limitations of the PMBus
 The output stream can be stopped at any point in the
interface for data readback. The PMBus remains as an active
output frame via a rising edge on the SPI_SS pin.
data bus and all configuration and register access must still be
 The MSB of each sample is output first.
completed over the PMBus interface. However, the SPI
interface can be used at the same time to serially output the  The output data line is high impedance when not
ADC monitoring data. It is a 3-pin serial interface capable of transmitting.
operating at speeds of up to 1 MHz. For example, if configuring the SPI interface to read back ADC
The SPI pins are only available on the ADM1278-2 model. If current samples (16 bits), 15 MCLK falling edges are required
the ADM1278-2 model is used but the SPI pins are not to clock out all of the bits after the initial falling edge on SPI_SS
required, tie the SPI input pins (SPI_SS, MCLK) to VCAP and . These bits can be clocked out at 1 MHz; therefore, with an ADC
the SPI output pin (MDAT) can be left floating or tied to GND. sample time of approximately 165 μs, the latency between
sample and data is 181 μs. See Figure 3 for SPI timing
SPI_SS is the slave select pin, and when it is held low, the
information.
MCLK pin can be used to clock data out on the MDAT serial
output pin. The SPI_SS pin is also used to frame the output data. Note that the MDAT output samples are offset by one sample
The SPI pins are compatible with SPI Mode 0 (CPOL = CPHA = from the ADC. 12198-019
IOUT VIN PIN VOUT TEMPERATURE

16 BITS 16 BITS 16 BITS 16 BITS 16 BITS
Figure 60. Output Data Format
SPI_SS
MCLK
MDAT I0 I1 I2
12198-020
ADC
I1 I2 I3
SAMPLING
Figure 61. Streaming Current Data Only
ADM1278 Data Sheet
VOUT MEASUREMENT power throttling can be configured independently of the active
The VOUT pin measures the output voltage after the FET. This hot swap current limit. However, the accuracy of the CSOUT
voltage is used by the device to determine the VDS of the MOSFET pin has to be taken into account when setting the power
for foldback operation. Add a 1 kΩ resistor in series between the throttling threshold.
source of the FET and the VOUT pin. This resistor provides The latest Intel® processors have a fast processor hot (fast
some separation between the ADM1278 and the FET source PROCHOT) input/output pin that can be used for power
during a fault condition; thus, ADM1278 operation is not throttling. Asserting this pin initiates a deep throttle of the
affected. processor. This is usually used as a last attempt at throttling
The VOUT pin on the ADM1278 can also be used to provide to avoid a card shutting down when all else has failed. The
an alternate voltage for the power monitor to measure. The HS_INLIM_FAULT alert signal or the CSOUT pin can be
user can choose to measure the input voltage at the HS+ pin used to drive this fast PROCHOT pin to achieve power
and/or the output voltage at the VOUT pin. throttling.
FET HEALTH POWER MONITOR

The ADM1278 provides a comprehensive method of detecting The ADM1278 features an integrated ADC that accurately meas-
a faulty pass MOSFET. When a faulty FET is detected, the ures the current sense voltage, the input voltage, and optionally,
following occurs: the output voltage and temperature at an external transistor.
The measured input voltage and current being delivered to the
 PWRGD is deasserted. load are multiplied together to give a power value that can be read
 FAULT is asserted and latched low. back. Each power value is also added to an energy accumulator
 FET health PMBus status bits are asserted and latched. that can be read back to allow an external device to calculate the
energy consumption of the load.
This detection feature ensures that any downstream dc-to-dc
converters are disabled, limiting the power dissipation in any The ADM1278 reports the measured current, input voltage,
faulty or overheating FETs until the user clears the fault, which output voltage, and temperature. The PEAK_IOUT, PEAK_VIN,
can be critical to avoid any catastrophic events due to faulty FETs. PEAK_VOUT, PEAK_PIN, and PEAK_TEMPERATURE
commands can be used to read the highest readings since the
A gate to source or gate to drain short is a common type of FET
value was last cleared.
failure. This type of failure is detected by the ADM1278 at any
time during operation. An averaging function is provided for voltage, current, and power
that allows a number of samples to be averaged together by the
A less common failure is a drain to source short. This normally
ADM1278. This function reduces the need for postprocessing
occurs due to a board manufacturing defect such as a solder short.
of sampled data by the host processor. The number of samples
This type of failure is detected during the initial power-on reset
that can be averaged is 2N, where N is in the range of 0 to 7.
cycle after power-up or after a 10 second autoretry attempt.
The power monitor current sense amplifier is bipolar and
There is also an option to disable FET health detection via the
measures both positive and negative currents. The power monitor
PMBus.
amplifier has an input range of ±25 mV.
POWER THROTTLING
The two basic modes of operation for the power monitor are
The ADM1278 provides a number of methods for initiating single shot and continuous. In single shot mode, the ADC samples
power throttling of a processor. The simplest method is to the input voltage and current a number of times, depending on the
configure one of the alert pins for HS_INLIM_ENx (Alert 1 averaging value selected by the user. The ADM1278 returns a
and Alert 2 configuration registers, Bit 4). A latched alert is single value corresponding to the average voltage and current
then generated within a few microseconds after the circuit measured. When configured for continuous mode, the power
breaker threshold is exceeded (that is, when the TIMER pin monitor continuously samples the voltage and current, making
starts ramping). This signal throttles the processor in an the most recent sample available to be read.
attempt to reduce the system current level below the circuit
The single shot mode can be triggered in a number of ways.
breaker threshold before the TIMER regulation period expires.
The simplest method is by selecting the single shot mode using
The CSOUT pin can be used for the purposes of power the PMON_CONFIG command and writing to the convert bit
throttling as well. The response time of the CSOUT pin to a using the PMON_CONTROL command. The convert bit can
VSENSE step of 10 mV is approximately 10 μs. The CSOUT pin also be written as part of a PMBus group command. Using a
can then be fed into a comparator (via a resistor divider) to set a group command allows multiple devices to be written to as part
programmable analog threshold for the system current. The of the same I2C bus transaction, with all devices executing the
output of the comparator can be used to throttle the processor command when the stop condition appears on the bus. In this
after the configured threshold has been exceeded. The way, several devices can be triggered to sample at the same
advantage of using the CSOUT pin is that the threshold for time.
Data Sheet ADM1278
Each time current sense and input voltage measurements are The power accumulator and power sample counter are read using
taken, a power calculation is performed, multiplying the two the same READ_EIN command to ensure that the accumulated
measurements together. This can be read from the device using value and sample count are from the same point in time. The
the READ_PIN command, returning the input power. bus host reading the data assigns a time stamp when the data is
At the same time, the calculated power value is added to a power read. By calculating the time difference between consecutive uses
accumulator register that may increment a rollover counter if the of READ_EIN and determining the delta in power consumed,
value exceeds the maximum accumulator value. The power it is possible for the host to determine the total energy
accumulator register also increments a power sample counter. consumed over that period.
ADM1278 Data Sheet
PMBUS INTERFACE
The I2C bus is a common, simple serial bus used by many devices Table 11. PMBus Address Decode (7-Bit Address)
to communicate. It defines the electrical specifications, the bus
ADR2 State ADR1 State Device Address (Hex)
timing, the physical layer, and some basic protocol rules.
Low Low 0x10
SMBus is based on I2C and aims to provide a more robust and Low Resistor 0x11
fault tolerant bus. Functions such as bus timeout and packet Low High-Z 0x12
error checking are added to help achieve this robustness, Low High 0x13
together with more specific definitions of the bus messages Resistor Low 0x40
used to read and write data to devices on the bus. Resistor Resistor 0x41
PMBus is layered on top of SMBus and, in turn, on I2C. Using the Resistor High-Z 0x42
SMBus defined bus messages, PMBus defines a set of standard Resistor High 0x43
commands that can be used to control a device that is part of a High-Z Low 0x44
power chain. High-Z Resistor 0x45
High-Z High-Z 0x46
The ADM1278 command set is based on the PMBus™ Power
High-Z High 0x47
System Management Protocol Specification, Part I and Part II,
High Low 0x50
Revision 1.2. This version of the standard is intended to
High Resistor 0x51
provide a common set of commands for communicating with
High High-Z 0x52
dc-to-dc type devices. However, many of the standard PMBus
High High 0x53
commands can be mapped directly to the functions of a hot swap
controller. SMBUS PROTOCOL USAGE
Part I and Part II of the PMBus standard describe the basic All I2C transactions on the ADM1278 are performed using
commands and their use in a typical PMBus setup. The SMBus defined bus protocols. The following SMBus protocols
following sections describe how the PMBus standard and the are implemented by the ADM1278:
ADM1278 specific commands are used.  Send byte
DEVICE ADDRESSING  Receive byte
The ADM1278 is available in three A grade models: the  Write byte
ADM1278-1, ADM1278-2, and ADM1278-3. There is also an  Read byte
AA grade version of the ADM1278-1 with improved power  Write word
monitoring accuracy and a B grade version with lower power  Read word
monitoring accuracy.  Block read
The PMBus device address is seven bits in size. There are no PACKET ERROR CHECKING
default addresses for any of the models; any device can be
The ADM1278 PMBus interface supports the use of the packet
programmed to any of 16 possible addresses. Two quad level
error checking (PEC) byte that is defined in the SMBus standard.
ADRx pins map to the 16 possible device addresses.
The PEC byte is transmitted by the ADM1278 during a read
Table 10. ADRx Pin Connections transaction or sent by the bus host to the ADM1278 during a
ADRx State ADRx Pin Connection write transaction. The ADM1278 supports the use of PEC with
Low Connect to GND all the SMBus protocols that it implements.
Resistor 150 kΩ resistor to GND The use of the PEC byte is optional. The bus host can decide
High-Z No connection (floating) whether to use the PEC byte with the ADM1278 on a message
High Connect to VCAP by message basis. There is no need to enable or disable PEC in
the ADM1278.
The PEC byte is used by the bus host or the ADM1278 to detect
errors during a bus transaction, depending on whether the
transaction is a read or a write. If the host determines that the
PEC byte read during a read transaction is incorrect, it can decide
to repeat the read if necessary. If the ADM1278 determines that
the PEC byte sent during a write transaction is incorrect, it
ignores the command (does not execute it) and sets a status flag.
Within a group command, the host can choose whether to send
a PEC byte as part of the message to the ADM1278.
Data Sheet ADM1278
PARTIAL TRANSACTIONS ON I2C BUS  S is the start condition.
2
If there is a partial transaction on the I C bus (for example,  Sr is the repeated start condition.
spurious data interpreted as a start command), the ADM1278  P is the stop condition.
I2C bus is not locked up, thinking it is in the middle of an I2C  R is the read bit.
transaction. A new start command is recognized even in the  W is the write bit.
middle of another transaction.  A is the acknowledge bit (0).
SMBUS MESSAGE FORMATS  A is the acknowledge bit (1).
Figure 62 to Figure 70 show all the SMBus protocols supported A, the acknowledge bit, is typically active low (Logic 0) when
by the ADM1278, along with the PEC variant. In these figures, the transmitted byte is successfully received by a device.
unshaded cells indicate that the bus host is actively driving the However, when the receiving device is the bus master, the
bus; shaded cells indicate that the ADM1278 is driving the bus. acknowledge bit for the last byte read is a Logic 1, indicated by A.
Figure 62 to Figure 70 use the following abbreviations:
S SLAVE ADDRESS W A DATA BYTE A P
S SLAVE ADDRESS W A DATA BYTE A PEC A P
MASTER TO SLAVE
SLAVE TO MASTER
NOTES
12198-021
1. THE SEND BYTE AND SEND BYTE WITH PEC PROTOCOLS ARE ONLY PERMITTED FOR USE WITH
THE CLEAR_FAULTS COMMAND AND THE POWER_CYCLE COMMAND. THE SEND BYTE MUST
NOT BE USED FOR ANY OTHER COMMANDS.
Figure 62. Send Byte and Send Byte with PEC
S SLAVE ADDRESS R A DATA BYTE A P
S SLAVE ADDRESS R A DATA BYTE A PEC A P
12198-022
MASTER TO SLAVE
SLAVE TO MASTER
Figure 63. Receive Byte and Receive Byte with PEC
S SLAVE ADDRESS W A COMMAND CODE A DATA BYTE A P
S SLAVE ADDRESS W A COMMAND CODE A DATA BYTE A PEC A P

12198-023
MASTER TO SLAVE
SLAVE TO MASTER
Figure 64. Write Byte and Write Byte with PEC
S SLAVE ADDRESS W A COMMAND CODE A Sr SLAVE ADDRESS R A DATA BYTE A P
S SLAVE ADDRESS W A COMMAND CODE A Sr SLAVE ADDRESS R A DATA BYTE A PEC A P

12198-024
MASTER TO SLAVE
SLAVE TO MASTER
Figure 65. Read Byte and Read Byte with PEC
S SLAVE ADDRESS W A COMMAND CODE A DATA BYTE LOW A DATA BYTE HIGH A P
S SLAVE ADDRESS W A COMMAND CODE A DATA BYTE LOW A DATA BYTE HIGH A PEC A P
12198-025
MASTER TO SLAVE
SLAVE TO MASTER
Figure 66. Write Word and Write Word with PEC
ADM1278 Data Sheet
S SLAVE ADDRESS W A COMMAND CODE A Sr SLAVE ADDRESS R A DATA BYTE LOW A
DATA BYTE HIGH A P
S SLAVE ADDRESS W A COMMAND CODE A Sr SLAVE ADDRESS R A DATA BYTE LOW A
DATA BYTE HIGH A PEC A P
12198-026
MASTER TO SLAVE
SLAVE TO MASTER
Figure 67. Read Word and Read Word with PEC
S SLAVE ADDRESS W A COMMAND CODE A Sr SLAVE ADDRESS R A BYTE COUNT = N A
DATA BYTE 1 A DATA BYTE 2 A DATA BYTE N A P
S SLAVE ADDRESS W A COMMAND CODE A Sr SLAVE ADDRESS R A BYTE COUNT = N A
DATA BYTE 1 A DATA BYTE 2 A DATA BYTE N A PEC A P
12198-027
MASTER TO SLAVE
SLAVE TO MASTER
Figure 68. Block Read and Block Read with PEC

ONE OR MORE DATA BYTES
S DEVICE 1 ADDRESS W A COMMAND CODE 1 A LOW DATA BYTE A HIGH DATA BYTE A
Sr DEVICE 2 ADDRESS W A COMMAND CODE 2 A LOW DATA BYTE A HIGH DATA BYTE A
Sr DEVICE N ADDRESS W A COMMAND CODE N A LOW DATA BYTE A HIGH DATA BYTE A P
12198-028
MASTER TO SLAVE
SLAVE TO MASTER
Figure 69. Group Command

S DEVICE 1 ADDRESS W A COMMAND CODE 1 A LOW DATA BYTE A HIGH DATA BYTE A PEC 1 A
Sr DEVICE 2 ADDRESS W A COMMAND CODE 2 A LOW DATA BYTE A HIGH DATA BYTE A PEC 2 A
Sr DEVICE N ADDRESS W A COMMAND CODE N A LOW DATA BYTE A HIGH DATA BYTE A PEC N A P
12198-029
MASTER TO SLAVE
SLAVE TO MASTER
Figure 70. Group Command with PEC
Data Sheet ADM1278
GROUP COMMANDS The default state of Bit 7 (also named the ON bit) of the
The PMBus standard defines what are known as group commands. OPERATION command is 1; therefore, the hot swap output is
Group commands are single bus transactions that send commands always enabled when the ADM1278 emerges from UVLO. If
or data to more than one device at the same time. Each device is the on bit is never changed, the UV input or the
addressed separately, using its own address; there is no special ENABLE/ENABLE input is the hot swap master on/off control
group command address. A group command transaction can signal.
contain only write commands that send data to a device. It is If the on bit is set to 0 while the UV signal is high, the hot swap
not possible to use a group command to read data from devices. output is turned off. If the UV signal is low or if the OV signal is
From an I2C protocol point of view, a normal write command high, the hot swap output is already off and the status of the
consists of the following: on bit has no effect.
 I2C start condition. If the on bit is set to 1, the hot swap output is requested to turn
on. If the UV signal is low or if the OV signal is high, setting the
 Slave address bits and a write bit (followed by an
on bit to 1 has no effect, and the hot swap output remains off.
acknowledge from the slave device).
 One or more data bytes (each of which is followed by an It is possible to determine at any time whether the hot swap output
acknowledge from the slave device). is enabled using the STATUS_BYTE or the STATUS_WORD
 I2C stop condition to end the transaction. command (see the Status Commands section).
The OPERATION command can also clear any latched faults in
A group command differs from a nongroup command in that
the status registers. To clear latched faults, set the on bit to 0 and
after the data is written to one slave device, a repeated start
condition is placed on the bus followed by the address of the then reset it to 1. This also clears the latched FAULT pin.
next slave device and data. This continues until all of the DEVICE_CONFIG Command
devices have been written to, at which point the stop condition The DEVICE_CONFIG command configures certain settings
is placed on the bus by the master device. within the ADM1278, for example, enabling or disabling FET
The format of a group command and a group command with health detection, general-purpose output pin configuration, and
PEC is shown in Figure 69 and Figure 70, respectively. modifying the duration of the severe overcurrent settings.
Each device that is written to as part of the group command POWER_CYCLE Command
does not immediately execute the command written. The The POWER_CYCLE command can be used to request that the
device must wait until the stop condition appears on the bus. At ADM1278 be turned off for approximately five seconds and then
that point, all devices execute their commands at the same time. turned back on. This command is useful if the processor that
Using a group command, it is possible, for example, to turn controls the ADM1278 is also powered off when the ADM1278 is
multiple PMBus devices on or off simultaneously. In the case of turned off. This command allows the processor to request that the
the ADM1278, it is also possible to issue a power monitor ADM1278 turn off and on again as part of a single command.
command that initiates a conversion, causing multiple ADM1278 INFORMATION COMMANDS
ADM1278 devices to sample together at the same time.
CAPABILITY Command
HOT SWAP CONTROL COMMANDS The CAPABILITY command can be used by host processors to
OPERATION Command determine the I2C bus features that are supported by
The GATE pin that drives the FET is controlled by a dedicated the ADM1278. The features that can be reported include the
hot swap state machine. The UV and OV input pins, the TIMER, maximum bus speed, whether the device supports the packet
PWGIN, and ENABLE pins, and the current sense all feed into the error checking (PEC) byte, and the SMBAlert reporting
state machine, and they control when and how strongly the gate function.
is turned off. PMBUS_REVISION Command
It is also possible to control the hot swap GATE output using The PMBUS_REVISION command reports the version of Part
commands over the PMBus interface. The OPERATION I and Part II of the PMBus standard.
command can be used to request the hot swap output to turn
MFR_ID, MFR_MODEL, and MFR_REVISION Commands
on. However, if the UV pin indicates that the input supply is less
than required, the hot swap output is not turned on, even if the The MFR_ID, MFR_MODEL, and MFR_REVISION commands
OPERATION command requests that the output be enabled. return ASCII strings that can be used to facilitate detection and
identification of the ADM1278 on the bus.
If the OPERATION command is used to disable the hot swap
output, the GATE pin is held low, even if all hot swap state These commands are read using the SMBus block read message
machine control inputs indicate that it can be enabled. type. This message type requires that the ADM1278 return a
byte count corresponding to the length of the string data that is
to be read back.
ADM1278 Data Sheet
STATUS COMMANDS STATUS_INPUT Command
The ADM1278 provides a number of status bits to report faults The STATUS_INPUT command returns a number of bits
and warnings from the hot swap controller and the power relating to voltage faults and warnings on the input supply as
monitor. These status bits are located in six different registers well as the overpower warning.
that are arranged in a hierarchy. The STATUS_BYTE and STATUS_VOUT Command
STATUS_WORD commands provide 8 bits and 16 bits of high
The STATUS_VOUT command returns a number of bits
level information, respectively. The STATUS_BYTE and
relating to voltage warnings on the output supply.
STATUS_WORD commands contain the most important
status bits, as well as pointer bits that indicate whether any of STATUS_IOUT Command
the five other status registers need to be read for more detailed The STATUS_IOUT command returns a number of bits
status information. relating to current faults and warnings on the output supply.
In the ADM1278, a particular distinction is made between STATUS_TEMPERATURE Command
faults and warnings. A fault is always generated by the hot swap The STATUS_TEMPERATURE command returns a number of
controller and is typically defined by hardware component bits relating to temperature faults and warnings at the external
values. Events that can generate a fault are transistor.
 Overcurrent condition that causes the hot swap timer to STATUS_MFR_SPECIFIC Command
time out
The STATUS_MFR_SPECIFIC command is a standard PMBus
 Overvoltage condition on the OV pin
command, but the contents of the byte returned are specific to
 Undervoltage condition on the UV pin
the ADM1278.
 Overtemperature condition
 FET health issue detected CLEAR_FAULTS Command
The CLEAR_FAULTS command clears fault and warnings bits
When a fault occurs, the hot swap controller always takes some
when they are set. Fault and warnings bits are latched when
action, usually to turn off the GATE pin, which is driving the
they are set. In this way, a host can read the bits any time after
FET. The FAULT pin is asserted, and the PWRGD pin is the fault or warning condition occurs and determine which
deasserted. A fault can also generate an SMBAlert on problem actually occurred.
the GPO2/ALERT2 pin.
If the CLEAR_FAULTS command is issued and the fault or
All warnings in the ADM1278 are generated by the power warning condition is no longer active, the status bit is cleared. If
monitor, which samples the voltage, current, and temperature the condition is still active—for example, if an input voltage is
and then compares these measurements to the threshold values below the undervoltage threshold of the UV pin—the
set by the various limit commands. A warning has no effect on CLEAR_FAULTS command attempts to clear the status bit, but
the hot swap controller, but it may generate an SMBAlert on that status bit is immediately set again.
one or both of the GPOx/ALERTx output pins.
GPO AND ALERT PIN SETUP COMMANDS
When a status bit is set, it always means that the status condition—
Two multipurpose pins are provided on the ADM1278:
fault or warning—is active or was active at some point in the
GPO1/ALERT1/CONV and GPO2/ALERT2.
past. When a fault or warning bit is set, it is latched until it is
explicitly cleared using either the OPERATION or the These pins can be configured over the PMBus in one of three
CLEAR_FAULTS command. Some other status bits are live, that output modes, as follows:
is, they always reflect a status condition and are never latched.  General-purpose digital output
STATUS_BYTE and STATUS_WORD Commands  Output for generating an SMBAlert when one or more
The STATUS_BYTE and STATUS_WORD commands obtain fault/warning status bits become active in the PMBus
a snapshot of the overall device status. These commands status registers
indicate whether it is necessary to read more detailed  Digital comparator
information using the other status commands. In digital comparator mode, the current, voltage, power and
The low byte of the word returned by the STATUS_WORD temperature warning thresholds are compared to the values read
command is the same byte returned by the STATUS_BYTE or calculated by the ADM1278. The comparison result sets the
command. The high byte of the word returned by the output high or low according to whether the value is greater or
STATUS_WORD command provides a number of bits that less than the warning threshold that has been set.
determine which of the other status commands needs to be For an example of how to configure these pins to generate an
issued to obtain all active status bits. The status bits for FET SMBAlert and how to respond and clear the condition, see the
health and power good are also found in the high byte of Example Use of SMBus ARA section.
STATUS_WORD.
Data Sheet ADM1278
ALERT1_CONFIG and ALERT2_CONFIG Commands on the VOUT pin is available if enabled with the
Using combinations of bit masks, the ALERT1_CONFIG and PMON_CONFIG command.
ALERT2_CONFIG commands select the status bits that, when READ_TEMPERATURE_1 Command
set, generate an SMBAlert signal to a processor, or control the Temperature measurement at an external transistor can also be
digital comparator mode. Pin 13 and Pin 14 (GPO1/ALERT1/ enabled with the PMON_CONFIG command. If enabled, the
CONV and GPO2/ALERT2) must be configured in SMBAlert temperature sensor takes over the ADC for 64 μs (typical) every
or digital comparator mode in the DEVICE_CONFIG register. 6 ms and returns a measurement every 12 ms.
When Pin 13 or Pin 14 is configured in GPO mode, the pin is READ_PIN, READ_PIN_EXT, READ_EIN, and
under software control. If this mode is set, the SMBAlert READ_EIN_EXT Commands
masking bits are ignored. The 12-bit input voltage (VIN) and 12-bit current (IOUT) measure-
POWER MONITOR COMMANDS ment values are multiplied by the ADM1278 to give the input
The ADM1278 provides a high accuracy, 12-bit current, power value. This is accomplished by using fixed point
voltage, and temperature power monitor. The power monitor arithmetic, and produces a 24-bit value. It is assumed that the
can be configured in a number of different modes of operation numbers are in the 12.0 format, meaning that there is no
and can run in either continuous mode or single shot mode fractional part. Note that only positive IOUT values are used to
with different sample averaging options. avoid returning a negative power.
The power monitor can measure the following quantities: This 24-bit value can be read from the ADM1278 using the
READ_PIN_EXT command, where the most significant bit
 Input voltage (VIN) (MSB) is always a zero because PIN_EXT is a twos complement
 Output voltage (VOUT) binary value that is always positive.
 Output current (IOUT)
The 16 most significant bits of the 24-bit value are used as the
 External temperature
value for PIN. The MSB of the 16-bit PIN word is always zero,
The following quantities are then calculated: because PIN is a twos complement binary value that is always
positive.
 Input power (PIN)
 Input energy (EIN) Each time a power calculation is completed, the 24-bit power
value is added to a 24-bit energy accumulator register. This is a
PMON_CONFIG Command twos complement representation as well; therefore, the MSB is
The power monitor can run in a variety of modes. The always zero. Each time this energy accumulator register rolls
PMON_CONFIG command sets up the power monitor. over from 0x7FFFFF to 0x000000, a 16-bit rollover counter is
The settings that can be configured are as follows: incremented. The rollover counter is straight binary, with a
maximum value of 0xFFFF before it rolls over.
 Single shot or continuous sampling
A 24-bit straight binary power sample counter is also
 VIN/VOUT/temperature sampling enable/disable
incremented by 1 each time a power value is calculated and
 Current and voltage sample averaging
added to the energy accumulator.
 Power sample averaging
 Simultaneous sampling enable/disable These registers can be read back using one of two commands,
depending on the level of accuracy required for the energy
 Temperature sensor filter enable/disable
accumulator and the desire to limit the frequency of reads from
Modifying the power monitor settings while the power monitor the ADM1278.
is sampling is not recommended. To ensure correct operation
A bus host can read these values, and by calculating the delta in
of the device and to avoid any potential spurious data or the
the energy accumulated, the delta in the number of samples,
generation of status alerts, stop the power monitor before any
and the time delta since the last read, the host can calculate the
of these settings are changed.
average power since the last read, as well as the energy
PMON_CONTROL Command consumed since then.
Power monitor sampling can be initiated via hardware or via The time delta is calculated by the bus host based on when it
software using the PMON_CONTROL command. This command sends its commands to read from the device, and is not
can be used with single shot or continuous mode. provided by the ADM1278.
READ_VIN, READ_VOUT, and READ_IOUT Commands To avoid loss of data, the bus host must read at a rate that
The ADM1278 power monitor always measures the voltage ensures the rollover counter does not wrap around more than
developed across the sense resistor to provide a current once, and if the counter does wrap around, that the next value
measurement. The input voltage measurement from the read for PIN is less than the previous one.
HS+ pin is also enabled by default. The output voltage present
ADM1278 Data Sheet
The READ_EIN command returns the top 16 bits of the energy OT_WARN_LIMIT Command
accumulator, the lower 8 bits of the rollover counter, and the The OT_WARN_LIMIT command sets the overtemperature
full 24 bits of the sample counter. threshold for the temperature measured at the external
The READ_EIN_EXT command returns the full 24 bits of the transistor.
energy accumulator, the full 16 bits of the rollover counter, and PIN_OP_WARN_LIMIT Command
the full 24 bits of the sample counter. The use of the longer
The PIN_OP_WARN_LIMIT command sets the overpower
rollover counter means that the time interval between reads of
threshold for the power delivered to the load.
the device can be increased from seconds to minutes without
losing any data. PMBUS DIRECT FORMAT CONVERSION
PEAK_IOUT, PEAK_VIN, PEAK_VOUT, PEAK_PIN, and The ADM1278 uses the PMBus direct format to represent real-
PEAK_TEMPERATURE Commands world quantities such as voltage, current, and power values.
In addition to the standard PMBus commands for reading A direct format number takes the form of a 2-byte, twos comple-
voltage and current, the ADM1278 provides commands that ment, binary integer value.
can report the maximum peak voltage, current, power, or It is possible to convert between direct format value and real-
temperature value since the peak value was last cleared. world quantities using the following equations. Equation 1
The peak values are updated only after the power monitor has converts from real-world quantities to PMBus direct values,
sampled and averaged the current and voltage measurements. and Equation 2 converts PMBus direct format values to real-
Individual peak values are cleared by writing a 0 value with the world values.
corresponding command. Y = (mX + b) × 10R (1)
−R
WARNING LIMIT SETUP COMMANDS X = 1/m × (Y × 10 − b) (2)
The ADM1278 power monitor can monitor a number of where:
different warning conditions simultaneously and report any Y is the value in PMBus direct format.
current, voltage, power, or temperature values that exceed the X is the real-world value.
user defined thresholds using the status commands. m is the slope coefficient, a 2-byte, twos complement integer.
All comparisons performed by the power monitor require the b is the offset, a 2-byte, twos complement integer.
measured value to be strictly greater or less than the threshold R is a scaling exponent, a 1-byte, twos complement integer.
value. The same equations are used for voltage, current, power, and
At power-up, all threshold limits are set to either minimum temperature conversions, the only difference being the values
scale (for undervoltage or undercurrent conditions) or to of the m, b, and R coefficients that are used. Table 12 lists all
maximum scale (for overvoltage, overcurrent, overpower, or the coefficients required for the ADM1278. The current and
overtemperature conditions). This effectively disables the power coefficients shown are dependent on the value of the
generation of any status warnings by default; warning bits are external sense resistor used in a given application. This means
not set in the status registers until the user explicitly sets the that an additional calculation must be performed to take the
threshold values. sense resistor value into account to obtain the coefficients for a
specific sense resistor value.
VIN_OV_WARN_LIMIT and VIN_UV_WARN_LIMIT
Commands The sense resistor value used in the calculations to obtain the
coefficients is expressed in milliohms. The m coefficients are
The VIN_OV_WARN_LIMIT and VIN_UV_WARN_LIMIT
defined as 2-byte, twos complement numbers in the PMBus
commands set the OV and UV thresholds on the input voltage,
standard; therefore, the maximum positive value that can be
as measured at the HS+ pin.
represented is 32,767. If the m value is greater than that, and is
VOUT_OV_WARN_LIMIT and VOUT_UV_WARN_LIMIT to be stored in PMBus standard form, then divide the m
Commands coefficients by 10, and increase the R coefficient by a value of 1.
The VOUT_OV_WARN_LIMIT and VOUT_UV_WARN_ For example, if a 10 mΩ sense resistor is used, the m coefficient
LIMIT commands set the OV and UV thresholds on the output for power is 6123, and the R coefficient is −1.
voltage, as measured at the VOUT pin. Example 1: IOUT_OC_WARN_LIMIT requires a current-limit
IOUT_OC_WARN_LIMIT Command value expressed in direct format.
The IOUT_OC_WARN_LIMIT command sets the OC threshold If the required current limit is 10 A and the sense resistor is
for the current flowing through the sense resistor. 2 mΩ, the first step is to determine the voltage coefficient. This
is simply m = 800 × 2, giving 1600.
Data Sheet ADM1278
Using Equation 1, and expressing X, in units of amperes, The m, b, and R coefficients defined for the PMBus conversion
Y = ((1600 × 10) + 20,475) × 10−1 are required to be whole integers by the standard and have,
therefore, been rounded slightly. Using this alternative method,
Y = 3647.5 = 3648 (rounded up to integer form) with the exact LSB values, can provide somewhat more accurate
Writing a value of 3648 with the IOUT_OC_WARN_LIMIT numerical conversions.
command sets an overcurrent warning at 10 A. To convert an ADC code to current in amperes, use the
Example 2: the READ_IOUT command returns a direct format following formulas:
value of 3339 representing the current flowing through a sense VSENSE_MO = LSBCURRENT × (IADC − 2048)
resistor of 1 mΩ.
IOUT = VSENSE_MO/(RSENSE × 0.001)
To convert this value to the current flowing, use Equation 2, with
m = 800 × 1. where:
VSENSE_MO = (VMO+) − (VMO−).
X = 1/800 × (3339 × 101 − 20,475) LSBCURRENT = 12.51 μV.
X = 16.14 A IADC is the 12-bit ADC code.
This means that, when READ_IOUT returns a value of 3339, IOUT is the measured current value in amperes.
16.14 A is flowing in the sense resistor. RSENSE is the value of the sense resistor in milliohms.
Note that the same calculations that are used to convert power To convert an ADC code to a voltage, use the following
values also apply to the energy accumulator value returned by formula:
the READ_EIN command because the energy accumulator is a VM = LSBVOLTAGE × (VADC + 0.5)
summation of multiple power values. where:
The READ_PIN_EXT and READ_EIN_EXT commands return VM is the measured value in volts.
24-bit extended precision versions of the 16-bit values returned LSBVOLTAGE = 5.104 mV.
by READ_PIN and READ_EIN. The direct format values must VADC is the 12-bit ADC code.
be divided by 256 prior to being converted with the coefficients To convert a current in amperes to a 12-bit value, use the
shown in Table 12. following formula (round the result to the nearest integer):
Example 3: The PIN_OP_WARN_LIMIT command requires a VSENSE_MO = IA × RSENSE × 0.001
power limit value expressed in direct format.
ICODE = 2048 + (VSENSE_MO/LSBCURRENT)
If the required power limit is 350 W and the sense resistor is
1 mΩ, the first step is to determine the m coefficient, that is, where:
m = 6123 × 1, which is 6123. VSENSE_MO = (VMO+) − (VMO−).
IA is the current value in amperes.
Using Equation 1, RSENSE is the value of the sense resistor in milliohms.
Y = ((6123 × 350) × 10−2 ICODE is the 12-bit ADC code.
Y = 21,430.5 = 21,431 (rounded up to integer form) LSBCURRENT = 12.51 μV.
Writing a value of 21,431 with the PIN_OP_WARN_LIMIT To convert a voltage to a 12-bit value, the following formula
command sets an overpower warning at 350 W. can be used (round the result to the nearest integer):
VOLTAGE AND CURRENT CONVERSION USING VCODE = (VA/LSBVOLTAGE) − 0.5

LSB VALUES where:
The direct format voltage and current values returned by the VCODE is the 12-bit ADC code.
READ_VIN, READ_VOUT, and READ_IOUT commands and VA is the voltage value in volts.
the corresponding peak versions are the data output directly by LSBVOLTAGE = 5.104 mV.
the ADM1278 ADC. Because the voltages and currents are 12-bit
ADC output codes, they can also be converted to real-world values
when there is knowledge of the size of the LSB on the ADC.
Table 12. PMBus Conversion to Real-World Coefficients

Coefficient Voltage (V) Current (A) Power (W) Temperature (°C)
m +19,599 +800 × RSENSE (in mΩ) +6123 × RSENSE (in mΩ) +42
b 0 +20,475 0 +31,880
R −2 −1 −2 −1
ADM1278 Data Sheet
ALERT PIN BEHAVIOR

The ADM1278 provides a very flexible alert system, whereby By default at power-up, the open-drain GPO1/ALERT1
one or more fault/warning conditions can be indicated to an /CONV and GPO2/ALERT2 outputs are high impedance;
external device. therefore, the pins can be pulled high through a resistor. The
FAULTS AND WARNINGS GPO1/ALERT1/ CONV and GPO2/ALERT2 pins are disabled
by default on the ADM1278.
A PMBus fault on the ADM1278 is typically generated due to
an analog event (the exception being a temperature fault) and Any one or more of the faults and warnings listed in the Faults
causes a change in state in the hot swap output, turning it off. and Warnings section can be enabled and cause an alert, making
The defined fault sources are as follows: the corresponding GPO1/ALERT1/CONV or GPO2/ALERT2
 Undervoltage (UV) event detected on the UV pin. pin active. By default, the active state of the GPO1/ALERT1/
 Overvoltage (OV) event detected on the OV pin. CONV and GPO2/ALERT2 pins are low.
 Overcurrent (OC) event that causes a hot swap timeout. For example, to use GPO2/ALERT2 to monitor the VOUT UV
 Overtemperature (OT) event detected at the external warning from the ADC, the followings steps must be performed:
transistor. 1. Set a threshold level with the VOUT_UV_WARN_LIMIT
 Fault detected with the pass MOSFET. command.
Faults are continuously monitored, and, as long as power is 2. Set the VOUT_UV_WARN_EN2 bit in the
applied to the device, they cannot be disabled. When a fault ALERT2_CONFIG register.
occurs, a corresponding status bit is set in one or more 3. Start the power monitor sampling on VOUT (ensure the
STATUS_xxx registers. power monitor is configured to sample VOUT in the
PMON_CONFIG register).
A value of 1 in a status register bit field always indicates a fault
or warning condition. Fault and warning bits in the status If a VOUT sample is taken that is below the configured VOUT UV
registers are latched when set to 1. To clear a latched bit to 0— value, the GPO2/ALERT2 pin is pulled low, signaling an
provided that the fault condition is no longer active—use the interrupt to a processor.
CLEAR_FAULTS command or use the OPERATION HANDLING/CLEARING AN ALERT
command to turn the hot swap output off and then on again.
When faults/warnings are configured on the GPO1/ALERT1/
A warning is less severe than a fault and never causes a change
CONV or GPO2/ALERT2 pins, the pin becomes active to signal
in the state of the hot swap controller. The sources of a warning
an interrupt to the processor. (The pin is active low, unless
are defined as follows:
inversion is enabled.) The GPO1/ALERT1 /CONV or
 CML: a communications error occurred on the I2C bus. GPO2/ALERT2 signal performs the functions of an SMBAlert.
 HS_INLIM_FAULT: the circuit breaker threshold was
Note that the GPO1/ALERT1/CONV and GPO2/ALERT2 pins
tripped and the TIMER pin started ramping, but did not
can become active independently but they are always made
necessarily shut the system down.
inactive together.
 IOUT OC warning from the ADC.
 VIN UV warning from the ADC. A processor can respond to the interrupt in one of two ways,
 VIN OV warning from the ADC. depending on whether there is a single or multiple devices on
 VOUT UV warning from the ADC. the bus.
 VOUT OV warning from the ADC. Single Device on Bus
 PIN overpower (OP) warning from the VIN × IOUT calculation. When there is only one device on the bus, the processor simply
 OT warning from the ADC. reads the status bytes and issues a CLEAR_FAULTS command
 Hysteretic output warning from the ADC. to clear all the status bits, which causes the deassertion of the
GPO1/ALERT1/CONV or GPO2/ALERT2 line. If there is a
GENERATING AN ALERT
persistent fault (for example, an undervoltage on the input), the
A host device can periodically poll the ADM1278 using the status bits remain set after the CLEAR_ FAULTS command is
status commands to determine whether a fault/warning is executed because the fault has not been removed. However, the
active. However, this polling is very inefficient in terms of GPO1/ ALERT1/CONV or GPO2/ALERT2 line is not pulled
software and processor resources. The ADM1278 has two low unless a new fault or warning becomes active. If the cause
output pins (GPO1/ALERT1/CONV and GPO2/ALERT2) of the SMBAlert is a power monitor generated warning and the
that can be used to generate interrupts to a host processor. power monitor is running continuously, the next sample
generates a new SMBAlert after the CLEAR_FAULTS command
is issued.
Data Sheet ADM1278
Multiple Devices on Bus generated, causing the GPO2/ALERT2 pin to become active
When there are several devices on the bus, the processor issues again.
an SMBus alert response address (ARA) command to find out
DIGITAL COMPARATOR MODE
which device asserted the SMBAlert line. The processor reads the
status bytes from that device and issues a CLEAR_FAULTS The GPO1/ALERT1/CONV and GPO2/ALERT2 pins can be
command. configured to indicate if a user defined threshold for voltage,
current, or power is being exceeded. In this mode, the output
SMBUS ALERT RESPONSE ADDRESS pin is live and is not latched when a warning threshold is
The SMBus ARA is a special address that can be used by the exceeded. In effect, the pin acts as a digital comparator, where
bus host to locate any devices that need to communicate with the threshold is set using the warning limit threshold commands.
the bus host. A host typically uses a hardware interrupt pin to The ALERTx_CONFIG command is used, as for the SMBAlert
monitor the SMBus alert pins of multiple devices. When the configuration, to select the specific warning threshold to be
host interrupt occurs, the host issues a message on the bus monitored. The GPO1/ALERT1/CONV or GPO2/ALERT2 pin
using the SMBus receive byte or receive byte with PEC then indicates if the measured value is above or below the
protocol. threshold.
The special address used by the host is 0x0C. Any devices that
TYPICAL APPLICATION CIRCUITS
have an SMB alert signal return their own 7-bit address as the RSENSE
4.5V TO 20V Q1
seven MSBs of the data byte. The LSB value is not used and can
be either 1 or 0. The host reads the device address from the
HS+ MO+ MO– HS–
received data byte and proceeds to handle the alert condition.
VCC ADM1278-1
+ –
More than one device may have an active SMBAlert signal and VCAP
×50 CHARGE
LDO PUMP
ISENSE
attempt to communicate with the host. In this case, the device UV VCP
+
with the lowest address dominates the bus and succeeds in 1.0V
–
GATE
DRIVE/ GATE
OV – LOGIC
transmitting its address to the host. The device that succeeds +
TEMP
1.0V TIMEOUT
disables its SMBus alert signal. If the host sees that the SMBus alert + PWGIN
ISET REF – +
signal is still low, it continues to read addresses until all devices that PSET
SELECT –
1.0V
1.0V
need to communicate have successfully transmitted their ISTART
CURRENT-
LIMIT
HS–
CONTROL
addresses. VOUT
VCBOS
EXAMPLE USE OF SMBUS ARA PWRGD

IOUT FAULT
TIMER
The full sequence of steps that occurs when an SMBAlert is TIMER TIMEOUT ENABLE
LOGIC GPO1/ALERT2
generated and cleared is as follows: HS+ AND
ISENSE GPO2/ALERT1/CONV
12-BIT PMBus
VOUT ADC SCL
SDA
1. A fault or warning is enabled using the ALERT2_CONFIG RETRY
TEMP
ADR1
ADR2
command, and the corresponding status bit for the fault or
ANALOG CSOUT
warning changes from 0 to 1, indicating that the fault or VOUT
12198-030
warning has just become active. PGND GND
2. The GPO2/ALERT2 pin becomes active (set low) to signal

Figure 71. ADM1278-1 Typical Application Circuit
that an SMBAlert is active.
3. The host processor issues an SMBus ARA command to
determine which device has an active alert.
4. If there are no other active alerts from devices with lower
I2C addresses, this device makes the GPO2/ALERT2 pin
inactive (set high) during the no acknowledge bit period
after it sends its address to the host processor.
5. If the GPO2/ALERT2 pin stays low, the host processor
must continue to issue SMBus ARA commands to devices
to determine the addresses of all devices that require a
status check.
6. The ADM1278 continues to operate with the GPO2/ALERT2
pin inactive and the contents of the status bytes unchanged
until the host reads the status bytes and clears them, or until a
new fault occurs. That is, if a status bit for a fault/warning
that is enabled on the GPO2/ALERT2 pin and that was not
already active (equal to 1) changes from 0 to 1, a new alert is
ADM1278 Data Sheet
4.5V TO 20V RSENSE Q1 4.5V TO 20V RSENSE Q1
HS+ MO+ MO– HS– HS+ MO+ MO– HS–
VCC ADM1278-2 VCC ADM1278-3

+ – + –
×50 CHARGE ×50 CHARGE
VCAP VCAP
LDO PUMP LDO PUMP
ISENSE ISENSE
UV VCP UV VCP
+ GATE + GATE
1.0V GATE 1.0V GATE
– DRIVE/ – DRIVE/
OV LOGIC OV – LOGIC
– TEMP TEMP
1.0V + TIMEOUT 1.0V + TIMEOUT
+ PWGIN + PWGIN
ISET REF – + ISET REF – +
SELECT – SELECT –
PSET 1.0V PSET 1.0V
1.0V CURRENT- 1.0V CURRENT-
ISTART HS– LIMIT ISTART LIMIT
CONTROL HS–
CONTROL
VOUT VOUT
VCBOS VCBOS
PWRGD PWRGD
IOUT FAULT IOUT FAULT
TIMER TIMER
TIMER TIMEOUT ENABLE TIMER TIMEOUT ENABLE
LOGIC GPO2/ALERT2 LOGIC GPO1/ALERT2
HS+ AND HS+
ISENSE GPO1/ALERT1/CONV AND GPO2/ALERT1/CONV
12-BIT PMBus ISENSE 12-BIT
SCL PMBus SCL
VOUT ADC VOUT ADC
TEMP SDA TEMP SDA
RETRY ADR1 RETRY ADR1
ADR2 ADR2
SPI_SS
SPI MCLK ANALOG CSOUT
VOUT
MDAT
12198-330
ANALOG CSOUT PGND GND
12198-031
VOUT
PGND GND
Data Sheet ADM1278
PMBUS COMMAND REFERENCE

Register addresses are in hexadecimal format.
Table 13. PMBus Command Summary

Address Name SMBus Transaction Type Number of Data Bytes Reset
0x01 OPERATION Read/write byte 1 0x80
0x03 CLEAR_FAULTS Send byte1 0 Not applicable
0x19 CAPABILITY Read byte 1 0xB0
0x42 VOUT_OV_WARN_LIMIT Read/write word 2 0x0FFF
0x43 VOUT_UV_WARN_LIMIT Read/write word 2 0x0000
0x4A IOUT_OC_WARN_LIMIT Read/write word 2 0x0FFF
0x4F OT_FAULT_LIMIT Read/write word 2 0x0FFF
0x51 OT_WARN_LIMIT Read/write word 2 0x0FFF
0x57 VIN_OV_WARN_LIMIT Read/write word 2 0x0FFF
0x58 VIN_UV_WARN_LIMIT Read/write word 2 0x0000
0x6B PIN_OP_WARN_LIMIT Read/write word 2 0x7FFF
0x78 STATUS_BYTE Read byte 1 0x00
0x79 STATUS_WORD Read word 2 0x0000
0x7A STATUS_VOUT Read byte 1 0x00
0x7B STATUS_IOUT Read byte 1 0x00
0x7C STATUS_INPUT Read byte 1 0x00
0x7D STATUS_TEMPERATURE Read byte 1 0x00
0x80 STATUS_MFR_SPECIFIC Read byte 1 0x00
0x86 READ_EIN Block read 6 0x000000000000
0x88 READ_VIN Read word 2 0x0000
0x8B READ_VOUT Read word 2 0x0000
0x8C READ_IOUT Read word 2 0x0000
0x8D READ_TEMPERATURE_1 Read word 2 0x0000
0x97 READ_PIN Read word 2 0x0000
0x98 PMBUS_REVISION Read byte 1 0x22
0x99 MFR_ID Block read 3 ASCII = ADI
0x9A MFR_MODEL Block read 10 ASCII = ADM1278-xy
0x9B MFR_REVISION Block read 1 0x33
0x9D MFR_DATE Block read 6 ASCII = YYMMDD
0xD0 PEAK_IOUT Read/write word 2 0x0000
0xD1 PEAK_VIN Read/write word 2 0x0000
0xD2 PEAK_VOUT Read/write word 2 0x0000
0xD3 PMON_CONTROL Read/write byte 1 0x01
0xD4 PMON_CONFIG Read/write word 2 0x0714
0xD5 ALERT1_CONFIG Read/write word 2 0x0000
0xD6 ALERT2_CONFIG Read/write word 2 0x0000
0xD7 PEAK_TEMPERATURE Read/write word 2 0x0000
0xD8 DEVICE_CONFIG Read/write word 2 0x000D
0xD9 POWER_CYCLE Send byte1 0 Not applicable
0xDA PEAK_PIN Read/write word 2 0x0000
0xDB READ_PIN_EXT Block read 3 0x000000
0xDC READ_EIN_EXT Block read 8 0x0000000000000000
0xF2 HYSTERESIS_LOW Read/write word 2 0x0000
0xF3 HYSTERESIS_HIGH Read/write word 2 0xFFFF
0xF4 STATUS_HYSTERESIS Read byte 1 0x00
0xF6 STRT_UP_IOUT_LIM Read/write word 2 0x000F
1
The send byte protocol is only permitted for the CLEAR_FAULTS command and the POWER_CYCLE command. Do not use the send byte protocol for any other commands.
ADM1278 Data Sheet
REGISTER DETAILS
OPERATION REGISTER
Address: 0x01, Reset: 0x80, Name: OPERATION
This command requests the hot swap turn on and turn off. When turning the hot swap on, it clears status bits for any faults or warnings
that are not active.
Table 14. Bit Descriptions for OPERATION

Bits Bit Name Settings Description Reset Access
7 ON Hot swap enable. 0x1 RW
0 Hot swap output disabled.
1 Hot swap output enabled.
[6:0] RESERVED Always reads as 0000000. 0x00 RESERVED
CLEAR FAULTS REGISTER

Address: 0x03, Send Byte, No Data, Name: CLEAR_FAULTS
This command clears fault and warning bits in all the status registers. Any faults that are still active are not cleared and remain set. Any
warnings and the OT_FAULT that are generated by the power monitor are cleared, but may be asserted again if they remain active
following the next power monitor conversion cycle.
This command does not require any data.
PMBUS CAPABILITY REGISTER

Address: 0x19, Reset: 0xB0, Name: CAPABILITY
Allows the host system to determine the SMBus interface capabilities of the device.
Table 15. Bit Descriptions for CAPABILITY

7 PEC_SUPPORT Packet error correction (PEC) support. 0x1 R
1 Always reads as 1. PEC is supported.
[6:5] MAX_BUS_SPEED Maximum bus interface speed. 0x1 R
01 Always reads as 01. Maximum supported bus speed is 400 kHz.
4 SMBALERT_SUPPORT SMBAlert support. 0x1 R
1 Always reads as 1. Device supports SMBAlert and ARA.
VOUT OV WARNING LIMIT REGISTER

Address: 0x42, Reset: 0x0FFF, Name: VOUT_OV_WARN_LIMIT
This register sets the overvoltage warning limit for the voltage measured on the VOUT pin.
Table 16. Bit Descriptions for VOUT_OV_WARN_LIMIT

[11:0] VOUT_OV_WARN_LIMIT Overvoltage warning threshold for the VOUT pin measurement, 0xFFF RW
expressed in direct format.
Data Sheet ADM1278
VOUT UV WARNING LIMIT REGISTER
Address: 0x43, Reset: 0x0000, Name: VOUT_UV_WARN_LIMIT
This register sets the undervoltage warning limit for the voltage measured on the VOUT pin.
Table 17. Bit Descriptions for VOUT_UV_WARN_LIMIT

[11:0] VOUT_UV_WARN_LIMIT Undervoltage warning threshold for the VOUT pin measurement, 0x000 RW
IOUT OC WARNING LIMIT REGISTER

Address: 0x4A, Reset: 0x0FFF, Name: IOUT_OC_WARN_LIMIT
This register sets the overcurrent warning limit for the current measured between the MO+ and the MO− pins.
Table 18. Bit Descriptions for IOUT_OC_WARN_LIMIT

[11:0] IOUT_OC_WARN_LIMIT Overcurrent warning threshold for the IOUT measurement, 0xFFF RW
OT FAULT LIMIT REGISTER

Address: 0x4F, Reset: 0x0FFF, Name: OT_FAULT_LIMIT
This register sets the overtemperature fault limit for the temperature measured on the TEMP pin.
Table 19. Bit Descriptions for OT_FAULT_LIMIT

[11:0] OT_FAULT_LIMIT Overtemperature fault threshold for the TEMP pin measurement, 0xFFF RW
OT WARNING LIMIT REGISTER

Address: 0x51, Reset: 0x0FFF, Name: OT_WARN_LIMIT
This register sets the overtemperature warning limit for the temperature measured on the TEMP pin.
Table 20. Bit Descriptions for OT_WARN_LIMIT

[11:0] OT_WARN_LIMIT Overtemperature warning threshold for the TEMP pin measurement, 0xFFF RW
VIN OV WARNING LIMIT REGISTER

Address: 0x57, Reset: 0x0FFF, Name: VIN_OV_WARN_LIMIT
This register sets the overvoltage warning limit for the voltage measured on the HS+ pin.
Table 21. Bit Descriptions for VIN_OV_WARN_LIMIT

[11:0] VIN_OV_WARN_LIMIT Overvoltage warning threshold for the HS+ pin measurement, 0xFFF RW
ADM1278 Data Sheet
VIN UV WARNING LIMIT REGISTER
Address: 0x58, Reset: 0x0000, Name: VIN_UV_WARN_LIMIT
This register sets the undervoltage warning limit for the voltage measured on the HS+ pin.
Table 22. Bit Descriptions for VIN_UV_WARN_LIMIT

[11:0] VIN_UV_WARN_LIMIT Undervoltage warning threshold for the HS+ pin measurement, 0x000 RW
PIN OP WARNING LIMIT REGISTER

Address: 0x6B, Reset: 0x7FFF, Name: PIN_OP_WARN_LIMIT
This register sets the overpower warning limit for the power calculated based on VIN × IOUT.
Table 23. Bit Descriptions for PIN_OP_WARN_LIMIT

15 RESERVED Always reads as 0. 0x0 RESERVED
[14:0] PIN_OP_WARN_LIMIT Overpower warning threshold for the VIN × IOUT power calculation, 0x7FFF RW
STATUS BYTE REGISTER

Address: 0x78, Reset: 0x00, Name: STATUS_BYTE
Provides status information for critical faults and certain top-level status commands in the device. This is also the lower byte returned by
STATUS_WORD. A bit set to 1 indicates that a fault or warning has occurred.
Table 24. Bit Descriptions for STATUS_BYTE

6 HOTSWAP_OFF Hot swap gate is off. This bit is live. 0x0 R
0 The hot swap gate drive output is enabled.
1 The hot swap gate drive output is disabled, and the GATE pin is
pulled down. This can be due to, for example, an overcurrent fault
that causes the device to latch off, an undervoltage condition on
the UV pin, or the use of the OPERATION command to turn the
output off.
4 IOUT_OC_FAULT IOUT overcurrent fault. This bit is latched. 0x0 R
0 No overcurrent output fault detected.
1 The hot swap controller detected an overcurrent condition and the
time limit set by the capacitor on the TIMER pin has elapsed,
causing the hot swap gate drive to shut down.
3 VIN_UV_FAULT VIN fault. This bit is latched. 0x0 R
0 No undervoltage input fault detected on the UV pin.
1 An undervoltage input fault was detected on the UV pin.
2 TEMP_FAULT Temperature fault or warning. This bit is live. 0x0 R
0 There are no active status bits to be read by
STATUS_TEMPERATURE.
1 There are one or more active status bits to be read by
STATUS_TEMPERATURE.
1 CML_FAULT CML fault. This bit is latched. 0x0 R
0 No communications error detected on the I2C/PMBus interface.
1 An error was detected on the I2C/PMBus interface. Errors detected
include an unsupported command, invalid PEC byte, and
Data Sheet ADM1278
incorrectly structured message.
0 NONEABOVE_STATUS None of the above. This bit is live. 0x0 R
0 No other active status bit reported by any other status command.
1 Active status bits are waiting to be read by one or more status
commands.
STATUS WORD REGISTER

Address: 0x79, Reset: 0x0000, Name: STATUS_WORD
Provides status information for critical faults and all top-level status commands in the device. The lower byte is also returned by
STATUS_BYTE.
Table 25. Bit Descriptions for STATUS_WORD

15 VOUT_STATUS VOUT warning. This bit is live. 0x0 R
0 There are no active status bits to be read by the STATUS_VOUT
register.
STATUS_VOUT.
14 IOUT_STATUS IOUT fault or warning. This bit is live. 0x0 R
0 There are no active status bits to be read by the STATUS_IOUT
register.
1 There are one or more active status bits to be read by the
STATUS_IOUT register.
13 INPUT_STATUS Input warning. This bit is live. 0x0 R
0 There are no active status bits to be read by the STATUS_INPUT
register.
STATUS_INPUT.
12 MFR_STATUS Manufacture specific fault or warning. This bit is live. 0x0 R
0 There are no active status bits to be read by the
STATUS_MFR_SPECIFIC register.
STATUS_MFR_SPECIFIC register.
11 PGB_STATUS Power is not good. This bit is live. 0x0 R
0 Output power is good. The voltage on the PWGIN pin is above the
threshold.
1 Output power is bad. The voltage on the PWGIN pin is below the
threshold.
[10:9] RESERVED 0x0 RESERVED
8 FET_HEALTH_FAULT FET health fault. This bit is latched. 0x0 R
0 No FET faults have been detected.
1 A fault condition has been detected on the FET.
7 RESERVED Always set to 0. 0x0 RESERVED
6 HOTSWAP_OFF Duplicate of corresponding bit in the STATUS_BYTE register. 0x0 R
5 RESERVED Always set to 0. 0x0 RESERVED
4 IOUT_OC_FAULT Duplicate of corresponding bit in the STATUS_BYTE register. 0x0 R
3 VIN_UV_FAULT Duplicate of corresponding bit in the STATUS_BYTE register. 0x0 R
2 TEMP_FAULT Duplicate of corresponding bit in the STATUS_BYTE register. 0x0 R
1 CML_FAULT Duplicate of corresponding bit in the STATUS_BYTE register. 0x0 R
0 NONEABOVE_STATUS Duplicate of corresponding bit in the STATUS_BYTE register. 0x0 R
ADM1278 Data Sheet
VOUT STATUS REGISTER
Address: 0x7A, Reset: 0x00, Name: STATUS_VOUT
Provides status information for warnings related to VOUT.
Table 26. Bit Descriptions for STATUS_VOUT

6 VOUT_OV_WARN VOUT Overvoltage Warning. 0x0 R
0 No overvoltage condition on the output supply detected by the power
monitor.
1 An overvoltage condition on the output supply was detected by the
power monitor. This bit is latched.
5 VOUT_UV_WARN VOUT UV warning. 0x0 R
0 No undervoltage condition on the output supply detected by the
power monitor.
1 An undervoltage condition on the output supply was detected by the
IOUT STATUS REGISTER

Address: 0x7B, Reset: 0x00, Name: STATUS_IOUT
Provides status information for faults and warnings related to IOUT.
Table 27. Bit Descriptions for STATUS_IOUT

7 IOUT_OC_FAULT IOUT overcurent fault. 0x0 R
0 No overcurrent output fault detected.
1 The hot swap controller detected an overcurrent condition and the
time limit set by the capacitor on the TIMER pin has elapsed, causing
the hot swap gate drive to shut down. This bit is latched.
5 IOUT_OC_WARN IOUT overcurrent warning. 0x0 R
0 No overcurrent condition on the output supply detected by the power
monitor using the IOUT_OC_WARN_LIMIT command.
1 An overcurrent condition was detected by the power monitor using
the IOUT_OC_WARN_LIMIT command. This bit is latched.
INPUT STATUS REGISTER

Address: 0x7C, Reset: 0x00, Name: STATUS_INPUT
Provides status information for faults and warnings related to VIN and PIN.
Table 28. Bit Descriptions for STATUS_INPUT

7 VIN_OV_FAULT VIN overvoltage fault. 0x0 R
0 No overvoltage detected on the OV pin.
1 An overvoltage was detected on the OV pin. This bit is latched.
6 VIN_OV_WARN VIN overvoltage warning fault. 0x0 R
0 No overvoltage condition on the input supply detected by the power
monitor.
1 An overvoltage condition on the input supply was detected by the
Data Sheet ADM1278
5 VIN_UV_WARN VIN undervoltage warning. 0x0 R
0 No undervoltage condition on the input supply detected by the power
monitor.
1 An undervoltage condition on the input supply was detected by the
4 VIN_UV_FAULT VIN undervoltage fault. 0x0 R
0 No undervoltage detected on the UV pin.
1 An undervoltage was detected on the UV pin. This bit is latched.
0 PIN_OP_WARN PIN overpower warning. 0x0 R
0 No overpower condition on the input supply detected by the power
monitor.
1 An overpower condition on the input supply was detected by the
TEMPERATURE STATUS REGISTER

Address: 0x7D, Reset: 0x00, Name: STATUS_TEMPERATURE
Provides status information for faults and warnings related to temperature.
Table 29. Bit Descriptions for STATUS_TEMPERATURE

7 OT_FAULT Overtemperature fault. 0x0 R
0 No overtemperature fault detected by the ADC.
1 An overtemperature fault was detected by the ADC. This bit is latched.
6 OT_WARNING Overtemperature warning. 0x0 R
0 No overtemperature warning detected by the ADC.
1 An overtemperature warning was detected by the ADC. This bit is
latched.
MANUFACTURER SPECIFIC STATUS REGISTER

Address: 0x80, Reset: 0x00, Name: STATUS_MFR_SPECIFIC
Provides status information for manufacturer specific faults and warnings.
Table 30. Bit Descriptions for STATUS_MFR_SPECIFIC

7 FET_HEALTH_FAULT FET health fault. 0x0 R
0 No FET health problems have been detected.
1 An FET health fault has been detected. This bit is latched.
6 UV_CMP_OUT UV input comparator fault output. 0x0 R
0 Input voltage to UV pin is above threshold.
1 Input voltage to UV pin is below threshold. This bit is live.
5 OV_CMP_OUT OV input comparator fault output. 0x0 R
0 Input voltage to OV pin is below threshold.
1 Input voltage to OV pin is above threshold. This bit is live.
4 SEVERE_OC_FAULT Severe overcurrent fault. 0x0 R
0 A severe overcurrent has not been detected by the hot swap.
1 A severe overcurrent has been detected by the hot swap. This bit is
latched.
ADM1278 Data Sheet
3 HS_INLIM_FAULT Hot swap in limit fault. 0x0 R
0 The hot swap has not actively limited the current into the load.
1 The hot swap has actively limited current into the load. This bit
differs from the IOUT_OC_FAULT bit in that the HS_INLIM_FAULT
bit is set immediately, whereas the IOUT_OC_FAULT bit is not set
unless the time limit set by the capacitor on the TIMER pin elapses.
This bit is latched.
[2:0] HS_SHUTDOWN_CAUSE Cause of last hot swap shutdown. This bit is latched until the status 0x0 R
registers are cleared.
000 The hot swap is either enabled and working correctly, or has been
shut down using the OPERATION command.
001 An OT_FAULT condition occurred that caused the hot swap to shut
down.
010 An IOUT_OC_FAULT condition occurred that caused the hot swap
to shut down.
011 An FET_HEALTH_FAULT condition occurred that caused the hot
swap to shut down.
100 A VIN_UV_FAULT condition occurred that caused the hot swap to
shut down.
110 A VIN_OV_FAULT condition occurred that caused the hot swap to
shut down.
READ EIN REGISTER

Address: 0x86, Reset: 0x000000000000, Name: READ_EIN
Read the energy metering registers in a single operation to ensure time consistent data.
Table 31. Bit Descriptions for READ_EIN

[47:24] SAMPLE_COUNT This is the total number of PIN samples acquired and accumulated in 0x000000 R
the energy count accumulator. This is an unsigned 24-bit binary value.
Byte 5 is the high byte, Byte 4 is the middle byte, and Byte 3 is the low
byte.
[23:16] ROLLOVER_COUNT Number of times that the energy count has rolled over from 0x7FFF to 0x00 R
0x0000. This is an unsigned 8-bit binary value.
[15:0] ENERGY_COUNT Energy accumulator value in PMBus direct format. Byte 1 is the high 0x0000 R
byte, and Byte 0 is the low byte. Internally, the energy accumulator is a
24-bit value, but only the most significant 16 bits are returned with
this command. Use the READ_EIN_EXT register to access the
nontruncated version.
READ VIN REGISTER

Address: 0x88, Reset: 0x0000, Name: READ_VIN
Reads the input voltage, VIN, from the device.
Table 32. Bit Descriptions for READ_VIN

[11:0] READ_VIN Input voltage from the HS+ pin measurement after averaging, 0x000 R
Data Sheet ADM1278
READ VOUT REGISTER
Address: 0x8B, Reset: 0x0000, Name: READ_VOUT
Reads the output voltage, VOUT, from the device.
Table 33. Bit Descriptions for READ_VOUT

[11:0] READ_VOUT Input voltage from the VOUT pin measurement after averaging, 0x000 R
READ IOUT REGISTER

Address: 0x8C, Reset: 0x0000, Name: READ_IOUT
Reads the output current, IOUT, from the device.
Table 34. Bit Descriptions for READ_IOUT

[11:0] READ_IOUT Output current derived from MO+/MO− sense pin voltage 0x000 R
measurement after averaging, expressed in direct format.
READ TEMPERATURE 1 REGISTER

Address: 0x8D, Reset: 0x0000, Name: READ_TEMPERATURE_1
Reads the temperature measured by the device.
Table 35. Bit Descriptions for READ_TEMPERATURE_1

[11:0] READ_TEMPERATURE_1 Temperature from the TEMP pin measurement after averaging, 0x000 R
READ PIN REGISTER

Address: 0x97, Reset: 0x0000, Name: READ_PIN
Reads the calculated input power, PIN, from the device.
Table 36. Bit Descriptions for READ_PIN

[15:0] READ_PIN Input power calculation, using VIN × IOUT, after averaging, expressed in 0x0000 R
PMBus direct format. PIN values are calculated for each VIN × IOUT sample, all
PIN values are then averaged before the value is returned to the READ_PIN
register.
PMBUS REVISION REGISTER

Address: 0x98, Reset: 0x22, Name: PMBUS_REVISION
Allows the system to read the PMBus revision that the device supports.
Table 37. Bit Descriptions for PMBUS_REVISION

[7:4] PMBUS_P1_REVISION PMBus Part I Support. 0x2 R
0010 Revision 1.2.
[3:0] PMBUS_P2_REVISION PMBus Part II Support. 0x2 R
0010 Revision 1.2.
ADM1278 Data Sheet
MANUFACTURER ID REGISTER
Address: 0x99, Reset: ASCII = ADI, Name: MFR_ID
Returns a string identifying the Manufacturer of the device.
Table 38. Bit Descriptions for MFR_ID

[23:0] MFR_ID String identifying manufacturer as Analog Devices (ADI). 0x494441 R
MANUFACTURER MODEL REGISTER

Address: 0x9A, Reset: ASCII = ADM1278-xy, Name: MFR_MODEL
Returns a string identifying the specific model of the device.
Table 39. Bit Descriptions for MFR_MODEL

[79:0] MFR_MODEL String identifying model as ADM1278-xy, where xy 0x41312D383732314D4441 R
identifies the particular model type. Note that the
ADM1278-1AA model is identified as ADM1278-1A in
the MFR_MODEL register.
MANUFACTURER REVISION REGISTER

Address: 0x9B, Reset: 0x33, Name: MFR_REVISION
Returns a string identifying the hardware revision of the device.
Table 40. Bit Descriptions for MFR_REVISION

[7:0] MFR_REVISION String identifying hardware revision as, for example, 3. 0x33 R
MANUFACTURER DATE REGISTER

Address: 0x9D, Reset: ASCII = YYMMDD, Name: MFR_DATE
Returns a string identifying the production test date of the device.
Table 41. Bit Descriptions for MFR_DATE

[47:0] DATE String identifying test date, in the form of YYMMDD. 0x313338303231 R
PEAK IOUT REGISTER

Address: 0xD0, Reset: 0x0000, Name: PEAK_IOUT
Reports the peak output current, IOUT. Writing 0x0000 with this command resets the peak value.
Table 42. Bit Descriptions for PEAK_IOUT

[11:0] PEAK_IOUT Peak output current measurement, IOUT, expressed in direct format. 0x000 R
Data Sheet ADM1278
PEAK VIN REGISTER
Address: 0xD1, Reset: 0x0000, Name: PEAK_VIN
Reports the peak input voltage, VIN. Writing 0x0000 with this command resets the peak value.
Table 43. Bit Descriptions for PEAK_VIN

[11:0] PEAK_VIN Peak input voltage measurement, VIN, expressed in direct format. 0x000 R
PEAK VOUT REGISTER

Address: 0xD2, Reset: 0x0000, Name: PEAK_VOUT
Reports the peak output voltage, VOUT. Writing 0x0000 with this command resets the peak value.
Table 44. Bit Descriptions for PEAK_VOUT

[11:0] PEAK_VOUT Peak output voltage measurement, VOUT, expressed in direct format. 0x000 R
POWER MONITOR CONTROL REGISTER

Address: 0xD3, Reset: 0x01, Name: PMON_CONTROL
This command starts and stops the power monitor.
Table 45. Bit Descriptions for PMON_CONTROL

0 CONVERT Conversion enable. 0x1 RW
0 Power monitor is not running.
1 Power monitor is sampling. Default. In single shot mode, this bit clears
itself after one complete cycle. In continuous mode, this bit must be
written to 0 to stop sampling. A rising edge on the conversion input
(CONV function of Pin 13) or a falling edge on SPI_SS sets this bit to 1.
During sampling, additional conversion edges on these pins are
ignored.
POWER MONITOR CONFIGURATION REGISTER

Address: 0xD4, Reset: 0x0714, Name: PMON_CONFIG
This command configures the power monitor. Different combinations of channels can be included in the rotational sampling, and
averaging can be set for different measurements.
Table 46. Bit Descriptions for PMON_CONFIG

15 TSFILT Temperature sensor filter enable. 0x0 RW
0 Disabled.
1 Enabled. Data sheet specifications are with the temperature sensor
filter disabled.
14 SIMULTANEOUS Simultaneous sampling. 0x0 RW
0 Disabled.
1 Enabled. Power monitoring accuracy is reduced. Data sheet
specifications are with simultaneous sampling disabled.
ADM1278 Data Sheet
[13:11] PWR_AVG PIN averaging. 0x0 RW
000 Disables sample averaging for power.
001 Sets sample averaging for power to two samples.
010 Sets sample averaging for power to four samples.
011 Sets sample averaging for power to eight samples.
100 Sets sample averaging for power to 16 samples.
[10:8] VI_AVG VIN/VOUT/IOUT averaging. 0x7 RW
000 Disables sample averaging for current and voltage.
001 Sets sample averaging for current and voltage to two samples.
010 Sets sample averaging for current and voltage to four samples.
011 Sets sample averaging for current and voltage to eight samples.
100 Sets sample averaging for current and voltage to 16 samples.
4 PMON_MODE Conversion mode. 0x1 RW
0 Single shot sampling.
1 Continuous sampling.
3 TEMP1_EN Enable temperature sampling. 0x0 RW
0 Temperature sampling disabled.
1 Temperature sampling enabled.
2 VIN_EN Enable VIN sampling. 0x1 RW
0 VIN sampling disabled.
1 VIN sampling enabled.
1 VOUT_EN Enable VOUT sampling. 0x0 RW
0 VOUT sampling disabled.
1 VOUT sampling enabled.
ALERT 1 CONFIGURATION REGISTER

Address: 0xD5, Reset: 0x0000, Name: ALERT1_CONFIG
This commands allows different combinations of faults and warnings to be configured on the GPO1 output of the GPO1/ALERT1/
CONV pin. The pin can operate in different modes, configured using the DEVICE_CONFIG command.
Table 47. Bit Descriptions for ALERT1_CONFIG

15 FET_HEALTH_FAULT_EN1 FET health fault enable. 0x0 RW
14 IOUT_OC_FAULT_EN1 IOUT overcurrent fault enable. 0x0 RW
13 VIN_OV_FAULT_EN1 VIN overvoltage fault enable. 0x0 RW
12 VIN_UV_FAULT_EN1 VIN undervoltage fault enable. 0x0 RW
11 CML_ERROR_EN1 Communications error enable. 0x0 RW
10 IOUT_OC_WARN_EN1 IOUT overcurrent warning enable. 0x0 RW
9 HYSTERETIC_EN1 Hysteretic output enable. 0x0 RW
8 VIN_OV_WARN_EN1 VIN overvoltage warning enable. 0x0 RW
7 VIN_UV_WARN_EN1 VIN undervoltage warning enable. 0x0 RW
6 VOUT_OV_WARN_EN1 VOUT overvoltage warning enable. 0x0 RW
5 VOUT_UV_WARN_EN1 VOUT undervoltage warning enable. 0x0 RW
4 HS_INLIM_EN1 Hot swap in-limit enable. 0x0 RW
Data Sheet ADM1278
3 PIN_OP_WARN_EN1 PIN overpower warning enable. 0x0 RW
2 OT_FAULT_EN1 Overtemperature fault enable. 0x0 RW
1 OT_WARN_EN1 Overtemperature warning enable. 0x0 RW
ALERT 2 CONFIGURATION REGISTER

Address: 0xD6, Reset: 0x0000, Name: ALERT2_CONFIG
This commands allows different combinations of faults and warnings to be configured on the GPO2 output of the GPO2/ALERT2 pin.
The pin can operate in different modes, configured using the DEVICE_CONFIG command.
Table 48. Bit Descriptions for ALERT2_CONFIG

15 FET_HEALTH_FAULT_EN2 FET health fault enable. 0x0 RW
14 IOUT_OC_FAULT_EN2 IOUT overcurrent fault enable. 0x0 RW
13 VIN_OV_FAULT_EN2 VIN overvoltage fault enable. 0x0 RW
12 VIN_UV_FAULT_EN2 VIN undervoltage fault enable. 0x0 RW
11 CML_ERROR_EN2 Communications error enable. 0x0 RW
10 IOUT_OC_WARN_EN2 IOUT overcurrent warning enable. 0x0 RW
9 HYSTERETIC_EN2 Hysteretic output enable. 0x0 RW
8 VIN_OV_WARN_EN2 VIN overvoltage warning enable. 0x0 RW
7 VIN_UV_WARN_EN2 VIN undervoltage warning enable. 0x0 RW
6 VOUT_OV_WARN_EN2 VOUT overvoltage warning enable. 0x0 RW
5 VOUT_UV_WARN_EN2 VOUT undervoltage warning enable. 0x0 RW
4 HS_INLIM_EN2 Hot swap in-limit enable. 0x0 RW
3 PIN_OP_WARN_EN2 PIN overpower warning enable. 0x0 RW
2 OT_FAULT_EN2 Overtemperature fault enable. 0x0 RW
1 OT_WARN_EN2 Overtemperature warning enable. 0x0 RW
PEAK TEMPERATURE REGISTER

Address: 0xD7, Reset: 0x0000, Name: PEAK_TEMPERATURE
Reports the peak measured temperature. Writing 0x0000 with this command resets the peak value.
Table 49. Bit Descriptions for PEAK_TEMPERATURE

[11:0] PEAK_TEMPERATURE Peak temperature measurement, expressed in direct format. 0x000 R
DEVICE CONFIGURATION REGISTER

Address: 0xD8, Reset: 0x000D, Name: DEVICE_CONFIG
This command configures the hot swap overcurrent threshold and filtering, and GPO1/GPO2 output modes. Note that dual function pin
names are referenced by the relevant function only, for example, GPO2 for the general-purpose output function of the GPO2/ALERT2
pin (see the Pin Configurations and Function Descriptions section for full pin mnemonics and descriptions).
Table 50. Bit Descriptions for DEVICE_CONFIG

11 FHDIS FET health disable. 0x0 RW
0 FET health checks enabled.
1 FET health checks disabled.
ADM1278 Data Sheet
10 PWR_HYST_EN When enabled, the general-purpose output alert hysteresis functions refer 0x0 RW
to power rather than current. The HYSTERETIC_ENx bit also needs to be set
in ALERT_CONFIG.
0 Current hysteresis mode.
1 Power hysteresis mode.
[9:8] GPO2_MODE GPO2 configuration mode. 0x0 RW
00 Default. GPO2 is configured to generate SMBAlerts.
01 GPO2 can be used as a general-purpose digital output pin. Use the
GPO2_INVERT bit to change the output state.
10 Reserved.
11 This is digital comparator mode. The output pin now reflects the live status
of the warning or fault bit selected for the output. In effect, this is a
nonlatched SMBAlert.
7 GPO2_INVERT GPO2 invert mode. 0x0 RW
0 In SMBAlert mode, the output is not inverted, and active low. In GPO mode,
the output is set low.
1 In SMBAlert mode, the output is inverted, and active high. In GPO mode,
the output is set high.
[6:5] GPO1_MODE GPO1 configuration mode. 0x0 RW
00 Default. GPO1 is configured to generate SMBAlerts.
01 GPO1 can be used as a general-purpose digital output pin. Use the
GPO1_INVERT bit to change the output state.
10 GPO1 is configured as a convert (CONV) input pin.
11 This is digital comparator mode. The output pin now reflects the live status
of the warning or fault bit selected for the output. In effect, this is a
nonlatched SMBAlert.
4 GPO1_INVERT GPO1 invert mode. 0x0 RW
0 In SMBAlert mode, the output is not inverted, and active low. In GPO mode,
the output is set low.
1 In SMBAlert mode, the output is inverted, and active high. In GPO mode,
the output is set high.
[3:2] OC_TRIP_SELECT Severe overcurrent threshold select. 0x11 RW
00 125%.
01 150%.
10 200%.
11 Default, 225%.
1 OC_RETRY_DIS Severe OC retry mode. 0x0 RW
0 Retry once immediately after severe overcurrent event.
1 Latch off after severe overcurrent event.
0 OC_FILT_SELECT Severe overcurrent filter select. 0x1 RW
0 200 ns.
1 Default, 900 ns.
POWER CYCLE REGISTER

Address: 0xD9, Send Byte, No Data, Name: POWER_CYCLE
This command is provided to allow a processor to request the hot swap to turn off and turn back on again approximately five seconds
later. This is useful in the event that the hot swap output is powering the processor.
This command does not require any data.
Data Sheet ADM1278
PEAK PIN REGISTER
Address: 0xDA, Reset: 0x0000, Name: PEAK_PIN
Reports the peak input power, PIN. Writing 0x0000 with this command resets the peak value.
Table 51. Bit Descriptions for PEAK_PIN

[15:0] PEAK_PIN Peak input power calculation, PIN, expressed in direct format. 0x0000 R
READ PIN (EXTENDED) REGISTER

Address: 0xDB, Reset: 0x000000, Name: READ_PIN_EXT
Reads the extended precision version of the calculated input power, PIN, from the device.
Table 52. Bit Descriptions for READ_PIN_EXT

[23:0] READ_PIN_EXT Extended precision version of peak input power calculation, PIN, 0x000000 R
expressed in PMBus direct format.
READ EIN (EXTENDED) REGISTER

Address: 0xDC, Reset: 0x0000000000000000, Name: READ_EIN_EXT
Read the extended precision energy metering registers in a single operation to ensure time consistent data.
Table 53. Bit Descriptions for READ_EIN_EXT

[63:40] SAMPLE_COUNT This is the total number of PIN samples acquired and accumulated in the 0x000000 R
energy count accumulator. This is an unsigned 24-bit binary value.
byte.
[39:24] ROLLOVER_EXT Number of times that the energy count has rolled over from 0x7FFFFF 0x0000 R
to 0x000000. This is an unsigned 16-bit binary value. Byte 4 is the high
byte, and Byte 3 is the low byte.
[23:0] ENERGY_EXT Extended precision energy accumulator value in PMBus direct format. 0x000000 R
byte.
HYSTERESIS LOW LEVEL REGISTER

Address: 0xF2, Reset: 0x0000, Name: HYSTERESIS_LOW
This sets the lower threshold used to generate the hysteretic output signal, which can be made available on a general-purpose output pin.
Table 54. Bit Descriptions for HYSTERESIS_LOW

[15:0] HYSTERESIS_LOW Value setting the lower hysteresis threshold, expressed in direct format. 0x000 RW
HYSTERESIS HIGH LEVEL REGISTER

Address: 0xF3, Reset: 0xFFFF, Name: HYSTERESIS_HIGH
This sets the higher threshold used to generate the hysteretic output signal, which can be made available on a general-purpose output pin.
Table 55. Bit Descriptions for HYSTERESIS_HIGH

[15:0] HYSTERESIS_HIGH Value setting the higher hysteresis threshold, expressed in direct format. 0xFFFF RW
ADM1278 Data Sheet
HYSTERESIS STATUS REGISTER
Address: 0xF4, Reset: 0x00, Name: STATUS_HYSTERESIS
This status register reports whether the hysteretic comparison is above or below the user defined thresholds, and the
IOUT_OC_WARNING status bit as well.
Table 56. Bit Descriptions for STATUS_HYSTERESIS

3 IOUT_OC_WARN IOUT overcurrent warning. 0x0 R
0 No overcurrent condition on the output supply detected by the power
monitor using the IOUT_OC_WARN_LIMIT command.
1 An overcurrent condition was detected by the power monitor using
the IOUT_OC_WARN_LIMIT command.
2 HYST_STATE Hysteretic comparison output. 0x0 R
0 Comparison output low.
1 Comparison output high.
1 HYST_GT_HIGH Hysteretic upper threshold comparison. 0x0 R
0 Compared value is below upper threshold.
1 Compared value is above upper threshold.
0 HYST_LT_LOW Hysteretic lower threshold comparison. 0x0 R
0 Compared value is above lower threshold.
1 Compared value is below lower threshold.
START-UP IOUT LIMIT REGISTER

Address: 0xF6, Reset: 0x000F, Name: STRT_UP_IOUT_LIM
This sets the current limit initially used while the hot swap is turning on the FET.
Table 57. Bit Descriptions for STRT_UP_IOUT_LIM

[15:4] RESERVED Always reads as 0x00. 0x00 RESERVED
[3:0] STRT_UP_IOUT_LIM Current limit used during startup, expressed in direct format. 0xF RW
0000 Current limit equal to (ISTART × 1/16) (hot swap start up current limit level).
0001 Current limit equal to (ISTART × 2/16).
… …
1110 Current limit equal to (ISTART × 15/16).
1111 Current limit equal to ISTART.
Data Sheet ADM1278
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
5.10 0.30
5.00 SQ 0.25
PIN 1
INDICATOR 4.90 0.18
AREA
25 32 P IN 1
IN D IC AT O R AR E A OP T I O N S
(SEE DETAIL A)
24 1
0.50
BSC
3.45
EXPOSED 3.30 SQ
PAD
3.15
17 8
0.50 16 9
0.20 MIN
TOP VIEW BOTTOM VIEW
0.40
0.30 3.50 REF
0.80 FOR PROPER CONNECTION OF
0.75 END VIEW THE EXPOSED PAD, REFER TO
0.05 MAX THE PIN CONFIGURATION AND
0.70
0.02 NOM FUNCTION DESCRIPTIONS
COPLANARITY SECTION OF THIS DATA SHEET.
SEATING 0.08
PLANE 0.20 REF
09-12-2018-B
PKG-003530
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.
Figure 74. 32-Lead Lead Frame Chip Scale Package [LFCSP]

5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-13)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADM1278-1AACPZ −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-13
ADM1278-1AACPZ-RL −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-13
ADM1278-1ACPZ −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-13
ADM1278-1ACPZ-RL −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-13
ADM1278-1BCPZ −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-13
ADM1278-1BCPZ-RL −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-13
EVAL-ADM1278EBZ Evaluation Kit
1
Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2014–2020 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
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Adm 1278

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Hot Swap Controller and Digital Power and

Energy Monitor with PMBus Interface

Telecommunication and data communication equipment

Rev. C Document Feedback

10/2018—Rev. A to Rev. B 6/2014—Revision 0: Initial Version

POWER MONITORING ACCURACY SPECIFICATIONS

SERIAL BUS TIMING CHARACTERISTICS

Figure 2. Serial Bus Timing Diagram

SPI TIMING CHARACTERISTICS (ADM1278-2)

MCLK DON’T DON’T

MDAT MSB LSB

Figure 3. SPI Timing Diagram

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 4. ADM1278-1 Pin Configuration Figure 5. ADM1278-3 Pin Configuration

Table 8. ADM1278-1 and ADM1278-3 Pin Function Descriptions

Figure 6. ADM1278-2 Pin Configuration

Table 9. ADM1278-2 Pin Function Descriptions

TYPICAL PERFORMANCE CHARACTERISTICS

–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80

TEMPERATURE (°C) VCC (V)

–40 –30 –20 –10 0 10 20 30 40 50 60 70 80

0 5 10 15 20 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80

–40 –30 –20 –10 0 10 20 30 40 50 60 70 80

–40 –30 –20 –10 0 10 20 30 40 50 60 70 80

–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80

MEASUREMENT ERROR (°C)

IMO+/ IMO– (nA)

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

IHS+ /IHS− (µA)

separate traces to prevent accuracy loss in the sense voltage + –

Figure 47. Hot Swap Current Sense Amplifier

Figure 51. Current-Limit Reference Selection

of how the ISTART, PSET, and ISET voltages interact during

components can be added, as shown in Figure 50, without

Figure 50. Power Monitor Current Sense Filtering PWRGD

Figure 52. Interaction of ISTART, PSET, and ISET Current Limits

To program the sense voltage from 5 mV to 25 mV, a resistor

Figure 56. Linear Voltage Ramp Power-Up

Figure 57. Undervoltage and Overvoltage Supply Monitoring

IOUT VIN PIN VOUT TEMPERATURE

Figure 60. Output Data Format

Figure 61. Streaming Current Data Only

FET HEALTH POWER MONITOR

S SLAVE ADDRESS W A DATA BYTE A P

S SLAVE ADDRESS W A DATA BYTE A PEC A P

Figure 62. Send Byte and Send Byte with PEC

S SLAVE ADDRESS R A DATA BYTE A P

S SLAVE ADDRESS R A DATA BYTE A PEC A P

Figure 63. Receive Byte and Receive Byte with PEC

S SLAVE ADDRESS W A COMMAND CODE A DATA BYTE A P

S SLAVE ADDRESS W A COMMAND CODE A DATA BYTE A PEC A P

Figure 64. Write Byte and Write Byte with PEC

S SLAVE ADDRESS W A COMMAND CODE A Sr SLAVE ADDRESS R A DATA BYTE A P

S SLAVE ADDRESS W A COMMAND CODE A Sr SLAVE ADDRESS R A DATA BYTE A PEC A P

Figure 65. Read Byte and Read Byte with PEC