AI 302

Embedded Systems
SPRING 2023

Lecture 09 - Memory Organization

Instructor: Dr. Tarek Abdul Hamid
Memory Hierarchy

Main memory can be implemented using SRAM/DRAM

Auxiliary memory is like HDD, CD, DVD where cost/bit is much more less than main
memory because its offered with high size and lower costs.

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Memory Hierarchy

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Main (Internal) Memory
 RAM – Random Access Memory.
 Temporary read/write memory.
 Applications are typically loaded into RAM during computer use. Types of RAM include:
 SRAM (Static)

 SRAM is called static because the memory retains its contents as long as power is supplied-
It does not have to be periodically refreshed as in DRAM.
 It is faster than DRAM (The contents of the memory can be read much faster), however is
more expensive and is larger in size
 DRAM (Dynamic )
 DRAM is called Dynamic RAM because the memory content needs to be refreshed
periodically (every few milliseconds) due to leakage of electrical charge.
 It is slower than SRAM, but cheaper and smaller in size
 EDO RAM (Extended Data Out) ,
 SDRAM (Synchronous Dynamic)
 Most new PC’s are equipped with this RAM which is able to synchronize itself with the
processor, enabling data transfer at more than twice the speed of previous RAM
technologies)
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Main (Internal) Memory

 ROM – Read Only Memory.

 ROM can typically be written once, but read many times.
 It is used to store BIOS (Basic Input/Output System-helps to load and locate an operating
system), external to microprocessor, and computer instruction sets, internal to
microprocessor
 The contents of the ROM are hard wired by the manufacturer in a typical ROM chip.
 When you turn the computer on, ROM automatically prepares the computer system and
loads the initial display screen prompt
 A variation of ROM is PROM (Programmable Read Only Memory), in which the user can
load programs and data that are read only.
 This can be done with device called a PROM programmer.
 Writing to a PROM destroys the internal links, so a basic PROM can only be
programmed once

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Main Memory

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Main Memory

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Example

SOLUTION:

a. 2048 / 128 = 16 chips

b. 2048 = 211 11 Lines to address 2048 bytes.

128 = 27 7 Lines to address each chip.
4 Lines to decoder for selecting 16 chips.

c. 4 x 16 decoder

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Example

A Computer employs RAM chips of 128 x 8 and ROM chips of 512 x 8.

The computer system needs total of 1k bytes, 512 bytes of RAM

and 512 bytes of ROM.

a) How many RAM and ROM chips are needed? indicate

what size decoders are needed.

b) Draw a memory-address map for the system.

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Solution:

a) RAM and ROM chips are connected to a CPU though the data
and address busses.

The lower-order lines in the address bus select the bus within the
chips and other lines in the address bus select a particular chip
though its chip select inputs.

RAM 512/128 = 4 chips 512=29 128=27

2 x 4 Decoder

ROM 512/512 = ONE chip 512=29 512=29

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Solution:

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Solution:
Memory Address Map

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Example

Extend the memory system of the pervious example to 4096

bytes of RAM and 4096 bytes of ROM.

List the memory-address map and indicate what size decoders

are needed.

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Solution:

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Cache Memory

Locality of Reference:
 The references to memory at any given time intervals tend to confined within a
localized areas.
 This area contains a set of information and the membership changes gradually as
time goes by.
 Temporally Locality:
 The information which will be used in near future is likely to be in use already
(e.g Reuse of information in loops).
 Spatial Locality:
 If word is accessed, adjacent (near) words are likely accessed soon (e.g Related
data items (arrays) are usually stored together; e.g instructions are executed
sequentially)

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Cache Memory

Cache
 The property of locality of reference makes the cache memory systems work.
 Cache is a fast small capacity memory that should hold those information which are
most likely to be accessed.

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Computer Organization and Architecture
Cache Access

 All the memory accesses are directed first to cache.

 If the word is in cache; Access cache to provide it to the CPU.
 If the word is not in cache; Bring a block including this word to replace a block
now in cache.

 How can we know if the word that is required is there?

 If a new block is to be replace one of the old block, Which one should we
choose?

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Cache Performance

Hit Ratio - % of Memory accesses satisfied by cache memory access

No. of Hits
Hit Ratio (h) =
No. of Hits + No. of Miss

Tc: Cache access time

Tm: Main Memory Access
Te: Effective memory access time in cache memory system

Te =( Tc * h) + ( Tm * ( 1 – h ) )

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Memory and Cache Mapping

Mapping Function:
Specification of correspondence between main memory blocks and cache blocks:

• Direct Mapping (√)

• Associative Mapping (×)

• Set-Associative Mapping (×)

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Direct Mapping

• Each memory block has only one Place to load in cache

• N-bits memory address consists of 2 parts:
• K = Index = Address corresponding to the cache ( K bits of Index field)
• N = Total Number of memory address ( N bits of Memory address)
• Tag = N - K

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Direct Mapping

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Direct mapping (Cont.)

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Direct mapping (Cont.)

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Example

A digital computer system has memory unit of 16K X 8 and cache memory of 128
words, the cache using the direct mapping with a block size of four words.

i) How many bits are there in the tag, index, word and fields of the address
format.

i) How many bits are there in each word of cache, and how are they divided, into
function?

i) How many blocks the cache can accommodate?

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Solution
I) 16k Memory ⇒ N = 14
128 Cache memory ⇒ K=7 ⇒ Tag = 7

7-bits 5-bits 2-bits

Tag Block Word

II) 8 + 7 = 15 bits
8 = data bits
7 = Tag address bits

III) 32 blocks

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Example

A digital computer system has memory unit of 512K X 16 and cache memory of 2 K
words, the cache using the direct mapping with a block size of four words.

I. Show how many bits are there in the tag, index, word and block fields of the
address format.

II. Show how many bits are there in each word of cache, and how are they
divided, into function?

III. Demonstrate how many blocks the cache can accommodate?

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Solution
I) 512k Memory ⇒ N = 19
2k Cache memory ⇒ K = 11 ⇒ Tag = 8

8-bits 9-bits 2-bits

Tag Block Word

II) 16 + 8 = 24 bits
16 = data bits
8 = Tag address bits

III) 512 blocks

27
Cache write

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