W25Q128JV aa Winbond sam apriflash 3V 128M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI For Industrial & Industrial Plus Grade Publication Release Date: March 27, 2018 Revision FGENERAL DESCRIPTIONS. FEATURES. PACKAGE TYPES AND PIN CONFIGURATIONS. at 32 33 34 35 36 37 38 39 PIN DESCRIPTIONS: W25Q1285V T] Winbond Table of Contents Pin Configuration SOIC 208-mil Pad Configuration WSON 6x5-mm/ 8x6.mm Pin Description SOIC 208-mil, WSON 6x5-mm 8x6-mm.. Pin Configuration SOIC 300-mil Pin Description SOIC 300-mil Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) Ball Description TFBGA 8x6-mm. Ball Configuration WLCSP...., Ball Description WLCSP24... 4.1 Chip Select (/CS) 4.2 Serial Data Input, Output and IOs (DI, DO and 100, 101, 102, 103).. 43° Write Protect (WP) 44 HOLD (/HOLD) 4.5 Serial Clock (CLK) 46 — Reset (RESET) BLOCK DIAGRAM. enn FUNCTIONAL DESCRIPTIONS. " 6.1 Standard SPI Instructions. 62 Dual SPI Instructions 6.3 Quad SPI Instructions. 64 — Software Reset & Herdware /RESET pin 65 — Write Protection. 12 6.5.1 Write Protect Features 12 STATUS AND CONFIGURATION REGISTERS 13 7.4 Status Registers 13 7.11 EraselWrite In Progress (BUSY) - Status Only. 18 7.1.2 Write Enable Latch (WEL) - Status Only. see 13 7.1.3 Block Protect Bits (BP2, BP1, BPO) - Volatle/Non-Volatile Writable, 13 7.1.4 ToplBottom Block Protect (TB) - Volatile/Non-Volatile Writable......uee 14 7.1.8 SectorfBlock Protact Bit (SEC) - Volatle/Non-Volatile Writable 14 7.1.6 Complement Protect (CMP) - Volatile/Non-Volatile Writebie 14W25Q1285V gees) Winbond «ssam 8 INSTRUCTIONS... at 82 7.11 Status Ragister Protect (SRP, SRL) - Volatile/Non-Volatile Writable 7.1.2 EraselProgram Suspend Status (SUS) - Status Only 16 7.1.3 Security Register Lock Bits (LB3, LB2, LB1) - Volatile/Non-Volatile OTP Writable.....16 7.1.4 Quad Enable (QE) - Volatile/Non-Volatle Writabie 16 7.1.8 Write Protect Selection (WPS) - Volatle/Non-Volatile Writable 7 7.1.6 Output Drivar Strength (DRV1, DRVO) - Volatile/Non- Volatile Writable 17 T..7 Reserved Bits - Non Functional. 7.1.8 W25Q128V Status Register Memory Protection (WPS = 0, CMP = 0) 7.1.8 W25Q128JV Status Register Memory Protection (WPS = 0, CMP = 1). 7.1.10 W250128JV Individual Block Memory Protection (WP§ Device ID and Instruction Set Tables........ 8.1.1 Manufacturer and Device Identification . 8.1.2 Instruction Sot Table 1 (Standard SPI Instructions), 8.1.3 Instruction Set Table 2 (Dual/Quad SPI Instructions) Notes: Instruction Descriptions... 8.2.1 Write Enable (06h) 822 Write Enable for Volatile Status Registor (50h) 8.23 Write Disable (04t). 8.24 Read Status Register (Osh, Status Registr-2 (G5n)& Status Register (15h) 8.2.5 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h) 8.2.6 Read Data (03h). 827 Fast Read (08h) 8.2.8 Fast Read Dual Output (38h). 8.29 Fast Read Quad Output (68h). 8.2.10 Fast Read Dual VO (BBh). 8.2.11 Fast Read Quad I/O (EBh) 8.2.12 Sot Burst with Wrap (77h) 8.2.13 Page Program (02h). 8.214 Quad Input Page Program (32h) 8.2.15 Sector Erase (20h) vs 8.2.16 $2KB Block Erase (52h) warn 8.2.17. G4KB Block Erase (D8h). 8.2.18 Chip Erase (C7h 60h) 8.2.19 Erase / Program Suspend (75h) 8.2.20 Erase / Program Resume (7Ah). 82.21 Power-down (B3h). 8.2.22 Rolease Power-down / Device ID (ABh). 82.23 Read Manufacturer / Device ID (90h). Publication Release Date: March 27, 2018 Revision F10. nu. 12, ELECTRICAL CHARACTERISTICS. 94 92 93 94 95 96 a7 98 99 PACKAGE SPECIFICATIONS... 10.1 10.2 103 10.4 105 108 107 ORDERING INFORMATION 4 REVISION HISTORY. W25Q1285V Tl Winbond «ssa 82.24 Read Manufacturer / Davice ID Dual I/O (92h) 8.2.25 Read Manufacturer / Device ID Quad 10 (94h) 48 8.2.26 Read Unique ID Number (48h) 49 8.2.27 Road JEDEC ID (Fh). 60 8.2.28 Road SFOP Rogistor (5Ah) 51 82.29 Erase Security Registers (44h). 8.2.30 Program Security Registers (42h) 62 53 8.2.31 Read Security Registors (48h) 54 8.2.32 Individual Block/Sector Lock (36h). see 55 8.2.33 Individual Block/Sector Unlock (32h). 56 8.2.34 Read Block/Sector Lock (30h) st 8.2.35 Global BlockSector Lock (7Eh) 58 8.2.36 Global Block/Sector Unlock (98h) 8.2.37 Enable Reset (86h) and Reset Device (92h). Absolute Maximum Ratings Operating Ranges. Power-Up Power-Down Timing and Requirements... DC Electrical Characteristics. AC Measurement Conditions. AC Electrical Characteristics) Serial Output Timing. Serial Input Timing... ANP Timing... &-Pin SOIC 208-mil (Package Code S).. 16-Pin SOIC 200-mil (Package Code F) 8-Pad WSON 6x5-mm (Package Code P) 8.Pad WSON 8x6-mm (Package Code E) 24-Ball TFBGA 8x6-mm (Package Code B, 5x5-1 ball array)... 24-Ball TFEGA 8x6-mm (Package Code C, 6x4 ball aray).. 24-Ball WLCSP (Package Code Y) SBFIIRBRRBRSBBBE Valid Part Numbers and Top Side MarkingW25Q128JV wae Winbond saga 1, GENERAL DESCRIPTIONS The W25Q128JV (126M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 250 series offers fexiblty and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current consumption as low as 1A for power-down. All devices are offered in space-saving packages. The W25Q128JV array is organized into 65,536 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q128]V has 4,096 erasable sectors and 256 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See Figure 2.) The W250128JV supports the standard Serial Peripheral Interface (SPI), Dual/Quad V/O SPI: Serial Clack, Chip Select, Serial Data 1/00 (DI), VO1 (DO), I/02 and 1/03. SPI clock frequencies of W25Q128/V of up to 133MHz are supported allowing equivalent clock rates of 266MHz (133MHz x 2) for Dual I/O and 532MHz (133MHz x 4) for Quad VO when using the Fast Read DualiQuad VO. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. Additionally, the device supports JEDEC standard manufacturer and device ID and SFDP, and @ 64-bit Unique Serial Number and three 256-bytes Security Registers. 2. FEATURES * New Family of SpiFlash Memories * Flexible Architecture with 4KB sectors -W25Q128JV: 128M-bit / 16M-byte — Uniform Sector/Block Erase (4K/32K/64K-Byte) = Standard SPI: CLK, /CS, DI, DO = Program 1 to 256 byte per programmable page — Dual SPI: CLK, /CS, !Oo, 10: — Erase/Program Suspend & Resume = Quad SPI: CLK, ICS, 10, |Os, 1O2, IOs * Advanced Security Features ~ Software & Hardware Reset” ~ Software and Hardware Write-Protect * Highest Performance Serial Flash - Power Supply Lock-Down = 133MH2 Single, Dual/Quad SPI clocks — Special OTP protection — 266/532MHz equivalent Dual/Quad SPI — Top/Bottom, Complement array protection ~ 66MB/S continuous data transfer rate ~ Individual Block/Sector array protection = Min, 100K Program-Erase cycles per sector = 64-Bit Unique ID for each device = More than 20-year data retention = Discoverable Parameters (SFDP) Register + Efficient “Continuous Read” = 3X256-Bytos Security Registers with OTP locks = Continuous Read with 8/10/32/64-Byte Wrap _—_~ Volatile & Non-volatile Status Register Bits ~ As few as 8 clocks to address memory, * Space Efficient Packaging — Allows true XIP (execute in place) operation — 8-pin SOIC 208-mil + Low Power, Wide Temperature Range = 16-pin SOIC 300-mil (addtional /RESET pin) ~ Single 27 to 3.8V supply = 8-pad WSON 6x5-mm / 8x6-mm ~ 1A Power-down (typ.) = 24-ball TFBGA 8x6-mm (6x4/5x5 ball aay) —-40°C to +85°C operating range ~ 24-ball WLOSP w 40°C to #105°C operating range = Contact Winbond for KGD and other options Nota: 1, Hardware /RESET pin is only available on TEBGA or SOICTS packages Publication Release Date: March 27, 2018 “4 Revision FW25Q1285V aan Winbond saga 3. PACKAGE TYPES AND PIN CONFIGURATIONS 3.1 Pin Configuration SOIC 208-mil Top View es Doo) Co vec /HOLD or RESET (105) MP (10) 4 enD clK DI (100) Figure 1@. W250728IV Pin Assignments, &-pin SOIG 208ml (Package Co 3.2. Pad Configuration WSON 6x5-mm/ 8x6-mm Top View ics 1 8 vec 5 | /HOLD or RESET Doo) => 2 7 Cy gy wp (10) [=> 3 6 CLK GND 4 5 <2} DI (lO) Figure 1b. W25Q128IV Pad Assignments, &-psd WSON Ox6-mm 8x6-mm (Package Code PE) 3.3. Pin Description SOIC 208-mil, WSON 6x5-mm / 8x6-mm PAD NO. PAD NAME vo FUNCTION 1 18 1 [is Set 2 DO (101) vo Data Output (Data Input Output 1)" 3 TWP (102) UO _| Write Protect input ( Data input Output 2)” 4 NO Ground 5 DI (lOO) vo Data Input (Data Input Output 0)" 8 aux 1 [Seria ack np 7 | MOLBGPRESET 1 | ses orResst mpi (Data inp Out 2% o vo Power Supply Note! 1) and 101 ave used for Standard and Dual PL instructions 2100108 ar used for Quad SPI istration, HOLD (or RESET) function i only avaiable for Standard Dual SPLW25Q128JV aa Winbond sam 3.4 Pin Configuration SOIC 300-mil Top View JHOLD (10s) e clk vec DI (10x) IRESET NC No No Ne No No No ics, GND DO (10,) MP (102) Figure 1c. W25Q128JV Pin Assignments, 1-pin SOIC 200-mul (Package Code F) 3.5 Pin Description SOIC 300-mil PIN NO. PIN NAME uo FUNCTION 1 | tbe | wo | How or Reset np Ome rp up) a vee over Sn a TRESET Rett 4 Ne Nocomect 5 Ne Ne correct € NC No Gore 7 16S [en selena Hi 50.10) | WO] Baia Out Ona RROD 8 WP (102) iO _| Write Protect Input (Data input Output 2) 0 ox Ground 1 No Ne conn 2 NC No Gone 8 NC Ne Gore 1 NG No Gomect 1s 1 (00)| WO | Bata Oat pt uO i uk 1 [Sera Gc rt Notes: 1.100 and 101 are used fr Standars and Dual SP instructions. 2.100103 are used for Quad SPI instructions, /HOLD (or RESET) function is only available for StandardiDusl SPI 3. The IRESET pin is @ dedicated hardware reset pin rogardess of device settings oF operation states. Ifthe hardware reset function isnot used, his pn can be left lating or connected to VCC in the system Publication Release Date: March 27, 2018 +6. Revision FW25Q1285V aa Winbond sam 3.6 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) Top View Top View @ 8 & @ oto) 2 8 6 Package Code B Package Code C Figure 1d. W250128JV Ball Assionments, 24-ball TFBGA &x6-mm (Package Code BO) 3.7 Ball Description TFBGA 8x6-mm BALLNO. | PINNAME vo FUNCTION. A (RESET 1 | Reset input® 52 CLK T__| Serial Glock input 83. GND Ground Bs voc Power Supply. 2 ics. T__| Chip Select input C4 MP (102) VO | Write Protect Input (Data Input Output 2)2 D2 Do (101) WO | Data Output (Data Input Output 1)" D3, Di (100) WO | Data input (Data Input Output 0)" Da THOLD (103) UO | Hold or Reset Input (Data Input Output 3)2 Mutiplo NC. Ne Connect Notes: 4. 100.nd 101 are used for Standard and Dual SP instructions 2 100-103 are used for Guad SP! instructions, ‘HOLD (or /RESET) function is only available fr Standard/Dusl SPL 3. Tho (RESET pin isa dosicated hardware reset pn regardless of dovco setngs or operation states. Ifthe hardware reset function is not used, this pin can be left foating or connected to VCC inthe systemW25Q1285V gees) Winbond sam 3.8 Ball Configuration WLCSP. Top View @) (3) (cay we Bion We o @ & GK Bos) @ oiiée) ate ® a) 2 @ @ co) s® «@ @ ® 3.9 Ball Description WLCSP24 Figure te W25Q128,V Ball Assignments, 24-ball WLOSP (Package Goce ¥) BALLNO. | PIN NAME to FUNCTION B2 vec Power Supply 63 (cs |_| chip select input e HOLD (103) 10 _| Hold Input (Data Input Output 3)°2 Cy Do (lor) 1 | Data Output Data Input Output 1)"* be uk |__| Serial Glock input D3 BWP (102) WO _| Write Protect input (Data Input Output 2)°2 2 i100) VO _| Data Input (Data Input Output 07 ES GND Ground Notes: 1100 and 101 are used fr Standard and Dual SPI instructions 2.100 ~103 are used for Guad SPI instructions, “HOLD (or /RESET) function is only avalable for Stsndard/Dual SPL Publication Release Date: March 27, 2018 ose Revision FW25Q128IV aa Winbond sam 4, PIN DESCRIPTIONS. 41 Chip Select (/CS) The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is deselected end the Serial Data Output (00, or 100, 101, 102, 103) pins are at high impedance. When deselected, the devices power consumption wil be at standby levels unless an intemal erase, program or write status register cycle is in progress. When /CS is brought low the device will be selected, power consumption wil increase to active levels and instructions can be writen to and data read from the device. After power-up, /CS must transition from high to low before a new instruction wil be accepted. The /CS input must track the VCC supply level at power-up and power-down (see “Write Protection” and Figure 58). If needed @ pull-up resister on the /CS pin can be used to accomplish this. 4.2 Serial Data Input, Output and IOs (DI, DO and 100, 101, 102, 103) ‘The W25Q128JV supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions Use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising edge of the Serial Ciock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge of CLK. Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or data to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. When QE=1, the (WP pin becomes 102 and the /HOLD pin becomes 103. 4.3 Write Protect (WP) The Write Protect (WP) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register's Block Protect (CMP, SEC, TB, 8P2, BP1 and BPO) bits and Status Register Protect (SRP) bits, @ portion as small as a 4KB sector or the entire memory array can be hardware protected. The /WP pin is active low. 4.4 HOLD (/HOLD) ‘The /HOLD pin allows the device to be paused while itis actively selected. When /HOLD is brought low, ‘while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don't care). When /HOLD is brought high, device operation can resume. The /HOLD function can be Useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the QE bit of Status Register-2 is set for Quad 1/0, the /HOLD pin function is not available since this pin is used for 103. See Figure 12-c for the pin configuration of Quad /O operation. 4.5 Serial Clock (CLK) The SP! Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI Operations") 4.6 Reset (JRESET) ‘A dedicated hardware IRESET pin is available on SOIC-16 and TFEGA packages. When it's driven low for a minimum period of ~1S, this device will terminate any external or intemal operations and return to its Power-on state. Note: Haraware RESET pin is avalable on SOIC-16 oF TFEGA; ploase contact Winbond fr ths package.W25Q128JV aan Winbond sam 5. BLOCK DIAGRAM ‘SFO? Regster ‘SecurtyRegster 1-3 rs Sock Segmentation Fron FFF cern ss 48) Pe] sex 288 aKa) 0h F000 -oriem FFOOFFH excor2ca@) UP SORE sca) floc 128 68K8) seo 010) ‘irteProtec Loge and Row Decode | | manvonae | ‘Seneraor MOLD (03) Pe goK 064K) RESET 0) 0020 oooaeen cus es ae jf se. f se putas Pane oaess onto boa ovum Desone and 2 Page utr io) >} 7 2010) +] Oy Assess caten / Courter Figure 2. W250128JV Serial Flash Memory Block Diagram Publication Release Date: March 27, 2018 +10+ Revision FW25Q128IV aa Winbond sam 6. FUNCTIONAL DESCRIPTIONS 6.1 Standard SPI Instructions ‘The W250128JV is accessed through an SPI compatible bus consisting of four signals: Serial Clack (CLK), Chip Select (/CS), Serial Data Input (Dl) and Serial Data Output (DO). Standard SPI instructions use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The DO output pin is used to read data or status from the device on the falling edge of CLK. SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is Not being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and rising edges of JCS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS. 6.2 Dual SPI Instructions ‘The W25Q128JV supports Dual SPI operation when using instructions such as “Fast Read Dual Output (38h)’ and ‘Fast Read Dual \/O (BBh)’. These instructions allow data to be transferred to or from the device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Reed instructions are ideal for quickly downloading code to RAM upen power-up (code-shadowing) or for executing non-speed- critical code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins become bidirectional /O pins: 100 and 101 6.3 Quad SPI Instructions ‘The W250128JV supports Quad SPI operation when using instructions such as “Fast Read Quad Output (6Bh)’, and “Fast Read Quad 1/O (EBh). These instructions allow data to be transferred to or from the device four to six times the rate of ordinary Serial Flash. When using Quad SPI instructions, the DI and 1 pins become bidirectional 100 and 101, with the additional 1/0 pins: 102, 103. 6.4 Software Reset & Hardware /RESET pin The W25Q128JV can be reset to the initial power-on state by a software Reset sequence. This sequence must include two consecutive instructions: Enable Reset (6¢h) & Reset (99h). If the instruction sequence is successfully accepted, the device will take approximately 30US (tRST) to reset. No instruction will be accepted during the reset period. For the SOIC-16 and TFBGA packages, W25Q128JV provides 2 dedicated hardware /RESET pin. Drive the /RESET pin low for a minimum period of ~1uS (RESET*) will interrupt any on-going extermalinternal operations and reset the device to its initial power-on state. Hardware /RESET pin has higher priority than other SPI input signals (/CS, CLK, IOs), Note 1. Hardware /RESET pin is available on SOIC-16 or TFEGA; plaase contact Winbond for his package 2. While @ faster (RESET pulse (as short as a Yew hundred nanoseconds) wil ofen reset the davies, @ 1us minimum is Fecemmended to ensure reliable operation, 3. There's an intemal pul-up resistor forthe decicated i is nat needed, tis pin can be lef floating in the system, {ESET pin onthe SOIC-16 and TFBGA-24 package. If the reset function “ueW25Q128JV aae Winbond sam 6.5 Write Protection ‘Applications that use non-volatile memory must take into consideration the possibilty of noise and other adverse system conditions thet may compromise data integrity. To address this concem, the W25Q128JV provides several means to protect the data fram inadvertent writes. 6.5.1 Write Protect Features Device resets when VCC is below threshold Time delay write cisable after Power-up Write enable/disable instructions and automatic write disable after erase or program Software and Hardware (WP pin) write protection using Status Registers ‘Adgitional Individual Block/Sector Locks for array protection Write Protection using Power-down instruction Lock Down write protection for Status Register until the next power-up (One Time Program (OTP) write protection for array and Security Registers using Status Register” Note: This feture is avalsble upon special ow. Please contact Winbond for deta Upon power-up or at power-down, the W25Q128JV will maintain a reset condition while VCC is below the threshold value of Vwi, (See Power-up Timing and Voltage Levels and Figure 43). While reset, all operations are disabled and no instructions are recognized. During power-up and afler the VCC voltage exceeds Vv), all program and erase related instructions are further disabled for a time delay of tPuw. This Includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until the VCC-min level and tvsi. time delay is reached, and it must also track the VCC supply level at power- down to prevent adverse command sequence. If needed a pull-up resister on /CS can be used to accomplish this. After power-up the device is automatically placed in a vrite-disabled state with the Status Register Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write- disabled state of 0. Software controlled write protection is facilitated using the Write Status Register instruction and setting the Status Register Protect (SRP, SRL) and Block Protect (CMP, TB, BP(3:0)) bits. These settings allow a Portion or the entire memory array to be configured as read only. Used in conjunction with the Write Protect (WP) pin, changes to the Status Register can be enabled or disabled under hardware control. See Status Register section for further information. Additionally, the Power-down instruction offers an extra level of write protection as all instructions are ignored except for the Release Power-down instruction, The W25Q128JV also provides another Write Protect method using the Individual Block Locks. Each 64KB block (except the top and bottom blocks, total of 126 blocks) and each 4KB sector within the topibottom blocks (total of 32 sectors) are equipped with an individual Block Lock bit. When the lock bit is 0, the corresponding sector or block can be erased or programmed; when the lock bitis set to 1, Erase or Program commands issued to the corresponding sector or block will be ignored. When the device is powered on, all Individual Block Lock bits will be 1, so the entife memory array is protected from Erase/Program. An Individual Block Unlock (38h)' instruction must be issued to unlock any spesific sector or block. ‘The WPS bit in Status Register-3 is used to decide which Write Protect scheme should be used. When WPS=0 (factory default), the device will only utilize CMP, SEC, TB, BP[2:0] bits to protect specific areas of the array; when WPS=1, the device will utilize the Individual Block Locks for write protection Publication Release Date: March 27, 2018 12+ Revision FW25Q128IV aa Winbond sam 7. STATUS AND CONFIGURATION REGISTERS ‘Three Status and Configuration Registers are provided for W25Q128JV. The Read Status Register-1/2/3 instructions can be used to provide status on the availabilty of the flash memory array, whether the device is write enabied or disabled, the state of write protection, Quad SPI setting, Security Register lock status, EraseiProgram Suspend status, output driver strength, power-up. The Write Status Register instruction can be used to configure the device write protection features, Quad SPI setting, Security Ragister OTP locks, and output driver strength. Write access to the Status Register is controlled by the state of the non-volatile Status Register Protect bits (SRL), the Write Enable instruction, and during Standard/Dual SPI operations 7.1. Status Registers sezrgarnorecr ronepyiourecrecy soogoacecres WRITE ENABLE LATCH \WRITEIN PROGRESS: Figure 48, Status Regstert 7.1.1 EraseMWrite In Progress (BUSY) - Status Only BUSY is a read only bit in the status register (SO) that is set to a 1 state when the device is executing 2 Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or Erase/Program Security Register instruction. During this time the device will ignore further instructions except for the Read Status Register and Erase/Program Suspend instruction (see tw, tpP, SE, tBe, and {cE in AC Characteristics). When the program, erase or write statusisecurity register instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions. 7.1.2. Write Enable Latch (WEL) - Status Only Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing @ Write Enable Instruction. The WEL status bit is cleered to 0 when the device is write disabled. A write disable state ocours upon power-up or after any of the following instructions: Write Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase Security Register and Program Security Register. 7.1.3 Block Protect Bits (BP2, BP1, BPO) ~ Volatile/Non-Volatile Writable ‘The Block Protect Bits (BP2, BP1, BPO) are non-volatile read/write bits in the status register (S4, S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status Register Instruction (see tw in AC characteristics). All, none or a portion of the memory array can be protected from Program and Erase instructions (see Status Register Memory Protection table). The factory default setting for the Block Protection Bits is 0, none of the array protected.W25Q128JV aae Winbond saga 7.4.4 Top/Bottom Block Protect (TB) ~ Volatile/Non-Volatile Writable The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BPO) protect from the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction depending on the state of the SRP, SRL and WEL bits. 7.4.5. Sector/Block Protect Bit (SEC) ~ Volatile/Non-Volatile Writable The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BPO) protect either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The default setting is SEC=0. 7.1.6 Complement Protect (CMP) - Volatile/Non-Volatile Writable ‘The Complement Protect bit (CMP) is @ non-volatile read/write bit in the status register (S14). It is used in conjunction with SEC, TB, BP2, BP1 and BPO bits to provide more flexibility for the array protection. Once CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BPO will be reversed. For instance, when CMP=0, a top 64KB block can be protected while the rest of the array is not; when CMP=1, the top 64KB block will become unprotected while the rest of the array become read-only. Please refer to the Status Register Memory Protection table for details. The default setting is CMP=0, Publication Release Date: March 27, 2018 wise Revision FW25Q1285V aae Winbond saga 71.4 Status Register Protect (SRP, SRL) ~ Volatile/Non-Volatile Writable Three Status and Configuration Registers are provided for W25Q128JV. The Read Status Register-1/2/3 instructions can be used to provide status on the availabilly of the flash memory array, whether the device is write enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock status, Erase/Program Suspend status,and output criver strength, The Write Status Register instruction can be used to configure the device write protection features, Quad SPI setting, Security Register OTP locks, output driver. Write access to the Status Register is controlled by the state of the non-volatile Status Register Protect bits (SRP, SRL), the Write Enable instruction, and during Standard/Dual SPI operations, the WP pin. Status srt |srP | we | Register Description o lo |x | Software ANP pin has no control. The Status register can be written to Protection _| after a Write Enable instruction, WEL=1. [Factory Default] o —|1 Jo | Hardware | When /WP pin is low the Status Register locked and cannot be Protected | writen to. o a 4 | Hardware | When /WP pin is high the Status register is unlocked and can Unprotected | be written to after a Write Enable instruction, WEL=1 + |x |x. [Power Supply | Status Register is protected and cannot be written to again until Lock-Down | the next power-down, power-up cycle.” + |x |x [OneTime | Status Register is permanently protected and cannot be writen Program® | to. (enabled by adding prefix command AAh, 55h) When SRL =" 2 power-dorn, power-up cycle wil change SRI =O state 2. Please contact Winbond for detais reyarang he special msruction sequence, assW25Q1285V am Winbond saa S15 S14 S13 S12 S11 S10 S958 ‘SUSPEND STATUS, (Sets Only (COMPLEMENT PROTECT, (valatie!Nen-VotatleViitabie ‘SEOURITY REGISTER LOCK TS. (atierNen-Volatle Wate) Reserved GUAD ENABLE, (Vatatienen-votatle vintabley STATUS REGISTER Lod (Valatie!Nen- late Witatle) Figure 4 Status Reaistor2 7.1.2 Erase/Program Suspend Status (SUS) - Status Only “The Suspend Status bit is a read only bitin the status register (S16) that is set to 1 after executing a Erase!Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume (7An) instruction as well as @ power-down, power-up cycle 7.1.3 Security Register Lock Bits (LB3, LB2, LB1) - Volatile/Non-Volatile OTP Writable The Security Register Look Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status Register (S13, $12, S11) that provide the write protect control and status to the Security Registers. The default state of LB3-1 is 0, Security Registers are unlocked. LB3-1 can be set to 1 individually using the Write Status Register instruction. LB3-1 are One Time Programmable (OTP), once it's set to 1, the corresponding 256-Byte Security Register will become read-only permanently 7.1.4 Quad Enable (QE) - Volatile/Non-Volatile Writable The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that enables Quad SPI operation. When the QE bit s set to @ 0 state (factory default for part numbers with ordering options “IM” & “JM"), the JHOLD are enabled, the device operates in Standard/Dual SPI modes. When the QE bitis set to @ 1 (factory fixed default for part numbers with ordering options “IQ & “JQ"), the Quad 102 and 103 pins are enabled, and /HOLD function is disabled, the device operates in Standard/Dua/Quad SPI modes. Note: QE bit is set to a 0 state, factory default for part numbers with ordering options “IM” or "JM"; please see W25Q128JV-DTR data sheet Publication Release Date: March 27, 2018 216+ Revision FW25Q128IV am Winbond saa 823 S22 S2 SO si9 Sie si? sie Leld=delel=[°[e] Reserved Output Daver strangtn (volatieiNon-Volatile Witabie) Reserved \Wete Protect Selection (volatieNon-Volatile Writable) Reserved Reserved Figure 4. Status Registers 7.1.5 Write Protect Selection (WPS) - Volatile/Non-Volatile Writable ‘The WPS bit is used to select which Write Protect scheme should be used. When WPS=0, the device will use the combination of CMP, SEC, TB, BP{2:0] bits to protect a specific area of the memory array. When WPS=1, the device will utilize the Individual Block Locks to protect any individual sector or blocks. The default value for all Individual Block Lock bits is 1 upon device power on or after reset. 7.1.6 Output Driver Strength (DRV1, DRVO) — Volatile/Non-Volatile Writable The DRV1 & DRVO bits are used to determine the output driver strength for the Read operations. DRV1, DRVO Driver Strength 0,0 100% 0.4 75% 1,0 50% 1A 25% (default) 7.1.7 Reserved Bits ~ Non Functional ‘There are a few reserved Status Register bits that may be read out as a “0 or “1”. It is recommended to ignore the values of those bits. During a “Write Status Register” instruction, the Reserved Bits can be ‘written as “0°, but there will not be any effects,Tl Winbond W25Q128JV am 71.8 W25Q128JV Status Register Memory Protection (WPS = 0, CMP = 0) STATUS REGISTER W25Q126JV (128M-BIT) MEMORY PROTECTION® sec | 13 | rer /ero| "Etockis) | ADDRESSES | DENSITY. | PORTION” x |x|ofolfo NONE NONE NONE NONE o {of o | o | 1 | 262thu25s | Fcoo0oh—FFFFFFn | 256KB Upper 1/64) o |o | o | 1 | o | 2sethu2ss | Feoo00h—FFFFFFh | 512KB Upper 1/32 o |o|o | 1 | 1 | 2s0thu2ss | Fooo00n-FFFFFFh 1MB Upper 1/16 o |o| + | 0 | o | 224thu2ss | €00000n - FFFFFFh 2MB Upper 1/8 o |o| + | o | 1 | te2tu25s | coooooh—FFFFFFh | 4MB Upper 1/4 o | of] 1 | 1 | 0 | 128thru25s | 800000n - FFFFFFh eMB Upper 1/2 ofifoj]ol]i4 Othru3 | 000000h—O3FFFFh | 256KB Lower 1/64) of[t[o[1]o Othru7 | 000000h—O7FFFFh | 512KB Lower 1/32 o [1 [o [1 [1 | othruts | c0000h- oFFFFFh 1MB Lower 1/16 o [1 {1 [0 | 0 | otmust | cocc00n-iFFFFFh 2MB Lower 1/8 o {1+ {+ [| 0 | 14 | othru6s | c00000n - 3FFFFFh 4MB Lower 1/4 o [1 { 4/1 | 0 | othwt27 | c00000n-7FFFFFh MB Lower 1/2 x |x] 1] 4 [4 [| otness | oo0000n—FFFFFFn | 16M ALL 1]Jolojolft 255 FFFOOOh — FFFFFFh 4KB U- 114096 1;olofifo 255 FFEO0Oh - FFFFFFh KB U- 12048 1folol1 [1 255 FFCOOOh-FFFFFFh | 16KB U-1/1024 1/ofl1]ol[x 255 FF8000h—FFFFFFh | 32KB U- 11512 1]1fojfoft 0 (000000h - OOOFFFh 4KB L- 1/4096 1f1fofafo a (000000h = OO1FFFh KB L- 1/2048 + f1fofa [1 0 (000000h ~ 003FFFh 16KB, L- 1/1024 1/1[1]o[x 0 (000000h — OO7FFFh 32KB L512 3. If any Erase or Program command specitias a memory region that contains protected data portion, this, command will be ignored. Publication Release Date: March 27, 2018 Revision FTl Winbond W25Q128JV am 71.9 W25Q128JV Status Register Memory Protection (WPS = 0, CMP = 1) STATUS REGISTER W25Q126JV (128M-BIT) MEMORY PROTECTION® sec | 13 | rer /ero| "Etockis) | ADDRESSES | DENSITY. | PORTION” x |x] o | 0 | 0 [ othmass | 000000h-FFFFFFh 168 ALL o {of o | o | 1 | otw2s1 | c00000n-FaFFFFn | 16,128KB | Lower 63/64 o |o|o | 1 | o | ottu247 | coov0ch-FrFFFFH | 15.872KB | Lower 31/32 o [of o| 7 | 1 | otww230 | o00000h-EFFFFFA | 15MB Lower 15/16 o |o| + | 0 | o | ottu223 | cooc00n-DFFFFFn | 14MB Lower 7/8 o {of + | o | 1 | otwie1 | c00000h- BFFFFFh 12MB Lower 5/4 o |of + | 1 | 0 | otu127 | o00000h- 7FFFFFh MB Lower 1/2 0 [1]o] 0 | 1 | 4tru2ss | os0c00h-FFFFFFh | 16,128KB | Upper 63/64 o | 1{o | 1 | o | stww255 | os0coon-FFFFFFh | 15,872KB | Upper 31/32 o [4 [0 | 1 | 1 | tethr255 | 100000h - FFFFFFh 19MB Upper 15/16 o | 1 {1 | 0 | o | sathu2ss | 200000h- FFFFFFh 14MB Upper 7/8 o | 4 {+ | 0 | 1 | @4thru255 | 400000h - FFFFFFh 12MB Upper 3/4 o | 1 { + | 1 | 0 | 126thu255 | s00000h - FFFFFFh MB Upper 1/2 x[xirfa [a NONE NONE NONE NONE 1 | 0] 0 | 0 | 1 | otnuass | oo00con-FrerFFn | 16,300KB | L- 4095/4096 1 | 0] 0 | 1 [| 0 | otnuass | cooo00n-FroFrFn | 16,376KB | L- 2047/2048 1 | 0] 0 | 1 [ 1 | othu2ss | oooocch—FrerFFn | 16,368KB | L- 1023/1024 + | 0] 1 | 0 | x | othwass | oo000oh—Fe7FFFh | 16,352KB | L-511/512 1] 1] 0 | 0 [| 1 [| othuass | oot000n—Frrrrrn | 16,360KB | U- 4095/4096 1 [1] 0 | 4 [0 | otnuass | oo2000n—Frrrrrn | 16,376KB | U- 2047/2048, 1 [1] 0 | 4 [1 | othru2ss | oos000h—FrFFFFH | 16,368KB | U-1023/1024 + [41] 4 [0 | x | othu2ss | ooso0cn—FrFFFFn | 16,252KB | U-511/512 3. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored 19+W25Q128JV aa Winbond sam 10 W25Q128JV Individual Block Memory Protection (WPS=1) yector 15 (KB) + 8s Secor 1G) a ee i =~ Sear TRB = Individual Block Looks: Sector 0 GKE) | ‘32 Sectors (Top/Bottom) 54 Botte Block 254 (64KB) + Individual Block Lock: So's atros leva! lock Uno So's Arse — (rear Bick Lock Son ncarese Block + (64K) att ck on n SST TRS St ot uns os Secorie ake} = Be i ee ‘Secior 114KB) <<) Seo VJ Figure 44 Individual Bloc Sector Locks Notes: 1. Indviduel Block/Sector protection is ony valid when WPS=1 2. All individual block sector lock bits are set to 1 by default ater power up, all memory aay is protected Publication Release Date: March 27, 2018 Revision FW25Q128IV aae Winbond sam 8. INSTRUCTIONS ‘The Standard/Dual/Quad SPI instruction set of the W25Q128JV consists of 47 basic instructions that are fully controlled through the SPI bus (see Instruction Set Table1-2). Instructions are initiated with the falling edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (don't care), and in some cases, a combination. Instructions are completed with the rising edge of edge CS. Clock relative timing diagrams for each instruction are included in Figures 5 through 57. All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or Erase must complete on a byte boundary (/CS driven high after a Tull 8-bits have been clocked) otherwise the instruction will be ignored. This feature further protects the device from inadvertent ‘writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register will be ignored until the program or erase cycle has completed. 8.1 Device ID and Instruction Set Tables 1 Manufacturer and Device Identification MANUFACTURER ID (ME7 - MFO) Winbond Serial Flash Fh Device ID (107 - 1D0) (ID15 - ID) Instruction ABh, 90h, 92h, 94h 9Fh W250128JV-IQJQ 17h 4018h W250128JV-IM"JM* 17h 7018h Note: For DTR, QP! supporting, please refer to W26Q128JV DTR datasheet,W25Q128JV aa Winbond saga 8.1.2 _ Instruction Set Table 1 (Standard SPI Instructions)" Data input Output Bet | Byer ene Bred Bye 6 Bye 6 ene Number of Clock 2 2 2 2 2 2 2 wt Enable 8h [vote SR wie Enable oh Wee Disbie on Release Pover doom ‘Abn | Dury Dany Dummy | _(OrsDoF Manu eDevoe 1D son | bumny | oun ooh wero) | ors00) | SEDEC 0 sen | werner) | vorsi08 | (O70) ead niga O een | ounmy [dummy | ounmy [Cum | (0850) ess Daa won| Amare | _AISAR ATA (27-00) Fast Rend oan | Azan | AISAE aT-A0 Dm oro) Page Provan oon | azeare | AIBA ATA 07-00 oro Sear crass KE) aon | Azar | _ANAR ATA Blok Erase (32K) son | soars | ais.aa ATA Block race (4K) oan | azsané | atsa8 ATA Chip Erase C760 Read Status Repsieny oon | Sram Were Sts Regster 1% ein | isrsoye Res Stats Regier? asn_|(si5-s97" Wte Stats Regster.2 ‘sih_| 1558) end Stas Rosier 3 on | 823810 we Sas Rests ain | 23516) end SFOP Register oy 0 ny AAD Danny | (07-00) Erase Secuiy Reise? aan | poate | ais.aa AT-A0 Program Secuny Regist | aan | aasare | AIS-AS ATA 7-00 oro Rens Sesrty Register won| azar | aise aT-A0 Dm (7-00) (bal Bock Lock Ten ‘cel Bor Unie ‘8h Res Block Lock aon | Azoate | ATEAS aA 49) Indl Black Lack ‘seh | azaare | asa 7.0 India! Block Unlock aon Azeare | ANA ATA Erase / Progra Suse Tah Erase / Progra Resue Ta Powe doun eh Enable Reset eh Reset Device eh Publication Release Date: March 27, 2018 Revision FW25Q1285V aae Winbond saga 8.1.3 _ Instruction Set Table 2 (Dual/Quad SPI Instructions) ata Input Output Byet | Gye? | SyeS [Syed | Byes | Bye6 | Gye? | Byee | Byes lumber ofclecksz 3 = 3 - < 2 2 < fFestReed Oval Oupa | 36m _| AzaTe | ArsaH | Ara | Ounmy | Dummy | OFOO amber of Clock @ 2 @ 4 - @ 4 = = Fast Read Dual vO Ban | amare | aisasm | arage | Donme™ | roam jieDevee DOI | ean _| azaror | areas | 09 | oummy | wrrMrD | (OTAOF Nomber of Clocks | _@ @ @ 2 2 2 z 2 2 [Road wet Pape Program| sah | sare | avsan | rao | room | @room FasResdaus oven | en | AzAto | Aas | ArAD_| unm | Dun | Sumy | Donmy | @TOO™ Nomberorciem—s [8 2 = = 2 z z z 2 ee eM dc ed Fast Read Gund eon _| wears | meas | Arad | ome” | oom | ome | Oro se austin Wap Tih | um | oumy | cure | wowo Notes: 1 2 3, 10. 14 Data bytes are shifted with Most Significant Bit frst. Byte felds with data in parenthesis “()" indicate data output from the device on either 1, 2 or 410 pins. ‘The Status Register contents and Device ID will repeat continuously until /CS terminates the instruction, At least one byte of data input is required for Page Program, Quad Page Program and Program Security Registers, up to 256 bytes of data input. If more than 266 bytes of data are sont to the device, the ‘addressing will wrap to the beginning of the page and overurite previously sent data ‘Write Status Register-1 (0th) can also be used to program Status Register-182, see section 8.2.5. Security Register Address: ‘Security Register 1: A2316 = 00h; A1S-8= 10h; AT-O= byte address Security Register2: A23-16 = 00h; A16-8= 20h; A7-0= byte address Security Register 3: 23.16 = 00h; 16-8 = 30h; A7-0= byte address Dual SPI address input format 22, A20, A18, A16, A14, A12, A10, AB AB, A4, A2, AD, M6, M4, M2, MO 101 = A23, A21, A19, A17, A16, A13, A11, AQ AT. AS. A, At, M7, M5. M3, Mt Dual SPI data output format (06, D4, D2, DO) (07, DS, D3, D1) Quad SPI address input format: ‘Set Burst with Wrap input format: 10D =x % % % WA, IO1=x xxx x x WS, x 1O2=x, xx x x, x, W8, x 103 = A23, A19, A15, A11, A7,A3, M7, M3 HOB=x xxx KKK x Quad SPI data inputloutput format: 100= (04, 00, ..) 101 = (05,01...) (x, X, x, X, D4, DO, D4, DO) {3 x 0% D8, BY, DS Ds) 102 = (& x x x, D8, D2, D8, D2) fe a,x, BY. B3) Tho frst dummy is M7-M0 should be set to FhW25Q128JV aae Winbond saga 8.2 Instruction Descriptions 8.2.1 Write Enable (06h) The Write Enable instruction (Figure 5) sets the Write Enable Latch (WEL) bit in the Status Register to @ 1. The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register and Erase/Program Security Registers instruction. The Write Enable instruction is entered by driving /CS low, shifting the instruction code "08h" into the Data Input (Dl) pin on the rising edge of CLK, and than driving /CS high, Do. High impedance Figure 5. Wito Enable Instruction for SPI Mode 8.2.2 Write Enable for Volatile Status Register (50h) The non-volatile Status Register bits described in section 7.1 can also be written to as volatile bits. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non- volatile bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile Status Register (50h) instruction must be issued prior to a Write Status Register (Oth) instruction. Write Enable for Volatile Status Register instruction (Figure 6) will not set the Write Enable Latch (WEL) bit, it is only valid for the Write Status Register instruction to change the volatile Status Register bt values f—— ntacion 05) ——of 8) XN NS \ rH 20 ‘on mpssones oy Figure 6 Write Enable for Vola Status ReaisterInsiruction for SPI Mode Publication Release Date: March 27, 2018 Revision FW25Q128IV aa Winbond sam 8.2.3 Write Disable (04h) The Write Disable instruction (Figure 7) resets the Write Enable Latch (WEL) bit in the Status Register to 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “O4h’ into the I pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status Register, Erase/Program Security Registers, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase and Reset instructions. Ps Instruction (4m) + o (ey XN _ LX bo High mpedenee Figure 7. White Disable instruction for SPI Mode 8.2.4 Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h) The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered by driving /CS low and shifting the instruction code “OSh" for Status Register-1, "35h" for Status Rogister-2 or "15h" for Status Register-3 into the DI pin on the rising edge of CLK. The status register bits are then shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure 8, Refer to section 7.1 for Status Register descriptions. ‘The Read Status Register instruction may be used at any time, even while a Program, Erase or Write Status Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. The Status Register can be read continuously, as shown in Figure 8. The instruction is completed by driving CS high. J Insiucionosnsnsny —x! On - co signinpesnee YS Reiter ou Stas Regete2Bout ee 10), DOSSOOOGOOGSGOGOOS a Figure 8a. Read Status Regstr instuctionW25Q128JV aae Winbond saam 8.25 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h) The Write Status Register instruction allows the Status Registers to be written. The writable Status Register bits include: SEC, TB, BP2:0] in Status Register-1; CMP, LB(S:1], QE, SRL in Status Register-2: DRV1, DRVO, WPS in Status Register-3. All other Status Register bit locations are read-only and will not be affected by the Write Status Register instruction. LB[3:1] are non-volatile OTP bits, once it is set to 4, it cannot be cleared to 0. To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have been executed for the device to accept the Write Status Register instruction (Status Register bit WEL must equal 1). Once write enabled, the instruction is entered by driving /CS low, sending the instruction code "O1hv3th/11h’, and then vmiting the status register data byte as illustrated in Figure 9a. To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must have been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0) However, SRL and LB|3:1] cannot be changed from “1” to “0” because of the OTP protection for these bits. Upon power off or the execution of a Software/Hardware Reset, the volatile Status Register bit values will be lost, and the non-volatile Status Register bit values wil be restored, During non-volatile Status Register write operation (08h combined with O1h/Sth/11h), after /CS is driven high, the self-timed Write Status Register cycle will commence for a time duration of tw (See AC Characteristics). While the Write Status Register cycle is in progress, the Read Status Register instruction may stil be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and a 0 when the cycle is finished and ready to accept other instructions again. After the Write Status Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0. During volatile Status Register write operation (50h combined with 01h/31h/11h), after /CS is driven high, the Status Register bits will be refreshed to the new values within the time period of tsHs.2 (See AC Characteristics). BUSY bit will remain 0 during the Status Register bt refresh period, Refer to section 7.1 for Status Register descriptions. a ar oy oy XX XEXEXOXEXEXIXOX X bo High impedance (Wow usa Figure 9a, Waite Status Register-112° Instucton Publication Release Date: March 27, 2018 Revision FW25Q128IV aan Winbond sam The W25Q128JV is also backward compatible to Winbond's previous generations of serial flash memories, in which the Status Register-182 can be written using a single “Write Status Register-1 (01h) command. To complete the Write Status Register-182 instruction, the /CS pin must be driven high after the sixteenth bit of data that is clocked in es shown in Figure 9b. If /CS Is driven high after the eighth clock, the Write Status Register-t (01h) instruction will only program the Status Register-1, the Status Register-2 will net be affected (Previous generations will clear CMP and QE bits). J tnstucton 1m) ——ele— sas regster1in ela Staus Repster2m ey XN XXX XXX KX DOD OXOODEXK bo Hon mpesance (0 oe Figure 9b. Write Status Register-1/2 InstructionW25Q128JV aae Winbond sam 8.2.6 Read Data (03h) The Read Data instruction allows one or more data bytes to be sequentially read from the memory, The instruction is initiated by driving the /CS pin low and then shifting the instruction code “O3h” followed by a 24-bit address (A23-A0) into the DI pin, The code and address bits are latched on the rising edge of the CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically incremented to the next higher address after each byte of data is shifted out allowing for @ continuous stream of data. This means that the entire memory can be accessed with a single instruction as long as the clock continues. The instruction is completed by driving /CS high. The Read Data instruction sequence is shown in Figure 14, If a Read Data instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle. The Read Data instruction allows clock rates from D.C. to a maximum of fF (see AC Electrical Characteristics). The Read Data (03h) instruction is only supported in Standard SPI mode, FP stucton 02%) ——ele— 248taaess ——ef « NOD OOOOH XX gn ipntance - 3 —aaan OXXXOXOXDOXL Figure 14. Read Data Instruction Publication Release Date: March 27, 2018 228+ Revision FW25Q128IV aae Winbond sam 8.2.7 Fast Read (OBh) The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight ‘dummy’ clocks after the 24-bit address as shown in Figure 16. The dummy clocks allow the devices internal circuits additional time for setting up the initial address. During the dummy clocks the data value on the DO pin is a “don't care” Jp nstucton 08) ele 2B Adress a 10) —& QE . cs _ uk r - 8 D—$ x XE 8. = (10) KEKE KEE OK XE E XE XOX Figure 16a, Fast Read instruction +29.W25Q128JV aae Winbond sam 8.2.8 Fast Read Dual Output (3Bh) The Fast Read Dual Output (38h) instruction is similar to the standard Fast Read (OBh) instruction except that data is output on two pins; IQp and IO. This allows data to be transferred at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for quickly downloading code from Flash to RAM upon power-up or for applications that cache code-segments to RAM for execution. Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight ‘dummy’ clocks after the 24-bit address as shown in Figure 18. The dummy clocks allow the device's internal circuits additional time for setting up the initial address. The input data during the dummy clocks is “don't care’. However, the IQo pin should be high-impedance prior to the falling edge of the first data out clock. too eH ar Insucten (6h) eat aves o 0) OOe, oo gh noetance 0) res ux f f bunny eas, ——e | utc a: 110, 8 GOCOCOC000000000. ws y bo. High impedence 0) OK EX XOXO EX DOK OK DOK OX OEXD OX A 0 Oa SE Data 02 2 a® Data Out es Data Ode Figure 18 Fast Read Duel ua Instruction Publication Release Date: March 27, 2018 230+ Revision FW25Q128IV aae Winbond saga 8.2.9 Fast Read Quad Output (6Bh) The Fast Read Quad Output (68h) instruction is similar to the Fast Read Dual Output (38h) instruction except that data is output on four pins, IQ, IOs, !Q2, and 1s. The Quad Enable (QE) bit in Status Register-2 must be set to 1 before the device will accept the Fast Read Quad Output Instruction. The Fast Read Quad Output Instruction allows data to be transferred at four times the rate of standard SPI devices. The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight ‘dummy’ clocks after the 24-bit address as shown in Figure 20. The dummy clocks allow the device's intemal circuits additional time for setting up the initial address. The input data during the dummy clocks is “don't care”. However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. Instruction (66) 26 Adie 10, mY ND 08-000. High impeanca” High impedance High impodanco + =us8 ck 10, satches rom Inpato Ououe High impedence High impedance High Impedance 10, - XX OXEXDOKOXEX Bytet | Byte2 | Byte3 | Bytes Figure 20, Fast Read Quad Output Instruction 231W25Q128JV wae Winbond saga 8.2.10 Fast Read Dual |/O (BBh) The Fast Read Dual /O (BBh) instruction allows for improved random access while maintaining two IO pins, 1p and IO. Itis similar to the Fast Read Dual Output (38) instruction but with the capability to input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code execution (XIP) directly from the Dual SPI in some applications, oN CuK Mode dt ue 2x7 POOOO@DODOOOOODOO (©) OX XOX XOXO OX EXD (BR BRUMSHHDDHEET BD Tossaten Fon me | — Into Ou 2) LIXXDOOOOOOODOOQOODOOE, y 00 . (0) 2 DRX OX DOK OXDXOKXEX XX OKO Figure 22a, Fast Read Dual 0 Instruction (M7 40 shouldbe set to Fx) Publication Release Date: March 27, 2018 Revision FW25Q128IV aa Winbond sam 8.2.11 Fast Read Quad /O (EBh) ‘The Fast Read Quad VO (EBh) instruction is similar to the Fast Read Dual /O (BBh) instruction except that address and data bits are input and output through four pins 1Os, IOs, !Oz and IOs and four Dummy clocks are required in SPI mode prior to the data output. The Quad 1/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bt (QE) of Status Register-2 must be set to enable the Fast Read Quad VO Instruction es XT DBOOOOOO? OOOO bie Bie? Bie PITttdd Figure 24a, Fast Read Quad 1/0 Instuction (M7-MO should be set to Fx)W25Q128JV aa Winbond sam Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around" in Standard SPI mode The Fast Read Quad /O instruction can also be used to access a specific portion within a page by issuing a “Set Burst with Wrap" (77h) command prior to EBh. The “Set Burst with Wrap” (77h) command can either enable or disable the “Wrap Around” feature for the following EBh commands. When ‘Wrap ‘Around’ is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until (CS is pulled high to terminate the commend. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fil the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. ‘The “Set Burst with Wrap" instruction allows three “Wrap Bits’, W6-4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section within a page. Refer to section 8.2.37 for detail descriptions. Publication Release Date: March 27, 2018 w34e Revision FW25Q128IV aae Winbond saga 8.2.12 Set Burst with Wrap (77h) In Standard SPI mode, the Set Burst with Wrap (77h) instruction is used in conjunction with “Fast Read Quad 1/0” instruction to access a fixed length of 8/16/32/64-byte section within a 256-byte page. Certain applications can benefit from this feature and improve the overall system code execution performance, Similar to @ Quad 1/0 instruction, the Set Burst with Wrap instruction is initiated by driving the JCS pin low and then shifting the instruction code "77h" followed by 24 dummy bits and 8 “Wrap Bits’, W7-0. The instruction sequence is shown in Figure 28. Wrap bit W7 and the lower nibble W3-0 are not used. Wo, ws waeo (Wa =1 (DEFAULT) . Wrap Around | WrapLength | Wrap Around | Wrap Length 00 Yes e-byte No. NA o4 Yes iebyie No. NAY 10 Yes No. NA. 7 Yes No. NA. Once Wé-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad 1/0” instruction will use the W6-4 setting to access the 816/32/64-byte section within any page. To exit the ‘Wrap Around” function and return to normal read operation, another Set Burst with Wrap instruction should be issued to set W4 = 1, The default value of W4 upon power on or after a software/hardware reset is 1 Te tacion as 2 TN SOSOSODO 10, . Figure 28, Sot Bust with Wrap Instucton 235+W25Q128JV aa Winbond sam 8.2.13 Page Program (02h) The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “02h” followed by a 24-bit address (A23-A0) and at least one data byte, into the DI pin. The /CS pin must be held low for the entire lenath of the instruction ‘while data is being sent to the devices, The Page Program instruction sequence is shown in Figure 29. Ian entice 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) should be set to 0. I the last address byte is not zero, and the number of clocks exceeds the remaining page length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (@ Partial page) can be programmed without having any effect on other bytes within the same page. One condition to perform a partial page program is that the number of clocks cannot exceed the remaining page length. if more then 256 bytes are sent to the device the addressing will wrep to the beginning of the page and overwrite previously sent data. ‘As with the write and erase instructions, the /CS pin must be driven high after the eighth bit ofthe last byte has been latched. I this is not done the Page Program instruction wil not be executed. After /CS is driven high, the self-timed Page Program instruction will commence for a time duration of tpp (See AC Chatacteristics). While the Page Program cycle is in progress, the Read Status Register instruction may sill be accessed for checking the status of the BUSY bit. The BUSY bit is @ 1 during the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BPO) bits or the Individual Block/Sector Locks. Istucon ©2h) —ela——_ 20 ess asi 1 ct | Pee ae ere2 oe oar ayte9 kB aia e256 + tea DOOOOOSOOOOOOOOOO DCODOQOOOE Figure 29a, Page Program Instruction Publication Release Date: March 27, 2018 236+ Revision FW25Q128IV aan Winbond saga 8.2.14 Quad Input Page Program (32h) The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously erased (FFh) memory locations using four pins: IOs, 10+, |Oz, and 1s. The Quad Page Program can improve performance for PROM Programmer and applications that have slow clock speeds <5MHz. Systems with faster clock speed will not realize much benefit for the Quad Page Program instruction since the inherent page program time is much greater than the time it take to clock-in the data. To use Quad Page Program the Quad Enable (QE) bit in Status Register-2 must be set to 1. A Write Enable insiruction must be executed before the device will accept the Quad Page Program instruction (Status Register-1, WEL=1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “32h" followed by a 24-bit address (A23-A0) and at least one data byte, into the 10 pins. The (CS pin must be hela low for the entire length of the instruction while data is being sent to the device, All other functions of Quad Page Program are identical to standard Page Program. The Quad Page Program instruction sequence is shown in Figure 30. rescten 2m) et nase %, SOE) 00--000€ : 16, 1, 1, —___ suse 22 aus oo cuK Byte | Bye | Byte | Byte Byte 1 | Byle2 | Byte 3 Suc) Sue | Bae | Bye XXDOOOO— OOOO OCKEX Figute 30. Quad Input Page Program instructionW25Q128JV wae Winbond sam 8.2.15 Sector Erase (20h) The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and! shifting the instruction code "20h" followed a 24-bit sector address (A23-A0). The Sector Erase instruction sequence is shown in Figure 31a, ‘The /CS pin must be driven high after the eighth bit ofthe last byte has been latched. If this is not done the Sector Erase instruction will not be executed. After /CS is driven high, the self-imed Sector Erase instruction will commence for a time duration of tS (See AC Characteristics). While the Sector Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bil. The BUSY bit is a 1 during the Sector Erase cycle and becomes @ 0 when the cycle is finished and the device is ready to accept other instructions again. After the Sector Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BPO) bits or the Individual Block/Sector Locks. CLK 7 Node Mose em AE ee OOK bo Hoh mpotance (0) Fas Figure 81a, Sector Erase instruction Publication Release Date: March 27, 2018 238+ Revision FW25Q128IV aan Winbond sam 8.2.16 32KB Block Erase (52h) The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of all 1s (Fh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “52h” followed a 24-bit block address (AZ3-A0). The Block Erase instruction sequence is shown in Figure 32a, ‘The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction will commence for a time duration of taE1 (See AC Characteristics). While the Block Erase cycle is in progress, the Read Status Register instruction may stil be accessed for checking the status of the BUSY bit. The BUSY bit is @ 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again, After the Block Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction wil not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BPO) bits or the Individual Block/Sector Locks. [+ Insinction 2m) ——wla— 246 Aces ef oy x top NS NS NS \ KO OOK bo High Impedance (a) Figure 22a, 32KB Block Erase Instruction 239+W25Q128JV aae Winbond sam 8.2.17 64KB Block Erase (D8h) ‘The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code "D8h” followed a 24-bit block address (A23-AQ). The Block Erase instruction sequence is shown in Figure 33a, ‘The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction will commence for @ time duration of t8 (See AC Characteristics). While the Block Erase cycle is in progress, the Read Status Register instruction may stil be accessed for checking the status of the BUSY bit. The BUSY bit is @ 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again, After the Block Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BPO) bits or the Individual Block/Sector Locks. wlea., D1 23 4 5 6 7 om mo oF . CLK "ede of Moda [a instrcton (06h) ———wla— 24 bt Access. —e! 1 x 0p) XT NS \___KEXEEXOEKK bo High impedance (oy) Figure 33a, G4KB Block Erase Insruction Publication Release Date: March 27, 2018 =40- Revision FW25Q128IV aan Winbond saga 8.2.18 Chip Erase (C7h / 60h) The Chip Erase instruction sets all memory within the device to the erased state of all 1s (Fh). A Write Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code "C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure 34. The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will commence for a time duration of ice (See AC Characteristics). While the Chip Erase cycle is in progress, the Read Status Register instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to accept other instructions again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed if any memory region is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BPO) bits or the Individual Block/Sector Locks. itu ervecn) —e| 0 High impedence Figure 34. Chip Erase Instruction Sequence Diagram aleW25Q128JV aan Winbond sam 8.2.19 Erase / Program Suspend (75h) The Erase/Program Suspend instruction *75h*, allows the system to interrupt a Sector or Block Erase operation or a Page Program operation and then read from or program/erase data to, any other sectors or blocks. The Erase/Program Suspend instruction sequence is shown in Figure 35a. ‘The Write Status Register instruction (01h) and Erase instructions (20h, 52h, DBh, C7h, 60h, 44h) are not allowed during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase operation. If written during the Chip Erase operation, the Erase Suspend instruction is ignored. The Write Status Register instruction (01h) and Program instructions (02h, 32h, 42h) are not allowed during Program ‘Suspend. Program Suspend is valid only during the Page Program or Quad Page Program operation, ‘The Erase/Program Suspend instruction °75h’ will be accepted by the device only if the SUS bit in the Status Register equals to 0 and the BUSY bit equals to 1 while a Sector or Block Erase or a Page Program operation is on-going. If the SUS bit equals to 1 or the BUSY bit equals to 0, the Suspend instruction will be ignored by the device. A maximum of time of “tsus” (See AC Characteristics) is required to suspend the erase or program operation. The BUSY bit in the Status Register will be cleared from 1 to 0 within “tsus" and the SUS bit in the Status Register will be set from 0 to 1 immediately after EraseiProgram Suspend. For a previously resumed Erase/Program operation, it is also required that the ‘Suspend instruction °75h’ is not issued earlier than a minimum of time of “tsus" following the preceding Resume instruction "7Ah" Unexpected power off during the Erase/Program suspend state will reset the device and release the suspend state, SUS bit in the Status Register will also reset to 0. The data within the page, sector or block that was being suspended may become corrupted. It is recommended for the user to implement system design techniques against the accidental power interruption and preserve data integrity during erase/program suspend state. bo High Impedance Accept insructions Figure 352, Erase/Program Suspend Instucton Publication Release Date: March 27, 2018 28+ Revision FW25Q128IV wae Winbond sam 8.2.20 Erase / Program Resume (7Ah) The Erase/Program Resume instruction “7Ah” must be written to resume the Sector or Block Erase operation or the Page Program operation after an Erase/Program Suspend. The Resume instruction “7Ah™ will be accepted by the device only if the SUS bit in the Status Register equals to 1 and the BUSY bit equals to 0. After issued the SUS bit will be cleared from 1 to 0 immediately, the BUSY bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase operation or the page will complete the program operation. If the SUS bit equals to 0 or the BUSY bit equals to 1, the Resume instruction “7Ah™ ‘will be ignored by the device. The Erase/Program Resume instruction sequence is shown in Figure 36a, Resume instruction is ignored if the previous Erase/Program Suspend operation was interrupted by Unexpected power off. It's also required that a subsequent Erase/Program Suspend instruction not to be issued within 2 minimum of time of *tsus" following a previous Resume instruction Resume pevousiy suspense Progiamar fase Figure 96a, Erase/Pragram Resume InstuctionW25Q128JV aa Winbond sam 8.2.21 Power-down (B9h) Although the standby current during normal operation is relatively low, standby current can be further reduced with the Power-down instruction. The lower power consumption makes the Power-down instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC Characteristics). ‘The instruction is initiated by driving the /CS pin low and shifting the instruction code “Bh” as shown in Figure 37a. ‘The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Power-down instruction will not be executed. After /CS is driven high, the power-down state will entered within the time duration of toP (See AC Characteristics). While in the power-down state only the Release Power-down / Device ID (ABh) instruction, which restores the device to normal operation, will be recognized. All other instructions are ignored. This includes the Read Status Register instruction, which is always available during normal operation. ignoring all but one instruction makes the Power Down state a useful condition for securing maximum write protection. The device always powers-up in the normal operation with the standby current of ICC ‘Stand-by current | Power-down current Figure 37@, Desp Power-down instucton Publication Release Date: March 27, 2018 248+ Revision FW25Q128IV aa Winbond saam 8.2.22 Release Powor-down / Device ID (ABh) The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to release the device from the power-down state, or obtain the devices electronic identification (ID) number. To release the device from the power-down state, the instruction is issued by driving the /CS pin low, shifting the instruction code "ABh” and driving /CS high as shown in Figure 38a. Release from power-down will take the time duration of tes: (See AC Characteristics) before the device will resume normal operation and other instructions are accepted. The /CS pin must remain high during the tRESt time duration, ‘When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by driving the /CS pin low and shifting the instruction code “ABh’ followed by 3-dummy bytes. The Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first. The Device ID value for the W250128JV is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction is completed by driving /CS high, When used to release the device from the power-down state and obtain the Device ID, the instruction is the same as previously described, and shown in Figure 380, except that after /CS is driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other instructions will be accepted. If the Release from Power-down / Device ID instruction is issued while an Erase, Program or Write cycle is in process (when BUSY equals 1) the instruction is ignored and will not have any effects on the current cycle. ‘Standby eutont Figure 38a, Release Power down Instruction “3 —\ F— con ch) ——oh— 30m Bie —af oe ® XE 8) err DODOOOOO Figure 386, Release Power dow / Device ID instruction 45W25Q128JV aa Winbond sam 8.2.23 Read Manufacturer / Device ID (90h) The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device ID instruction. The instruction is initiated by driving the JCS pin low and shifting the instruction code “20h” followed by a 24-bit address (A23-A0) of 000000h, After which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 39. The Device ID values for the W25Q128JV are listed in Manufacturer and Device Identification table. The instruction is completed by driving /CS high. Inston (0h) ‘cress (c0000h) —+| 1 . 9 aT __09--000€ : 00 Yagnweedance 109 wos «s / Li 2H eS STE SOND OS ax 1 ~ (0) XT ; bo (io) XEXEXEXXEXEXD |< Manufacturer 1D (EFh) ——ee#—— Device 1D) ———» Figure 39. Read Manufacturer / Devi ID Instruction Publication Release Date: March 27, 2018 246+ Revision FW25Q128IV aae Winbond saga 8.2.24 Read Manufacturer / Device ID Dual 1/0 (92h) The Read Manufacturer / Device ID Dual W/O instruction is an alternative to the Read Manufacturer / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 2x speed. The Read Manufacturer / Device ID Dual VO instruction is similar to the Fast Read Dual 1/0 instruction. ‘The instruction is inated by driving the /CS pin low and shifting the instruction code "82h" followed by a 24-bit address (A23-A0) of 000000h, but with the capability to input the Address bits two bits per clock. After which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out 2 bits per clock on the falling edge of CLK with most significant bits (MSB) first as shown in Figure 40. The Device ID values for the W25Q128JV are listed in Manufacturer and Device Identification table. The Manufacturer and Device IDs can be read continuously, altemating from one to the other. The instruction is completed by driving /CS high, cs ux “Thoaeo FH lestucton (22m) els — azi5 ele ats ele 474000) ee wD al oy ee ) XT KX XOXOXO OXOKK XXX OOKE 20 gn ingen . (0) OODX XO QXOOOOOOXDDEKE cs f— ou LPL ren XKXOOK XY OXKOOCKK DK KEXOKE y DOO OQODOOOOOOOODM DOK 20 @) Figure 40. Read Manufacturer Dovieo ID Dual 10 Instuction Note: “The “Continuous Read Mode” bits MIT-0) must beset to Fx to be compatible wth Fast Rest Dual VO instructionW25Q128JV aae Winbond saga 8.2.25 Read Manufacturer / Device ID Quad 1/0 (94h) The Read Manufacturer / Device ID Quad 1/0 instruction is an alternative to the Read Manufacturer / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 4x speed. The Read Manufacturer / Device ID Quad /O instruction is similar to the Fast Read Quad I/O instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code “@4h” followed by a four clock dummy cycles and then a 24-bit address (A23-A0) of 000000h, but with the capability to input the Address bits four bits per clock. After which, the Manufacturer ID for Winbond (EF) and the Device ID are shifted out four bits per clock on the falling edge of CLK with most significant bit (ISB) first as shown in Figure 41. The Device ID values for the W25Q128JV are listed in Manufacturer and Device Identification table. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving /CS high. ux mo Figure 41. Read Manufacturer / Device ID Quad VO Instruction Note: “Tho “Continuous Read Mode” bits MCT-0) must be set fo Fxh to be compatible wth Fast Read Quad W/O instruction, Publication Release Date: March 27, 2018 248+ Revision FW25Q128IV aan Winbond sam 8.2.26 Read Unique ID Number (4Bh) The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each W250128JV device. The ID number can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the /CS pin ow and shifting the instruction code "4Bh’ followed by a four bytes of dummy clocks. After which, the 64- bit ID is shifted out on the falling edge of CLK as shown in Figure 42. es \ To? eee Te SUH ORES STO ODAD OD, J rsiucton at) el ——ourmy are? le —— oumryave2, ——o| o venison cu f— ommayes ——o —— omy njen ——a so snus wise (=F seonunmie Sem turow | Figure 42. Read Uniguo ID Number instruction 495W25Q128JV aae Winbond saga 8.2.27 Read JEDEC ID (9Fh) For compatiblity reasons, the W25Q128JV provides several instructions to electronically determine the identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial memories that was adopted in 2003. The instruction is initiated by driving the /CS pin low and shifting the instruction code “SFh”. The JEDEC assigned Manufacturer ID byte for Winbond (EFn) and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 43a. For memory type and capacity values refer to Manufacturer and Device Identification table, 9). & XX XX XXX (0) == Menon Tipe 0168 onacty 107-0 to DOGOOOOGOOGOGOOS. Figure 438, Read JEDEG ID Instruction Publication Release Date: March 27, 2018 =50- Revision FW25Q128IV aan Winbond saga 8.2.28 Read SFDP Register (5Ah) The W25Q128JV features a 256-Byte Serial Flash Discoverable Parameter (SFDP) register that contains information about device configurations, available instructions and other features. The SFDP parameters are stored in one or more Parameter Identification (PID) tables. Currently only one PID table is specified, but more may be added in the future. The Read SFDP Reoister instruction is compatible with the SFDP standard initially established in 2010 for PC and other applications, as well as the JEDEC standard 4JESD216-serials that is published in 2011. Most Winbond SpiFlash Memories shipped after June 2011 (date code 1124 and beyond) support the SFOP feature as specified in the applicable datasheet. ‘The Read SFDP instruction is initiated by driving the /CS pin low and shifting the instruction code “SAh” followed by a 24-bit address (A23-A0)" into the DI pin. Eight "dummy" clocks are also required before the SFOP register contents are shifted out on the falling edge of the 40% CLK with most significant bit (MSB) first as shown in Figure 44. For SFDP register values and descriptions, please refer to the Winbond Application Note for SFDP Definition Table. Note 1: A23-A8 = 0; A7-AO are used to define the starting byte address for the 258-Byte SFOP Register Je nsructon Bt Ashes ——xl BVA) 200-0006 oo ion npeaares () ws. DRERHESTSO OOH SOMES TOOHRAS OES ck a+ - (0) - Deiat Dan? bo. High impedance “— 10) OX KEK XXX XO OKOXK XO OOK KOT Figure 44 Reed SFDP Register Instuction Sequence Diagram o5leW25Q128JV wae Winbond saga 8.2.29 Erase Security Registers (44h) The W25Q128JV offers three 256-byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array. ‘The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable instruction must be executed before the device will accept the Erase Security Register Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code "44h" followed by a 24-bit address (A23-A0) to erase one of the three security registers. ADDRESS 823-16 A15-12 ANt8 Ar-0 ‘Security Register #1 00h 0004 000 Don't Care ‘Security Register #2 ‘00h 0010 0000 Don't Care ‘Security Register #3 0h 0011 0000 Don't Care ‘The Erase Security Register instruction sequence is shown in Figure 45. The /CS pin must be driven high after the eighth bit ofthe last byte has been latched. If this is not done the instruction will not be executed. After JCS is driven high, the self-timed Erase Security Register operation will commence for a time duration of tse (See AC Characteristics). While the Erase Security Register cycle isin progress, the Read Status Register instruction may stil be accessed for checking the status of the BUSY bit. The BUSY bit is 2 1 during the erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Erase Security Register cycle has finished the Write Enable Latch (WEL) bitin the Status Register is cleared to 0. The Security Register Lock Bits (LB3-1) in the Status Register-2 can be used to OTP protect the security registers. Once @ lock bit is set to 1, the corresponding security register will be permanently locked, Erase Security Register instruction to that register will be ignored (Refer to section 7.1.8 for detail descriptions). ot 2 oe 5 9 we Nae CLK " odeo” Mod f+ instruction (44m) 248i Acres — x! (oy XN S\ J O- XXX X bo High Impedance (0) + =use Figure 45 Erase Security Registers Instruction Publication Release Date: March 27, 2018 252+ Revision FW25Q128IV aa Winbond saga 8.2.30 Program Security Registers (42h) ‘The Program Security Register instruction is similar to the Page Program instruction. It allows from one byte to 256 bytes of security register data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Program Security Register Instruction (Status Register bit WEL= 1), The instruction is initiated by driving the /CS pin low then shifting the instruction code "42h followed by a 24-bit address (A23-A0) and at least one data byte, into the DI pin. ‘The /CS pin must be held low for the entire length of the instruction while data is being sent to the device ADDRESS 23-16 15-12 ANt8 AT-0 ‘Security Register #1 ‘0h 0001 0000 | Byte Address ‘Security Register #2 00h 0010 0000 | Byte Address ‘Security Register #3 (00h 0011 0000 _| Byte Address ‘The Program Security Register instruction sequence is shown in Figure 48. The Security Register Lock Bits (LB3-1) in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding security register will be permanently locked, Program Security Register instruction to that register wil be ignored (See 7.1.9 for detail descriptions) fe — sven cen) 24.8 Aaoiess —— ole aia ate 1 + «ep —N QOO--DOOCOOOOOOOE SEEEESES W2eee oe eeoeennroons 8 2 SEE EE vee fp casa 0) DOODOOOCOOOOOOCOES- DOOOSOOK Datapje? elaine 256 +f Figure 46, Program Secunly Ragistars InstructionW25Q128JV aan Winbond saga 8.2.31 Read Security Registers (48h) ‘The Read Security Reaister instruction is similar to the Fast Read instruction and allows one or more data bytes to be sequentially read from one of the four security registers, The instruction is initiated by driving the /CS pin low and then shifting the instruction code “48h” followed by a 24-bit address (A23-A0) and eight “dummy” clocks into the DI pin. The code and address bits are latched on the rising edge of the CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The byte address is automatically incremented to the next byte address after each byte of data is shifted out. Once the byte address reaches the last byte of the register (byte address FFh), it will reset to address O0h, the first byte of the register, and continue to increment. The instruction is completed by driving /CS high. The Read Security Register instruction sequence is shown in Figure 47. If a Read Security Register instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will rot have any effects on the current cycle. The Read Security Register instruction allows clock rates from D.C, toa maximum of FR (see AC Electrical Characteristics). ADDRESS 23-16 Ats-12 ANt8 ATO ‘Security Register #1 ‘0h 0001 0000 | Byte Address ‘Security Register #2 00h 010 0000 | Byte Address ‘Security Register #3 ‘0h oon 0000 _| Byte Address Digg teeTesm wow a, Insucton (48) 2B Ades «e) ~OOOC! co. Hon inpesance (0) Figure 47. Read Socurty Registers Instruction| Publication Release Date: March 27, 2018 a Revision FW25Q128IV aa Winbond saam 8.2.32 Individual Block/Sector Lock (36h) The Individual Block’Sector Lock provides an alternative way to protect the memory array from adverse Erase/Program. In order to use the Individual Biock/Sector Locks, the WPS bit in Status Register-3 must be set to 1. If WPS=0, the write protection will be determined by the combination of CMP, SEC, TB, BP[2.0] bits in the Status Registers. The Individual Block/Sector Lock bits are volatile bits. The default values after device power up or after a Reset are 1, so the entire memory array is being protected. To lock a specific block or sector as illustrated in Figure 4, en Individual Block/Sector Lock command must be issued by driving /CS low, shifting the instruction code “36h” into the Data Input (Dl) pin on the rising edge of CLK, followed by a 24-bit address and then driving (CS high. A Write Enable instruction must be executed before the device will accept the Individual Block/Sector Lock Instruction (Status Register bit WEL 1), f+ nstueton(@6t) ——e}e— 2484Addrss —ef (by) SRN NSN KX -OOEKE High impedance vo (103 Figure 63a, Individual Block’Sectar Lock Instruction 2552W25Q128JV aan Winbond saga 8.2.33 Individual Block/Sector Unlock (39h) The Individual Block’Sector Lock provides an alternative way to protect the memory array from adverse Erase/Program. In order to use the Individual Block/Sector Locks, the WPS bit in Status Register-3 must be set to 1. If WPS=0, the write protection will be determined by the combination of CMP, SEC, TB, BP[2.0] bits in the Status Registers. The Individual Block/Sector Lock bits are volatile bits. The default values after device power up or after a Reset are 1, so the entire memory array is being protected. To unlock @ specific block or sector as illustrated in Figure 44, an Individual Block/Sector Unlock command must be issued by driving /CS low, shifting the instruction code “39h into the Data Input (DI) pin on the rising edge of CLK, followed by a 24.bit address and then driving /CS high. A Write Enable instruction must be executed before the device will accept the Individual Block/Sector Unlock Instruction (Status Register bit WEL= 1), J lnswueion (298) ——ele— 24-8 Addross —e[ b xX (09 ENN SY OX EL bo Hig inpedance (0) as Figure 54a, Individual Block Unlock Instruction Publication Release Date: March 27, 2018 256+ Revision FW25Q128IV aa Winbond saga 8.2.34 Read Block/Sector Lock (3Dh) The Individual Block’Sector Lock provides an alternative way to protect the memory array from adverse Erase/Program. In order to use the Individual Block/Sector Locks, the WPS bit in Status Register-3 must be set to 1. If WPS=0, the write protection will be determined by the combination of CMP, SEC, TB, BP[2.0] bits in the Status Registers. The Individual Block/Sector Lock bits are volatile bits. The default values after device power up or after a Reset are 1, so the entire memory array is being protected. To read out the lock bit value of a specific block or sector as illustrated in Figure 4d, 2 Read Block/Sector Lock command must be issued by driving /CS low, shifting the instruction code "3Dh’ into the Data Input (DI) pin on the rising edge of CLK, followed by a 24-bit address. The Block/Sector Lock bit value will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure 55. If the least significant bit (LSB) is 1, the corresponding block/sector is locked; if LSB=0, the corresponding biock/sector is unlocked, Erase/Program operation can be performed, estucton(30r) rasnaacress (® SOOO xx Lack Vout ——e 00 gu impecance Boy (1 OOOXOXOXOOOKT Figure 55a, Read Block Lock instructionW25Q128JV aa Winbond sam 8.2.35 Global Block/Sector Lock (7Eh) All Block/Sector Lock bits can be set to 1 by the Global Block/Sector Lock instruction. The command must be issued by driving /CS low, shifting the instruction code ‘7Eh” into the Data Input (D1) pin on the rising edge of CLK, and then driving JCS high. A Write Enable instruction must be executed before the device will accept the Global Block/Sector Lock Instruction (Status Register bit WEL= 1). bo gn impecance Figure 56. Global Block Lock Instruction for $PI Modo 8.2.36 Global Block/Sector Unlock (98h) All Block/Sector Lock bits can be set to 0 by the Global Block/Sector Unlock instruction. The command must be issued by driving /CS low, shifting the instruction code "98h" into the Data Input (D1) pin on the rising edge of CLK, and then driving /CS high. A Write Enable instruction must be executed before the device will accept the Global Block/Sector Unlock Instruction (Status Register bit WEL= 1), Figure 57. Global Block Uniock Instruction for SPI Mode Publication Release Date: March 27, 2018 258+ Revision FW25Q128IV aae Winbond saga 8.2.37 Enable Reset (66h) and Reset Device (99h) Because of the small package and the limitation on the number of pins, the W25Q128JV provide 2 software Reset instruction instead of a dedicated RESET pin. Once the Reset instruction is accepted, any ‘on-going internal operations will be terminated and the device will return to its default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch (WEL) status, Program/Erase Suspend status, Read parameter setting (P7-P0), and Wrap Bit setting (W6-W4).. “Enable Reset (66h)’ and “Reset (99h)' instructions can be issued in SPI. To avoid accidental reset, both instructions must be issued in sequence. Any other commands other than "Reset (99h)’ after the “Enable Reset (66h)’ command will disable the “Reset Enable” state. A new sequence of “Enable Reset (86h)" and “Reset (98h)" is needed to reset the device. Once the Reset command is accepted by the device, the device will take approximately t2ST=30us to reset. During this period, no command will be accepted. Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence. fe nsrcton 66m). ——of fe tnstacten (99m) ——of bo. High impedance @,) Figure 580. Enable Reset end Reset Instruction Sequence 592W25Q128JV aae Winbond sam 9. ELECTRICAL CHARACTERISTICS 9.1. Absolute Maximum Ratings PARAMETERS ‘SYMBOL | CONDITIONS RANGE UNIT ‘Supply Voltage vec 06 104.6 v Voltage Applied to Any Pin vio Relative to Ground | -0.6 to VOC+0.4 v <20n8 Transient Transient Voltage on any Pin | Viot Folttve Grama | ~20Vtovec+20v) Vv Storage Temperature Ts16 65 to +150 °C Lead Temperature TLEAD ‘See Note ® °C Electrostatic Discharge Voltage _| VSD Human Body Model® | -2000 to +2000 v Notes: 1. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability Exposure beyond absolute maximum ratings may cause permanent damage. 2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive on restrictions on hazardous substances (RoHS) 2002/95/EU. 3, JEDEC Sid JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms). 9.2 Operating Ranges SPEC PARAMETER SYMBOL | CONDITIONS —— UNIT MIN” | MAX Fas 133MHz,_ f= 50MH2 30 | 36 | V ‘Supply Voltage vec Fae 104MHz, f= 50MHz 27 | 30 | V Ambient Temperature, |p, | Industrial —4o [+5 | gd gd MILLIMETERS. INCHES, SYMBOL 7 Nom | Max Min ‘Nom Max a 070 075 080 028 | 0.030 ast Al 0.00 0.02 0.05 3.000 | 0.001 0.002 © 035 0.40 0.48 ao | 006 D019 - (0.20 Ref = - 0.008 Ret, = 730 8.00 a0 asi 035 0s18 D2 335 3.40 345, or | 0134 0.136 E 500 6.00 610 22 | 026 0.240 = 225 430 435 ner] 0.169 or 127 BSC 0.050 BSC, 045 050 055 01 | 0.020 0.022 0.00 0.05 0.000) = ‘.002 Note: ‘The metal pad area on the bottom center of the package is not connected fo any internal electrical signals. It can be left floating or connected to the device ground (GND pin). Avoid placement of exposad PCB vias under the pad. Publication Release Date: March 27, 2018 70+ Revision FW25Q128IV gees) Winbond saga 10.5 24-Ball TFBGA 8x6-mm (Package Code B, 5x5-1 ball array) [5 +e) Note Ball land: 045mm, Ball Opening: 0:35mm PCB bal land suggested <= 0.35mm ‘symbol ___ Millimeters : Inches Min Nom | Max Min | _Nom Max x = = 120) = = 0.047 ai 025 030 035 | oo | oor oor 2 = 085 - - 0.085 b 035 040 045 | o0r4 | 0016 oor8 o 7.90 800 310 | oat 0315 0310 ot Z00BSC (0157 BSC E 390 600 ei | om | 0230 0240 = 400886 0157 BSC SE 100 TYP. 0.039 TYP SD. 100 YP (0.098 1¥P @ 00886 (0039 BSC The