System Verilog: Coverage
System Verilog: Coverage
COVERAGE
Coverage
Types of Coverage's:
o Code Coverage.
o Functional Coverage.
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Functional Coverage
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covergroup
Syntax:
covergroup cg_name [(port_list)]
[coverage_event];
//coverage_specs;
endgroup [ : cg_name]
Example:
covergroup cg;
……
endgroup
cg cg1=new;
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Coverpoint
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Example
Syntax:
[label : ] coverpoint expression [ iff
(expression)]
[{
//bins specifications;
}] ;
Example:
covergroup cg;
coverpoint a iff (!reset);
endgroup
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bins
bins are buckets which are used to collect number of times a particular
value/transaction has occurred.
If bins construct is not used inside coverpoint then automatic bins are
created based on the variable type and size.
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Example1
cg cg1;
initial cg1=new;
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Example2
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Example3
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Example4
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Covergroup inside a class
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Example
class xyz;
bit [3:0] m_x;
int m_y;
bit m_z;
covergroup cov1 @ (m_z); //Embedded Covergroup
coverpoint m_x; //16 bins
coverpoint m_y; //2^32 bins
endgroup
function new(); cov1=new; endfunction
endclass
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Bins for Transition
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Specifying Transition
Sequence of Transitions
(value1=> value2 => value3=> value4)
Set of Transitions
(value1, value2 => value3, value4)
bit [4:1] a;
covergroup cg @ (posedge clk);
coverpoint a
{ bins sa [ ]= ( 4=>5=>6 ), ( [7:9],10=>11,12) ;
bins allother= default sequence;
}
endgroup
Sa will be associated with individual bins (4=>5=>6) ,
(7=>11), (7=>12), (8=>11), (8=>12), (9=>11), (9=>12),
(10=>11), (10=>12)
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Example2
Consecutive Repetition
bins sb={ 4 [*3] } ;
// (4=>4=>4)
bins sc [ ]={ 3 [*2:4] };
// (3=>3) , (3=>3=>3), (3=>3=>3=>3)
Non-Consecutive Repetition
bins sd [ ]={ 2 [->3] };
//2=>…. =>2 …. =>2
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Excluding bins
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Ignore Bins
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Illegal Bins
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Cross Coverage
Examples:
o Was write enable 1 when address was 4’b1101.
o Have we provide all possible combination of inputs to a Full
Adder.
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Example1
bit [3:0] a, b;
covergroup cg @ (posedge clk);
cross_cov: cross a , b;
endgroup
bit [31:0] a;
bit [3:0] b;
covergroup cg @ (posedge clk);
cova: coverpoint a { bins low [ ]={ [0:9] }; }
cross_cov: cross b, cova;
endgroup
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