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33 views10 pagesChapter 5 Processor Fundamentals
Uploaded by
Syed ShahCopyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
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/ 10
Processor Fundamentals
Learning objectives
By the end of this chapter you should be able to:
‘show understanding of the basic Von Neumann model
show understanding ofthe roles carried out by registers
show understanding ofthe roles carried out by the
Arithmetic and Logic Unit (ALU), Control Unit and system
clock
show understanding of how data are transferred between
various components ofthe computer system using the
address bus, data bus and control bus
show understanding of how the bus width and clock
speed are factors that contribute to the performance of
the computer system
show understanding ofthe need for ports
describe the stages ofthe fetch-execute cycle
show understanding of ‘register transfer’ notation
describe how interrupts are handled, ambridge Internation.
5.01 The Von Neumann model of aicomputer system
‘The simplest form of what might be described as a computer system model or computer
system architecture is usually attributed to John von Neumann. This recognises the fact that
he was the first to describe the basic principles in a publication.
The model has the following basic features:
+ There is a processor, a central processing unit.
+ The processor has direct access to. a memory.
‘+ The memory contains a ‘stored progam’ (which can be replaced by another at any time}
and the data required by the program.
‘+ The stored program consists of individual instructions.
‘+ The processor executes instructions sequentially.
5.02 Central processing unit (CPU) architecture
Modern processors are extremely complex; some
of the complexities will be discussed in Chapter
19 (Sections 19.02 and 19.03). In this chapter the
focus ison the fundamentals of the operation of
‘an up-to-date version of a simple von Neumann
computer system
Figure 5:01 givesa simplified schematic diagram
‘ofa processor that could be part ofthis simple
system. The dotted outiineshows the boundary.
‘of the processax, The logical arrangement of some.
of the processor components js indicated. The
arrows show possible directions of flow of data,
’As the following discussion will show, the data for
some of the arrowsis specifically an address or an
instruction. However, in general, data might be an
struction, an address ora value.
‘Components of the CPU
‘The two major components of the CPU are the
arithmetic and logic unit (ALU} (or Arithmetic
Logic Unit} and the controlunit. As its name
implies, the ALUis responsible for any arithmetic
‘or logic processing that might be needed when 2
program is running. The funetions of the control
Unit are more diverse. One aspect is controlling the flow of data throughout the processor
and, indeed, throughout the whole computer system. Another's ensuring that program
instructions are handled correctly. A vital part of the control units a clock which is used
by the unit to synchronise processes. Strictly speaking there are two clocks. The fist isan
internal clock which controls the cycles of activity within the processor. The otheris the
system clock which controls activities outside the processor, The CPU will have a defined
frequency forts clock eycle, which is usually referred to as the clock speed. The frequency
defines the minimum period of time that separates successive activities within the system,
Figure 5.01 A schematic diagram of the architecture of simple CPU erat
Extenslon question 5.01
nt for a laptop computer, the system is described as 4GB, 178, 1.76
in an advertisem
1. Which three cor
2 Have
e discuss
ponents are being referred to here?
min Chapter } (Section
logy
1e minirmum time period that co cessive activities on this
Registers,
The other components of the GPUare the registers. These are storage components which,
because of their proximity tothe ALU, allowery-short access timessEach register has limited
storage capacity, typically 16/32 or 64 bits. A register is either general purpose or special
purpose. Ifthere is only one general-purpose register itis referred to-as the accumulator.
For the rest of this discussion and for the discussion in Chapter 6, the assumption will be that
the processor does have just this one general-purpose register. The Accumulator used to
store a single value at any one time A values stored in the Accumulator that is to be used
by the ALU for the execution of an instruction. The ALU can then store different value in the
Accumulator after the execution of the instruction
Figure 5.01 shows some of the special: purpose registers as individual components. The box.
labelled ‘Other registecs’ can be considered to comprise the Accumulator plus the special-
purpose registers not identified individually, The full names of the special-purpose registers
included in the simple CPU which we are going to discuss are given in Table 01 with a brief
description of thei function,
Currentinstruction | cig ‘Stores the current instruction while itis being
egistey decoded and executed
lndex register ie Stores a value; only used for indexed addressing.
Memory address —_| a Stores the address of memory location which is
register about to have a value read from or written to,
‘emory data register
‘Stores data that has just been read from memory or
(memory buffer |MDR(MBR) | t about to be written to memory
register
Stores the address of where the next instruction is,
Pr PC
rogram counter rm \aieteanaa
Status register SRe Contains individual bits that are either set or cleared
Table 5.01 Registers in a simple CPU
‘Two points are worth making at this point, The firsts that the alternative name for the MDR
‘emphasises that this particular register mustact as a buffer because transfers of data within
the processor take place much more quickly than transfers outside the processor, This statement has to be slightly qualified because the transfer could be to or from cache memory
which would be a fast process butiitis otherwise generally applicable. The mention of cache
memory brings us to the second point which is that all discussion in this chapter and Chapter
6 ignores the fact that cache memory exists. All references are simply to memory as in
Table 5.01
further point to note hereis that the index register (I) can be abbreviated as IR but in some
sources the current instruction register (CIR) is abbreviated as IR’ which is an unnecessary
potential cause of confusion. n this book, the index register is always iXand the current
instruction registers CiRFinally, thereis also possible confusion ifthe abbreviation PC is
‘used. This will only be used in this book when register transfer notation is being used as you
will see later in the chapter. Everywhere else, a PC is a computer.
‘The SRis used when an instruction requiresarithmetic or logic processing: Each individual
bitin the SRoperates.asa flag, The bitis set to 1 if a condition s detected. As an example, the
use of the following three flags will be illustrated:
+ The carry flag, identified as C, is set to 1if there is a carry.
+ The negative flag, identified as Nyisset to 1ifa results negative
+ The overflow flag, identified as V, is setto 1 ifoverflowis detected
Usingthe status register duringan arithmeticoperation.
1. Consider the addition of two positive values where the sum ofthe two produces an
answer that is too large to be correctly identified with the limited number of bits used to
‘represent the values, For, example ifan eight bit binary integer representation is being,
used and an attempt is made to add denary 66 to denary 6athe following happens:
0100 0010
+ 01000100
Flags: N VC
1000 0110 o220
‘The value produced as an answer is denary—122+Two positive numbers have been
added to get a negative number. This impossibility is detected by the combination of
the negative flag and the overflow flag being set to-2. The processor has identified the
probiem and can therefore send out an appropriate message.
2 Consider using the same eight-bit binary integer representation but tis time two
negative numbers (-66 and -68 in denary) are added
20111110
+ 1011,1100
| Fagen ve
(yous s0%0 1
This time we get the answer +122. This impossibility is detected by the combination of
the negative flag not being set and both the overflow and the carry lag being set tox, Extension question 3.02
Carry out a comparable calculation for the a
proces
5.03 The'systemibus
Abus is @ parallel transmission component with each separate wire carrying asinglesit. It
is important not to describe a bus as a storage device, A bus does not hold data, Instead it
is amechanism for data to be transferred from one system
component to another,
in binary o'
carry bit
In the simple computer system described in this chapter
there will bea system bus that comprises three distinct
components: the address bus, the data bus and the control
‘bus, The schematic diagram of the CPU in Figure 5.01
shows the logical connection between each bus and a CPU
‘Component. The address busis connected to the MAR; the
data bus to the MOR and the control bus to the control unit,
i
|
The system bus allows data flow between the CPU, the | nf 1
L
"memory, and input or output VO} devices as shown in the
schematic diagram in Figure 5.02.
Figure 5.02 schematic dlagram of the system bus
The address bus
The sole function of the address bus is to carry an address. This addressis loadedon to the E
bus from the MAR as and when directed by the control unit, The address specifies a location,
inmemoty which is due to receive data or from which data isto be read. The address bus isa
‘one-way street: It can only be used to send an address to a memory controliez tcannotbe:
Used to carry an address from the memory controller back to the CPUs
‘The crucial aspect ofthe address bus isthe ‘bus width; whichis the number of separate wires,
in the bus. The number of wires defines the number of bitsin the address's binary code. In
the simple computer system considered here we will assume that the bus width is 16 bits
allowing 65 536 memory locations tp be directly addressed. Such a memory size would, of
course, be totally inadequate for a modern computer system. Even doubling the address bus
width to 32 bits would only allow the direct addressing of alittle over four billion addresses. IF
the memory sizes too large special techniques have to be used.
The data bus.
The function of the data buss to carrydata, This might be an instruction, an address ora
value. As can be seen from Figure 5.02, the data bus might be carrying the data from CPU to
‘memory orfrommemory to CPUs
However, another option isto carry data to orfrom an WO devicerThe diagram does not
make clear whether, forinstance, data coming from an input device is carried first to the CPU
or directly to the memory. There is a good reason for this. Some computer systems will only allow input to the CPU before the data can be stored in memory, Other systems will allow
direct transfer to memory.
Bus width is again an important factorin considering how the data bus is used. Before
discussing this, itis useful to introduce the concept of a word. A word consists ofa number
ofbytesand for any system the word lengthis defined. The significanceof the word lengths
that defines a grouping that the system will handle as one unit. The word length might be
stated asa number of bytes oras a number of bts: Typical word lengths are 16, 32 or 64 bits
that fs,2, 4 or 8 bytes respectively, For a given computer system, the bus width is ideally the
‘same as the word length: this is not possible the bus width can be half the word length so
that a fullword can be transmitted by two consecutive data transfers.for our simple system
we assume a data bus width of 16 bits and a word length of two bytes to match this.
ny
Extension question 5.03
Can you find out the bus widths used in the computer system you are using?
‘The control bus
The control bus is another bidirectional buswihich transmits a signal rom the control unit to
any other system component or transmits a signal to the control unit.;There is no need for
extended width so the control bus typically has just elght wireseAmajor use of the control
‘bus i to carry timing signals described in Section 5.02, the system clockiin the control
nit defines the clock cycle for the computer system. The control bus carries timing signals
at time intervals dictated by the clock cycle. This ensurestthat the time that one component
transmits data is synchronised with the time that another component reads its
‘The clockspeedis the most important factor governing the processingspeed.of thesystem,
Homever, itis not the only factor. The performance will be limited if the bus widths are
insufficienefor the whole of a data value to be transferred in one clock cycle. For optimum
performance itis also particularly important that memory access sas efficient as possible.
‘The schematic diagram in Figure 5.02 slightly misrepresents the situation because it looks 2s
ifthe CPU, the memory and the /0 devices have similar access to the data and control buses.
‘The reality is different, Each I/O device is connected to an interface called a port. Each port
is connected to the YO or device controller. This controller handles the interaction between
the CPU and an i/0 device: port is described as internal'ifthe connected I/O device is an
integral part of the computer system. An externabport allows the computer user to connect a
peripheral YO device
The universal serial bus (USB)
In the early days ofthe PC, the process of connecting a peripheral was time-consuming and
required technical expertise. The aim of the plug-and-play concept was to remove the need
for technical knowledge so that any computer user could connect a peripheral and start
using itstraight away. The plug-and-play concept was only fully realised by the creation of the
USB (Universat Serial Bus) standard. Nowadays anyone buying a new peripheral device will
expect it to connect to a USB port. There isan alternative technology known as FireWire but
this js not so commonly used in computer systems. Chapter 5: Processor Fundamentals
Us@— dSynchtenoss serps oh
cee Shretoleok Cable « 7D pouet oth fer rams
Some information zbout the USBstendard: pad SOD Nbot
¢ Ahierarchy of connections is supported.
«The computeris at the root of this hierarchy and can handle 127 attached devices.
* Devices can be attached while the computer is switched on and are automatically
