Logic Synthesis with Design Vision

授課教師：洪進華老師
jhhong@nuk.edu.tw
實習助教：陳龍風
lfchen@soc.ee.nuk.edu.tw

1
 What is synthesis

„ Synthesis = translation + optimazation +mapping

module mul(a,b,out); Translate no timing info
input [3:0]a,b; (HDL Compiler)
output [7:0]out;

assign out=a*b;

endmodule Optimization + Map

(Design Compiler)

timing info

2
Synopsys Design Flow

Specification

RTL Coding Prepare

Setting Design Environment

Setting Design Constraint

Compile Design

Analysis

Verilog Netlist 3
 執行步驟

一、進入工作站並鍵入環境設定檔
二、上傳所需資料
三、進入Synopsys (Design Vision)
四、讀取檔案(Compile語法)
五、設定Constrains
六、合成
七、存檔(.v & .sdf)
八、Gate Level Simulation

4
 Invoke Design Vision

„ source synthesis.csh

„ mkdir xxxx

„ cd xxxx

„ 複製 “.synopsys_dc.setup” 到你目前的目錄xxxx

5
 Invoke Design Vision (.cont)
„ design_vision& (or dv & )

Command Mode 6
 Read File 1

„ File > Read

„ Data Format
„ Verilog: .v
„ DB: .db
„ DDC: .ddc
„ Others

如果無法讀檔，或發生錯誤，請看P.8
讀檔成功可跳過P.8 7
 Read File 2

„ File > Analyze 1

„ Check verilog for syntax
and synthesizability.

Format一定要選 2
Auto,不然Work 3
library不能輸入

„ File > Elaborate

選擇之前建立的
Work library, 及
design

8
 Four Different View - Hierarchy View

„ Hierarchy > New Logical Hierarchy View

可選擇想合成的
module，若點選
Top module則是
全都合成。

9
 Four Different View - Design View

„ List > Design Veiw

不常用

10
 Four Different View - Schematic View
2

11
 Four Different View - Symbol View
2

12
Setting Design Environment

13
 Setting Operating Condition

„ Attributes>Operating Environment>Operating Conditions

Worst Best

set_operating_conditions -min_library fast -min fast -max_library slow -max slow

0.18可直接在Command
Mode輸入
14
 Setting Input Drive Impedance

„ set_drive [drive_of "tpz973pnwc/PDIZ/C"] [all_inputs]

„ PDIZ ： I/O PAD Name
„ C ： Pin Name
„ 可化簡成 = > set_drive 1 [all_inputs]

15
 Setting Output Loading

„ set_load [load_of "tpz773pnwc/PDT02TZ/I"] [all_outputs]

„ PDT02TZ ： I/O PAD Name
„ I ： Pin Name
„ 可化簡成 = > set_load 1 [all_outputs]

Control single

16
 Setting Wire Load Model
„ Attributes > Operating Environment > Wire Load

strict

relax

„ set auto_wire_load_selection false

„ set_wire_load_mode enclosed
„ top (worst case) ，enclosed (middle) ，segmented (optimistic)

17
 Setting Design Constraint

„ Define clock specification

1. Period
2. Waveform
3. Uncertainty Æ skew
4. Source latency
5. Network latency
6. Input tarnsition
7. Clock transition

18
 Specify Clock

„ create_clock -name "A" -period B -waveform {C D} {E}

„ A Æ clock name.
„ B Æ工作時脈，ex. 10 (ns)
„ C Æ rising edge ex. 0
„ D Æ failling edge，ex.工作時脈/2 = 5 (ns)
„ E Æ your module clock pin name.

„ set_dont_touch_network [ find clock A ]

„ Don’t add any buffer in clock network

„ set_fix_hold [ find clock A ]

19
 Clock Skew

„ set_clock_uncertainty -setup 0.1 [get_clocks A ]

0.7
FF
clk
0.5 0.65

FF FF

uncertainty = 0.7 - 0.5 = 0.2ns

20
 Specify Latency

„ set_clock_latency -source 3 [get_clocks A ]

„ set_clock_latency 1 [get_clocks A ]

clk FF
clock source latency network latency

21
 Specify Transition Time

„ set_input_transition -max 0.2 [get_ports E ]

0.2 ns

„ set_clock_transition -max 0.2 A

0.2 ns

22
 Setting Input & Output Delay

„ In Symbol View select all input ports

„ Attributes > Operating Environment > Input Delay

0.381012 0.600213
0.133056 0.209607

23
 Setting Input & Output Delay (cont.)

„ In Symbol View select all output ports

„ Attributes > Operating Environment > Output Delay

2.54066 1.94154
0.887273 0.678041

24
 Setting Area Constraint

„ Attributes > Optimization Constraints > Design Constraints

„ Unit：um x um

設為“0”
Tool會自動合
出最小的面積

25
 Save Constraints & Attributes

„ File > Save Info > Design Setup

„ 將之前下的所有命令存檔 => top_setup.dc

26
 Assign Problem

„ 在top_setup.dc中加入以下描述，以消除gate level netlist

中的assign

set verilogout_no_tri true

foreach_in_collection design [ get_designs "*"] {

current_design $design
set_fix_multiple_port_nets -all -buffer_constants
}

set_fix_multiple_port_nets -all -buffer_constants

27
 Change Naming Rule

„ 在top_setup.dc中加入以下描述

set bus_inference_style {%s[%d]}

set bus_naming_style {%s[%d]}
set hdlout_internal_busses true

change_name -hierarchy -rules verilog

define_name_rules name_rule -allowed "a-z A-Z 0-9 _" -max_length 255 -type cell
define_name_rules name_rule -allowed "a-z A-Z 0-9 _[]" -max_length 255 -type net
define_name_rules name_rule -map {{"\*cell\*" "cell"}}
define_name_rules name_rule -case_insensitive

change_names -hierarchy -rules name_rule

28
 Execute Script File

„ File > Execute Script

„ 執行你的top_setup.dc

29
 Check Design

„ Execute check_design before you compile the design

„ Design > Check Design
„ Error (只要有任何的Error，合成即會失敗)
„ Warning (部分Warning可忽略，但Multiple Design Instance不可忽略)

module REG4 (q,qn,data,clk,clrn);

output [3:0] q, qn;
input [3:0] data;
input clk, clrn;
DFF d0 (q[0],qn[0],data[0],clk,clrn);
DFF d1 (q[1],qn[1],data[1],clk,clrn);
DFF d2 (q[2],qn[2],data[2],clk,clrn);
DFF d3 (q[3],qn[3],data[3],clk,clrn);
endmodule

30
 Method 1: dont_touch
1. Select the multiple design instances block
2. Compile the block(否則做完don’t_touch會不能compile)
3. Attributes > Optimization Directives > Design
4. Compile the whole design

切換到Design view,
並選擇multiple
design instance

不建議使用
31
 Method 1: dont_touch (.cont)

„ Attributes > Optimization Directives > Design

不建議使用
32
 Method 2: ungroup
1. Select the multiple design instances block
2. Attributes > Optimization Directives > Design
3. Compile the whole design

不建議使用

33
 Method 3: Uniquify

1. Select the most top design of the hierarchy

2. Hierarchy > Uniquify > Hierarchy

選擇TOP
module

建議使用
34
 Method 3: Uniquify (.cont)

Remaping

記得在top_setup.dc中加入uniquify
35
 Compile design
„ Optimizes and maps the design
„ 切換到top module
„ Design > Compile Design

36
 Timing Result

„ Timing > Report Timing

Violated

OK

37
 Save Results

„ write -hierarchy -format ddc -output xxxx.ddc

„ 儲存合成後的資料。

„ write -hierarchy -format verilog -output xxxx_syn.v

„ Save gate level netlist.

„ write_sdf -version 2.1 -context verilog xxxx_syn.sdf

„ For Gate Level Simulation (Pre - Simulation ).

„ write_sdc xxxx.sdc
„ For Automation Place and Route.

38
 Gate Level Simulation

„ Modify testbanch file

„ 在testbanch開頭加入：`timescale 1ns/10ps
„ Add commands in the testbench files：

initial module mult_test;

begin reg Clk,Reset;
reg [7:0] OpA,OpB;
$dumpfile("xxx_syn.vcd");
wire [15:0] Sum;
$dumpvars integer i,j;
$sdf_annotate(" xxx_syn.sdf ", inst1);
end mult inst1(Clk,Reset,OpA,OpB,Sum);

„ verilog xxxx_test.v xxxx_syn.v –v tsmc18.v

„ Simulation your gate level netlist.

39