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Reduction of Output Impedance of Buck

Converter with Genetic Algorithm
Farzin Asadi

Abstract—This paper introduces a technique to reduce the Continuous Conduction Mode (CCM) to control a Buck
output impedance in the PWM buck converters with voltage-mode converter which feeds a low voltage microprocessor load.
control (VMC) without requiring low Equivalent Series Resistance Experimental results for a 5.0 V input, 3.1V output, 13A Buck
(ESR) output capacitors. Proposed technique uses the infinity converter are included to verify the design. In [7] analytical
norm (𝑯∞ ) to convert the problem into an optimization problem.
equations are derived for a DC-DC converter at high slew-rate
Obtained optimization problem is solved with the aid of Genetic
Algorithm (GA). The proposed technique is applied to a sample
load current transients. The analyzed model includes
buck converter operating in Continuous Conduction Mode synchronous buck converter, controller, output capacitor and
(CCM). Simulink simulation is used to test the suggested method. supply bus parasitic. This paper studies the impacts of system
Simulation results showed a considerable decrease in the low parameters on output voltage transient response. [8] studied the
frequency region of output impedance. Such a decrease in output role of the inductor on dynamic response of the converter and
impedance is very desired for low voltage high current loads like used optimization to determine the best value to obtain a fast
computer CPU’s. response for loads like microprocessor. [9] presented a method
to synthesis a zero-impedance converter. This method requires
both a positive current feedback and a negative voltage
Index Terms— DC-DC converters, load transients, output
feedback for synthesis as well as a current sensing device. [10]
impedance of buck converter, State Space Averaging (SSA).
presented a method to achieve near optimum dynamic
regulation by combining feed-forward of the output current and
input voltage with current-mode control (CMC). A common
I. INTRODUCTION
method used in industry to control the output impedance is to

M ANY ATTEMPTS have been made to improve the

dynamic response of PWM buck converters to a step
change in load current. In [1] an averaged model of an active
use many output filter capacitors placed in parallel to reduce the
ESR. In this approach, the feedback compensator is designed to
provide the loop gain and phase margin for stability and the
clamp buck converter was obtained. In this paper, output peak closed-loop output impedance is achieved through proper
impedance of the active clamp buck converter has been selection of low ESR output capacitors.
modeled including the clamp capacitor effect. In [2] V2 control Feedback control is another technique to decrease the output
is used to achieve fast transient response. V2 control can take impedance of a converter. [11] discussed the technical
advantage of the instant feedback of the output voltage during motivation behind compensation, derivation of analytical and
the load transient and delay of the error amplifier is eliminated. design oriented transfer functions. It provides an illustrative
In [3] the effects of various control techniques on the transient example as well. [12] used loop shaping to design an optimum
response of switching power supply have been discussed and controller for a buck converter. Loop shaping method is easy
compared. In this paper, transient response of switching power and intuitive and the controller can be designed accurately for a
supply is improved by using double voltage loop control specific phase margin and cross over frequency. [13] is a
technique. In [4] the transient response of the Voltage Regulator tutorial on how to design different types of classic controllers
Module (VRM) output voltage when the processor has a fast for a Buck converter. [14] presents the internal control loop
load change is analyzed. Effect of parasitic are considered in operation of the BQ 2472x/3x Buck controller IC as well as the
this paper. In [5] fast and efficient controller for a buck external compensator design guideline. It contains a design
converter which supplies a microprocessor is developed and example based on practical specifications is demonstrated. [15-
tested. Experimental data shows: tight static and dynamic 17] contains some guidelines to select the components of a
regulation (± 55mV), fast transient response (within 1us), high second order compensation network which controls a buck
efficiency (up to 90%), and stable operation with good noise converter. [18] discussed the digital PI controller design
immunity. [6] used hysteretic current-mode control in procedure for a buck converter. Experimental results showed
the effectiveness of designed controller to keep the output
FARZIN ASADI, is with the Department of Electrical Engineering, Maltepe
University, Istanbul, Turkey, (e-mail: farzinasadi@maltepe.edu.tr). voltage stable despite of disturbances like input voltage
variations and output load changes. [19] discussed the
https://orcid.org/0000-0002-5928-0807
procedure to extract the input and output impedance of dc-dc
Manuscript received March 31, 2022; accepted July 18, 2022. converters. Input and output impedance of buck, buck-boost
DOI: 10.17694/bajece.1096188
and boost converters are studied there. Extraction of small

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BALKAN JOURNAL OF ELECTRICAL & COMPUTER ENGINEERING, Vol. 10, No. 3, July 2022

signal model is the first step for designing a linear controller for When MOSFET is opened, the diode is closed (Fig. 3).
a converter. [20] discussed the procedure to extract the small
signal linear model of dc-dc converters. [21] used a
synchronous buck converter with Gallium Nitride (GaN) to
design a driver for a laser diode. Use of GaN based switch
increased the efficiency to 96.6%.
In this paper effect of parasitic elements on the operation of the
converter is studied. This paper introduces a technique to Fig. 3. Equivalent circuit of a buck converter for opened MOSFET.
reduce the output impedance in the PWM buck converters. The
technique translates the reduction of output impedance into an The circuit differential equations can be written as:
optimization problem. Obtained optimization problem is solved
with the aid of GA. 𝑑𝑖𝐿 (𝑡) 1 𝑅 × 𝑟𝐶 𝑅 𝑅 × 𝑟𝐶
This paper is organized as follows: Dynamics of buck = (− (𝑟𝐷 + 𝑟𝐿 + )𝑖 − 𝑣 + 𝑖 − 𝑣𝐷 ) (4)
𝑑𝑡 𝐿 𝑅 + 𝑟𝐶 𝐿 𝑅 + 𝑟𝐶 𝐶 𝑅 + 𝑟𝐶 𝑂
converter is studied in the second section. Small signal transfer 𝑑𝑣𝐶 (𝑡) 1 𝑅 1 𝑅
= ( 𝑖𝐿 − 𝑣𝐶 − 𝑖 ) (5)
functions of buck converter are extracted with the aid of State { 𝑑𝑡 𝐶 𝑅 + 𝑟𝐶 𝑅 + 𝑟𝐶 𝑅 + 𝑟𝐶 𝑂
Space Averaging (SSA). Third section introduces the suggested 𝑑𝑣𝐶
𝑣𝑜 = 𝑟𝐶 𝐶 + 𝑣𝐶
technique. Simulink simulations are done in the fourth section. 𝑑𝑡
𝑅 × 𝑟𝐶 𝑅 𝑅 × 𝑟𝐶
Finally, suitable conclusions are drawn. = 𝑖 + 𝑣 − 𝑖 (6)
𝑅 + 𝑟𝐶 𝐿 𝑅 + 𝑟𝐶 𝐶 𝑅 + 𝑟𝐶 𝑂

State Space Averaging (SSA) can be used to extract the small

II. DYNAMICS OF THE BUCK CONVERTER signal transfer functions of the DC-DC converter. The
The circuit diagram of an open-loop buck converter is shown in procedure of state space averaging is explained in detail in [22]
Fig. 1. The buck converter composed of two switches, a and [23].
MOSFET switch and a diode. In this schematic, Vg, rg, L, rL, The MATLAB program applies the SSA procedure to a buck
C, rC and R shows input DC source, input DC source internal converter with component values as given in Table 1.
resistance, inductor, inductor ESR, capacitor, capacitor ESR Component (the capacitor, the inductor and the load resistance)
and load, respectively. iO is a fictitious current source added to values shown in Table 1 are calculated with the aid of the
the schematic in order to calculate the output impedance of procedure given in [22]. In this table, for the sake of simplicity,
converter. In this section we assume that converter works in typical values are assumed for diode and MOSFET parameters.
CCM. MOSFET switch is controlled with the aid of a Pulse
Width Modulator (PWM) controller. MOSFET switch keeps TABLE I
closed for 𝐷. 𝑇 seconds and (1 − 𝐷). 𝑇 seconds open. 𝐷 and 𝑇 THE BUCK CONVERTER PARAMETERS
show duty ratio and switching period, respectively. Nominal Value
Output voltage, Vo 1.5 V
Duty ratio, D 0.156
Input DC source voltage, Vg 12 V
Input DC source internal resistance, 0Ω
rg
MOSFET Drain-Source resistance, 15 mΩ
rds
Fig. 1. Schematic of a buck converter. Capacitor, C 3290 μF
Capacitor ESR, rC 1.4 mΩ
When MOSFET is closed, the diode is opened (Fig. 2).
Inductor, L 13 μH
Inductor ESR, rL 9 mΩ
Diode voltage drop, vD 0.39 V
Diode forward resistance, rD 15 mΩ
Load resistor, R 0.2-3 Ω
Nominal load resistor 1Ω
Switching Frequency, Fsw 200 kHz
Fig. 2. Equivalent circuit of a buck converter for closed MOSFET.

Following results are obtained after running the MATLAB

The circuit differential equations can be written as:
code:
𝑣̃𝑜 (𝑠 + 6079)(𝑠 + 1846)
𝑑𝑖𝐿 (𝑡) 1 𝑅 × 𝑟𝐶 𝑅 𝑅 × 𝑟𝐶 = 0.0476 2 (7)
= (− (𝑟𝑔 + 𝑟𝑑𝑠 + 𝑟𝐿 + )𝑖 − 𝑣 + 𝑖 + 𝑣𝑔 ) (1) 𝑖̃𝑜 𝑠 + 5799𝑠 + 2.28 × 107
𝑑𝑡 𝐿 𝑅 + 𝑟𝐶 𝐿 𝑅 + 𝑟𝐶 𝐶 𝑅 + 𝑟𝐶 𝑂 𝑣̃𝑜 (𝑠 + 6079)
𝑑𝑣𝐶 (𝑡) 1 𝑅 1 𝑅 = 571.43 2 (8)
= ( 𝑖 − 𝑣 − 𝑖 ) (2) 𝑣̃𝑔 𝑠 + 5799𝑠 + 2.28 × 107
{ 𝑑𝑡 𝐶 𝑅 + 𝑟𝐶 𝐿 𝑅 + 𝑟𝐶 𝐶 𝑅 + 𝑟𝐶 𝑂 𝑣̃𝑜 (𝑠 + 6079)
𝑣𝑜 = 𝑟𝐶 𝐶
𝑑𝑣𝐶
+ 𝑣𝐶 =
𝑅×𝑟𝐶
𝑖 +
𝑅
𝑣𝐶 −
𝑅×𝑟𝐶
𝑖 (3) = 45385 2 (9)
𝑑𝑡 𝑅+𝑟𝐶 𝐿 𝑅+𝑟𝐶 𝑅+𝑟𝐶 𝑂 𝑑̃ 𝑠 + 5799𝑠 + 2.28 × 107

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Bode diagram of these transfer functions are shown in Figs. 4,

5 and 6. All of the obtained transfer functions are stable and
minimum phase since they don’t have any pole or zero in the
Right Half Plane (RHP). Based on the obtained results, the
dynamic model shown in Fig. 7 can be suggested to the studied
converter.

Fig. 7. Dynamical model of the studied buck converter.

III. SUGGESTED METHOD

This section introduces the suggested method. Infinity norm
and genetic algorithm make the foundations of the proposed
method and are studied briefly.
A. 𝑯∞ Norm
The steady-state output of the SISO stable system,
𝑥̇ = 𝐴𝑥 + 𝐵𝑢
(10)
𝑦 = 𝐶𝑥
to the input function,
𝑢(𝑡) = 𝑎𝑠𝑖𝑛(𝜔𝑡 + 𝜑) (11)
𝑣̃𝑜 (𝑠+6079)(𝑠+1846) with unknown 𝑎 ≠ 0, 𝜔, 𝜑 ∈ ℝ1 is
Fig. 4. Bode diagram of = 0.0476 .
𝑖̃𝑜 𝑠 2 +5799𝑠+2.28×107 𝑦𝑠𝑠 (𝑡) = |𝐺(𝑗𝜔)|. 𝑎. sin(𝜔𝑡 + 𝜑 + 𝑎𝑟𝑔(𝐺(𝑗𝜔))) (12)
where 𝐺(𝑠) = 𝐶(𝑠𝐼 − 𝐴)−1 𝐵. The 𝐻∞ -norm is the maximal
possible amplification, i.e.
𝑠𝑢𝑝|𝐺(𝑠). 𝑈(𝑠)|
‖𝐺(. )‖∞ = 𝜔 ∈ ℝ1 =
𝑠𝑢𝑝|𝐺(𝑗𝜔)|
(13)
𝑠𝑢𝑝|𝑈(𝑠)| 𝜔 ∈ ℝ1
𝜔 ∈ ℝ1
The 𝐻∞ -norm of a MIMO system is its maximum singular
value [24].
‖𝐺(. )‖∞ = 𝑠𝑢𝑝 𝜎̅ {𝐺(𝑗𝜔)} (14)
𝜔

The 𝐻∞ -norm of a scalar transfer function can be obtained

graphically. Infinity norm of a SISO system 𝐺 is the distance in
the complex plane from the origin to the farthest point on the
Nyquist plot of G, and it also appears as the peak value on the
Bode magnitude plot of |G(jω)|. For instance, the infinity norm
𝑣̃𝑜 (𝑠+6079) 10 10
Fig. 5. Bode diagram of = 571.43 . of 𝐺(𝑠) = is 7.91. Bode plot of 𝐺(𝑠) = is
𝑣̃𝑔 𝑠 2 +5799𝑠+2.28×107 𝑠+0.4𝑠+10 𝑠+0.4𝑠+10
shown in Fig. 8. Maximum of the Bode graph occurs around 42
Rad
and its value is 17.96 dB which is equivalent to gain of
s
17.96
10 20 = 7.91.

𝑣̃ (𝑠+6079) 10
Fig. 6. Bode diagram of ̃𝑜 = 45385 2 . Fig. 8. Bode plot of 𝐺(𝑠) = . Peak occurs at 3.15 Rad/s with
𝑑 𝑠 +5799𝑠+2.28×107 𝑠+0.4𝑠+10
magnitude of 17.96 dB.

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B. Genetic Algorithm (GA) C. Suggested Method

In 1960 the first serious investigation into Genetic Algorithm The open loop dynamical model of the studied buck converter
(GA) was undertaken by John Holland. These search techniques is shown in Fig. 7. Block diagram of closed loop voltage mode
are based on the process of biological evolution and are used to control of the converter is shown in Fig. 10. The controller is PI
provide useful solutions to optimization and search problems. (Proportional Integral) since it is good enough for most of
As they are based on biological evolution, they use techniques applications.
that are emulated from the concepts of inheritance, mutation
and selection. The PI controller must stabilize the loop. According to the
Genetic algorithms explore a parameter space while optimizing Routh-Hurwitz stability test, following inequality must be
a function. The problem is broken down into a population of satisfied in order to stabilize the loop.
candidate solutions which are refined over a number of (𝑎. 𝑑 + 𝑏. 𝑐)𝑘𝑝 + (𝑎. 𝑐 − 𝑏)𝑘𝑖 + 𝑐. 𝑑 + 𝑎2 . 𝑘𝑝 𝑘𝑖 + 𝑎. 𝑏. 𝑘𝑝 2 > 0 (15)
generations. where, 𝑎 = 45385, 𝑏 = 45385 × 6079 = 275895415, 𝑐 =
A single candidate solution is represented by a chromosome 5799, 𝑑 = 2.28 × 107 . 𝑘𝑝 > 0 and 𝑘𝑖 > 0 are unknown
which essentially encodes all of the optimizable parameters into proportional gain and integral gain, respectively.
a single entity. Each candidate is ranked using a fitness function According to the Fig. 10, the closed loop output impedance is:
and those with the best fitness score are selected for further
refinement. The refinement stage then operates on each of the 𝑣̃𝑜 (𝑠) 1
𝑍𝐶𝐿 = × (16)
chromosomes by 𝑖̃𝑜 (𝑠) 𝑣̃ (𝑠)
1 + 𝐶(𝑠). ̃𝑜
I) breeding - a process where a new population of improved 𝑑 (𝑠)
candidates are generated using the present generation’s or,
population, and 𝑍𝐶𝐿
II) mutation - in which chromosomes are modified in some way. (𝑠 + 6079)(𝑠 + 1846)
= 0.0476
Both of these operations permit the parameter space to be more 𝑠 2 + 5799𝑠 + 2.28 × 107
1
effectively explored. The whole process is iterated for many × (17)
𝑘𝑖 (𝑠 + 6079)
generations where the candidate solutions can be seen to evolve 1 + (𝑘𝑝 + ).45385 2
𝑠 𝑠 + 5799𝑠 + 2.28 × 107
and, hopefully, converge towards a single solution. The use of
natural evolution method for the optimization of control system
Equation (17) has two unknowns: 𝑘𝑝 and 𝑘𝑖 . We want to solve
has been of interest for the researchers since a long time. Fig. 9,
illustrate the GA flowchart. the following optimization problem:
Ready to use implementation of GA is available in the
MATLAB’s optimization toolbox. 𝑚𝑖𝑛 ‖𝑍𝐶𝐿 ‖∞
𝑣̃𝑜 (𝑠) (18)
𝑠. 𝑡. 𝐶(𝑠) 𝑠𝑡𝑎𝑏𝑖𝑙𝑖𝑧𝑒
𝑑̃ (𝑠)

Ideally 𝑍𝐶𝐿 would be zero across the frequency bandwidth.

However, since that would require an infinite loop gain, it is not
practical for synthesis. The GA can be used to solve this
optimization problem. GA changes the 𝑘𝑝 and 𝑘𝑖 values until
the minimum is obtained. After running the GA, 𝑘𝑝 = 3.733
and 𝑘𝑖 = 1.108 × 104 and min ‖𝑍𝐶𝐿 ‖∞ = 0.476 Ω.

Fig. 9. GA flowchart.

Fig. 10. Block diagram of the system with PI controller. Fig. 11. Comparison between open loop output impedance and closed loop
output impedance.

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Fig. 11 compares the closed loop output impedance (Equation In the second scenario load current changes from 0.5 A to 5 A
(17) with 𝑘𝑝 = 3.733 and 𝑘𝑖 = 1.108 × 104 ) and open loop at t=25 ms. Simulation result is shown in Figs. 15 and 16.
output impedance (Equation (7)). Closed loop output Simulation result shows that the controller is able to keep
impedance decreased considerably in the low frequency range tracking the reference voltage even when the load changes.
of the graph. Reduction of output impedance means a smaller According to Fig. 16, maximum deviation for change of output
voltage drop for larger currents. Such a property is highly current from 0.5 A to 5 A is 1.5-1.4=0.1 V. In other words,
desired in low voltage high current applications. change of 900% in output current generates change of 6.66% in
output voltage. Such a small change in output voltage shows
IV. SIMULATION RESULTS that the designed controller decreased the output impedance
considerably.
Designed PI controller is tested in the Simulink environment.
Simulation diagram is shown in Fig. 12. In the first test
scenario, reference (Fig. 10) changes from 1.5 V to 3 V at t= 25
ms. Simulation result is shown in Figs. 13 and 14. Simulation
result shows that the designed controller is able to follow the
reference signal with zero steady state error. This is expected
since the controller contains an integrator term.

Fig. 12. Simulation diagram of the system.

Fig. 15. Effect of change in output load.

Fig. 13. Effect of change in reference.

Fig. 16. Close-up Fig. 15 around t= 25 ms.

V. CONCLUSIONS
A technique to reduce the output impedance in the PWM buck
converters with voltage-mode control is studied in this paper.
Proposed technique used the 𝐻∞ infinity norm to convert the
impedance reduction problem into an optimization problem and
use genetic algorithm to solve the obtained optimization
problem. Suggested technique is cheaper in comparison to the
classical solution of using the capacitors with lower ESR.
Because in the suggested technique, there is no need to use any
expensive low ESR capacitor and reduction of output
impedance is done by good selection of controller parameters.
Suggested technique is tested with the aid of Simulink
simulations. According to the simulation results, the output
impedance of converter decreased considerably in the low
Fig. 14. Close-up Fig. 13 around t= 25 ms. frequency region. Such a decrease is very desired for low

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BALKAN JOURNAL OF ELECTRICAL & COMPUTER ENGINEERING, Vol. 10, No. 3, July 2022

voltage high current loads like computer CPU’s. Suggested BIOGRAPHY

method can be applied to other types of converters as well. FARZIN ASADI received his B.Sc. in
Electronics Engineering, M.Sc. in
REFERENCES Control Engineering, and Ph.D. in
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