Eps 2204 A

Greetings from Georgia Tech
Semiconductor Packaging
The Future is Now!
Madhavan Swaminathan
John Pippin Chair in Microsystems Packaging & Electromagnetics
School of Electrical & Computer Engg.
School of Materials Science & Engg (Joint Appt.)
Director, 3D Systems Packaging Research Center (PRC)
www.prc.gatech.edu
Recent Events/Announcements in Semiconductors….
❑ Global semiconductor industry projected to become a trillion-
dollar industry by 2030 (Source: McKinsey & Company)
▪ Drivers: Automotive, Computing & Wireless
❑ 2021: CHIPS for America Act ($52B)

▪ Reshoring and U.S. Leadership
▪ 2021: U.S. Innovation and Competition Act (USICA) - Senate
▪ 2022: America COMPETES Act – House
▪ Mar. 1, 2022: State of the Union Address by the President, USA
▪ Mar 9, 2022: President’s Roundtable with CEOs and Bipartisan
Governors Support of Bipartisan Innovation Act
❑ Continuation of Moore’s law becoming challenging

▪ DARPA ERI recognized this
▪ 2017: CHIPS (Common Heterogeneous Integration and IP Reuse
Strategies) Program
▪ Relying on Advanced Packaging for continuing Moore’s law
2
GT-3D Systems Packaging Research Center SEMICONDUCTOR PACKAGING - THE FUTURE IS NOW Apr. 14, 2022
Advanced Packaging – its relevance for the Future of
Semiconductor Systems
1. Higher yield using smaller dies in advanced nodes.
2. Shorter time to design with smaller dies from optimized legacy technology nodes
with enhanced functionality.
3. Move towards HETEROGENEOUS INTEGRATION.
Courtesy: TSMC
Courtesy: GT-PRC, Chip Scale Review, 2022

Courtesy: EDAPS Keynote, 2020 Courtesy: AMD 3
Heterogeneous Integration – Industry SOTA
2D Connectivity 2D & 3D Connectivity
https://www.anandtech.com/show/17054/amd-announces-instinct-mi200-accelerator- https://www.nextplatform.com/2021/08/24/intels-ponte-vecchio-
family-cdna2-exacale-servers/2 gpu-better-not-be-a-bridge-too-far/
Ponte-Vecchio - 47 dielets with over 100 billion transistors

4
Role of Universities
Universities have two important roles:
❑ Workforce development
▪ K-12, 2 Year, 4 Year, Advanced Degrees Prototyping
R&D
▪ Technical Training.
❑ Academic research driving US leadership

▪ Support fundamental, applied, and
translational research, from concepts to Workforce Technology
prototypes, that will ensure the U.S. is a Development Transfer
global leader in semiconductor based
electronic systems manufacturing, while also
securing the supply chain.
5
Our Vision – The Future of Packaging
SYSTEM ON PACKAGE (SOP)
❑ Advanced Devices (Transistor Scaling)

▪ 3D Transistors, Monolithic 3D
❑ Advanced Packaging (Package Scaling)
▪ High density interconnectivity between chips with integrated and embedded 2D & 3D
❑ Transistor Scaling + Package Scaling = System Scaling 6
Emerging Distributed Computing & Communication
Requirements
▪ Neuromorphic (& Quantum) Computing
▪ Bandwidth Density: 1000Tbps/mm2 @ fJ/bit
▪ Thermal Design Power (TDP): >1kW/cm2
▪ Power Delivery: 1kW to 50kW with >80% efficiency
▪ Unmanned mobility (Automotive)

▪ Pervasive Connectivity: 106 devices/km2 (5G) to 107 devices/km2 (6G)
▪ Capacity: 20Gbps (5G) to 1Tbps (6G)
▪ High Energy Efficiency
Advanced Packaging & Heterogeneous Integration
State of the Art
Our Focus
Our Focus
S. Ravichandran & M. Swaminathan, Heterogeneous Integration for AI Applications: Status & Future Needs, Chip Scale Review, 2022 8
Glass Interposer w/ 2D & 3D Connectivity
Features
❑ High density 2D & 3D Connectivity
❑ Eliminate assembly for embedded dies
❑ Panel (square) scalable to 500mm
❑ Tailorable CTE for maximizing 1st and 2nd level reliability
❑ Thermal insulation between dies
❑ High heat flux removal from top & bottom
❑ Large Panel Size to reduce cost 9
3D Heterogeneous Integration
TSV-based Non-TSV
3D IC /w TSV Hybrid Bonding 3D Glass
[Zhang, et al. ‘18] [Chen, et al, ‘19] Embedding
[Ravichandran, et al, ‘19]
Status Commercial Commercial Research
Dielectric Constant 3.9* 3.9* 2.5-3
IO pitch 40 µm 10 µm 20 µm
Interconnect length 75 µm* 50 µm* 35-50 µm
Interconnect density
625 10000 2500
(IO/mm2)
Vswing 0.7 V* 1 V* 1V
Ron/CTx/CRx (Ω/F/F) n/a n/a 50/50f/50f
Data rate/IO 1.69 Gbps n/a 1.86 Gbps
Bandwidth density 1.76 Tbps/mm2* n/a 4.65 Tbps/mm2
Energy-per-bit 76.2 fJ/bit 7 fJ/bit* 11.2 fJ/bit

* Derived metric
S. Ravichandran and M. Swaminathan, Chip Scale Review (2022) 10
What can this enable? Case for Chiplets/Dielets!
partitioned into Logic
4 dielets Logic
0.94mm
0.82mm
1.6 mm
Memory Memory
0.82mm 0.82mm
2D Monolithic (RISC-V) Glass Interposer Silicon Interposer

Collaboration with Pruek Vanna-iampikul (GT), Sungkyu Lim (GT) & Ravi Agarwal (Meta) 11
Interconnect Wiring Details
CoWoS (TSMC)
SOTA
Glass Interposer Silicon Interposer
# Metal Layer 3 4
Metal thickness 4um 1um
Dielectric thickness 15um 1um
Min. Wire width / spacing 2um / 2um 0.4um / 0.4um
Via size 12um 0.4um
Pad size 22um 0.7um
Die-to-Die spacing 100um 100um
Micro-bump pitch 35um 40um
PDN width/spacing 40um / 100um
12
Dielet-to-Dielet Connectivity
❑ Dielets communicate with each other through AIB

signaling
13
Area & Wire Length Comparison
❑ Huge savings with 3D Glass due to 3D connectivity
❑ 3D Glass 1.36X smaller than 2D Monolithic
3D 2.5D
Parameter 2D 3D vs. 2.5D
(glass) (silicon)
Metal layer used - 2 4 2x
Total interposer WL (mm) - 29.69 620.21 20.8x
-
Average interposer WL (mm) 0.43 0.50 -
-
Max interposer WL (mm) - 0.67 3.01 5x
interposer via usage - 21 + 924 1542 1.6x
Footprint ( mm x mm ) 1.6 x 1.6 1.84 x 1.02 2.2 x 2.2 -
Area (mm2) 2.56 1.87 4.84 2.6x
❑ 12% Power Overheard for 3D Glass over 2D Monolithic

❑ 5% increase in frequency with 3D Glass over 2D Monolithic 14
Glass Panel Embedding (GPE) Process
Laminated cavities Die placement
Fully fabricated GPE substrate
After dielectric lamination

After die embedding
15
Bandwidth Density
via diameter
15µm
Flip-chip die
bump pitch: 35µm
15µm
15µm
300µm Embedded die Embedded die
300µm Glass
Cross section of the 3D embedded die

with die-to-die interconnects
Cavity drilling process Cavity wall top profile Panel with some
17 Gbps embedded dies
EHcenter 0.2 V
• Signal-to-GND ratio 2:1
EW 0.55 UI • Based on 0.2 V EH - 0.2UI EW and BER=1e-12
– Data rate / IO = 17 Gbps / IO
– BW density = 9.25 Tbps/mm2
Ctx = Crx = 0.5pF, Ron = 50 Ohm Courtesy: Serhat Erdogan, Ph.D. Student, GT 16
Power Delivery – Going Vertical
❑ 1000W; 2-5 A/mm2; >80% Efficiency

▪ Integrated Voltage Regulator (IVR)
▪ Integrated Inductors
▪ Vertical Power Delivery
▪ Minimum routing losses
▪ Effective heat removal
K. Radhakrishnan, M. Swaminathan & B. Bhattacharyya, TCPMT, 2021 17
Embedded Inductors for Power Delivery
Magnetic Materials Fabricated Inductors Inductor Response
Inductance Conversion Switching frequency, Sat. current (A) Energy Stored/per

(nH) (D) fsw (MHz) cycle (W)
Coax (Intel) [ECTC ‘21] 2.5 1.8V-to-1V 140 8 23
Air core (Intel) [APEC ‘14] 1.2 1.8V-to-1V 140 9.6 17
Array (Intel) [ECTC ‘20] 3 1.8V-to-1V 140 4 7
Toroid HPE1 (GT PRC) 450 48V-to-1V 5 0.02 3
[ECTC ‘21]
Dual spiral (GT PRC) 400 48V-to-1V 5 4 32 (ongoing) 18
Micro-coolers for Power Delivery
Heat map of the 3D IVR
Collaboration with Vanessa Smet & Yogendra Joshi (GT) Courtesy: Venkatesh Avula, Ph.D. Student, GT 19
Wireless Communication Link – 6G
Transmitter arrays
100m
Path Loss (Free + Channel) = Handset antennas
133dB @140GHz (D-Band – 6G)
Courtesy: ComSenTer
EIRP
+72dBm
AiP
1 Free space
128-QAM
SINR 30dB (BW=8GHz)
Channel Loss
Heat Ant. Gain Ant. Gain Rx Power
Removal Loss -133dB
+36dBm +36dBm -26dBm
Link Margin
3 2
11dB
-37dBm
Tx Radio Package Package Rx Radio
Signal
Tx Psat Loss Tx Power -61dBm Rx Power Loss Rx NF
37dBm 1dB +36dBm -25dBm 1dB 8dB
150 W/cm2 Courtesy: Adapted from Shahriar Shahramian, Bell Labs – Nokia 20
Enabling Connectivity @ sub-THz Frequencies
Scalable Antenna Array
140GHz 205 GHz 280 GHz
l/2=1.1mm l/2=0.7mm l/2=0.54mm
❑ l/2 lattice for Antenna Array and interconnects (AiP)

❑ Enough elements to achieve appreciable gain
❑ 1dB or less loss between PA input and Antenna Array
❑ Efficient heat removal
21
Tx Antenna Array in Package (AiP): D-Band
4x4 Array
Gain Return Loss E-Plane H-Plane

meas. meas.
0 sim. 0 sim.
0 330 30 0 330 30
-10 -10
-20 300 60 -20 300 60
-30 -30
-40 -40
270 90 270 90
dB
dB
-40 -40
-30 -30
-20 240 120 -20 240 120
-10 -10
210 150 210 150
0 0
180 180
Kai-Qi Huang et al, ECTC 2021 22
Rx Antenna Array in Package (AiP): D-Band
23
D-Band (140GHz) Interconnects
1. Co-planar Waveguide (CPW)
2. Microstrip (MS)
3. Substrate Integrated Waveguide (SIW)
4. Via-less Interconnect
5. Planar Goubau Lines (PGL)
Via-less
CPW & MS SIW PGL
CPW Loss: 0.25dB/mm Via-less Loss: 1.8dB Goubau Loss:

SIW Loss: 0.7dB/mm
MS Loss: 0.25dB/mm 0.34dB/mm
Mutee Rehman et al, IMS 2021 L. Vijaykumar et al, ECTC 2022
Xiaofan Jia et al, IMS 2022
0.43dB/mm Mutee Rehman et al, CPMT 2021 24
Reducing Loss by Eliminating Assembly
Wirebond Flip chip
Rao Tummala, McGraw Hill, 2019

Chip Embedding
Micro-vias
Dielectric (ABF)
PA
CMOS Glass No
Tx Assembly
Ag-epoxy
❑ RDL to Chip loss reduction!

❑ 0.15dB lower than Flip chip
❑ 1.65dB lower than Wirebond Serhat et al, ECTC, 2021 25
Embedded Heterogeneous Dies for mmWave
ABF Lamination Via drilling
CMOS Glass CMOS Glass

PA PA
Carrier 1 Carrier 1
X. Jia et al, 2022 ECTC (under review)

Qorvo Die
2um surface planarity
Before ABF lamination 30um ABF GL102 laminated Laser Via Drilling Panel 26
Functional Antenna in Package Module (D-Band)
Mark Rodwell, UCSB
Antenna Array
Embedded PA & CMOS
Xiaofan Jia et al, ECTC 2022 27
Hybrid Beamforming Tx Antenna Array
Phase
Shifter
❑ Building Block: 2x2 sub-array

❑ Large Arrays using 2x2 sub-array
❑ Ex: 256 antenna elements using 64 (8x8) sub-
arrays: Gain~25-28dBi (D-Band)
▪ 8 basic beams
▪ Active beamformers steer the beam in 2D
within each 1/8 (azimuth) of the half space
❑ 64x32 elements (32x16 sub-array): Gain~36dBi K. Huang & M. Swaminathan, APS, 2021 28
Electronics on Flexible Thin Glass
❑ Ultra-thin, flexible glass (30 μm Schott AF

32) on two different build up dielectrics (JSR
GT-N01 and Taiyo PID)
29
Antenna on Thin Glass
Tensile Compressive
❑ 4x3 patch array; 3.05 mm (L) x 4.05 mm (W); 8.56 mm (S); 10dBi Gain
❑ 50 Ohm feed lines (135um width)
❑ Taiyo PID followed by SAP process
❑ Design frequency: 24GHz
30
Emerging Design Challenges
Large
(Multi-physics)
❑ Fact: Design Space can be large and exploring trade-offs can be painful.
❑ Fact: Simulators are slow and using them in design optimization has had only limited success.
❑ Key Takeaway: Why not re-think the Design process with a focus on Heterogeneous Integration &
System Scaling?
❑ Can fast-to-evaluate “learned” model accurately replace detailed slow model in design and
optimization?
M. Swaminathan, H. M. Torun, H. Yu, J. Hejase, and D. Becker, “Demystifying Machine Learning for Signal and Power Integrity Problems in Packaging”, IEEE CPMT, 2020 31
Rethinking Design & Optimization
Micro
Bayes Theorem
x Electronic y Posterior y
System Prior y
❑ Rather than using point simulations:

𝑥 →𝑦
❑ Why not repose the problem using
probabilities: Likelihood y
𝑥 → 𝑃(𝑦|𝑥)
❑ Machine Learning provides enormous
opportunities here for searching design
spaces and design optimization.
❑ Establish confidence in the predictions and
solutions by establishing confidence bounds. https://kevintshoemaker.github.io/NRES-746/LECTURE6.html
M. Swaminathan, H. M. Torun, H. Yu, J. Hejase, and D. Becker, “Demystifying Machine Learning for Signal and Power Integrity Problems in Packaging”, IEEE CPMT, 2020 32
Inverters for Electric Vehicles
Denso Half-Bridge Module
❑ 3D package architectures
❑ Integrated cooling
❑ Material Innovations
❑ What is the appropriate package architecture, geometries & materials for half-bridge
inverter power modules for electric vehicles?
❑ Electrical-Mechanical-Thermal multi-physics simulations required for Co-Design!
Collaboration with Vanessa Smet, GT 33
Inverter Module Mixed-Variable Parameter Space
Denso Half-Bridge Module
Package Architecture #1 Package Architecture #2
❑ 4 objectives to minimize (Pareto Front): Parasitic inductance, parasitic : Thickness Related Continuous
capacitance, package volume, temperature. : Layout Related Parameters
❑ 8 continuous, 5 categorical parameters (Total 144 combinations). : Material Categorical
❑ Data generation through electrical-thermal multi-physics simulations. : Package Architecture Parameters
Torun et al., IEEE Access, under review. 34
Optimization Environment
Fast (Function Evaluations) Slow (Data Samples hard to obtain)
35
Inverter Module Results
Radial Visualization of the 4-D Pareto Front
❑ Imagine ML predicting the best package architecture with the appropriate materials & geometries.
❑ Optimized design has up to (compared to hand-tuned design):
▪ 68.7% reduced package volume.
▪ 29.4% reduced parasitic capacitance.
▪ 2.7% reduced max. junction temperature. H. Torun, Ph.D. thesis, 2021 36
Recent Translational Activities
❑ SK Group to Locate First of its Kind Glass-

based Semiconductor-part Venture in
Covington, GA (based on GT-PRC research)
❑ Announcement by Governor Brian P. Kemp ❑ Qorvo wins SHIP RF Center
(Atlanta, GA – October 28, 2021) ▪ $75M from US Government
❑ Company will invest more than $473 million ▪ GT-PRC will focus on Glass Based Advanced Packaging for
in this unprecedented venture and will create RF (Start Date: Mar. 2022)
more than 400 new jobs in Newton County
https://www.georgia.org/press-release/sk- https://www.qorvo.com/newsroom/news/2020/qorvo-wins-
group-locate-first-its-kind-glass-based- us-gov-project-to-create-advanced-state-of-the-art-rf-
semiconductor-part-venture-covington semiconductor-packaging-center 37
Packaging Research Center (PRC) – A Snapshot
❑ Graduated NSF Engineering Research
Center (in its 28th year)
❑ Research, Education & Workforce
development in heterogeneous
integration, advanced packaging and
system miniaturization.
❑ Design, Materials, Process, Assembly,
Reliability, Thermal & System
Integration.
❑ Center team:
▪ 29 faculty from five schools (ECE,
MSE, ME, ChBE, CS) Collaborators
▪ 11 research/administrative staff ▪ Industry: 43
▪ 60+ graduate/undergraduate students ▪ 14 Univs
▪ SRC, DARPA, DoD, NSF,
▪ Visiting engineers.
iNEMI, Semi 38
The Future ….
Category Granularity Technology Interconnect Examples
Density (mm-2)
3D Transistor Transistor § Epitaxial growth 109
(before M1) § Stacked nanosheet
§ Sequential Integration
§ in situ dep and
Transistors
anneal
C-FET Stacked Nanosheet Ge nanosheet PMOS
§ layer transfer & on FinFET NMOS
bonding
Monolithic 3D Gate, Block § Sequential Integration >108
(after M1) § in situ dep and
anneal
§ layer transfer &
bonding
3D Transpose SRAM 3D RRAM 3D eDRAM 3D FeFET TCAM
Polylithic 3D Block, § Parallel Integration

(W2W bonding) Chiplet § Hybrid bonding
106 -108
§ Metal ALD
SiO2-reconstituted tier in the BEOL

Packaging
§ 3D Packaging
Heterogeneous
2.5/3D
Chiplets,
Modules
104 – 105
Stacked and assembled chiplets
Packaging on glass interposer
3
Adapted from Suman Datta, U. Notre Dame
❑ Addressing multiple length scales critical.

❑ THE FUTURE IS ABOUT SCALING SEMICONDUCTOR SYSTEMS THROUGH BOTH PACKAGE &
TRANSISTOR SCALING. LET’S START NOW! 39
Thank You
Join us in our Journey!
www.prc.gatech.edu 40

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Greetings from Georgia Tech

❑ 2021: CHIPS for America Act ($52B)

❑ Continuation of Moore’s law becoming challenging

Courtesy: GT-PRC, Chip Scale Review, 2022

Ponte-Vecchio - 47 dielets with over 100 billion transistors

❑ Academic research driving US leadership

❑ Advanced Devices (Transistor Scaling)

▪ Unmanned mobility (Automotive)

Status Commercial Commercial Research

Dielectric Constant 3.9* 3.9* 2.5-3

Interconnect length 75 µm* 50 µm* 35-50 µm

Ron/CTx/CRx (Ω/F/F) n/a n/a 50/50f/50f

Data rate/IO 1.69 Gbps n/a 1.86 Gbps

Bandwidth density 1.76 Tbps/mm2* n/a 4.65 Tbps/mm2

Energy-per-bit 76.2 fJ/bit 7 fJ/bit* 11.2 fJ/bit

2D Monolithic (RISC-V) Glass Interposer Silicon Interposer

❑ Dielets communicate with each other through AIB

❑ 12% Power Overheard for 3D Glass over 2D Monolithic

Fully fabricated GPE substrate

After dielectric lamination

bump pitch: 35µm

300µm Embedded die Embedded die

Cross section of the 3D embedded die

❑ 1000W; 2-5 A/mm2; >80% Efficiency

Inductance Conversion Switching frequency, Sat. current (A) Energy Stored/per

Heat map of the 3D IVR

l/2=1.1mm l/2=0.7mm l/2=0.54mm

❑ l/2 lattice for Antenna Array and interconnects (AiP)

Gain Return Loss E-Plane H-Plane

-20 300 60 -20 300 60

-20 240 120 -20 240 120

Kai-Qi Huang et al, ECTC 2021 22

CPW Loss: 0.25dB/mm Via-less Loss: 1.8dB Goubau Loss:

Rao Tummala, McGraw Hill, 2019

❑ RDL to Chip loss reduction!

CMOS Glass CMOS Glass

X. Jia et al, 2022 ECTC (under review)

Mark Rodwell, UCSB

Embedded PA & CMOS

Xiaofan Jia et al, ECTC 2022 27

❑ Building Block: 2x2 sub-array

❑ Ultra-thin, flexible glass (30 μm Schott AF

❑ Rather than using point simulations:

Denso Half-Bridge Module

Denso Half-Bridge Module

Package Architecture #1 Package Architecture #2

❑ SK Group to Locate First of its Kind Glass-

Polylithic 3D Block, § Parallel Integration

SiO2-reconstituted tier in the BEOL

Adapted from Suman Datta, U. Notre Dame

❑ Addressing multiple length scales critical.

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