CN803

CONSONANCE
Ultra Low Power Microprocessor Reset IC

CN803/809/CN810
General Description Features
The CN803/809/810 series are microprocessor  Precise Reset Threshold: ±2.5%
(µP) supervisory circuits used to monitor the  CMOS Output(CN809/810) and Open Drain
power supplies in µP and digital systems. They Output(CN803)
provide excellent circuit reliability and low cost  140ms min Reset Pulse Width
by eliminating external components.  3.2µA Supply Current @VCC=3V
These circuits perform a single function: they  Guaranteed Reset Valid to VCC = +1.15V
assert a reset signal whenever the VCC supply  Power Supply Transient Immunity
voltage declines below a preset threshold, keeping  Operating Temperature Range
it asserted for at least 140ms after VCC has risen -40°C to +85°C
above the reset threshold.  Available in SOT23-3
The CN809/810 have CMOS outputs, the CN803
has open drain output. The CN803/809 have an
active-low output, while the CN810 has
Pin Assignment
an active-high RESET output. The reset
comparator is designed to ignore fast transients on GND 1 CN803
VCC, and the outputs are guaranteed to be in the CN809
3 VCC
correct logic state for VCC down to 1.15V over the CN810
temperature range. RESET
2
The device is available in 3 pin SOT23 package. (RESET)
SOT23-3
( ) is for CN810 only

Applications
 Computers
 Portable/Battery-Powered Equipment
 Intelligent Instruments
 Controllers
www.consonance-elec.com Rev 1.2 1

Device Function Reference Table:
Reset Reset active
Part No. Output Type Marking
threshold Low or High
CN809L 4.63V Low CMOS AAAA
CN810L 4.63V High CMOS AGAA
CN809M 4.38V Low CMOS ABAA
CN810M 4.38V High CMOS AHAA
CN809J 4.00V Low CMOS CWAA
CN809T 3.08V Low CMOS ACAA
CN803S 2.93V Low Open Drain ABC
CN809S 2.93V Low CMOS ADAA
CN810S 2.93V High CMOS AKAA
CN803R 2.63V Low Open Drain ABD
CN809R 2.63V Low CMOS AFAA
Block Diagram
VCC
OSC
VCC
RESET
(RESET)
+ Delay
COMP Generator
1.25V
-
GND
Fig.1 Block Diagram For CMOS Output
Rev 1.2 2
Pin Description
Pin No.
Symbol Description
1 GND Ground terminal

CMOS Output. This output remains low if VCC drops
below VRES, and for at least 140ms after VCC rises above
(CN809)
VRES + VHYST .
CMOS Output. This output remains high if VCC drops
RESET
2 below VRES, and for at least 140ms after VCC rises above
(CN810)
VRES + VHYST.
Open Drain Output. This output remains low if VCC
drops below VRES, and for at least 140ms after VCC rises
(CN803)
above VRES + VHYST .
Analog Input. This pin is both the power supply to
3 VCC
internal circuit and the voltage to be monitored.
ABSOLUTE MAXIMUM RATINGS

Terminal Voltage (With respect to GND) Thermal Resistance…………………..300°C/W
VCC.............…...…......-0.3V to +6.0V Operating Temperature.…..……...-40 to +85°C
, RESET …....-0.3V to +6.0V Storage Temperature.....…….......-65 to +150°C
Input/Output Current Maximum Junction Temperature... +150°C
VCC .........................................20mA Lead Temperature (soldering, 10s) .......+300°C
, RESET ..…….….....20mA ESD Rating(HBM)……….……….………4KV
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
Rev 1.2 3
Electrical Characteristics (VCC=3V, TA= －40℃ to 85℃, Typical values are at TA=25℃,
unless otherwise noted.)

Parameters Symbol Test Conditions Min Typ Max Unit
Maximum input
VCCMAX 5.5 V
voltage
Minimum input
VCCMIN 1.15 V
voltage
VCC=2.0V 2.8 5.5
Supply current IVCC VCC=3.0V 3.2 6 uA
VCC=5.0V 4.0 7.5
CN8__L 4.51 4.63 4.75
CN8__M 4.25 4.38 4.5
CN8__J 3.89 4.00 4.11
Reset Threshold VRES CN8__T 3.0 3.08 3.15 V
CN8__S 2.86 2.93 3.0
CN8__R 2.56 2.63 2.7
CN8__Z 2.26 2.32 2.38
Reset Threshold
VHYST 0.013VRES V
hysteresis
VCC transitions from
VCC to
20 us
Delay(CN803/809) VRES+0.1V to VRES－0.1V
VCC transitions from

VCC to RESET
20 us
Delay(CN810) VRES+0.1V to VRES－0.1V
VRES>VCC=2V,ISINK=1.5mA 0.3
Output
Voltage Low VOL VRES>VCC=3V,ISINK=3.2mA 0.3 V
(CN803/809)
VRES>VCC=4V,ISINK=5mA 0.3
Output VRES<VCC=3V,ISRC=1.2mA VCC-0.4
Voltage High VOH VRES<VCC=4V,ISRC=2mA VCC-0.4 V
(CN809) VRES<VCC=5V,ISRC=2.5mA VCC-0.4
RESET Output VRES<VCC=3V,ISINK=3.2mA 0.3
Voltage Low VOL VRES<VCC=4V,ISINK=5mA 0.3 V
(CN810) VRES<VCC=5V,ISINK=6mA 0.3
RESET Output VRES>VCC=2V,ISRC=600uA VCC-0.4
Voltage High VOH VRES>VCC=3V, ISRC=1.2mA VCC-0.4 V
(CN810) VRES>VCC=4V, ISRC=2mA VCC-0.4
Reset Pulse Width TRES 140 240 400 ms
o
Note : Parts are 100% production tested at 25 C. Specifications over full temperature range are
guaranteed by design
Rev 1.2 4
Detailed Description
A microprocessor’s (µP’s) reset input starts the µP in a known state. The CN803/809/810 series assert reset
to prevent code-execution errors during power-up, power-down, or brownout conditions. The device
consists of a comparator, a low current high precision voltage reference, voltage divider, output delay
circuit and output driver. They assert a reset signal whenever the VCC supply voltage declines below a
preset threshold, keeping it asserted for at least 140ms after VCC has risen above the reset threshold.
The CN809/810 have a CMOS output stage, the CN803 has an open drain output stage. The CN803/809
have an active-low output, while the CN810 has an active-high RESET output. The reset
comparator is designed to ignore fast transients on VCC, and the outputs are guaranteed to be in the correct
logic state for VCC down to 1.15V over the temperature range.
The operation of the device can be best understood by referring to figure 3.
VCC
VRES VRES + VHYST
VCCMIN VCCMIN
RESET
TRES
Fig.2 Timing waveform
Applications Information
Negative-Going VCC Transients
In addition to issuing a reset to the µP during power-up, power-down, and brownout conditions, the
CN803/809/810 series are relatively immune to short-duration negative-going VCC transients (glitches). As
the magnitude of the transient increases (goes farther below the reset threshold), the maximum allowable
pulse width decreases. Typically, a VCC transient that goes 100mV below the reset threshold and lasts 10µs
or less will not cause a reset pulse. A 0.1µF bypass capacitor mounted as close as possible to the VCC pin
provides additional transient immunity.
Ensuring a Valid Reset Output Down to VCC = 0
When VCC falls below 1.15V, the CN809 output no longer sinks current—it becomes an open
circuit. Therefore, high-impedance CMOS logic inputs connected to can drift to undetermined
voltages. This presents no problem in most applications, since most µP and other circuitry is inoperative
with VCC below 1.15V. However, in applications where must be valid down to 0V, a pull-down
resistor is needed from pin to GND as shown in Figure 4, then output will be held at
low state. The resistor’s value is not critical, it should be about 100KΩ, large enough not to load ,
Rev 1.2 5
small enough to pull to ground.
A 100KΩ pull-up resistor to VCC is also recommended for the CN810 if active high RESET is
required to remain valid for VCC < 1.15V.
CN809
RESET
Fig.3 RESET Valid to Ground Circuit
Rev 1.2 6
Package Information
Consonance Electronics does not assume any responsibility for use of any circuitry described. Consonance
reserves the right to change the circuitry and specifications without notice at any time.
Rev 1.2 7

CN803

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CN803

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CONSONANCE

Ultra Low Power Microprocessor Reset IC

( ) is for CN810 only

www.consonance-elec.com Rev 1.2 1

Fig.1 Block Diagram For CMOS Output

1 GND Ground terminal

ABSOLUTE MAXIMUM RATINGS

unless otherwise noted.)

VCC transitions from

VRES VRES + VHYST

Fig.2 Timing waveform

Fig.3 RESET Valid to Ground Circuit

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