Microprocessor & Programming

(Theory)
CST/4/401

Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
 Unit 1
Basics of Microprocessor

1. Microprocessor
Microprocessor is a multipurpose programmable integrated device that has computing and
decision making capability. This semiconductor IC is manufactured by using LSI technique. It
includes all the functional elements of a CPU (Registers, ALU, CU) on a single chip.

2. Features of Microprocessor
(a) Cost
(b) Size - Small in size due to of LSI technique
(c) Power consumption - Low power consumption due to MOS technology
(d) Versatility - Keeping the some basic hardware, a microprocessor has wide versatility
depending on simple change in software program
(e) Reliability - High reliability due to lower chip count in the system

3. Application of Micro processor

(i) Single board microprocessor is the simplest and cheapest general purpose microcomputer
based system.
(ii) Terminals are used for communicate between a computer system and its user.
(iii) Used in personal computers.
(iv) Used in CAD machines.
(v) Used in instrumentation applications live frequency meter, function generator, spectrum
analyzer, pathological analyzer etc.
(vi) Used in distributed control system.

4. Micro controller
It is a device that includes microprocessor, memory and I/O signal lines on a single chip
fabricated using VLSI technique.

5. Micro Computer
It is a computer that is designed using a microprocessor as its CPU. It includes microprocessor,
memory and I/O.

6. Monitor program
It is a program that interprets the input from a keyboard and converts the input into its binary
equivalent.

Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
7. First Microprocessor
INTEL 4004 was the first microprocessor introduced by Intel in 1971.

8. Block diagram of Microprocessor

(i) Register Section - A set of registers for temporary storage of instructions, data and
address of data.
(ii) Arithmetic and Logic unit (ALU) - ALU is a part of microprocessor that performs
arithmetic operations (addition, subtraction, multiplication, division, increment, decrement,
compare) and logical operations (AND, OR, XOR, NOT, SHIFT/ROTATE, CLEAR).
(iii) Control Unit (CU) - CU controls and co-ordinates all the sections of microprocessor
and other devices connected to the interface section of microprocessor.
(iv) Interface Section: I/O lines through which microprocessor communicate with user. It
contains address bus, data bus, control bus and utility lines.

Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
9. Functional Block diagram of 8085 microprocessor

10. Pin Details of 8085 microprocessor

 Address Bus (AB) - 8085 microprocessor has 8 unidirectional signal lines (A8-A15) that
are used as high order A/B.
 Multiplex Address/Data Bus - Bidirectional signal lines (AD0-AD7) are used as low
order address bus and data bus.
 Control and Status Signal-
(i) Address Latch Enable (ALE) - ALE is a positive going pulse generated every time
the 8085 within an operation. This signal is used initially to latch the low order address
from the multiplex bus and generated a separate set of 8 address lines A0-A7. These
control signals may be used to latch the address information in some external register, so
that the memory or I/O devices get complete address information even after a part of it is
withdrawn by microprocessor.
(ii) RD’ - This active low read control signal is used to select the I/O or memory device is
to be read and data are available on the data bus.
Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
 (iii) WR’ - This active low write control signal is used to write data into selected memory
or I/O location.
(iv) IO/M’ - This is a status signal is to differentiate between IO and memory operations.
While it is high, it indicates I/O operation. When it is low it indicates memory operation.
(v) S1,S0. – These status signals can identify various operations.
 Power Supply and Clock frequency -
(i) VCC - +5v power supply
(ii) VSS - Ground
(iii) X1,X2 - A crystal (for RC, LC network) is connected at these two pins. The frequency
is initially divided by two pins.
(iv) CLK OUT – Clock output signal can be used as the system clock for other devices.

 Interrupt and externally initiated signals:

(i) INTR - Interrupt request is used as a general purpose interrupt.

Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
 (ii) INTA’ - Interrupt acknowledge is used to acknowledge an interrupt. Microprocessor
has two or more control signals which suspend the execution of the current program and
jump to a subroutine at a predetermined location.
(iii) RST7.5, RST6.5, RST5.5 - These restart interrupts transfer the program control to
specific memory locations. These vector interrupts has higher priorities than INTR.
(iv) TRAP - This is a non-maskable interrupt and has the highest priority.
(v) HOLD - This signal indicates DMA controller is requesting the use of the AB and
DB.
(vi) HLDA - HOLD acknowledge signal acknowledges the HOLD request.
(vii) READY - This signal is used to delay microprocessor R/W cycles until a slow
responding peripheral is ready to send or accept data.
(viii) RESTIN’ - When the signal on this pin goes low, the PC is set to 0, the buses are
tri-stated and microprocessor is reset.
(viii) RESTOUT’ - This signal is used to reset all the connected devices when the
microprocessor is reset.

11. Intel 8085 programmable register

(i) Accumulator (ACC) - It is used as a source of operands of instruction and as a
destination of result of arithmetic and logical operation. The size of the accumulator is
requiring to the size of microprocessor.
(ii) Flag Register (FR) – ALU included five flip-flops which are set or reset according to
data conditions in the ACC and the other registers .They are called Sign (S), Zero (Z),
Auxiliary Carry (AC), Parity (P), Carry (C). The flags have critical importance in decision
making process of microprocessor. It is also called Status Register / Program Status Word /
Condition Code Register.
(iii) General Purpose Register (GPR) - A register consist a set of binary storage cells or
flip-flops with parallel reading and/or writing techniques. Registers are used for temporary
storage of instruction data and address of data. 8085 microprocessor has 6 GPRs to store 8 bit
data during program execution. The registers are identified as B, C, D, E, H, L. They are also
combined as BC, DE, HL to perform 16 bit operations.
(iv) Special Purpose Register (SPR) -
(a) Stack Pointer (SP) - It is a 16 bit register used as a memory pointer. It points to a
memory location in R/W memory, called stack. Stack is an array of registers organized in
LIFO manner.
(b) Program Counter (PC) - It is used to store the address of instruction to be executed
next. The execution of a program is initialized by loading PC by address of a first
instruction to be executed, PC is automatically incremented (unless jump occurs) to point
the next instruction i.e. next memory location. Program counter is a 16 bit Special
Purpose Register.

12. Non programmable Register

(i) Memory Address Register (MAR) - Contains the address of location in memory.

Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
 (ii) Memory Buffer Register (MBR) - Contains a word of data when it is to be written in
the memory.
(iii) Instruction Register (IR) - Fetch instruction from memory to IR temporarily for
decoding.
(iv) Temporary Register (TR) - Every microprocessor contains some TR for proper
functioning of ALU.

13. Bus Structure

Buses are the group of lines use for interconnection between various building blocks within a
computing system. These lines transmit electrical signals, over them and provide communication
between these blocks. Each line is capable of transmitting one electrical pulse representing a
binary bit.
(i) Address Bus - 8085 microprocessor has 16 unidirectional AB, A15-A8 are upper address
lines & AD7-AD0 are lower address lines. If the length of the address bus is „n‟ then the
microprocessor is capable of addressing 2n memory locations.
(ii) Data Bus - 8085 microprocessor has 8 bi-directional data bus. AD7-AD0 are multiplexed
AB/DB to transfer data between CPU and peripheral devices.

Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
 Unit 2
16 bit microprocessor 8086

1. Difference between 8085 & 8086 microprocessor

8085 Microprocessor 8086 Microprocessor

(i) Based on NMOS technology. (i) Based on HMOS technology.
(ii) 16 bit address bus. (ii) 20 bit address bus.
(iii) 8 bit data bus. (iii) 16 bit data bus.
(iv) 8 lower-order address bus is (iv) 16 low order address bus
multiplexed to its data bus. multiplexed to its data bus and 4 high
order address bus is multiplexed with
control signals.
(v) Directly access 64KB memory. (v) Directly access 1MB of memory.
(vi) Accumulator and all GPRs are of 8 (vi) All registers are of 16 bits.
bits.
(vii) Multiprogramming is not possible. (vii) Allows multiprogramming.
(viii) There is no concept of physical (viii) Physical memory access is obtained
memory address and logical memory by adding the logical memory to contain
address. of a segment register multiplexed by 16.
(ix) Operates in single mode. (ix) Operates in MN/(MX)‟

2. Architecture of 8086 microprocessor

The functional block diagram of 8086 microprocessor is subdivided into two units- Execution
Unit (EU) and Bus Interface Unit (BIU).

(i) Execution unit (EU)

EU contains- ALU, eight 16b GPRS (AX, BX, CX, DX, SP, BP, SI, DI), 16b Flag Register,
CU. AX, BX, CX, and DX can be further divided into two 8b registers- AH, AL, BH, BL,
CH, CL, DH, and DL.

AX/AL - AX/AL is used as the accumulator. It is used in the multiplication, division, I/O
operations, decimal and ASCII adjustment instruction.

BX - It holds the offset address of a location in the memory.

CX/CL- CX is used to hold the count value while executing the repeated string instructions
and the loop instructions. CL is used to hold the count value while executing the shift/rotate
instructions. The count value indicates the number of times the same code has to be executed
when the loop instruction is used and the number of times the data item has to be
shifted/rotated when the SHIFT/ROTATE instruction is used.

Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
 DX - DX is used to hold a part of the result during a multiplication operation and a part of the
dividend before a division operation. It‟s also used to hold the I/O device address while
executing the IN & OUT instructions.

Stack Pointer (SP) -SP is used to hold the offset address of the data stored at the top of the
top segment, SP is used along with the SS register to decide the address at which the data is
to be pushed or popped during the execution of instruction respectively.

Base Pointer (BP) -To hold the offset address of the data to be read from or write into the
stag segment.

Source Index (SI) -SI register is used to hold the offset address of the source data in the data
segment while executing string instructions.

Destination Index (DI) -DI register is used to hold the offset address of the destination data in
the extra segment while executing string instructions.

Flag Register (FR) - In the 16 bit flag register 6 bits are used as conditional flags, 3 bits are
used as control flags and rest 7 bits are unused.

- - - - OF DF IF TF SF ZF - AF - PF - CF

Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
 (i) Carry Flag (CF) - CF holds the carry after addition / subtraction.
(ii) Parity Flag (PF) - If the lower 8bits of the result have an odd parity then PF is set to „0‟
otherwise it set to „1‟.
(iii) Auxiliary carry Flag (AF) - It indicates when an arithmetic carry or borrow has been
generated out of the four least significant bits, or lower nibble.
(iv) Zero Flag (ZF) - It indicates that the result of an arithmetic or logical operation is zero. If
Z=1 the result is zero, if Z=0 the result is not zero.
(v) Sign Flag (SF) - SF holds the arithmetic sign of the result after an arithmetic or logic
instruction is executed. If S=0 then the sign bit is „0‟ and the result is positive.
(vi) Trap Flag (TF) - It is used to debug a program using a single step technique. If TF=1
then 8086 microprocessor gets interrupted after the execution of each instruction in the
program. If TF=0 the trapping or debugging feature is disabled.
(vii) Interrupt Flag (IF) - It controls the operation of INTR interrupt pin of the 8086
microprocessor. If IF=0 then the INTR pin is disabled. If IF=1, then the INTR pin is enabled.
This flag can be set and cleared using the STI and CLI instruction respectively.
(viii) Direction Flag (DF) - It selects either the increment or decrement for the DI and/or SI
register during the execution of the string instructions. If DF=1 the registers are automatically
decremented, if DF=0 then the registers are automatically incremented.
(ix) Overflow Flag (OF) - If the result of an operation is too large for a positive number or
too small for a negative number to fit in the destination operand then the OF is set, otherwise
reset.

Arithmetic Logic Unit (ALU) - ALU is a part of microprocessor, which performs arithmetic
operations (Addition, Subtraction, Increment, Decrement, Compare) and logical operations
(OR, AND, NOT, SHIFT/ROTATE, CLEAR).

Control Unit (CU) - CU controls and coordinates all the sections of microprocessor and other
devices connected to the interface section of microprocessor.

(ii) Bus Interface Unit (BIU)

BIU contains adder, four 16 bit segment registers (CS, SD, SS,ES), 16 bit instruction pointer,
6 byte instruction queue, bus control logic.

Code Segment (CS) - It contains the instructions of a program.

Data Segment (DS) - It contains the data for the program.

Stack Segment (SS) - It holds the stack of the program which is needed while executing the
CALL and RET instructions and also to handle interrupts.

Extra Segment (ES) - It is a data segment that is used by some string instructions.

Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
 Instruction Queue (IQ) - 8086 microprocessor fetches instructions ahead of the execution
time and places them in a 6 Byte instruction queue. This pre-fetching is done when the buses
are free.

Instruction Pointer (IP) - The offsets within the code segment are referenced using the IP.
The IP sequences the instructions and always points to the next instruction to be executed.

3. Pin diagram of 8086 microprocessor

GND : Ground

AD0-AD15 : Bi-directional AD/DB. There are low order AD bus are multiplied with data

NMI : Non Musk able Interrupt request

CLK : Clock with 5/8/10 MHz

INTR : Interrupt Request

RESET : System request

Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
 READY: I/O or Memory sends acknowledgement through this pin

TEST : Wait for test control

QS1, INTA‟ : Interrupt acknowledgement

QS0, ALE : Address Latch Enable

S0, DEN‟ : Data Enable

S1, DT/R‟ : Data Transmit/Receive. When it is high data are send out, when it is low data
are received.

S2, M/IO‟ : Memory or I/O access. When it is high then CPU wants to access memory, when
it is low CPU wants to access I/O devices.

WR‟ : When it is low, CPU performs memory or IO write operation.

LOCK‟ : When it is low all interrupts are masked and no HOLD request is granted.

RQ‟/GT1‟, RQ‟/GT0‟ : Bi-directional local bus priority control. Other processors ask the CPU
through this line to release the local bus.

HLDA : Hold acknowledge. It is issued by the processor when it receives hold signal. It is
active high signal. When hold request is removed HLDA goes low.

RD‟ : This signal is used for read operation.

MN/MX‟ : It decides the operating mode of 8086 microprocessor. When it is high the CPU
operates in minimum mode, when it is low the CPU operates in maximum mode.

BHE‟/S7 : Bus High Enable/Status. It is multiplexed with status signal S7.

A16-A19 : High order Address Bus. These are multiplexed with status signals.

Vcc : +5V power supply.

4. Pipeline Architecture of 8086 Microprocessor

8086 microprocessor consist of 2 distinct blocks - EU and BIU. Both these units work
asynchronously.
Whenever EU is ready to execute a new instruction, it fetches the instruction‟s object
code from the font of the BIU‟s instruction object code queue. It then executes the instruction
in some definite number of clock cycles. If a memory or I/O device has to be accessed in the
Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
 course of an instruction, the EU informs the BIU of its needs. The BIU executes an
appropriate external access bus cycle in response to the EU‟s demand.
If there are two or more empty bytes in the instruction queue then the BIU executes an
instruction fetch cycle. BIU works independently & tries to keep the queue filled with the
instruction object codes from the program memory. If the EU issues a request for the bus
access while the BIU is in the middle of an instruction fetch bus cycle, the BIU first
completes the current instruction fetch before honoring the EU bus access request. If the
queue is full or only one byte space is empty & if there is no pending EU bus access request,
the BIU enters the idle state.

5. External memory address generation from segment offset address

(i) Fetching of an instruction from memory
Let us assume, CS=3000H, IP=2000H
Then CPU calculates the memory address from which the next instruction is to be fetch.
Base address of the code segment = CS10H =30000H
Offset values = 2000H
Effective address from where the next instruction is taken = CS10H + IP = 32000H

(ii) Fetching of data from the memory using the DS and BX register
Let us assume, DS=1000H, BX=3000H and the instruction is MOV AX,[BX] where the data
is obtained from the memory indicated by BX register is moved to the AX register.
Base address of the data segment = DS10H = 10000H
Offset values = 3000H
Effective address from where the data is taken = CS10H + IP = 13000H

(iii) Pushing data into stack segment using PUSH instruction

Let us assume SS=3000H, SP=0105H, AX=3C2BH and the instruction is PUSH AX
Initially SP is decremented by 1 that is SP becomes 0104H and a content of the AH register
is pushed into the stack segment. Then SP is again decremented by 1 that is SP becomes
0103H & the content of Al register is pushed into the offset address specified by SP in the
stack segment.
The value of AL is 2BH which will be stored in the memory location SS10H + SP = 30000H
+ 0104H = 30104H and the value of AH is 3CH which will be stored in the memory location
SS10H + SP = 30000H + 0103H = 30103H.

6. Minimum and maximum Mode Operation

There are two available modes of operation for the 8086 microprocessor - Minimum mode
and Maximum mode. Minimum mode operation is obtain by connecting the mode selection
pin MN/MX‟ to +5V and maximum mode is selected by grounding by pin. Both modes
enable different control structures for the 8086 microprocessor.
Minimum mode operation - This operation is least expensive way to operate the 8086
microprocessor. It cost less because all the control signals for the memory and I/O are

Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
 generated by the microprocessor. The pins are used in the minimum mode are – M/IO‟, WR‟,
DT/R‟, DEN‟, ALE, INTA‟, HOLD, HLDA.
Maximum mode operation - In this operation some control signals are externally
generated by 8288 bus controller. There are not enough pins on the 8086 microprocessor for
bus control during maximum mode because new pins and new features have replaced some
of them. Maximum mode is used only when the system contains external coprocessor such as
8087 arithmetic coprocessor. The pins are used in the maximum mode are – S2‟, S1‟, S0‟,
LOCK‟, RQ‟/GTO‟, RQ‟/GT1‟, QS1, QS0.

Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
 Unit 3
8086 Instruction Set

1. Addressing mode of 8086 microprocessor

The way in which operands are specified in an assembly language instruction is called it‟s
addressing mode.
(i) Register Addressing mode:
The data present in the register is moved or manipulated and the result is stored in the
register.
MOV AL, BL [AL] [BL] Byte operation
MOV AL, BH [AL]  [BH] Byte operation
MOV CH, BL [CH] [BL] Byte operation
MOV SI, BX [SI] [BX] Word operation
MOV ES, AX [ES] [AX] Word operation
MOV BX, DX [BX] [BX] + [DX] Word operation
(ii) Immediate Addressing mode:
The destination can be either a memory location or a register. The data can be
8-bit or 16-bit wide and is directly given in the instruction.
MOV AL, 50 [AL] 50H
MOV BX, 2340 [BX] 2340H
MOV [SI], 43C0 M[SI] 43C0H
MOV CL, Q [CL]  ASCII value of Q
MOV ABC, 40 [memory location with label ABC] 40H
MOV XYZ, OFC6 [memory location XYZ] OFC6H
(iii) Direct Addressing mode:
Either the source or the destination will be the memory address.
MOV AX, [2345] [AX] M[2345]
MOV [1089], AL M[1089]  [AL]
(iv) Indirect Addressing mode:
The address of the data is held in a register. The register AX as a pointer to the data.
MOV AL, [BX] [AL] M[DS] 10+[BX]]
MOV [SI], CL M[[D5]10+[SI] ] [CL]]
MOV [DI], AX M[DI] [AL], M[DI+1] <AH
(v) Register Relative Addressing mode:
In relative addressing mode a number or displacement is part of the effective address.
MOV [CL], 10[BX] [CL] M[DS]10+[BX]+10]
(vi) Base Indexed Addressing mode:
An index register and a base register together carry the effective address. The content of
these two registers are added and called the effective address.
MOV AL, [BX][SI] [AL]  M[DS]10+[BX]+[SI]]
MOV [BX][DI], CX M[DS]10+[BX]+[DI]] [CX]
(vii) Relative-Based Indexed Addressing mode:
The effective address is the sum of the Base register, Index register and displacement.

Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
 MOV DL, 5[BX][DI] [DL]  M[DS]10+[BX]+[DI]+5]
MOV 5[BP][SI],AX M[DS]10+[BP]+[DI]+5]  [AX]
2. Find the address of Physical memory for the following instructions if the
content of the registers are SS=2344H, DS=4022H, BX=0200H, BP=1402H,
SI=4442H.
(i) MOV CL, 1234H[SI] // Register Relative Addressing Mode
Here the effective address is obtained from the instruction to be the sum of the displacement
and SI i.e. the effective address is 1234H+4442H=5676H. The segment base address is
obtained from DS. The physical address is the sum of the segment base address and the
effective address i.e. 4022H×10 + 5676H=45896H

(ii) MOV AL,5H[SI][BP] // Relative Base Index Mode

Here the effective address is calculated as the sum of the displacement and the content of the
registers SI and BP i.e. effective address: 5H+4442H+1402H=5849H
The segment base address is obtained from SS. The physical address is the sum of the
segment base address and the effective address i.e. 2344H×10+5849H=28C89H

3. Find the Physical Address if DS=1112H, AX=EE78H, BX=3400H.

(i) MOV[0422],AL //direct addressing
Data segment base address = 1112H×10=11120H
Offset is=0422H.
So, Physical Address is= 11120H+0422H=11542H
Since AX=EE78H i.e. AH=EE and AL=78, so M [11542H] = 78

(ii) MOV [0422H],AX //direct addressing

Data segment base address = 1112H×10=11120H
Offset is=0422H.
So, Physical Address is= 11120H+0422H=11542H
Since AX=EE78H i.e. AH=EE and AL=78, so M [11542H] = 78 & M [11543H] = EE

4. Instruction Set of 8086 microprocessor

(I) Data Transfer Instruction
(i) MOV dest, src  Copy the content of the source to the destination.
MOV BL,50 [BL]50
MOV CX,[BX] [CX]M[[DS] ×10+[BX]]
MOV AX,CX [AX][CX]
(ii) PUSH src  Transfer one word from source to the top of the stack.
PUSH CX [TOS][CX]
PUSH DS [TOS][DS]
PUSH [BX] [TOS] M[[DS] ×10+[BX]]
(iii) POP dest  Transfer word at the TOP of the Stack to the destination.
POP CX [BX][TOS]

Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
 POP DS [DS][TOS]
POP [SI] M[SI][TOS]
(iv) XCHG dest, src  Exchange the contents of the destination and source.
XCHG AL,BL [AL][BL]
XCHG CX,BX [CX][BX]
XCHG AX,[BX] [AX]M[[DS] ×10+[BX]]
(v) XLAT  Replaces the byte in AL with byte from a user table, addressed
by BX.
(vi) IN  Copies data from a port to the AL or AX register.
IN AL,80 [AL]  Port[80] // Byte transfer
IN AX,80 [AX]  Port[80] // Word transfer
(vii) OUT  Transfer a byte from AL or a word from AX to the specified port.
OUT 48,AL Port[48]  [AL] // Byte transfer
IN F0,AX Port[F0]  [AX] // Word transfer
(viii) LEA reg16,mem Load effective address i.e. load the offset of specified memory
location in the 16-bit register.
LEA BX, ABC Load BX with the offset address of ABC in the data
segment where ABC is the name assigned to a memory
location in the data segment.
LEA CX, [BX],[SI] Load CX with the value= [BX]+[SI]
(ix) LDS reg16,mem  Copies a word from the memory location specified in the
instruction into the register and then copies a word from the
next memory location in the DS register.
LDS SI, 2000 Copy the content of the memory at the offset address 2000
in DS to the lower order byte of SI and the content of 2001
to the higher order byte of SI. Copy the content at the offset
address 2002 in the data segment to the lower order byte of
DS and the content of 2003 to the higher order byte of DS.
(x) LES reg16,mem  Load far pointer to ES and register.
(xi) LSS reg16,mem  Load far pointer to SS and register.
(xii) LAHF  Copies the lower order byte of the flag registers into AH.
(xiii) SAHF  Stores the content of AH in the lower order byte of the flag
register.

(II) Arithmetic Instruction

(i) ADD dest, src  ADD destination and source.
ADD BL, 80 [BL]  [BL]+80
ADD CX, 1280 [CX]  [CX]+1280
ADD AX, CX [AX]  [AX]+[CX]
ADD AL, [BX] [AL]  [AL] + M[[DS] 10 +[BX]]
ADD CX, [SI] [CX]  [CX] + M[[DS] 10 +[SI]]
ADD [BX], DL M[[DS]10 +[BX]] [DL] + M[[DS] 10 +[BX]]
(ii) ADC dest,src  ADD destination, source and CF
(iii) SUB dest,src  Subtract source form destination
SUB AL, BL [AL] [AL]-[BL]
Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
 SUB CX, BX [CX] [CX]-[BX]
SUB BX, [DI] [BX] [BX]-M[[DS]10 + [DI]]
SUB [BP], DL M[[DS]10 + [BP] ]  M[[DS]  10+[BP]] – [DL]
(iv) SBB dest, src  Subtracts source and CF from destination
(v) INC dest  Add 1 to the destination.
INC CL [CL] ← [CL] +1
INC AX [AX] ← [AX]+1
(vi) DEC dest  Subtract 1 from destination
(vii) NEG dest  2‟s complement negation
NEG CL [CL] ← 2‟s complement of [CL]
NEG AX [AX] ← 2‟s complement of [AX]
(viii) CMP dest, src  subtract source from destination and updates the flags but does
not save result, only flags are affected.
(ix) MUL src  Unsigned multiplication
MUL CH [AX] ← [AL] × [CH]
MUL BX [DX-AX] ← [AX] × [BX] i.e. MSB is stored in DX and
LSB is stored in AX
(x) IMUL src  Signed multiplication
IMUL BL [AX] ← [AL] × [CH]
IMUL AX [DX-AX] ← [AX] × [BX]
(xi) DIV src  Unsigned binary division.
DIV DL Divide the word in AX by the byte in DL. The quotient is
stored in AL and the remainder are stored in AH.
DIV CX Divide the double word (32 bits) in DX-AX by the word in
CX. The Quotient is stored in AX and the remainder is
stored in DX.
(xi) IDIV src  Signed integer division.
(xii) DAA  Decimal adjust AL after BCD addition
(xiii) DAS  Decimal adjust after BCD subtraction
(xiv) AAA  ASCII adjust for addition.
(xv) AAS  ASCII adjust for subtraction
(xvi) AAM  ASCII adjust for multiplication
(xvii) AAD  ASCII adjust for division

(III) Logical Instruction

(i)AND  Performs Logical AND operation between the corresponding
bits in the source and destination and stores the result in the
destination.
(ii)OR  Performs Logical OR operation between the corresponding bits
in the source and destination and stores the result in the
destination.
(iii)XOR  Performs Logical XOR operation between the corresponding
bits in the source and destination and stores the result in the
destination.
(iv)NOT  Inverts each bit of the byte on word at a specified destination.
Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
 (v)TEST  To test whether a bit is set or not.

(IV) Flag Manipulation Instruction

(i) LAHF  Load the lower order byte of the flag register in AH.
(ii) SAHF  Store AH in the lower order byte of the flag register.
(iii) PUSHF  Push the flag register content onto the Stack.
(iv) POPF  Pop the top word from the stack onto the flag register.
(v) CMC  Complement the carry flag.
(vi) CLC  Clear the carry flag. (CF=0)
(vii) STC  Set the carry flag. (CF=1)
(viii) CLD  Clear the direction flag. (DF=0)
(ix) STD  Set the direction flag. (DF=1)
(x) CLI  Clear the interrupt flag. (IF=0)
(xi) STI  Set the interrupt flag. (IF=1)

(V) Control Transfer (Branch) Instruction

(i) JMP addr  Jump unconditionally to address.
(ii) CALL addr  Call the procedure or subroutine starting an address.
(iii) RET  Return from procedure or subroutine.
(iv) JA addr  Jump if above to address. (Jump if CF=ZF=0)
(v) JLE  Jump if above or equal to address. (Jump if CF=0)
(vi) JB addr  Jump if below to address. (Jump if CF=1)
(vii) JBE addr  Jump if below or equal to address. (Jump if CF=1, ZF=1)
(viii) JC addr  Jump if carry to address.
(ix) JCXZ addr  Jump if CX=0 to address.
(x) JE addr  Jump if equal to address. (jump if ZF=1)
(xi) JG addr  Jump if greater to address. (Jump if ZF=0, SF=OF)
(xii) JGE addr  Jump if greater or equal to address. (Jump if SF=OF)
(xiii) JL addr  Jump if leaser to address. (Jump if SFOF)
(xiv) JLE addr  Jump if leaser or equal to address. (Jump if ZF=1 or SFOF)
(xv) JNA addr  Jump if not above to address. (Jump if CF=1, ZF=1)
(xvi) JNAE addr  Jump if not above or equal to addr (jumps if CF=1).
(xvii) JNB addr  Jump if not below to addr (jumps if CF=0).
(xviii) JNBE addr  Jump if not below or equal to addr (Jumps if CF=ZF=0).
(xix) JNC addr  Jump if no carry to addr (Jumps if CF=0).
(xx) JNE addr  Jump if not equal to addr (Jumps if ZF=0).
(xxi) JNG addr  Jump if not greater to addr (Jumps if ZF=1 or SF ≠ OF).
(xxii) JNGE addr  Jump if not greater or equal to addr (Jump if SF ≠ OF).
(xxiii) JNL addr  Jump if not lesser to addr (Jumps if SF=OF).
(xxiv) JNLE addr  Jump if not lesser or equal to addr (Jumps if ZF=0 or SF=OF).
(xxv) JNO addr  Jump if no overflow to addr (Jumps if OF=0).
(xxvi) JNP addr  Jump if no parity to addr (Jumps if PF=0).
(xxvii) JNS addr  Jump if no sign to addr (Jumps if SF=0).
(xxviii) JNZ addr  Jump if no zero to addr (Jumps if ZF=0).
(xxix) JO addr  Jump if overflow to addr (Jumps if OF=1).

Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
 (xxx) JP addr  Jump if parity to addr (Jumps if PF=1).
(xxxi) JPE addr  Jump if parity is even to addr (Jumps if PF=1).Jump if parity is
even to addr (Jumps if PF=1).
(xxxii) JPE addr  Jump if parity is odd to addr (Jumps if PF=0).
(xxxiii) JS addr  Jump if sign to addr (Jumps if SF=1).
(xxxiv) JZ addr  Jump if zero to addr (Jumps if ZF=1).

(VI) Shift/Rotate Instruction

The shift/rotate instruction performs logical left shift and right shift operation (on unsigned
data) and arithmetic left shift and right shift operation (on signed data).
(i) SAL/SHL
SAL AX, 1 Shift left [AX] by 1 bit.
SAL BL, 1 Shift left [BL] by 1 bit.
SAL BYTE PTR [SI],1 Shift left the byte content of the memory at [SI] by
1 bit.
SAL WORD PTR [BX],1 Shift left the word content of the memory at [BX]
by 1 bit.
(ii) SAR  It shifts each bit in the destination a specify number of bit
positions to the right.
(iii) SHR  The destination can be a register or a memory location and a
byte or a word.
(iv) ROR  This instruction rotates all the bits of the bit of the specified
byte or word by a specified number of bit positions to the right.
ROR CH, 1 Rotate right the byte in CH by 1 bit position.
ROR BX, CL Rotate right the word in BX by the number of bit positions
given by CL.
(v) ROL  ROL rotates all the bits in a byte or word in the destination to
the left by 1 or more bit positions using CL.
(vi) RCR  RCR rotates the bytes or word in the destination right through
the CF either by 1 bit position or by the number of bit positions
given by CL.
(vii) RCL  RCL rotates the byte or word in the destination left through CF
either by 1 bit position or by the number of bit positions given
by CL.

(VII) String Instruction

The string instruction operates on elements of strings, bytes or words. The register SI
contains the offset address of an element (Byte or word) in the source string, which is present
in the data segment. The register DI contains the offset address of an element (Byte or word)
in the destination string, which is present in the extra segment. After each string operation SI
and/or DI are automatically incremented or decrement by 1 or 2, for byte or word operation
respectively, according to the D flag in the flag register.
(i) MOV SB  Move the string byte from DS:[SI] to ES:[DI].
(ii) MOV SW  Move the string word from DS:[SI] to ES:[DI].
(iii) CMP SB  Compare string bytes (done by subtracting the byte at ES:[DI]

Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
 from the byte at DS:[SI]). Only flags are affected, the content of
the bytes compared is unaffected.
(iv) CMP SW  Compare string words (done by subtracting the byte at ES:[DI]
from the byte at DS:[SI]). Only flags are affected, the content of
the words compared is unaffected.
(v) LODSB  Load the string byte at DS:[SI] into AL.
(vi) LODSW  Load the string word at DS:[SI] into AX.
(vii) STOSB  Store the string byte in AL at ES:[DI]
(viii) STOSW  Store the string word in AX at ES:[DI]
(ix) SCASB  Compare string bytes (done by subtracting the byte at ES:[DI]
from the byte at AL). Only flags are affected, the content of the
byte compared is unaffected.
(x) SCASW  Compare string word (done by subtracting the byte at ES:[DI]
from the byte at AX). Only flags are affected, the content of the
bytes compared is unaffected.
(xi) REP  Decrement CX and repeat the following string operation of
CX≠0
(xii) REPE or REPZ  Decrement CX and repeat the following string operation of
CX≠0 and ZF=1
(xiii) REPNE or REPNZ  Decrement CX and repeat the following string operation of
CX≠0 and ZF=0

(VIII) Machine or Processor Control Instruction

(i) HLT  Stops the execution of all instructions and places the processor
in halt state.
(ii) LOCK  Provides the processor and exclusive hold on the use of the
system bus.
(iii) NOP  This no operation instruction is used to insert a delay in
software delay programs.
(iv) ESC  Pass instructions to a co-processor such as the 8087, which
shares the address and data bus with an 8086 microprocessor.
(v) WAIT  When this instruction is executed, 8086 microprocessor checks
the status of its TEST‟ input pin and if the TEST‟ input is high,
it enters and idle condition during which it does not do any
processing. The 8086 microprocessor remains in this state until
the 8086 microprocessor‟s TEST‟ input pin is made low or an
interrupt signal is received on the INTR or NMI pins.

Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
 Unit 4
The Art of Assembly Language Programming

1. Line Assembler
It converts each mNemonic of an instruction immediately into an opcode as it is entered in the
system and this type of assembler is used in microprocessor trainer kit. The line assembler is
stored in any one of the ROM type memories in the trainer kit. The assembler needs a personal
computer for generating the opcodes of an assembly language program. The generated opcodes
can be downloaded to the microprocessor based system such as the microprocessor trainer kit or
the microprocessor based prototype hardware through the serial or parallel port of the computer.

2. Assembler Directive
MASM (Microsoft Macro Assembler), TASM (Turbo Assembler) and DOS Assembler are used
to convert the 8086 assembly language program into machine language program. Assembler
directives are commands to the assembler to indicate the size of a variable (either byte or word),
number of bytes or words to be reserved in the memory, value of a content, name of a segment
etc. in a program. Assembler directives are not converted directly into opcode, but are used to
generate the proper opcode of an instruction.

The Assembler Directives commonly are used as follows –

(i) Assembler Directives for variable and constant definition
eg.: CITY DB “Kolkata”  stores the ASCII codes of the characters specified within
double quotes in the array or list name CITY.

(ii) Assembler Directives related to program location

eg.: ORG 100H  when these directives are placed at the beginning of the
code segment, the location counter is initialized with 0100H
and the first instruction is stored from the offset address 0100H
within the code segment. If it is placed in the data segment, the
next data storage starts from the offset address 0100H within
the data segment.

(iii) Assembler Directives for segment declaration

eg.: ASSUME CS: CODE1, DS: DATA1  this statement informs assembler that the
segment address where the logical segments
CODE1 and DATA1 are loaded in memory during
execution is to be stored in the CS and DS registers
respectively.

(iv) Assembler Directives for declaring procedures

eg.: SQUARE_ROOT PROC NEAR  this statement indicates the beginning of a
procedure SQUARE_ROOT, which is to be called
by program, located in the same segment.
Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
3. Model Directive
The model directive selects a standard memory model for the program. It determines the way
segments are linked together, as well as the maximum size of each segment.

Model Description
Tiny Code and data together may not be greater than 64k
Small Neither code nor data may be greater than 64k
Medium Only the code may be greater than 64k
Compact Only the data may be greater than 64k
Large Both code and data may be greater than 64k
Huge All available memory can be used for code and data

4. Linker program
The linker program, which executes of the second part of machine language, reads the object
files, created by the assembler programs and links them into a single execution file.

5. Debugger
A debugger is a software supported by IDE and is used to test, run and debug the user written
programs. The application code developed by the programmer can be examined by running or
executing the code on an Instruction Set Simulator (ISS). The debugger allows the user to halt
the program simulation when specific conditions are encountered. Debugger provides the facility
to run a program step by step (single stepping) and stopping (breaking) the program at user
define points, modify state of the program.

Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
 Unit 5
Procedure and Macro

1. Procedure
When a group of instructions are to be used several times to perform a same function in a
program then we can write them as a separate sub program called procedure or subroutine.
The procedures are written or assembled as separate program modules and stored in
memory. When a procedure is called in main program, the program control is transferred to
procedure and after executing the procedure the program control is transferred back to the main
program.
In 8086 microprocessor, the instruction CALL is used to call a procedure in the main
program and the instruction RET is used to return the control to the main program.
A procedure begins with the PROC directive and ends with the ENDP directive. Each directive
appears with the name of the procedure. The PROC directive is followed by the type of
procedure- NEAR or FAR.
The main advantage of using a procedure is that the machine codes for the group of
instructions in the procedure has to be put in memory only once. The disadvantages of using the
procedure are the need for a stack, and the overload time required to call the procedure and
return to the calling program.

2. CALL
The CALL instruction transfers the flow of the program to the procedure. The CALL instruction
defers from the JUMP instruction because a call saves a return address on the stack. The return
address returns control to the instruction that immediately follows the call in the program when a
RET instruction executes.
8086 microprocessor has two types of CALL instructions and they are – Intransigent
CALL (NEAR CALL) and Intersegment CALL (FAR CALL). A procedure can be called using
NEAR CALL instruction if it is stored in the same segment where the main program is also
stored. A procedure can be called using FAR CALL instruction if the procedure and main
program are stored in different memory segment.
NEAR CALL instruction is 3B long, the first byte contains opcode, 2nd and 3rd byte
contain the displacement. When the NEAR CALL executes, it first pushes the offset address of
the next instruction on the stack. The offset address of the next instruction appears in the
Instruction Pointer (IP). After saving the return address, it then adds the displacements from
bytes 2 and 3 to the IP to transfer control to the procedure.
FAR CALL instruction calls a procedure to store in any memory location in the system.
The FAR CALL is a 5B instruction that contains an opcode followed by the next value for the IP
and CS registers. Bytes 2 and 3 contain the new contents of the IP and bytes 4 and 5 contain the
new contents of CS. FAR CALL places the contents of both IP and CS on the stack before
jumping to the address indicated by bytes 2-5 of the instruction. This allows the FAR CALL to
call a procedure located any where in the memory and return from the procedure.

Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
3. RET
RET instruction is placed at the end of the procedure to return the CPU to the calling location. If
the calling location is in the same segment, RET pops the stack into IP and increments SP. This
causes the program to continue execution at the new address in IP.
8086 microprocessor has two types of RET instruction and they are - NEAR RETURN
and FAR RETURN. The NEAR RETURN instruction is used to terminate a procedure stored in
the same segment. The FAR RETURN instruction is used to terminate a procedure stored in a
different segment.

4. MACRO
When a group of instruction are to be used several times to perform a same function in a program
and they are too small to be written as a procedure, then they can be defined as a MACRO.
MACRO is a small group of instructions enclosed by the assembler directives macro and
ENDM. Macros are identified by their names and usually defined at the start of a program.
The macro is called by its name in the program. Whenever a macro is called in a
program, the assembler will insert the defined group of instructions in place of the CALL.
The disadvantage of using macro is that the program may take up more memory space
due to insertion of the machine codes in the program at the place of Macros. Hence, the macros
should be used only when its body has a few program statements.

5. Differences between PROCEDURE and MACRO

PROCEDURE MACRO
(i) Access by CALL and RET mechanism (i) Accessed during assembly with name
during program execution. given to macro when defined.
(ii) Machine code for instructions are stored (ii) Machine codes are generated for
in memory once. instructions in the macro each time it is
called.
(iii) Parameters are passed in registers, (iii) Parameters are passed as part of
memory locations or stack. statement which calls macro.

6. DOS interrupt
DOS provides a large number of procedures to access devices, files, memory and process control
services. These procedures can be called in any user program using software interrupts “INT n”
instruction. The various DOS interrupts are as follows-
Interrupt Service provide by interrupt Interrupt Service provide by interrupt
type type
INT-20H Program Terminate INT- 26H Absolute Disk Write
INT-21H DOS System Call INT-27H Terminate and Stay Resident (TSR)
INT -22H Terminate Address INT-28H DOS time slice
INT-23H Control Break Address INT-2EH Perform DOS command

Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
INT-24H Critical Error Handler Address INT-2FH Multiplexed Interrupts
INT-25H Absolute Disk Read
Unit 6
System Interfacing

1. Comparison between Memory Mapping and I/O Mapping of I/O devices

Memory Mapping of I/O devices I/O Mapping of I/O devices

(i) 20-bit addresses are provided for I/O (i) 8-bit or 16-bit addresses are provided for
devices. I/O devices.
(ii) The I/O ports or peripherals can be (ii) Only IN and OUT instructions can be
treated like memory locations and so all used for data transfer between I/O device and
instructions related to memory can be used the processor.
for data transfer between I/O device and the
processor.
(iii) In memory mapped ports, the data can be (iii) In I/O map ports the data transfer can
moved from any register to the ports and take place only between the accumulator and
vice versa. the ports.
(iv) When memory mapping is used for I/O (iv) When I/O mapping is used for I/O
devices the full memory address space devices, then the full memory address can be
cannot be used for addressing memory. used for addressing memory. Hence, it is
Hence, memory mapping is useful only for suitable for systems which requires large
small systems, where the memory memory capacity.
requirement is less.
(v) For accessing the memory mapped (v) For accessing the I/O mapped devices the
devices, the processor executes memory read processor executes I/O read or write cycle.
or write cycle. During this cycle M/IO‟ During This cycle M/IO‟ becomes low.
becomes high.

2. Programmable Peripheral Interface (IC-8255)

Intel 8255 IC is used the implement parallel data transfer between processor and slow peripheral
devices like ADC, DAC, keyboard, 7-segment display, LCD etc.

Features-
(i) It has three 8 bit ports- A, B and C connected to the output pins.
(ii) Port C is divided into two groups, Port C upper (PCU) and Port C lower (PCL) of 4 bits
each. Each of them can be programmed independently or as 4 bit ports for input and output
operations.
(iii) All the ports can be programmed for simple I/O or handshake I/O in the I/O mode.
(iv) Each port C can be set/reset individually in bit set/reset mode.
(v) The bits of Port A and PCU are grouped as group A (GA).
(vii) The bits of Port B and PCU are grouped as group B (GB).

Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
The three operating modes are-
(i) Mode-0: In this mode all the three ports can be programmed either as input or output port.
The outputs are latched and the inputs are not latched. The ports do not have handshake or
interrupt capability. The ports in mode-0 can be used to interface DIP switches, Hex-keypad,
LEDs and 7-segment LEDs to the processor.
(ii) Mode-1: In this mode only ports A and B can be programmed either as input or output port.
Handshake signals are exchanged between the processor and peripheral prior to data transfer.
The port C pins are used for handshake signals, Input and output data are latched. Interrupt
driven data transfer is possible.
(iii) Mode-2: In this mode port will be a bi-directional port i.e. the processor can perform both
read and write operations with and I/O device connected to a port in mode-2. Only port A can be
programmed work in mode-2. Five-pins of Port C are used for handshake signals. This mode is
used primarily in applications such as data transfer between two computers or floppy disk
controller interface.

Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
3. Programmable Interrupt Control (IC-8259)
For applications that used interrupt from multiple sources, the hardware can use an external
device called Programmable Interrupt Controller or Priority Interrupt Controller (8259).

Features-
(i) It is programmed to work with either 8085 or 8086 processor.
(ii) It manages 8 interrupts according to the instructions written into its control register.
(iii) In an 8086 processor based system, it supplies the type number of the interrupt and the
type number is programmable. In an 8085 processor based system, it vectors an interrupt
request anywhere in the memory map and the interrupt vector address is programmable.
(iv) The priorities of the interrupts are programmable. The different operating modes which
decide the priorities are automatic rotation mode, specific rotation mode and fully nested
mode.
(v) The interrupts can be masked or unmasked individually.
(vi) 8259 is programmed to accept either level-triggered interrupt signal or edge-triggered
interrupt signal.
(vii) 8255 provides the status of the pending interrupts, masked interrupts and the interrupt
being serviced.
(viii) 8259 can be cascaded to accept a maximum of 64-interrupt.

Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School
4. DMA Controller (8237/8257)
Direct Memory Access (DMA) is used to provide high-speed data transfer directly between the
memory and peripheral devices without the intervention of the microprocessor. This method is
often used when a huge volume of data is to be transferred. DMA data transfer is controlled
using a separate DMA controller. The microprocessor must be disabled during the DMA data
transfer process. To start the DMA process, the microprocessor loads an external register in the
DMA controller with the data files starting address and the terminal count register with the total
number of bytes to be transferred. The microprocessor disabled the address and data buses and
gives memory system control to the DMA controller. The DMA controller places sequential
addresses on the microprocessor‟s memory bus and issues the read/write pulses. As each byte is
transferred the terminal count register is decremented. When the register is decremented to 0, it
tells the external device that the data transfer is complete.

Features-
(i) 4 independent DMA channels.
(ii) Enable or disable control of individual requests.
(iii) Possibility of memory to memory transfer.
(iv) Address increment or decrement.
(v) Cascading into expand to any number of DMA channels.

Prepared by – Kinshuk Majumder, Lecturer, CST Dept., The Calcutta Technical School