VN920-E

VN920B5-E / VN920SO-E

HIGH SIDE DRIVER

Table 1. General Features Figure 1. Package

Type RDS(on) IOUT VCC
VN920-E
VN920B5-E 16mΩ 30 A 36 V
VN920SO-E

PENTAWATT P2PAK
■ CMOS COMPATIBLE INPUT
■ PROPORTIONAL LOAD CURRENT SENSE

■ SHORTED LOAD PROTECTION

■ UNDERVOLTAGE AND OVERVOLTAGE

SHUTDOWN
■ OVERVOLTAGE CLAMP
SO-16L
■ THERMAL SHUTDOWN

■ CURRENT LIMITATION

■ PROTECTION AGAINST LOSS OF GROUND Active current limitation combined with thermal
AND LOSS OF VCC shutdown and automatic restart protect the device
against overload. The device integrates an analog
■ VERY LOW STAND-BY POWER DISSIPATION current sense output which delivers a current
■REVERSE BATTERY PROTECTION (*) proportional to the load current. Device
■IN COMPLIANCE WITH THE 2002/95/EC automatically turns off in case of ground pin
disconnection.
EUROPEAN DIRECTIVE

DESCRIPTION
The VN920-E, VN920B5-E, VN920SO-E is a
monolithic device made by using
STMicroelectronics VIPower M0-3 Technology,
intended for driving any kind of load with one side
connected to ground. Active VCC pin voltage
clamp protects the device against low energy
spikes (see ISO7637 transient compatibility table).

Table 2. Order Codes

Package Tube Tape and Reel

PENTAWATT VN920-E -
2
P PAK VN920B5-E VN920B5TR-E
SO-16L VN920SO-E VN920SOTR-E

Note: (*) See application schematic at page 9.

Rev. 1
October 2004 1/24
VN920-E / VN920B5-E / VN920SO-E

Figure 2. Block Diagram

VCC

VCC OVERVOLTAGE
CLAMP DETECTION

UNDERVOLTAGE
DETECTION

GND
Power CLAMP

DRIVER
OUTPUT
INPUT LOGIC
CURRENT LIMITER

VDS LIMITER

IOUT CURRENT
K SENSE
OVERTEMPERATURE
DETECTION

Table 3. Absolute Maximum Ratings

Value
Symbol Parameter Unit
PENTAWATT P2PAK SO-16L
VCC DC Supply Voltage 41 V
- VCC Reverse DC Supply Voltage - 0.3 V
- IGND DC Reverse Ground Pin Current - 200 mA
IOUT DC Output Current Internally Limited A
- IOUT Reverse DC Output Current - 21 A
IIN DC Input Current +/- 10 mA
Current Sense Maximum Voltage -3 V
VCSENSE
+15 V
Electrostatic Discharge
(Human Body Model: R=1.5KΩ; C=100pF)
- INPUT 4000 V
VESD
- CURRENT SENSE 2000 V
- OUTPUT 5000 V
- VCC 5000 V
Maximum Switching Energy
EMAX 364 352 mJ
(L=0.25mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IL=45A)
PTOT Power Dissipation TC≤25°C 96.1 96.1 8.3 W
Tj Junction Operating Temperature Internally limited °C
Tc Case Operating Temperature - 40 to 150 °C
TSTG Storage Temperature - 55 to 150 °C

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 VN920-E / VN920B5-E / VN920SO-E

Figure 3. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins

VCC 1 16 VCC
N.C. OUTPUT
OUTPUT 5 OUTPUT
5 GND OUTPUT
4 CSENSE 4 CSENSE
VCC
INPUT OUTPUT
3 3 VCC
INPUT CSENSE OUTPUT 2 INPUT
2
1 GND N.C. OUTPUT 1 GND
N.C. OUTPUT
VCC 8 9 VCC

PENTAWATT SO-16L P2PAK

Connection /
Current Sense N.C. Output Input
Pin
Floating X X X
To Ground Through 1KΩ resistor X Through 10KΩ resistor

Figure 4. Current and Voltage Conventions

IS

VCC VF VCC

IOUT
OUTPUT
IIN VOUT
INPUT
VIN ISENSE
CURRENT SENSE
VSENSE
GND

IGND

Table 4. Thermal Data

Value
Symbol Parameter Unit
PENTAWATT P2PAK SO-16L
Rthj-case Thermal Resistance Junction-case Max 1.3 1.3 °C/W
Rthj-lead Thermal Resistance Junction-lead Max 15 °C/W
51.3 (1) 65 (3) °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 61.3
37 (2) 48 (4) °C/W

(1) When mounted on a standard single-sided FR-4 board with 0.5cm 2 of Cu (at least 35µm thick).
(2) When mounted on a standard single-sided FR-4 board with 6cm 2 of Cu (at least 35µm thick).
(3) When mounted on a standard single-sided FR-4 board with 0.5cm 2 of Cu (at least 35µm thick) connected to all VCC pins.
(4) When mounted on a standard single-sided FR-4 board with 6cm 2 of Cu (at least 35µm thick) connected to all VCC pins.

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ELECTRICAL CHARACTERISTICS (8V<VCC<36V; -40°C<Tj<150°C unless otherwise specified)

Table 5. Power
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VCC Operating Supply Voltage 5.5 13 36 V
VUSD Undervoltage Shut-down 3 4 5.5 V
VOV Overvoltage Shut-down 36 V
IOUT=10A; Tj=25°C 16 mΩ
On State Resistance
RON IOUT=10A 32 mΩ
IOUT=3A; VCC=6V 55 mΩ
Vclamp Clamp Voltage ICC=20mA (See note 1) 41 48 55 V
Off State; VCC=13V; VIN=VOUT=0V 10 25 µA
Supply Current Off State; VCC=13V; VIN=VOUT=0V; 10 20 µA
IS Tj=25°C
On State; VCC=13V; VIN=5V; IOUT=0A;
RSENSE=3.9KΩ 5 mA

IL(off1) Off State Output Current VIN=VOUT=0V 0 50 µA

IL(off2) Off State Output Current VIN=0V; VOUT=3.5V -75 0 µA
IL(off3) Off State Output Current VIN=VOUT=0V; VCC=13V; Tj=125°C 5 µA
IL(off4) Off State Output Current VIN=VOUT=0V; VCC=13V; Tj=25°C 3 µA
Note: 1. Vclamp and VOV are correlated. Typical difference is 5V.

Table 6. Switching (VCC =13V)

Symbol Parameter Test Conditions Min. Typ. Max. Unit
td(on) Turn-on Delay Time RL=1.3Ω (see figure 6) 50 µs
td(off) Turn-off Delay Time RL=1.3Ω (see figure 6) 50 µs
See
dVOUT/
Turn-on Voltage Slope RL=1.3Ω (see figure 6) relative V/µs
dt(on)
diagram
See
dVOUT/
Turn-off Voltage Slope RL=1.3Ω (see figure 6) relative V/µs
dt(off)
diagram

Table 7. Logic Input

Symbol Parameter Test Conditions Min. Typ. Max. Unit
VIL Input Low Level 1.25 V
IIL Low Level Input Current VIN=1.25V 1 µA
VIH Input High Level 3.25 V
IIH High Level Input Current VIN=3.25V 10 µA
VI(hyst) Input Hysteresis Voltage 0.5 V
IIN=1mA 6 6.8 8 V
VICL Input Clamp Voltage
IIN=-1mA -0.7 V

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 VN920-E / VN920B5-E / VN920SO-E

ELECTRICAL CHARACTERISTICS (continued)

Table 8. VCC - Output Diode
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VF Forward on Voltage -IOUT=2A; Tj=150°C 0.6 V

Table 9. Protections (see note 1)

Symbol Parameter Test Conditions Min Typ Max Unit
TTSD Shut-down Temperature 150 175 200 °C
TR Reset Temperature 135 °C
Thyst Thermal Hysteresis 7 15 °C
VCC=13V 30 45 75 A
Ilim DC Short Circuit Current
5V<VCC<36V 75 A
Turn-off Output Clamp
Vdemag IOUT=2A; VIN=0V; L=6mH VCC-41 VCC-48 VCC-55 V
Voltage
Output Voltage Drop
VON IOUT=1A; Tj=-40°C....+150°C 50 mV
Limitation

Note: 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be
used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration
and number of activation cycles.

Table 10. Current Sense (9V≤VCC≤16V) (See Fig. 5)

Symbol Parameter Test Conditions Min Typ Max Unit
IOUT=1A; VSENSE=0.5V;
K1 IOUT/ISENSE 3300 4400 6000
Tj= -40°C...150°C
IOUT=1A; VSENSE=0.5V;
dK1/K1 Current Sense Ratio Drift -10 +10 %
Tj= -40°C...+150°C
IOUT=10A; VSENSE=4V; Tj=-40°C 4200 4900 6000
K2 IOUT/ISENSE
Tj=25°C...150°C 4400 4900 5750
IOUT=10A; VSENSE=4V;
dK2/K2 Current Sense Ratio Drift -8 +8 %
Tj=-40°C...+150°C
IOUT=30A; VSENSE=4V; Tj=-40°C 4200 4900 5500
K3 IOUT/ISENSE
Tj=25°C...150°C 4400 4900 5250
IOUT=30A; VSENSE=4V;
dK3/K3 Current Sense Ratio Drift -6 +6 %
Tj=-40°C...+150°C

Analog Sense Leakage VCC=6...16V; IOUT=0A;VSENSE=0V;

ISENSEO 0 10 µA
Current Tj=-40°C...+150°C

Max Analog Sense Output VCC=5.5V; IOUT=5A; RSENSE=10KΩ 2 V

VSENSE
Voltage VCC>8V; IOUT=10A; RSENSE=10KΩ 4 V
Sense Voltage in
VSENSEH Overtemperature VCC=13V; RSENSE=3.9KΩ 5.5 V
conditions
Analog Sense Output
Impedance in
RVSENSEH VCC=13V; Tj>TTSD; Output Open 400 Ω
Overtemperature
Condition
Current sense delay
tDSENSE to 90% ISENSE (see note 2) 500 µs
response

Note: 2. current sense signal delay after positive input slope.

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Figure 5. IOUT/ISENSE versus IOUT

IOUT/ISENSE

6500

6000
max.Tj=-40°C
5500
max.Tj=25...150°C
5000

min.Tj=25...150°C typical value

4500

4000 min.Tj=-40°C

3500

3000
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32

IOUT (A)

Figure 6. Switching Characteristics (Resistive load RL=1.3Ω)

VOUT

90%
80%

dVOUT/dt(on) dVOUT/dt(off)

tr 10% tf

t
ISENSE

90%

t
tDSENSE
INPUT
td(on) td(off)

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 VN920-E / VN920B5-E / VN920SO-E

Table 11. Truth Table

CONDITIONS INPUT OUTPUT SENSE

L L 0
Normal operation Nominal
H H
L L 0
Overtemperature
H L VSENSEH
L L 0
Undervoltage
H L 0
L L 0
Overvoltage
H L 0
L L 0
Short circuit to GND H L (Tj<TTSD) 0
H L (Tj>TTSD) VSENSEH
L H 0
Short circuit to VCC
H H < Nominal
Negative output voltage
L L 0
clamp

Table 12. Electrical Transient Requirements On VCC Pin

TEST LEVELS
ISO T/R 7637/1
Delays and
Test Pulse I II III IV
Impedance
1 -25 V -50 V -75 V -100 V 2 ms 10 Ω
2 +25 V +50 V +75 V +100 V 0.2 ms 10 Ω
3a -25 V -50 V -100 V -150 V 0.1 µs 50 Ω
3b +25 V +50 V +75 V +100 V 0.1 µs 50 Ω
4 -4 V -5 V -6 V -7 V 100 ms, 0.01 Ω
5 +26.5 V +46.5 V +66.5 V +86.5 V 400 ms, 2 Ω

ISO T/R 7637/1 TEST LEVELS RESULTS

Test Pulse I II III IV
1 C C C C
2 C C C C
3a C C C C
3b C C C C
4 C C C C
5 C E E E

CLASS CONTENTS
C All functions of the device are performed as designed after exposure to disturbance.
E One or more functions of the device is not performed as designed after exposure to disturbance
and cannot be returned to proper operation without replacing the device.

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Figure 7. Waveforms

NORMAL OPERATION
INPUT
LOAD CURRENT
SENSE

UNDERVOLTAGE
VCC
VUSDhyst
VUSD
INPUT
LOAD CURRENT
SENSE

OVERVOLTAGE

VOV
VCC
VCC > VUSD VOVhyst
INPUT
LOAD CURRENT
SENSE

SHORT TO GROUND
INPUT
LOAD CURRENT
LOAD VOLTAGE
SENSE

SHORT TO VCC
INPUT
LOAD VOLTAGE
LOAD CURRENT
SENSE
<Nominal <Nominal

OVERTEMPERATURE
TTSD
Tj
TR

INPUT
LOAD CURRENT
VSENSEH
SENSE ISENSE=
RSENSE

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 VN920-E / VN920B5-E / VN920SO-E

Figure 8. Application Schematic

+5V

Rprot VCC

INPUT

Dld

µC Rprot OUTPUT

CURRENT SENSE

RSENSE GND

RGND
VGND DGND

This small signal diode can be safely shared amongst

several different HSD. Also in this case, the presence of
GND PROTECTION NETWORK AGAINST the ground network will produce a shift (j600mV) in the
REVERSE BATTERY input threshold and the status output values if the
Solution 1: Resistor in the ground line (RGND only). This microprocessor ground is not common with the device
can be used with any type of load. ground. This shift will not vary if more than one HSD
shares the same diode/resistor network.
The following is an indication on how to dimension the
RGND resistor. Series resistor in INPUT line is also required to prevent
that, during battery voltage transient, the current exceeds
1) RGND ≤ 600mV / (IS(on)max). the Absolute Maximum Rating.
2) RGND ≥ (−VCC) / (-IGND) Safest configuration for unused INPUT pin is to leave it
where -IGND is the DC reverse ground pin current and can unconnected, while unused SENSE pin has to be
be found in the absolute maximum rating section of the connected to Ground pin.
device’s datasheet.
LOAD DUMP PROTECTION
Power Dissipation in RGND (when VCC<0: during reverse
battery situations) is: Dld is necessary (Voltage Transient Suppressor) if the
load dump peak voltage exceeds VCC max DC rating.
PD= (-VCC)2/RGND The same applies if the device will be subject to
This resistor can be shared amongst several different transients on the VCC line that are greater than the ones
HSD. Please note that the value of this resistor should be shown in the ISO T/R 7637/1 table.
calculated with formula (1) where IS(on)max becomes the
sum of the maximum on-state currents of the different µC I/Os PROTECTION:
devices. If a ground protection network is used and negative
Please note that if the microprocessor ground is not transients are present on the VCC line, the control pins will
common with the device ground then the RGND will be pulled negative. ST suggests to insert a resistor (Rprot)
produce a shift (IS(on)max * RGND) in the input thresholds in line to prevent the µC I/Os pins to latch-up.
and the status output values. This shift will vary The value of these resistors is a compromise between the
depending on how many devices are ON in the case of leakage current of µC and the current required by the
several high side drivers sharing the same RGND. HSD I/Os (Input levels compatibility) with the latch-up
If the calculated power dissipation leads to a large limit of µC I/Os.
resistor or several devices have to share the same -VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax
resistor then the ST suggests to utilize Solution 2 (see Calculation example:
below).
For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤ Rprot ≤ 65kΩ.
Solution 2: A diode (DGND) in the ground line.
Recommended Rprot value is 10kΩ.
A resistor (RGND=1kΩ) should be inserted in parallel to
DGND if the device will be driving an inductive load.

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VN920-E / VN920B5-E / VN920SO-E

Figure 9. Off State Output Current Figure 10. High Level Input Current
IL(off1) (uA) Iih (uA)
9 5

8 4.5
Vin=3.25V
4
7
3.5
6
3
5
2.5
4
2
3
1.5
2
1

1 0.5

0 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175

Tc (°C) Tc (°C)

Figure 11. Input Clamp Voltage Figure 13. On State Resistance Vs VCC
Vicl (V) Ron (mOhm)
8 50

7.8 45
Iin=1mA
7.6 40

7.4 35
Tc= 150ºC
7.2 30

7 25

6.8 20
Tc= 25ºC
6.6 15

6.4 10
Tc= - 40ºC
6.2 5

6 0
-50 -25 0 25 50 75 100 125 150 175 5 10 15 20 25 30 35 40

Tc (°C) Vcc (V)

Figure 12. On State Resistance Vs Tcase Figure 14. Input High Level
Ron (mOhm) Vih (V)
50 3.6

45
3.4
Iout=10A
40
Vcc=8V; 36V 3.2
35
3
30

25 2.8

20 2.6

15
2.4
10
2.2
5

0 2
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175

Tc (ºC) Tc (°C)

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 VN920-E / VN920B5-E / VN920SO-E

Figure 15. Input Low Level Figure 18. Input Hysteresis Voltage
Vil (V) Vhyst (V)
2.6 1.5

1.4
2.4
1.3
2.2
1.2
2
1.1

1.8 1

0.9
1.6
0.8
1.4
0.7
1.2
0.6

1 0.5
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)

Figure 16. Turn-on Voltage Slope Figure 19. Turn-off Voltage Slope
dVout/dt(on) (V/ms) dVout/dt(off) (V/ms)
700 550

500
650
Vcc=13V
Vcc=13V 450
600 Rl=1.3Ohm
Rl=1.3Ohm 400
550
350

500 300

450 250

200
400
150
350
100
300 50

250 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175

Tc (ºC) Tc (°C)

Figure 17. Overvoltage Shutdown Figure 20. ILIM Vs Tcase

Vov (V) Ilim (A)
50 100

48 90
Vcc=13V
46 80

44 70

42 60

40 50

38 40

36 30

34 20

32 10

30 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)

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VN920-E / VN920B5-E / VN920SO-E

Figure 21. P2PAK Maximum turn off current versus load inductance

ILM AX (A)
100

A
B
C
10

1
0.01 0.1 1 10 100
L(mH)

A = Single Pulse at TJstart=150ºC Values are generated with RL=0Ω

B= Repetitive pulse at TJstart=100ºC In case of repetitive pulses, Tjstart (at beginning of
C= Repetitive Pulse at TJstart=125ºC each demagnetization) of every pulse must not
exceed the temperature specified above for
Conditions: curves B and C.
VCC=13.5V

VIN, IL
Demagnetization Demagnetization Demagnetization

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 VN920-E / VN920B5-E / VN920SO-E

Figure 22. SO-16L Maximum turn off current versus load inductance

ILMAX (A)
100

B
C
10

1
0.01 0.1 1 10 100
L(mH)

A = Single Pulse at TJstart=150ºC Values are generated with RL=0Ω

B= Repetitive pulse at TJstart=100ºC In case of repetitive pulses, Tjstart (at beginning of
C= Repetitive Pulse at TJstart=125ºC each demagnetization) of every pulse must not
exceed the temperature specified above for
Conditions: curves B and C.
VCC=13.5V

VIN, IL
Demagnetization Demagnetization Demagnetization

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VN920-E / VN920B5-E / VN920SO-E

SO-16L Thermal Data

Figure 23. SO-16L PC Board

Layout condition of Rth and Zth measurements (PCB FR4 area= 41mm x 48mm, PCB thickness=2mm,
Cu thickness=35µm, Copper areas: 0.5cm2, 6cm2).

Figure 24. SO-16L R thj-amb Vs PCB copper area in open box free air condition

RTH j-amb (°C/W)

70

65

60

55

50

45

40
0 1 2 3 4 5 6 7
PCB Cu heatsink area (cm^2)

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 VN920-E / VN920B5-E / VN920SO-E

P2PAK Thermal Data

Figure 25. P2PAK PC Board

Layout condition of Rth and Zth measurements (PCB FR4 area= 60mm x 60mm, PCB thickness=2mm,
Cu thickness=35µm, Copper areas: 0.97cm2, 8cm2).

Figure 26. P2PAK Rthj-amb Vs PCB copper area in open box free air condition

RTHj_amb (°C/W)
55
Tj-Tamb=50°C
50

45

40

35

30
0 2 4 6 8 10
PCB Cu heatsink area (cm^2)

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VN920-E / VN920B5-E / VN920SO-E

Figure 27. P2PAK Thermal Impedance Junction Ambient Single Pulse

ZT H (°C/W)
1000

100
0.97 cm2

6 cm2

10

0.1

0.01
0.0001 0.001 0.01 0.1 1 10 100 1000
Time (s)

Figure 28. Thermal fitting model of a single Pulse calculation formula

channel HSD in P2PAK = R TH ⋅ δ + Z THtp ( 1 – δ )
THδ

where δ = tp ⁄ T

Table 13. Thermal Parameter

Area/island (cm2) 0.97 6
Tj R1 (°C/W) 0.02
C1 C2 C3 C4 C5 C6
R2 (°C/W) 0.1
R1 R2 R3 R4 R5 R6 R3 ( °C/W) 0.22
R4 (°C/W) 4
Pd
R5 (°C/W) 9
T_amb R6 (°C/W) 37 22
C1 (W.s/°C) 0.0015
C2 (W.s/°C) 0.007
C3 (W.s/°C) 0.015
C4 (W.s/°C) 0.4
C5 (W.s/°C) 2
C6 (W.s/°C) 3 5

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Figure 29. SO-16L Thermal Impedance Junction Ambient Single Pulse

ZTH (°C/W)

100
0.5 cm2

6 cm2

10

0.1

0.01
0.0001 0.001 0.01 0.1 1 10 100 1000
Time (s)

Figure 30. Thermal fitting model of a single Pulse calculation formula

channel HSD in SO-16L
THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where δ = tp ⁄ T

Table 14. Thermal Parameter

Area/island (cm2) 0.5 6
Tj R1 (°C/W) 0.02
C1 C2 C3 C4 C5 C6
R2 (°C/W) 0.1
R1 R2 R3 R4 R5 R6 R3 ( °C/W) 2.2
R4 (°C/W) 12
Pd
R5 (°C/W) 15
T_amb R6 (°C/W) 35 20
C1 (W.s/°C) 0.0015
C2 (W.s/°C) 7.00E-03
C3 (W.s/°C) 1.50E-02
C4 (W.s/°C) 0.14
C5 (W.s/°C) 1
C6 (W.s/°C) 5 8

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PACKAGE MECHANICAL

Table 15. SO-16L Mechanical Data

millimeters
Symbol
Min Typ Max
A 2.35 2.65
A1 0.10 0.30
B 0.33 0.51
C 0.23 0.32
D 10.10 10.50
E 7.40 7.60
e 1.27
H 10.00 10.65
h 0.25 0.75
L 0.40 1.27
k 0º 8º
ddd 0.10
Package Weight 0.4Gr. (Typ.)

Figure 31. SO-16L Package Dimensions

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PACKAGE MECHANICAL

Table 16. PENTAWATT (VERTICAL) Mechanical Data

millimeters
Symbol
Min Typ Max
A 4.8
C 1.37
D 2.4 2.8
D1 1.2 1.35
E 0.35 0.55
F 0.8 1.05
F1 1 1.4
G 3.2 3.4 3.6
G1 6.6 6.8 7
H2 10.4
H3 10.05 10.4
L 17.85
L1 15.75
L2 21.4
L3 22.5
L5 2.6 3
L6 15.1 15.8
L7 6 6.6
M 4.5
M1 4
Diam. 3.65 3.85

Figure 32. PENTAWATT (VERTICAL) Package Dimensions

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PACKAGE MECHANICAL

Table 17. P2PAK Mechanical Data

millimeters
Symbol
Min Typ Max
A 4.30 4.80
A1 2.40 2.80
A2 0.03 0.23
b 0.80 1.05
c 0.45 0.60
c2 1.17 1.37
D 8.95 9.35
D2 8.00
E 10.00 10.40
E1 8.50
e 3.20 3.60
e1 6.60 7.00
L 13.70 14.50
L2 1.25 1.40
L3 0.90 1.70
L5 1.55 2.40
R 0.40
V2 0º 8º
Package Weight 1.40 Gr (typ)

Figure 33. P2PAK Package Dimensions

P010R

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 VN920-E / VN920B5-E / VN920SO-E

Figure 34. SO-16L TUBE SHIPMENT (no suffix)

Base Q.ty 50
Bulk Q.ty 1000
Tube length (± 0.5) 532
C
B A 3.5
B 13.8
C (± 0.1) 0.6

All dimensions are in mm.

A

Figure 35. SO-16L TAPE AND REEL SHIPMENT (suffix “TR”)

REEL DIMENSIONS
Base Q.ty 1000
Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 16.4
N (min) 60
T (max) 22.4

All dimensions are in mm.

TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width W 16
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 12
Hole Diameter D (± 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 7.5
Compartment Depth K (max) 6.5
Hole Spacing P1 (± 0.1) 2

All dimensions are in mm. End

Start

Top No components Components No components

cover
tape 500mm min
Empty components pockets 500mm min
saled with cover tape.

User direction of feed

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VN920-E / VN920B5-E / VN920SO-E

Figure 36. P2PAK TUBE SHIPMENT (no suffix)

Base Q.ty 50
Bulk Q.ty 1000
B Tube length (± 0.5) 532
A 18
B 33.1
C
C (± 0.1) 1

All dimensions are in mm.

A

Figure 37. P2PAK TAPE AND REEL SHIPMENT (suffix “TR”)

REEL DIMENSIONS
Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 24.4
N (min) 60
T (max) 30.4

All dimensions are in mm.

TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width W 24
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 16
Hole Diameter D (± 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 11.5
Compartment Depth K (max) 6.5
Hole Spacing P1 (± 0.1) 2

All dimensions are in mm. End

Start

Top No components Components No components

cover
tape 500mm min
Empty components pockets 500mm min
saled with cover tape.

User direction of feed

22/24
 VN920-E / VN920B5-E / VN920SO-E

REVISION HISTORY

Table 18. Revision History

Date Revision Description of Changes

Oct. 2004 1 - First Issue.

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VN920-E / VN920B5-E / VN920SO-E

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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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