(12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT)

(19) World Intellectual Property Organization

WO 03/090343 A2
International Bureau

(43) International Publication Date (10) International Publication Number

30 October 2003 (30.10.2003) PCT WO 03/090343 A2
(51) International Patent Classification7: H03F (81) Designated States (national): AE, AG, AL, AM, AT, AU,
AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CO, CR, CU,
(21) International ApplicationNumber: PCT/IB03/01253 CZ, DE, DK, DM, DZ, EC, EE, ES, FI, GB, GD, GE, GH,
GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC,
(22) International Filing Date: 1 April 2003 (01.04.2003) LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW,
MX, MZ, NI, NO, NZ, OM, PH, PL, PT, RO, RU, SC, SD,
(25) Filing Language: English SE, SG, SK, SL, TJ, TM, TN, TR, TT, TZ, UA, UG, US,
UZ, VC, VN, YU, ZA, ZM, ZW.
(26) Publication Language: English

(30) Priority Data: (84) Designated States (regional): ARIPO patent (GH, GM,
02076543.4 19 April 2002 (19.04.2002) EP KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZM, ZW),
Eurasian patent (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM),
(71) Applicant (for all designated States except US): KONIN- European patent (AT, BE, BG, CH, CY, CZ, DE, DK, EE,
KL1JKE PHILIPS ELECTRONICS N.V. [NL/NLJ; ES, FI, FR, GB, GR, HU, IE, IT, LU, MC, NL, PT, RO,
Groenewoudseweg 1, NL-5621 BA Eindhoven (NL). SE, SI, SK, TR), OAPI patent (BF, BJ, CF, CG, CI, CM,
GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Inventor; and
Inventor/Applicant (for US only): PUTZEYS, Bruno, J., Published:
G. [BE/NL]; ■without international search report and to be republished
WO 03/090343 A2 Prof. Holstlaan 6, NL-5656 AA Eindhoven
(NL). upon receipt of that report

(74) Agent: GROENENDAAL, Antonius, W., M.; Interna- For two-letter codes and other abbreviations, refer to the "Guid­
tionaal Octrooibureau B.V., Prof. Holstlaan 6, NL-5656 ance Notes on Codes and Abbreviations" appearing at the begin­
A A Eindhoven (NL). ning of each regular issue of the PCT Gazette.

(54) Title: POWER AMPLIFIER

WO 03/090343 A2

(57) Abstract: A switching power amplifier of class D has switching means for generating a block wave signal by alternately switch­
ing the block wave signal between supply voltages. A filter (24,25) generates a power output signal (22) corresponding to an input
signal to be amplified, which is coupled to a linear input (19) that is free of hysteresis. A control circuit (27,28,29) provides feedback
between the output power signal and the linear input for controlling boththe gain in the operational frequency range and also said
alternately switching of the switching means. Hence the amplifier oscillates controlled via the same feedback loop that also controls
the operational behavior of the amplifier, resulting in low output impedance and low distortion.
 WO 03/090343 PCT/IB03/01253
1
Power amplifier

The invention relates to a power amplifier for amplifying an electric signal in

an operational frequency range comprising switching means for generating a block wave
signal by alternately switching the block wave signal to a first supply voltage or a second
supply voltage, filter means for generating a power output signal by low pass filtering the
5 block wave signal, input means for receiving the electric signal and driving the switching
means, and a control circuit coupled to the output power signal and the input means for
controlling the power amplifier.

A switching power amplifier is known from US 6,297,692. The document

10 describes pulse modulation amplifiers, also called pulse width modulation amplifiers or class
D amplifiers. In such amplifiers there is an input stage for receiving an electrical input signal
to be amplified, a modulating / switching stage and a filter. The switching stage generates a
block wave signal which has a frequency that is much higher than the highest frequency in
the operational frequency range of the electric signal to be amplified. The pulse width ratio of
15 the block wave is modulated so that the average value of the block wave signal is
proportional to the input signal. The filter filters the block wave signal to a power output
signal. The modulation frequency may be derived from an oscillator, or the amplifier may be
self-oscillating. Further the power amplifier comprises a control circuit. For achieving a high
quality power output signal the control circuit has to control the amplifier in order to
20 compensate numerous non-ideal features of the components of the class D amplifier. Several
prior art options for such control circuits are described, and a cascaded control circuit is
proposed in the document. The control circuit has a first feedback loop from the output power
signal to the input for controlling the operational frequency behavior of the amplifier. The
oscillation is controlled by a second feedback circuit coupled between the block wave signal
25 and an input of the modulation circuit. The cascaded control circuit is complicated and
requires both feedback circuits to be designed and tuned accurately.

It is an object of the invention to provide a power amplifier of high quality

which has a less complicated structure.
 WO 03/090343 PCT/IB03/01253
2
For this purpose, the power amplifier as described in the opening paragraph is
characterized in that the control circuit is connected between the power output signal and a
linear input of the input means for controlling both the gain in the operational frequency
range and also said alternately switching of the switching means, said linear input being
5 substantially free of hysteresis. The measures have the advantage that a low output
impedance of the amplifier is achieved, even at the filter resonance frequency. Further a large
reduction of inductor-related distortion and a very wide loop bandwidth are achieved,
resulting in substantially frequency-independent distortion figures.
The invention is also based on the following recognition. In some prior art
10 switching amplifiers self-oscillation is based on the hysteresis of an element in the input
stage. Although such “hysteresis-controlled” oscillating amplifiers may appear relatively
uncomplicated, the inventors have seen that such hysteresis results in a number of non-linear
errors and distortion products. Further the switching frequency may vary with modulation
index, limiting the modulation swing. Efforts by other researchers concentrated on
15 controlling the hysteresis voltage to reduce frequency modulation. The inventors seen that in
a hysteresis free amplifier according to the invention a combined feedback loop for both gain
and oscillation control can be connected between the output power signal after the filter and
the linear input. In addition to the advantages described above, this allows a significantly
larger modulation swing before the switching frequency becomes unacceptably low.
20 In an embodiment of the power amplifier, the switching means comprise a first
switching unit for switching to the first supply voltage and a second switching unit for
switching to the second supply voltage, and the input means comprise a voltage comparator
having complementary current outputs for respectively driving the first and second switching
unit. This has the advantage that due to the symmetrical construction of the circuit, distortion
25 products in the output signal are kept low. In an embodiment of the power amplifier the
voltage comparator comprises a difference amplifier and a switching current mirror providing
said complementary current outputs. A result of this is that none of the transistors in this
circuit are used in saturation, insuring fast reaction speeds.
In an embodiment of the power amplifier, the switching means comprise a first
30 switching unit for switching to the first supply voltage and a second switching unit for
switching to the second supply voltage, both switching units being substantially identical.
This has the advantage that due to the symmetrical construction of the circuit, distortion
products in the output signal are kept low.
 WO 03/090343 PCT/IB03/01253
3
These and other aspects of the invention will be apparent from and elucidated
further with reference to the embodiments described by way of example in the following
description and with reference to the accompanying drawings, in which
Figure 1 shows a block diagram of a switching power amplifier,
5 Figure 2 shows an electrical diagram of a switching power amplifier,
Figure 3 shows a switching power amplifier having a comparator having
complementary outputs and identical switching units,
Figure 4 shows a comparator having complementary outputs,
Figure 5 shows a switching unit,
10 Figure 6 shows the gain versus frequency graph, and
Figure 7 shows the output impedance versus frequency graph.
Corresponding elements in different Figures have identical reference numerals.

Figure 1 shows a block diagram of a switching power amplifier. The amplifier

15 has an input circuit 11 which receives a signal from a summing node 16 at a hysteresis free
input 19. The input circuit 11 is coupled to a driver element 12, which is driving a switching
power stage 13. The output of switching power stage 13 is a block wave signal which has a
frequency well above the operational frequency range of the electrical signal to be amplified.
The block wave signal is coupled to a low pass filter 14, which removes the high frequency
20 block wave and results in a power output signal 18. A control circuit 15 provides a feedback
loop from the power output signal 18 to the summing node 16 at the input. The summing
node further receives the electrical input signal 17 which is to be amplified. Some delay is
present in the elements 11,12,13 of the amplifying chain due to the physical nature of the
circuits used, e.g. semiconductors. The control circuit 15 is provided with oscillation
25 feedback elements having a high feedback, i.e. a low impedance, at a high frequency. Due to
the delay and the phase shift caused by the filter and the oscillation feedback elements in
control circuit 15 the amplifier will be self oscillating at a high frequency. The control circuit
15 also has operational feedback elements for controlling the gain and characteristics of the
power amplifier in the operational frequency range.
30 Figure 2 shows an electrical diagram of a switching power amplifier. The
amplifier has an amplifier circuit 23 which has a differential input stage, e.g. positive and
negative input of a comparator. The inputs are free of hysteresis. The positive input receives
an electrical input signal 21 to be amplified. The amplifier circuit 23 comprises driver
elements and a switching power stage. The output of switching power stage is a block wave
 WO 03/090343 PCT/IB03/01253

signal which has a frequency well above the operational frequency range of the electrical
signal to be amplified. The block wave signal is coupled to a low pass filter constituted by an
inductor 24 and a capacitor 25, which removes the high frequency block wave and results in
a power output signal 22. The power output signal 22 is connected to a load 26, e.g. a
5 loudspeaker having an impedance Zl, which load is not part of the amplifier. A control circuit
provides a feedback loop having a feedback function H from the power output signal 22 to
the negative input of the amplifier circuit 23. The negative input of the amplifier circuit 23 is
connected to ground via a resistor Rg. The control circuit is provided with oscillation
feedback elements having a high feedback at a high frequency, i.e. a resistor Rl 28 in series
10 with a capacitance Cl 29. The control circuit also has an operational feedback element
resistor Rf 27 for controlling the gain and characteristics of the power amplifier in the
operational frequency range. Due to delay in the amplifier circuit and the phase shift caused
by the filter and the oscillation feedback elements in control circuit the amplifier will be self
oscillating at a high frequency.
15 The oscillation condition is met when the total phase shift of the loop gain is
360°, for the small-signal gain of the combined comparator and power stage is undefined but
sufficiently large. The feedback function H can be written as

H(S) = ,--------- ,
(l + Tb ■ s) + An ■ (l + Ta • s)

where
Ta =RL’CL
20 5

Tb = (Rf +Rl)'Cl
and

The output filter function G can be written as

G(s) =------------- ----------------

ZL C L s2 +L s + Zl
25
Finally, the delay function is written as

§(s) = e_S Td ® I - s • Td

The system will oscillate at the frequency where the total phase shift becomes 360°. From the
above, the switching frequency is found by requiring that
Arg(8(s
30 sw) ■ G(ssw) • H(ssw)) = 180°
 WO 03/090343 PCT/IB03/01253

The Low-Frequency Gain is determined as follows. By oscillating, the comparator plus the
power stage are linearized and become a gain block. To determine the gain, we need to know
what the carrier looks like at the input of the comparator. Known is that the signal at the
switching output stage is a square wave of amplitude Vcc and pulsation cosw. Known, too is
5 that the signal at the comparator will be an attenuated and low-pass filtered version. Due to
this low-pass filtering action the wave shape will be approximately sinusoidal i.e. only the
fundamental of the switching waveform needs to be considered. The amplitude of the carrier
is thus:
C = Vcc-|G(ssw)H(ssJ

10 The linearized gain of a class D output stage is related to the dV/dt of the carrier as

A 4-V CC
f 'SW

which becomes, for a sinusoidal carrier

A _.4Vcc-fsw_ 4
cosw ■ C 2 - 7t - |g(ssw ) • H(ssw )j

This makes the LF loop gain

15 Al(s) = Av-8(s)g(s)h(s)
and the LF closed loop gain:

Av 8(s) G(s)
1 +Al(s)

As expected, the DC closed loop gain reduces to:

20
Ay_____ | + Rf
I + Ay ■ H(o) * +rJ

The output impedance is the parallel impedance of the output filter divided by the loop gain:

Figure 3 shows a switching power amplifier having a comparator having

25 complementary outputs and identical switching units. The basic configuration is described
above with reference to Figures 1 and 2. The amplifier circuit is shown in more detail as
follows. The input stage is constituted by a comparator 32 having a positive and negative
differential input. The comparator 32 has two complementary outputs coupled to switching
 WO 03/090343 PCT/IB03/01253
6
units 33 and 34. The switching unit 33 drives a MOSFET semiconductor power switch 38
and derives its power supply from a power supply unit 35. The power supply unit 35 is
referenced to the negative power supply voltage -V and may be a capacitor arrangement
which derives its positive supply voltage from the ground level or from the positive power
5 supply voltage +V. The switching unit 34 drives a second MOSFET semiconductor power
switch 39 and derives its power supply from a power supply unit 36. The power supply unit
36 is floating and has its reference on the block wave signal output and may be a capacitor
arrangement which derives its positive supply voltage via a bootstrap diode 37 from the
power supply unit 35.
10 Figure 4 shows a comparator having complementary outputs. The comparator
has positive and negative inputs Ini and In2. A first comparator branch is constituted by
transistor QI is series with Q5, and has an output Outl from transistor Q3. A second
comparator branch, in a mirror configuration, is constituted by transistor Q2 is series with
Q6, and has an output Out2 from transistor Q4. Both branches have a common current source
15 lb as power supply and a common resistor Rb for the mirroring, and two limiting diodes DI
and D2 between the collectors of QI and Q2. Rb is used to set the output current. The circuit
constitutes a very simple yet fast voltage comparator with complementary current outputs.
These outputs connect to two MOSFET gate drivers, one of which is floating. Q1 and Q2
form a differential amplifier, actually a differential transimpedance stage. All base currents
20 are assumed to be negligible. Equation 1 is

•c.QI + 'c,Q2 = >b = 'c,Q5 + ■c.Qfi

and

'c,Q5 ~ 'c,Q6

Note that any deviation will cause a DC offset error. When Vini>Vjn2 then Ic,qi<Ic,q2. In order
25 to maintain the equality of the bottom pair, the excess current of Q2 will be diverted through
D2. This will cause VB,Q4 to be one diode drop higher than VBiQ3. Because of that, only Q4
will conduct to hold the bases of Q5 and Q6 at the voltage required to maintain Equation 1.

'C,Q4 - 'Rb ~ -—
Kb

and

30 ■c,Q3 = 0

When Vini<Vin23 the converse goes. The “bottom half’ of the circuit can also
be seen as a current mirror of which the input and output are swapped depending on the state
 WO 03/090343 PCT/IB03/01253

7
of the comparator. Hence the two branches formed by Q3-Q6 and common elements lb and
Rb constitute a switching cunent mirror. A result of this is that none of the transistors in this
circuit are used in saturation, insuring high reaction speeds.
Figure 5 shows a switching unit. The two driver circuits 33, 34 shown in
5 Figure 3 are identical. One such driver circuit is shown here. A positive drive circuit is
constituted by a transistor QI 1 in combination with base resistor R1. The collector output of
QI 1 is coupled via a resistor R3 and a diode D12 to the MOSFET Ml, power switch 38. The
negative drive circuit is constituted by QI2 and base resistor R12 which act as an active pull-
up 51. QI is operated as a switch with baker-clamp DI 1 to prevent saturation. When QI 1 is
10 turned on, gate charge is supplied to Ml through R3 and D12. When QI 1 is turned off, the
gate is discharged by Q12+R2 which act as an “active pull-up” to speed up the discharge.
Ideally, the discharge current should be about twice as large as the charge current and the
circuit dimensioned accordingly. The voltage source 35 is either the supply of the low-side
driver or the “bootstrap” capacitor of the high-side driver. In the latter case, charge is
15 replenished through the bootstrap diode every time the low-side MOSFET is turned on.
Figure 6 shows the gain versus frequency graph. The graph has frequency
along the X-axis indicated by arrow 61, and gain indicated by arrow 62 along the Y-axis. A
first gain curve 63 indicates the gain with a load of 600 Q. A second curve 64 indicates the
gain with a load of 6 Q. The amplifier circuit has been implemented according to the
20 following requirements/boundary conditions: Power bandwidth: 35kHz into 6Q, Gain: 20
and Td=200ns. This delay is given by the implementation of the comparator and driver stage.
The output filter is chosen to cut off at 35kHz with a Q just over 0.7 to insure no attenuation
occurs below cut-off by L=30pH, C=680nF and Zl=6Q. A DC gain of approximately 20 is
given by Rf=4.7kQ and Rg=220fi. Switching frequency is chosen as at least ten times power
25 bandwidth: fsw>350kHz. This requirement is met by the combination Rl=910Q and
CL=560pF. Oscillation frequency fsw becomes 415kHz and linearized gain Av becomes 457.
The closed-loop gain against frequency is given in Figure 6. The gain shows a peak at the
switching frequency, but as the amplifier is already oscillating at this frequency, this peak has
little meaning. Meaningful is the remaining portion of the graph, which shows that the gain is
30 just over 26dB and that a 1st order roll off occurs at 60kHz. Regardless of the load
impedance, the physical corner frequency of the filter does not manifest itself.
Figure 7 shows the output impedance versus frequency graph. The graph has
frequency along the X-axis indicated by arrow 61, and output impedance indicated by arrow
71 along the Y-axis. An output impedance curve 72 indicates the output impedance. The
 WO 03/090343 PCT/IB03/01253
8

output impedance curve 72 shows no trace of the impedance of the output filter, which
should be infinite at the cut-off frequency. In fact, at 35 kHz it is 0.3Q, at 20 kHz it is 0.2Q,
which is a very good result. The output impedance translates into an equivalent output
inductance of 1.6pH. This is less than the inductances commonly inserted at the output of
5 linear amplifiers. It may be said that this control method solves one of the biggest problems
in class D, to guarantee a flat frequency response across a wide range of loads.
Although the invention has been explained mainly by embodiments using an
audio class D amplifier, similar embodiments are suitable for other power control systems,
for example industrial control amplifiers. It is noted, that in this document the word
10 ‘comprising’ does not exclude the presence of other elements or steps than those listed and
the word ‘a’ or ‘an’ preceding an element does not exclude the presence of a plurality of such
elements, that any reference signs do not limit the scope of the claims, that the invention may
be implemented by means of both hardware and software, and that several ‘means’ may be
represented by the same item of hardware. Further, the scope of the invention is not limited to
15 the embodiments, and the invention lies in each and every novel feature or combination of
features described above.
 WO 03/090343 PCT/IB03/01253
9
CLAIMS:

1. Power amplifier for amplifying an electric signal in an operational frequency

range comprising
switching means for generating a block wave signal by alternately switching the block
wave signal to a first supply voltage or a second supply voltage,
5 - filter means for generating a power output signal by low pass filtering the block wave
signal,
- input means for receiving the electric signal and driving the switching means, and
- a control circuit coupled to the output power signal and the input means for controlling
the power amplifier,
10 characterized in that
the control circuit is connected between the power output signal and a linear input of the
input means for controlling both the gain in the operational frequency range and also said
alternately switching of the switching means, said linear input being substantially free of
hysteresis.
15
2. Power amplifier as claimed in claim 1, wherein the control circuit only has a
voltage feedback from the power output signal.

3. Power amplifier as claimed in claim 2, wherein the control circuit comprises a

20 first element, in particular a resistor, for controlling said gain and a second element, in
particular a capacitance in series with a resistor, for controlling said alternately switching.

4. Power amplifier as claimed in claim 1, wherein the filter means comprise a

self-inductance and a capacitance.
25
5. Power amplifier as claimed in claim 1, wherein the switching means comprise
a first switching unit for switching to the first supply voltage and a second switching unit for
switching to the second supply voltage, and the input means comprise a voltage comparator
 WO 03/090343 PCT/IB03/01253
10

having complementary current outputs for respectively driving the first and second switching
unit.

6. Power amplifier as claimed in claim 5, wherein the voltage comparator

5 comprises a difference amplifier and a switching current mirror providing said
complementary current outputs.

7. Power amplifier as claimed in claim 1, wherein the switching means comprise

a first switching unit for switching to the first supply voltage and a second switching unit for
10 switching to the second supply voltage, both switching units being substantially identical.

8. Power amplifier as claimed in claim 7, wherein one of the switching units is

floating with respect to said supply voltages, and derives its power from a bootstrap diode
power circuit.
15
9. Power amplifier as claimed in claim 1, wherein the switching means comprise
a driver circuit for a MOSFET type power switch, the circuit including active pull-up circuit
for discharging a gate of said power switch.

20 10. Power amplifier circuit for use in a power amplifier as claimed in any of the
preceding claims for amplifying an electric signal in an operational frequency range, the
circuit comprising
switching means for generating a block wave signal by alternately switching the signal to
a first supply voltage or a second supply voltage,
25 - input means for receiving the electric signal and driving the switching means,
characterized in that
the input means have a linear input for connecting a controlling circuit for controlling both
the gain in the operational frequency range and also said alternately switching of the
switching means, said controlling circuit being connected between the linear input and a
30 power output signal generated by low pass filtering the block wave signal, said linear input
being substantially free of hysteresis.
WO 03/090343 PCT/IB03/01253
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FIG. 5
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4/4