BCA: 3

BCA-S203: Computer Architecture & Assembly Language

Dr. Aditya Kumar Gupta
Associate Professor
 Unit – II
Instruction Formats
When the assembler processes an Instruction it converts the instruction from its mnemonics
code to standard machine language format called the "Instruction format". In the process of
conversion, the assembler must determine the type of instruction, convert symbolic labels and
explicit notation to a standard format, determine the lengths of certain operands and parse
literal and constants.

An instruction format defines layout of bits of an instruction, in terms of its constituent parts.
An instruction format must include an opcode and implicitly or explicitly, zero or more
operands. Each explicit operand is referenced using one of addressing modes. For most
instruction sets, more than on instruction format is used. The General Instruction Format may
be give as:

Opcode-Field Address-Field

Here the Op-field: specifies the operation to be performed, and the Address-field provides
operands or the CPU register/MM addresses of the operands.

A computer will usually have a variety of instruction code formats. It is the function of the control
unit within the CPU to interpret each instruction code and provide the necessary control functions
needed to process the instruction.

The bits of the instruction are divided into groups called fields. The most common fields found in
instruction formats are:

1. A mode field that specifies the way the operand or the effective address is determined
2. An operation code field that specifies the operation to be performed.
3. An address field that designates a memory address or a processor register.

Other special fields are sometimes employed under certain circumstances, as for example a field
that gives the number of shifts in a shift-type instruction.

The operation code field of an instruction is a group of bits that define various processor
operations, such as add, subtract, complement, and shift. The bits that define the mode field of an
instruction code specify a variety of alternatives for choosing the operands from the given address.

BCA-S203: Computer Architecture & Assembly Language

Operations specified by computer instructions are executed on some data stored in memory or
processor registers. Operands residing in memory are specified by their memory address. Operands
residing in processor registers are specified with a register address.

A register address is a binary number of k bits that defines one of '2k ' registers in the CPU. Thus a
CPU with 16 processor registers R0 through R15 will have a register address field of four bits.
Computers may have instructions of several different lengths containing varying number of
addresses. The number of address fields in the instruction format of a computer depends on the
internal organization of its registers. Most computers fall into one of three types of CPU
organizations:
1. Single Accumulator Organization
2. General Register Organization
3. Stack Organization

Single Accumulator Organization

In Single Accumulator-type organization all operations are performed with an implied
accumulator register. The instruction format in this type of computer uses one address field. For
example, the instruction that specifies an arithmetic addition is defined by an assembly language
instruction as ADD X where X is the address of the operand. The ADD instruction in this case
results in the operation

AC ← AC + M [X].
Here, AC is the accumulator register and M [X] symbolizes memory word located at address X.

General Register Organization

In a general register type of organization, the instruction format in this type of computer needs
three register address fields. Thus the instruction for an arithmetic addition may be written in an
assembly language as ADD R1, R2, R3 to denote the operation:

R1 ← R2 + R3.

The number of address fields in the instruction can be reduced from three to two if the destination
register is the same as one of the source registers. Thus the instruction ADD R1, R2 would denote
the operation R1 ← R1 + R2. Only register addresses for R1 and R2 need be specified in this
instruction. Computers with multiple processor registers use the move instruction with a
mnemonic MOV to symbolize a transfer instruction. Thus the instruction MOV R1, R2 denotes
the transfer R1 ← R2 (or R2 ← R1, depending on the particular computer). Thus transfer-type
instructions need two address fields to specify the source and the destination.

BCA-S203: Computer Architecture & Assembly Language

Three-Address Instructions
Computers with three-address instruction formats can use each address field to specify either a
processor register or a memory operand. The program in assembly language that evaluates X = (A
+ B) * (C + D) is shown below, together with comments that explain the register transfer operation
of each instruction.

ADD R1, A, B  R1 ← M[A] + M[B]

ADD R2, C, D R2 ← M[C] + M[D]
MUL X, R1, R2  M[X] ← R1 * R2

It is assumed that the computer has two processor registers, R1 and R2. The symbol M[A] denotes
the operand at memory address symbolized by A.
The Advantage of the three-address format is that it results in short programs when evaluating
arithmetic expressions.
The Disadvantage is that the binary-coded instructions require too many bits to specify three
addresses.

Two-Address Instructions
Two-address instructions are the most common in commercial computers. Here again each
address field can specify either a processor register or a memory word. The program to evaluate
X = (A + B) * (C + D) is as follows:

MOV R1, A  R1 ← M[A]

ADD R1, B  R1 ← R1 + M[B]
MOV R2, C  R2 ← M[C]
ADD R2, D  R2 ← R2 + M[D]
MUL R1, R2  R1 ← R1 * R2
MOV X, R1  M[X] ← R1

The MOV instruction moves or transfers the operands to and from memory and processor
registers. The first symbol listed in an instruction is assumed to be both a source and the
destination where the result of the operation is transferred.

BCA-S203: Computer Architecture & Assembly Language

One-Address Instructions
One-address instructions use an implied accumulator (AC) register for all data manipulation. For
multiplication and division there is a need for a second register. However, here we will neglect the
second register and assume that the AC contains the result of all operations. The program to
evaluate X = (A + B) * (C + D) is give bellow:

LOAD A  AC ← M[AJ
ADD B  AC ← AC + M[B]
STORE T  M[T] ← AC
LOAD C  AC ← M[C]
ADD D  AC ← AC + M[D]
MOL T  AC ← AC*M[T]
STORE X  M[X] ← AC

All operations are done between the AC register and a memory operand. T is the address of a
temporary memory location required for storing the intermediate result.

Zero-Address Instructions
A stack-organized computer does not use an address field for the instructions ADD and MUL.
The PUSH and POP instructions, however, need an address field to specify the operand that
communicates with the stack. The following program shows how X = (A + B) * (C + D) will be
written for a stack organized computer. (TOS stands for top of stack.)

PUSH A TOS ← A
PUSH B TOS ← B
ADD  TOS ← (A + B)
PUSH C  TOS ← C
PUSH D TOS ← D
ADD TO  S ← (C + D)
MUL  TOS ← (C + D)*(A + B)
POP X  M[X] ← TOS

To evaluate arithmetic expressions in a stack computer, it is necessary to convert the expression

into reverse Polish notation. The name "zero-address" is given to this type of computer because of
the absence of an address field in the computational instructions.

References: Mano, M. Morris. 1984. Digital Design. Pearson

BCA-S203: Computer Architecture & Assembly Language