Sem 1 2022/2023

TUTORIAL 1 (SOLUTION)
DIGITAL IC DESIGN
(BENC 4473)

1. Describe and differentiate between a combinational and a sequential logic circuit, in terms
of their characteristics.

ANSWER Q1:
Characteristics of combinational circuits are;
• Output depends only to current input
• No feedback from output of the system
• Unable to remember past values
• Continuous assignment
• Data type wire
• Logic gates – AND, OR, XOR, NOT

Characteristics of sequential circuits are;

• Output depends not only on current input but also on past input values
• Output from the system is feedback as new input
• Capable of storing binary information : memory
• Procedural block
• Data type reg
• Latches, flip-flops and logic gates

2. Explain briefly, what is meant the following terms, as used in digital system design.
a) Field Programmable Gate Array (FPGA)
b) Application Specific Integrated Circuit (ASIC), and

ANSWER Q2
a) Field Programmable Gate Array (FPGA)
• FPGA is an IC designed to be configured by a customer or a designer after
manufacturing.
• The FPGA configuration is generally specified using a hardware description
language (HDL), similar to that used for an application-specific integrated
circuit (ASIC).
• FPGAs can be used to implement any logical function that an ASIC could
perform.

b) Application Specific Integrated Circuit (ASIC), and

• An application-specific integrated circuit (ASIC) is an integrated circuit (IC)
that’s custom-designed for a particular task or application.
• Unlike FPGA boards that can be programmed to meet a variety of use case
requirements after manufacturing, ASIC designs are tailored early in the
design process to address specific needs.
• The two primary ASIC design methods are gate-array and full-custom.

3. Briefly describe THREE (3) advantages of HDL design as compared to classical

methods of design based on schematics.

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ANSWER Q3:

i) HDLs provide a means to describe large digital systems without the need for
schematics, which can become impractical in very large designs.
ii) HDLs have evolved to support logic simulation at different levels of abstraction. This
provides designers the ability to begin designing and verifying functionality of large
systems at a high level of abstraction and postpone the details of the circuit
implementation until later in the design cycle. This enables a top-down design
approach that is scalable across different logic families.
iii) HDLs have also evolved to support automated synthesis, which allows the CAD tools
to take a functional description of a system (e.g., a truth table) and automatically
create the gate-level circuitry to be implemented in real hardware.

4. What is design specification? Explain THREE (3) types of simulation in design

verification i.e. timing simulation, behavioral simulation and functional simulation.

ANSWER Q4: (potential

What is design specification?
• Statement of functionality (required)
Timing, Silicon area, Power consumption
• Testability
• Fault coverage

THREE (3) types of simulation in design verification.

i) Behavioural Simulation.
• Behavioural modeling describe the functionality of a design , not how to build it in
hardware. Specifies the input-output model of a logic circuit and suppresses details
about the physical, gate-level implementation
• Once verified through this behavioural simulation, a technology-independent design
can now be synthesized.

ii) Functional Simulation.

• Test plan: functional test features, how to test. Eg. instruction set test for ALU,
specific input data, etc.
• Testbench: unit under test (UUT) is your designed circuit. Testbench will instantiate
(call) UUT with set of test input patterns.
• Test execution: Response of simulation must matched with the expected theoretical
results

ii) Timing Simulation.

• Timing checked on critical signal paths
• Longest paths do not violate timing requirements
• Circuit needs device replacement, transistor resizing or architectural modification or
rerouting if timing specification is violated
• Changes will require resynthesis if any modification done

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5. Hardware designer use design abstraction technique to eliminate unnecessary details in

order to handle the complexity issues. With aid of diagram, explain each levels of that
technique.

ANSWER Q5:

• system level -At this level, behavior of a system is described by stating a set of broad
specifications.
• algorithmic level -At this level, the specifications begin to be broken down into
subsystems, each with an associated behavior that will accomplish a part of the
primary task.
• register transfer level (RTL)- At this level, the details of how data is moved between
and within subsystems are described in addition to how the data is manipulated based
on system inputs.
• gate level -At this level, the design is described using basic gates and registers (or
storage elements).
• circuit level -The circuit level describes the operation of the basic gates and registers
using transistors, wires, and other electrical components such as resistors and
capacitors.
• material level - This level describes how different materials are combined and shaped
in order to implement the transistors, devices, and wires from the circuit level.

6. Computer Aided Design (CAD) tool are intended to support all phases of digital design.
Draw the design cycle that supported by this CAD module. With aid of diagram, explain
each steps in the design cycle.

ANSWER Q6:

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7. There are few terms in the design tool flow for a HDL-based design process that targets
to an FPGA implementation. Explain clearly what are meant by the terms:
a) Design partition,
b) design entry,
b) synthesis and technology mapping

ANSWER Q7:
a) Design Partition
§ large circuits are break up into smaller and simpler functional units/blocks/modules.
• Each unit/block/module is described by a behavioural model of its functionality.
This is called Top-down design' or 'hierarchical design'

b) Design entry
• Once the specification and behaviour of the system are completely understood, a model
that specifies its structure and functionality can be developed.
• This model is described at RT level and the corresponding HDL source code can be
entered into the CAD system for compilation and logic synthesis.
• Behavioural modeling describes the functionality of a design, not how to build it in
hardware. Specifies the input-output model of a logic circuit and suppresses details
about the physical, gate-level implementation
• HDL allows mixed levels of design abstractions such as some modules/units/blocks
are described structurally while some are at behavioural descriptions

c) synthesis and technology mapping

• Synthesis tool create an optimal Boolean description
• Remove redundant logic
• Reduce area used by logic
• Compose gates in an available technology
• Report speed performance

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8. State THREE (3) styles of ASIC design and explain each of them.

ANSWER Q8:
i) Full-Custom ASICs
• Some (possibly all) logic cells are customized and all mask layers are customized.
• ASIC is so specialized that some circuits must be custom designed.

ii) Semicustom ASICs

All logic cells are predesigned (defined in cell library) and some (possibly all) of the mask
layers are customized
Types: Standard-cell based and Gate-array-based ASICs

iii) Programmable ASICs

• All logic cells are predesigned (defined in cell library) and none of the mask layers
are customized
• Types: PLD and FPGA (Field Programmable Gate Array)

9. Describe briefly the TWO (2) approaches of a Hierarchical Modular Design Technique.

ANSWER Q9:
i) Top-down approach,
• decomposes the system into subsystems that themselves are decomposed into simpler
subsystems, until a level is reached at which the subsystems can be realized directly
with available modules.
ii) Bottom-up approach,
• Connects available modules to form subsystems, and these subsystems are connected
to other sub-systems until the required functional specification is fulfilled.

10. State and explain briefly the THREE (3) models of a Verilog HDL.

ANSWER Q10:

11. Convert the decimal value to binary, hexadecimal and octal values using the least number
of bits in Verilog format.
a) 47510

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b) 21610

ANSWER Q11:

a) 47510
Binary – 9’b111011011
Hexadecimal – 9’h1DB
Octal – 9’o733

b) 21610
Binary – 8’b11011000
Hexadecimal – 8’hD8
Octal – 8’o330

12. Derive the Boolean equation generated by the synthesis of the Verilog code fragment
below.
// mux4to1:
always @ (a or b or c or d or S)
if (S == 0) X = a;
else if (S == 1) X = b;
else if (S == 2) X = c;
else X = d;

ANSWER Q12:
𝑋 = 𝑆$! 𝑆
%%%" 𝑎 + 𝑆$! 𝑆" 𝑏 + 𝑆! 𝑆
%%%" 𝑐 + 𝑆! 𝑆" 𝑑

13. Referring to the following Verilog program (which is a mix of behavioral and dataflow
coding style),
a) Complete the missing lines in the IO declaration part,
b) Draw the functional block diagram (fbd) of this module.
c) Derive the Boolean equation for the output f (no need to minimize), and
d) Write the Verilog code to implement the derived f, in dataflow modelling style.

// Verilog-1995
module logic2 (a, b, c, d, f) ;
……. // IO declaration part
wire [0:1] y;
always @ (a or b or c or d)
if (d==1) f=y1;
else f=y0;
assign y1 = ~b | (a & b) ;
assign y0 = (a & b & ~c) | (~a & b);
endmodule

ANSWER Q13:
a) Complete the missing lines in the IO declaration part,
// Verilog-1995
module logic2 (a, b, c, d, f) ;
input a, b, c, d;
output [1:0] f;

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reg [1:0] f;
wire [0:1] y;
always @ (a or b or c or d)
if (d==1) f=y1;
else f=y0;
assign y1 = ~b | (a & b) ;
assign y0 = (a & b & ~c) | (~a & b);
endmodule

b) Draw the functional block diagram (fbd) of this module.

c) Derive the Boolean equation for the output f (no need to minimize)
𝑓 = 𝑑$𝑏& + (𝑎𝑏)+ + 𝑑̅ [𝑎𝑏𝑐̅ + 𝑎&𝑏]

d) Write the Verilog code to implement the derived f, in dataflow modelling style.

// Verilog-1995
module logic2 (a, b, c, d, f) ;
input a, b, c, d;
output [1:0] f;
wire [0:1] y;
assign y1= ~b | (a & b) ;
assign y0 = (a & b & ~c) | (~a & b);
assign f = (d & y1) | (~d & y0);
endmodule

14. Design the logic diagram as shown in Figure 1 using:

a) Dataflow modeling style
b) Structural modeling style.

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Figure 1

ANSWER Q12:
a) Dataflow modeling style.
module comb_cct(a,z);
input [3:0] a;
output z;
wire [1:6] y;
assign y1 = ~a[1];
assign y2 = ~a[0];
assign y3 = y1 & a[2];
assign y4 = y2 ^ a[1];
assign y5= y3 | a[0];
assign y6 = y4 | a[3];
assign z = y5 ^ y6;
endmodule

b) Structural modeling style.

module comb_cct(a,z);
input [3:0] a;
output z;
wire [1:6] y;
not m1(a[1],y1);
not m2(a[0],y2);
and m3(y1,a[2],y3);
xor m4(y2,a[1],y4);
or m5(a[0],y3,y5);
or m7(y4,a[3],y6);
xor m6(y5,y6,z);
endmodule

15. Design the 4-bit ripple carry adders (Addr_4), two 4-bit ripple-carry adders (Addr_8) and
four 4-bit ripple-carry adders (Addr_16) as shown in Figures 2 to 4 by using the structural
modelling style. Then, write separate testbench files to check the functionality of each of
the modules.

Figure 2

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Figure 3

Figure 4

ANSWER Q15-Figure 2:
module Adder_4 (a, b, c_in, c_out,sum) ;
input [3:0] a,b;
input c_in;
output c_out;
output [3:0] sum;

Addr_4 M1(a[3:0], b[3:0], c_in, sum[3:0], c_out);

endmodule

Testbench
`timescale 10ns/1us
module t;
// input as reg
// output as wires
reg [3:0] a,b; // 4-bit inputs
reg c_in, clk;
wire c_out;
wire [3:0] sum;
// instantiate top module to test
Adder_4 m(a, b, c_in, c_out,sum);

// initialize inputs & set simulation end time

initial begin

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clk=1’b1; a=4’b0000; b=4’b0000; c_in=1’b0;

#100 $finish; end
parameter clk_high=1;
// clock generator
always #clk_high clk=~clk;
//input signal generation
reg [8:0]cnt; // 9-bit counter
initial cnt=0;
always @(posedege clk)
begin a<=cnt[3:0]; b=cnt[7:4]; c_in<=cnt[8]; cnt<=cnt+1;
end
endmodule

ANSWER Q15-Figure 3:

module Adder_8 (a, b, c_in, c_out,sum) ;

input [7:0] a,b;
input c_in;
output c_out;
output [7:0] sum;
wire cin1,cin2,cin3;
Addr_4 M1(a[3:0], b[3:0], cin, cin1,sum[3:0]);
Addr_4 M2(a[7:4], b[7:4], cin1, c_out,sum[7:4]);
endmodule

Testbench
`timescale 10ns/1ns
module t;
// input as reg
// output as wires
reg [7:0] a,b;
reg c_in, clk;
wire c_out;
wire [7:0] sum;
// instantiate top module to test
Adder_8 m(a, b, c_in, c_out,sum);
// initialize inputs & set simulation end time
initial begin
clk=1’b1; a=8’h00; b=16’h00; c_in=1’b0;
#100 $finish; end
parameter clk_high=1;
// clock generator
always #clk_high clk=~clk;
//input signal generation
reg [16:0]cnt; // 17-bit counter
initial cnt=0;
always @(posedege clk)
begin a<=cnt[8:1]; b=cnt[16:9]; c_in<=cnt[0]; cnt<=cnt+1;
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end
endmodule

ANSWER Q15-Figure 4:

module Adder_16 (a, b, c_in, c_out,sum) ;

input [15:0] a,b;
input c_in;
output c_out;
output [15:0] sum;
wire cin1,cin2,cin3;
Addr_4 M1(a[3:0], b[3:0], cin, cin1,sum[3:0]);
Addr_4 M2(a[7:4], b[7:4], cin1, cin2,sum[7:4]);
Addr_4 M3(a[11:8], b[11:8], cin2, cin3,sum[11:8]);
Addr_4 M4(a[15:12], b[15:12], cin3, c_out,sum[15:12]);
endmodule

Testbench
`timescale 10ns/1ns
module t;
// input as reg
// output as wires
reg [15:0] a,b;
reg c_in, clk;
wire c_out;
wire [15:0] sum;
// instantiate top module to test
Adder_16 m(a, b, c_in, c_out,sum);
// initialize inputs & set simulation end time
initial begin
clk=1’b1; a=16’h0000; b=16’h0000; c_in=1’b0;
#200 $finish; end
parameter clk_high=1;
// clock generator
always #clk_high clk=~clk;
//input signal generation
reg [32:0]cnt; // 33-bit counter
initial cnt=0;
always @(posedege clk)
begin a<=cnt[16:1]; b<=cnt[32:17]; c_in<=cnt[0]; cnt<=cnt+1;
end
endmodule

16. Obtain the fbd of the module Array_Adder described by the Verilog code below.
module FA (Cin, x, y, S, Cout) ;
input Cin, x, y;
output S, Cout ;

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assign S = ( x ^ y ^ Cin ) ;
assign Cout = (x & y) | (Cin & x) | (Cin & y);
endmodule

module Array_Adder (Ci, a, b, sum);

input Ci;
input [3:0] a, b;
output [4:0] sum;
wire [4:0] C;
FA U[3:0] ( C[3:0], a, b, sum[3:0], C[4:1] );
assign sum[4] = C[4] ;
endmodule

17. Figure 5 shows the schematic diagram of a 4-to-1 line multiplexer. Design the circuit using
structural coding and develop a testbench for an exhaustive test in Verilog to verify this
design.

Figure 5

ANSWER Q17:
module comparator_cct(A,B,A_gt_B,A_lt_B,A_eq_B);
input [1:0] A,B;
output A_gt_b,A_lt_B,A_eq_B;
wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10;
and M1(w6,B1,w1);
and M2(w6,w7,B0,w2);
and M3(w7,B1,B0,w3);
xnor M4(B1,A1,w4);
xnor M5(A0,B0,w5);
nor M6(w10,A_eq_B,A_gt_B);
and M7(w4,w5,A_eq_B);
or M8(w1,w2,w3,w10);
not M9(A1,w6);
not M10(A0,w7);
not M11(A_gt_B,w8);

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not M12(w8,w9,A_lt_B);
not M13(A_eq_B,w9);
endmodule

Testbench
`timescale 10ns/1ns
module t;
// input as reg
// output as wires
reg [1:0] A,B;
reg clk;
wire A_gt_b,A_lt_B,A_eq_B;

// instantiate top module to test

comparator_cct m(A,B,A_gt_B,A_lt_B,A_eq_B);
// initialize inputs & set simulation end time
initial begin
clk=1’b1; A=2’b00; B=2’b00;
#70 $finish; end
parameter clk_high=1;
// clock generator
always #clk_high clk=~clk;
//input signal generation
reg [3:0]cnt; // 4-bit counter
initial cnt=0;
always @(posedege clk)
begin A<=cnt[0:1]; B=cnt[2:3]; cnt<=cnt+1;
end
endmodule

18. Figure 6 shows the schematic diagram of a 4-to-1 line multiplexer. Design the circuit using
structural coding and develop a testbench for an exhaustive test in Verilog to verify this
design.

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Figure 6

ANSWER Q18:
module MUX_4X1(A,B,C,D,S0,S1,Y);
input A,B,C,D,S0,S1;
output Y;
wire w1,w2,w3,w4,w5,w6;
and M0(w6,w5,A,w1);
and M1(w6,S0,B,w2);
and M2(w5,C,S1,w3);
and M3(D,S1,S0,w4);
or M4(w1,w2,w3,w4,Y);
not M5(S0,w5);
endmodule

Testbench
`timescale 10ns/1ns
module t;
// input as reg
// output as wires
reg A,B,C,D,S0,S1;
reg clk;
wire Y;

// instantiate top module to test

MUX_4X1 m(A,B,C,D,S0,S1,Y);
// initialize inputs & set simulation end time
initial begin
clk=1’b1; A=1’b0; B=1’b0; C=1’b0; D=1’b0; S0=1’b0; S1=1’b0;
#70 $finish; end
parameter clk_high=1;
// clock generator
always #clk_high clk=~clk;
//input signal generation

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reg [5:0]cnt; // 6-bit counter

initial cnt=0;
always @(posedege clk)
begin {S1,S0}<=cnt[1:0]; {A,B,C,D}<=cnt[5:2]; cnt<=cnt+1;
end
endmodule

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