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49 Uf 6700

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0% found this document useful (0 votes)

176 views57 pages

49 Uf 6700

Uploaded by

NORBERTO OVALLOS C

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

You are on page 1/ 57

Internal Use Only

North/Latin America http://aic.lgservice.com

Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com

LED TV
SERVICE MANUAL
CHASSIS : LA54H

MODEL : 49UF6700 49UF6700-UC

CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

P/NO : MFL68682506 (1503-REV00) Printed in Korea

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CONTENTS

CONTENTS ............................................................................................... 2

SAFETY PRECAUTIONS ......................................................................... 3

SERVICING PRECAUTIONS .................................................................... 4

SPECIFICATION ....................................................................................... 6

ADJUSTMENT INSTRUCTION .............................................................. 10

TROUBLESHOOTING ............................................................................ 17

BLOCK DIAGRAM .................................................................................. 30

EXPLODED VIEW ................................................................................... 31

SCHEMATIC CIRCUIT DIAGRAM ............................................ APPENDIX

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SAFETY PRECAUTIONS

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

General Guidance Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC Do not use a line Isolation Transformer during this check.
power line. Use a transformer of adequate power rating as this Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
protects the technician from accidents resulting in personal injury between a known good earth ground (Water Pipe, Conduit, etc.)
from electrical shocks. and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
It will also protect the receiver and it's components from being with 1000 ohms/volt or more sensitivity.
damaged by accidental shorts of the circuitry that may be Reverse plug the AC cord into the AC outlet and repeat AC voltage
inadvertently introduced during the service operation. measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
If any fuse (or Fusible Resistor) in this TV receiver is blown, 0.5 mA.
replace it with the specified. In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
When replacing a high wattage resistor (Oxide Metal Film Resistor, repaired before it is returned to the customer.
over 1 W), keep the resistor 10 mm away from PCB.
Leakage Current Hot Check circuit
Keep wires away from high voltage or high temperature parts.

Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed

metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.

Leakage Current Cold Check(Antenna Cold Check)

With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩ and 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.

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SERVICING PRECAUTIONS
CAUTION: Before servicing receivers covered by this service 2. After removing an electrical assembly equipped with ES
manual and its supplements and addenda, read and follow the devices, place the assembly on a conductive surface such as
SAFETY PRECAUTIONS on page 3 of this publication. aluminum foil, to prevent electrostatic charge buildup or expo-
NOTE: If unforeseen circumstances create conflict between the sure of the assembly.
following servicing precautions and any of the safety precautions 3. Use only a grounded-tip soldering iron to solder or unsolder ES
on page 3 of this publication, always follow the safety precautions. devices.
Remember: Safety First. 4. Use only an anti-static type solder removal device. Some solder
removal devices not classified as “anti-static” can generate
General Servicing Precautions electrical charges sufficient to damage ES devices.
1. Always unplug the receiver AC power cord from the AC power 5. Do not use freon-propelled chemicals. These can generate
source before; electrical charges sufficient to damage ES devices.
a. Removing or reinstalling any component, circuit board mod- 6. Do not remove a replacement ES device from its protective
ule or any other receiver assembly. package until immediately before you are ready to install it.
b. Disconnecting or reconnecting any receiver electrical plug or (Most replacement ES devices are packaged with leads electri-
other electrical connection. cally shorted together by conductive foam, aluminum foil or
c. Connecting a test substitute in parallel with an electrolytic comparable conductive material).
capacitor in the receiver. 7. Immediately before removing the protective material from the
CAUTION: A wrong part substitution or incorrect polarity leads of a replacement ES device, touch the protective material
installation of electrolytic capacitors may result in an explo- to the chassis or circuit assembly into which the device will be
sion hazard. installed.
2. Test high voltage only by measuring it with an appropriate CAUTION: Be sure no power is applied to the chassis or circuit,
high voltage meter or other voltage measuring device (DVM, and observe all other safety precautions.
FETVOM, etc) equipped with a suitable high voltage probe. 8. Minimize bodily motions when handling unpackaged replace-
Do not test high voltage by "drawing an arc". ment ES devices. (Otherwise harmless motion such as the
3. Do not spray chemicals on or near this receiver or any of its brushing together of your clothes fabric or the lifting of your
assemblies. foot from a carpeted floor can generate static electricity suf-
4. Unless specified otherwise in this service manual, clean ficient to damage an ES device.)
electrical contacts only by applying the following mixture to the
contacts with a pipe cleaner, cotton-tipped stick or comparable General Soldering Guidelines
non-abrasive applicator; 10 % (by volume) Acetone and 90 % 1. Use a grounded-tip, low-wattage soldering iron and appropriate
(by volume) isopropyl alcohol (90 % - 99 % strength) tip size and shape that will maintain tip temperature within the
CAUTION: This is a flammable mixture. range or 500 °F to 600 °F.
Unless specified otherwise in this service manual, lubrication of 2. Use an appropriate gauge of RMA resin-core solder composed
contacts in not required. of 60 parts tin/40 parts lead.
5. Do not defeat any plug/socket B+ voltage interlocks with which 3. Keep the soldering iron tip clean and well tinned.
receivers covered by this service manual might be equipped. 4. Thoroughly clean the surfaces to be soldered. Use a mall wire-
6. Do not apply AC power to this instrument and/or any of its bristle (0.5 inch, or 1.25 cm) brush with a metal handle.
electrical assemblies unless all solid-state device heat sinks are Do not use freon-propelled spray-on cleaners.
correctly installed. 5. Use the following unsoldering technique
7. Always connect the test receiver ground lead to the receiver a. Allow the soldering iron tip to reach normal temperature.
chassis ground before connecting the test receiver positive (500 °F to 600 °F)
lead. b. Heat the component lead until the solder melts.
Always remove the test receiver ground lead last. c. Quickly draw the melted solder with an anti-static, suction-
8. Use with this receiver only the test fixtures specified in this type solder removal device or with solder braid.
service manual. CAUTION: Work quickly to avoid overheating the circuit
CAUTION: Do not connect the test fixture ground strap to any board printed foil.
heat sink in this receiver. 6. Use the following soldering technique.
a. Allow the soldering iron tip to reach a normal temperature
Electrostatically Sensitive (ES) Devices (500 °F to 600 °F)
Some semiconductor (solid-state) devices can be damaged eas- b. First, hold the soldering iron tip and solder the strand against
ily by static electricity. Such components commonly are called the component lead until the solder melts.
Electrostatically Sensitive (ES) Devices. Examples of typical ES c. Quickly move the soldering iron tip to the junction of the
devices are integrated circuits and some field-effect transistors component lead and the printed circuit foil, and hold it there
and semiconductor “chip” components. The following techniques only until the solder flows onto and around both the compo-
should be used to help reduce the incidence of component dam- nent lead and the foil.
age caused by static by static electricity. CAUTION: Work quickly to avoid overheating the circuit
1. Immediately before handling any semiconductor component or board printed foil.
semiconductor-equipped assembly, drain off any electrostatic d. Closely inspect the solder area and remove any excess or
charge on your body by touching a known earth ground. Alter- splashed solder with a small wire-bristle brush.
natively, obtain and wear a commercially available discharging
wrist strap device, which should be removed to prevent poten-
tial shock reasons prior to applying power to the unit under test.

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IC Remove/Replacement 3. Solder the connections.
Some chassis circuit boards have slotted holes (oblong) through CAUTION: Maintain original spacing between the replaced
which the IC leads are inserted and then bent flat against the cir- component and adjacent components and the circuit board to
cuit foil. When holes are the slotted type, the following technique prevent excessive component temperatures.
should be used to remove and replace the IC. When working with
boards using the familiar round hole, use the standard technique Circuit Board Foil Repair
as outlined in paragraphs 5 and 6 above. Excessive heat applied to the copper foil of any printed circuit
board will weaken the adhesive that bonds the foil to the circuit
Removal board causing the foil to separate from or "lift-off" the board. The
1. Desolder and straighten each IC lead in one operation by following guidelines and procedures should be followed whenever
gently prying up on the lead with the soldering iron tip as the this condition is encountered.
solder melts.
2. Draw away the melted solder with an anti-static suction-type At IC Connections
solder removal device (or with solder braid) before removing To repair a defective copper pattern at IC connections use the
the IC. following procedure to install a jumper wire on the copper pattern
Replacement side of the circuit board. (Use this technique only on IC connec-
1. Carefully insert the replacement IC in the circuit board. tions).
2. Carefully bend each IC lead against the circuit foil pad and
solder it. 1. Carefully remove the damaged copper pattern with a sharp
3. Clean the soldered areas with a small wire-bristle brush. knife. (Remove only as much copper as absolutely necessary).
(It is not necessary to reapply acrylic coating to the areas). 2. carefully scratch away the solder resist and acrylic coating (if
used) from the end of the remaining copper pattern.
"Small-Signal" Discrete Transistor 3. Bend a small "U" in one end of a small gauge jumper wire and
Removal/Replacement carefully crimp it around the IC pin. Solder the IC connection.
1. Remove the defective transistor by clipping its leads as close 4. Route the jumper wire along the path of the out-away copper
as possible to the component body. pattern and let it overlap the previously scraped end of the
2. Bend into a "U" shape the end of each of three leads remaining good copper pattern. Solder the overlapped area and clip off
on the circuit board. any excess jumper wire.
3. Bend into a "U" shape the replacement transistor leads.
4. Connect the replacement transistor leads to the corresponding At Other Connections
leads extending from the circuit board and crimp the "U" with Use the following technique to repair the defective copper pattern
long nose pliers to insure metal to metal contact then solder at connections other than IC Pins. This technique involves the
each connection. installation of a jumper wire on the component side of the circuit
board.
Power Output, Transistor Device
Removal/Replacement 1. Remove the defective copper pattern with a sharp knife.
1. Heat and remove all solder from around the transistor leads. Remove at least 1/4 inch of copper, to ensure that a hazardous
2. Remove the heat sink mounting screw (if so equipped). condition will not exist if the jumper wire opens.
3. Carefully remove the transistor from the heat sink of the circuit 2. Trace along the copper pattern from both sides of the pattern
board. break and locate the nearest component that is directly con-
4. Insert new transistor in the circuit board. nected to the affected copper pattern.
5. Solder each transistor lead, and clip off excess lead. 3. Connect insulated 20-gauge jumper wire from the lead of the
6. Replace heat sink. nearest component on one side of the pattern break to the lead
of the nearest component on the other side.
Diode Removal/Replacement Carefully crimp and solder the connections.
1. Remove defective diode by clipping its leads as close as pos- CAUTION: Be sure the insulated jumper wire is dressed so the
sible to diode body. it does not touch components or sharp edges.
2. Bend the two remaining leads perpendicular y to the circuit
board.
3. Observing diode polarity, wrap each lead of the new diode
around the corresponding lead on the circuit board.
4. Securely crimp each connection and solder it.
5. Inspect (on the circuit board copper side) the solder joints of
the two "original" leads. If they are not shiny, reheat them and if
necessary, apply additional solder.

Fuse and Conventional Resistor

Removal/Replacement
1. Clip each fuse or resistor lead at top of the circuit board hollow
stake.
2. Securely crimp the leads of replacement component around
notch at stake top.

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SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.

1. Application range
This spec sheet is applied to the LED TV used LA54H chassis

2. Test condition
Each part is tested as below without special notice.

1) Temperature : 25 ºC ± 5 ºC, (77 ± 9 ºF), CST : 40±5 ºC

2) Relative Humidity: 65 % ± 10 %
3) Power Voltage
Standard input voltage (100~240V@ 50/60Hz)
4) Specification and performance of each parts are followed
each drawing and specification by part number in
accordance with BOM.
5) The receiver must be operated for about 20 minutes prior to
the adjustment.

3. Test method
1) Performance: LGE TV test method followed
2) Demanded other specification
- Safety : UL, CSA, IEC specification
- EMC: FCC, ICES, IEC specification

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4. General Specification
No Item Specification Result Remark
1. Receiving System ATSC / NTSC-M / 64 & 256 QAM
2. Available Channel 1) VHF : 02~13
2) UHF : 14~69
3) DTV : 02-69
4) CATV : 01~135
5) CADTV : 01~135
3. Input Voltage AC 100 ~ 240V 50/60Hz Mark : 110V, 60Hz
4. Market NORTH AMERICA
5. Screen Size 55 inch Wide (3840X2160)
6. Aspect Ratio 16:9
7. Tuning System FS
8. Module LC490EQE-FHM2 LGD 49UF6700-UC
9. Operating Environment 1) Temp : 0 ~ 40 deg
2) Humidity : ~ 80 %
10. Storage Environment 1) Temp : -20 ~ 60 deg
2) Humidity : ~ 85 %

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5. Supported video resolutions
5.1. Component input(Y, CB/PB, CR/PR)
No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed
1 720*480 15.730 60.000 13.513 SDTV ,DVD 480I
2 720*480 15.730 59.940 13.500 SDTV ,DVD 480I
3 720*480 31.500 60.000 27.027 SDTV 480P
4 720*480 31.470 59.940 27.000 SDTV 480P
5 1280*720 45.000 60.000 74.250 HDTV 720P
6 1280*720 44.960 59.940 74.176 HDTV 720P
7 1920*1080 33.750 60.000 74.250 HDTV 1080I
8 1920*1080 33.720 59.940 74.176 HDTV 1080I
9 1920*1080 67.500 60.000 148.500 HDTV 1080P
10 1920*1080 67.432 59.940 148.352 HDTV 1080P
11 1920*1080 27.000 24.000 74.250 HDTV 1080P
12 1920*1080 26.970 23.976 74.176 HDTV 1080P
13 1920*1080 33.750 30.000 74.250 HDTV 1080P
14 1920*1080 33.710 29.970 74.176 HDTV 1080P

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5.2. HDMI Input (PC/DTV)
No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remarks
PC
1 640*350 31.468 70.09 25.17 EGA
2 720*400 31.469 70.08 28.32 DOS
3 640*480 31.469 59.94 25.17 VESA(VGA)
4 800*600 37.879 60.31 40.00 VESA(SVGA)
5 1024*768 48.363 60.00 65.00 VESA(XGA)
6 1152*864 54.348 60.053 80.00 VESA
7 1280*1024 63.981 60.02 108.00 VESA (SXGA) Support to HDMI-PC
8 1360*768 47.712 60.015 85.50 VESA (WXGA)
9 1920*1080 67.5 60 148.5 WUXGA(Reduced Blanking)
10 3840*2160 54 24.00 297.00 UDTV 2160P UHD only
11 3840*2160 56.25 25.00 297.00 UDTV 2160P UHD only
12 3840*2160 67.5 30.00 297.00 UDTV 2160P UHD only
13 4096*2160 53.95 23.97 296.703 UDTV 2160P UHD only
14 4096*2160 54 24.00 297.00 UDTV 2160P UHD only
DTV
1 640 * 480 31.469 59.94 25.125 SDTV 480P
2 640 * 480 31.5 60 25.125 SDTV 480P
3 720 * 480 15.73 59.94 13.500 SDTV 480I Spec. out but display
4 720 * 480 15.75 60.00 13.514 SDTV 480I Spec. out but display
5 720 * 480 31.5 60 27.027 SDTV 480P
6 720 * 480 31.47 59.94 27.00 SDTV 480P
7 1280*720 45 60.00 74.25 HDTV 720P
8 1280*720 44.96 59.94 74.176 HDTV 720P
9 1920*1080 33.75 60.00 74.25 HDTV 1080I
10 1920*1080 33.72 59.94 74.176 HDTV 1080I
11 1920*1080 26.97 23.976 63.296 HDTV 1080P
12 1920*1080 27.00 24.00 63.36 HDTV 1080P
13 1920*1080 33.71 29.97 79.120 HDTV 1080P
14 1920*1080 33.75 30.00 79.20 HDTV 1080P
15 1920*1080 67.432 59.94 148.350 HDTV 1080P
16 1920*1080 67.5 60.00 148.50 HDTV 1080P
17 3840*2160 53.95 23.98 296.703 UDTV 2160P UHD only
18 3840*2160 54 24.00 297.00 UDTV 2160P UHD only
19 3840*2160 56.25 25.00 297.00 UDTV 2160P UHD only
20 3840*2160 61.43 29.97 296.703 UDTV 2160P UHD only
21 3840*2160 67.5 30.00 297.00 UDTV 2160P UHD only
22 3840*2160 135 60.00 594 UDTV 2160P UHD only(Port1)
23 3840*2160 135 59.94 593.407 UDTV 2160P UHD only(Port1)
24 4096*2160 53.95 23.98 296.703 UDTV 2160P UHD only
25 4096*2160 54 24.00 297 UDTV 2160P UHD only
26 4096*2160 56.25 25.00 297 UDTV 2160P UHD only
27 4096*2160 61.43 29.97 296.703 UDTV 2160P UHD only
28 4096*2160 67.5 30.00 297 UDTV 2160P UHD only
29 4096*2160 135 60.00 594 UDTV 2160P UHD only(Port1)
30 4096*2160 135 59.94 593.407 UDTV 2160P UHD only(Port1)

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ADJUSTMENT INSTRUCTION
1. Application 4. MAIN PCBA Adjustments
This spec. sheet applies to LA54H Chassis applied LED TV all 4.1. ADC Adjustment
models manufactured in TV factory
4.1.1. Overview
- ADC adjustment is needed to find the optimum black level and
gain in Analog-to-Digital device and to compensate RGB
2. Specification deviation..
(1) Because this is not a hot chassis, it is not necessary to use
an isolation transformer. However, the use of isolation 4.1.2. Equipment & Condition
transformer will help protect test instrument. (1) Protocol: RS-232C
(2) Adjustment must be done in the correct order. (2) Inner Pattern
(3) The adjustment must be performed in the circumstance of - Resolution : 1080p(Comp) / 1024*768(RGB)
25 ±5 ºC of temperature and 65±10% of relative humidity if - Pattern : Horizontal 100% Color Bar Pattern
there is no specific designation - Pattern level : 0.7±0.1 Vp-p
(4) The input voltage of the receiver must keep 100~240V,
50/60Hz 4.1.3. Adjustment
(5) The receiver must be operated for about 5 minutes prior to 4.1.3.1. Adjustment method
the adjustment when module is in the circumstance of over - Connect to Jig by using RS-232(USB), adjust Component
15 ºC
In case of keeping module is in the circumstance of 0°C, it ※ Manual adj (If needed in Final Assembly)
should be placed in the circumstance of above 15°C for 2 - Required equipment : Adjustment R/C
hours - Enter Service Mode by pushing “ADJ” key,
In case of keeping module is in the circumstance of below - Start ‘OTP’ ADC Type by pushing ‘►’ key at [7. ADC Calibration]
-20°C, it should be placed in the circumstance of above ※ In L13 case, Adjust ADC(OTP) is automatically ‘OK’
15°C for 3 hours.
4.1.3.2. Adj. protocol (only Internal patten)
※ Caution
When still image is displayed for a period of 20 minutes or
longer (especially where W/B scale is strong. 4.2. EDID Download
Digital pattern 13ch and/or Cross hatch pattern 09ch), there 4.2.1. Overview
can some afterimage in the black level area ▪ I t is a VESA regulation. A PC or a MNT will display an
optimal resolution through information sharing without any
necessity of user input. It is a realization of “Plug and Play”.
3. Adjustment items 4.2.2. Equipment
3.1. Main PCBA Adjustments ▪ Since embedded EDID data is used, EDID download JIG,
(1) ADC adjustment(OTP) : Component HDMI cable and D-sub cable are not need.
(2) EDID downloads for HDMI ▪ Adjust by using remote controller

3.2. Final assembly adjustment 4.2.3. Download method

(1) White Balance adjustment 1) Press Adj. key on the Adj. R/C,
(2) RS-232C functionality check 2) Select EDID D/L menu.
(3) Factory Option setting per destination 3) By pressing Enter key, EDID download will begin
(4) Shipment mode setting (In-Stop) 4) If Download is successful, OK is display, but If Download is
(5) GND and HI-POT test failure, NG is displayed.
5) If Download is failure, Re-try downloads.

3.3. Appendix ※ Caution) When EDID Download, must remove RGB/HDMI

(1) Shipment conditions Cable.
(2) Tool option menu
(3) USB Download (S/W Update, Option and Service only)
(4) Preset CH Information

Copyright © LG Electronics. Inc. All rights reserved. - 10 - LGE Internal Use Only
Only for training and service purposes

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4.2.4. EDID DATA ▪ HDMI2 (E6 , 3F) – HDMI DEEP COLOR OFF
4.2.4.1. PCM
▪ HDMI1 (A0 , 6E) – HDMI DEEP COLOR ON

4.2.4.2. AC3
▪ HDMI1 (A0 , FC) - HDMI DEEP COLOR ON
▪ HDMI1 (E6 , 4F) – HDMI DEEP COLOR OFF

▪ HDMI1 (E6 , DD) - HDMI DEEP COLOR OFF

▪ HDMI2 (A0 , 5E) – HDMI DEEP COLOR ON

Copyright © LG Electronics. Inc. All rights reserved. - 11 - LGE Internal Use Only
Only for training and service purposes

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▪ HDMI2 (A0 , EC) - HDMI DEEP COLOR ON ▪ HDMI1 (E6 , D4) - HDMI DEEP COLOR OFF

▪ HDMI2 (A0 , E3) - HDMI DEEP COLOR ON

▪ HDMI2 (E6 , CD) - HDMI DEEP COLOR OFF

▪ HDMI2 (E6 , C4) - HDMI DEEP COLOR OFF

4.2.4.3. DTS
▪ HDMI1 (A0 , F3) - HDMI DEEP COLOR ON

Copyright © LG Electronics. Inc. All rights reserved. - 12 - LGE Internal Use Only
Only for training and service purposes

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5. Final Assembly Adjustment 5.1.4. Adjustment Command (Protocol)
(1) RS-232C Command used during auto-adj.
5.1. White Balance Adjustment
RS-232C COMMAND
5.1.1. Overview Explanation
5.1.1.1. W/B adj. Objective & How-it-works CMD DATA ID
(1) Objective: To reduce each Panel’s W/B deviation Wb 00 00 Begin White Balance adj.
(2) How-it-works: When R/G/B gain in the OSD is at 192, it
Wb 00 ff End White Balance adj.
means the panel is at its Full Dynamic Range.
(internal pattern disappears )
● Case : Cool Mode
- To adjust the white balance without the saturation, G gain
(2) Adjustment Map
should be adjust at least 172 and change the others (R,B
Gain) Adj. item Command Data Range
▪ When R or B gain is over 255, G gain can be adjust below (lower caseASCII) (Hex.)
172) CMD1 CMD2 MIN MAX
● Case : Medium / Warm Mode
Cool R Gain j g 00 C0
- To adjust the white balance without the saturation, Fix the
one of R/G/B gain to 192 (default data) and decrease the G Gain j h 00 C0
others. B Gain j i 00 C0
(3) Adj. condition: normal temperature
- Surrounding Temperature: 25 ± 5 °C Medium R Gain j a 00 C0
- Warm-up time: About 5 Min G Gain j b 00 C0
- Surrounding Humidity: 20% ~ 80% B Gain j c 00 C0
- Before White balance adjustment, Keep power on status,
don’t power off Warm R Gain j d 00 C0
G Gain j e 00 C0
5.1.1.2. Adj. condition and cautionary items B Gain j f 00 C0
(1) Lighting condition in surrounding area surrounding lighting
should be lower 10 lux. Try to isolate adj. area into dark
surrounding. 5.1.5. Adjustment method
(2) Probe location : Color Analyzer (CA-210) probe should be 5.1.5.1. Auto WB calibration
within 10cm and perpendicular of the module surface (1) Set TV in ADJ mode using P-ONLY key (or POWER ON
(90 ° ± 2.5 °) key)
(3) Aging time (2) Place optical probe on the center of the display
- A fter Aging Start, Keep the Power ON status during 5 - It need to check probe condition of zero calibration before
Minutes. adjustment.
- In case of LCD, Back-light on should be checked using no (3) Connect RS-232C Cable
signal or Full-white pattern. (4) Select mode in ADJ Program and begin a adjustment.
(5) When WB adjustment is completed with OK message,
check adjustment status of pre-set mode (Cool, Medium,
5.1.2. Equipment Warm)
(1) Color Analyzer: CA-210 (NCG: CH 9 / WCG: CH12 / LED:
(6) Remove probe and RS-232C cable.
CH14)
▪ W/B Adj. must begin as start command “wb 00 00” , and
(2) A dj. Computer (During auto adj., RS-232C protocol is
finish as end command “wb 00 ff”, and Adj. offset if need
needed)
(3) Adjust Remocon
5.1.5.2. Manual adjustment
(4) V ideo Signal Generator MSPG-925F 720p/204-Gray
(1) Set TV in Adj. mode using POWER ON
(Model: 217, Pattern: 49)
(2) Zero Calibrate the probe of Color Analyzer, then place it on
→ Only when internal pattern is not available
the center of LCD module within 10cm of the surface..
※ Color Analyzer Matrix should be calibrated using CS-1000
(3) Press ADJ key → EZ adjust using adj. R/C → 8. White-
Balance then press the cursor to the right (KEY►).
5.1.3. Equipment connection ( When KEY(►) is pressed 204 Gray(80IRE) internal
pattern will be displayed)
(4-a) Adjust modes (Cool) : Fix the G gain at least 172 and
change the others (R/B Gain).
▪ If R or B gain is over 255, G gain can be adjust below 172.
(4-b) Adjust two modes ( Medium / Warm) : Fix the one of
R/G/B gain to 192 (default data) and decrease the others

Copyright © LG Electronics. Inc. All rights reserved. - 13 - LGE Internal Use Only
Only for training and service purposes

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※ CASE : Cool mode ** (normal line) LGD Cell
First adjust the coordinate far away from the target value(x, ** Gumi winter season (Jan ~ Feb) & Global, except Cinema
y).B Screen models
(1) x, y >target ▪ S tandard color coordinate and temperature using
(2) x, y< target CA-210(CH-14) – by aging time
(3) x >target , y< target Cool Medium Warm
(4) x < target , y >target Aging time
-E very 4 case have to fit y value by adjusting B Gain and NC4 X Y X Y X Y
(Min)
then fit x value by adjusting R-Gain 271 270 286 289 313 329
- In this case, increasing/decreasing of B Gain and R Gain
1 0-2 286 295 301 314 328 354
can be adjusted.
2 3-5 284 290 299 309 326 349
► How to adjust 3 6-9 282 287 297 306 324 346
(1) Fix G gain at least 172 : Adjust R, B Gain ( In Case of
4 10-19 279 283 294 302 321 342
Mostly Blue Gain Saturation )
(2) When R or B Gain > 255, Release Fixed G Gain and 5 20-35 276 278 291 297 318 337
Readjust 6 36-49 274 275 289 294 316 334
7 50-79 273 272 288 291 315 331
※ CASE : Medium / Warm mode
First adjust the coordinate far away from the target value(x, y). 8 80-119 272 271 287 290 314 330
(1) x, y >target 9 Over 120 271 270 286 289 313 329
i) Decrease the R, G.
(2) x, y< target ** INX, AUO, Sharp, CSOT Models (Cool Mode Spec :
i) First decrease the B gain, 13000K)
ii) Decrease the one of the others. ▪ S tandard color coordinate and temperature using
(3) x >target , y< target CA-210(CH-14) – by aging time
i) First decrease B, so make y a little more than the target.
ii) Adjust x value by decreasing the R cool med warm
(4) x < target , y >target x y x y x y
i) First decrease B, so make x a little more than the target. spec 271 270 286 289 313 329
ii) Adjust x value by decreasing the G
target 278 280 293 299 320 339
5.1.6. Reference (White Balance Adj. coordinate and
color temperature) 5.2. Option selection per country
▪ Luminance: 204 Gray, 80IRE 5.2.1. Overview
(1) Tool option selection is only done for models in Non-USA
** (normal line) LGD Cell North America due to rating
** Except Gumi winter season (Mar ~ Dec) & Global (2) Applied model: LA54H/J Chassis applied to CANADA and
▪ S tandard color coordinate and temperature using MEXICO
CA-210(CH-14) – by aging time
Cool Medium Warm 5.2.2. Country Group selection
Aging time (1) Press ADJ key on the Adj. R/C, and then select Country
L15 X Y X Y X Y
(Min)
Group Menu
271 270 286 289 313 329
(2) Depending on destination, select US, then on the lower
1 0-2 282 289 297 308 324 348 Country option, select US, CA, MX.
2 3-5 281 287 296 306 323 346 Selection is done using +, - KEY
3 6-9 279 284 294 303 321 343
4 10-19 277 280 292 299 319 339
5.2.3. Tool Option inspection
▪ Press Adj. key on the Adj. R/C, then select Tool option
5 20-35 275 277 290 296 317 336
Model Module Tool 1 Tool 2 Tool 3 Tool 4 Tool 5 Tool 6
6 36-49 274 274 289 293 316 333
55UF6700- EDGE 432 2473 35660 5667 514 325
7 50-79 273 272 288 291 315 331 UC (LGD)
8 80-119 272 271 287 290 314 330
9 Over 120 271 270 286 289 313 329

** (Aging chamber) LGD Cell

▪ S tandard color coordinate and temperature using
CA-210(CH-14) – by aging time

Copyright © LG Electronics. Inc. All rights reserved. - 14 - LGE Internal Use Only
Only for training and service purposes

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6. GND and HI-POT Test 8. Control Key Check UI
6.1. GND & HI-POT auto-check preparation 8.1. Test method
(1) Check the POWER CABLE and SIGNAL CABE insertion (1) Condition : Power Only Full White Mode
condition (2) When you check the operation of control key, appear the UI
such as below figure on TV Screen.
6.2. GND & HI-POT auto-check (3) In case of the model applied the joystick type control key
(1) Pallet moves in the station. (POWER CORD / AV CORD is (xxLF56, xxLF55, xxLF60 and xxLF62), the UI Sequence is
tightly inserted) CH+, CH-, Vol+, Vol-, Enter and TEST OK such as figure 1.
(2) Connect the AV JACK Tester. (4) In case of the model applied rotary switch type (xxLF640R-
(3) Controller (GWS103-4) on. NA KR only), the UI Sequence is Channel Up, Channel
(4) GND Test (Auto) Down, Volume Up, Volmue Down, Enter, Test OK, Input
- If Test is failed, Buzzer operates. Select and Power such as figure 2.
- If Test is passed, execute next process (Hi-pot test).
(Remove A/V CORD from A/V JACK BOX)
(5) HI-POT test (Auto)
- If Test is failed, Buzzer operates.
- If Test is passed, GOOD Lamp on and move to next process
automatically.

6.3. Checkpoint
(1) Test voltage
- GND: 1.5KV/min at 100mA
- SIGNAL: 3KV/min at 100mA Fig.1
(2) TEST time: 1 second
(3) TEST POINT
- GND Test = POWER CORD GND and SIGNAL CABLE GND.
- Hi-pot Test = POWER CORD GND and LIVE & NEUTRAL.
(4) LEAKAGE CURRENT: At 0.5mArms

7. AUDIO output check

7.1. Audio input condition
(1) RF input: Mono, 1KHz sine wave signal, 100% Modulation
(2) CVBS, Component: 1KHz sine wave signal (0.4Vrms) Fig.2
(3) RGB PC: 1KHz sine wave signal (0.7Vrms)

7.2. Specification
No Item Min Typ Max Unit Remark
1 Audio practi- 9.0 10.0 12.0 W (1) Measurement
cal max 8.5 8.9 9.8 Vrms condition
Output, L/R -E Q/AVL/Clear
(Distor- Voice: Off
tion=10% (2) Speaker (8Ω
max Output) Impedance)
(3) LF62, LF60, LF59,
LF56
2 Audio practi- 4.5 5.0 6.0 W (1) Measurement
cal max 6.0 6.32 6.93 Vrms condition
Output, L/R -E Q/AVL/Clear
(Distor- Voice: Off
tion=10% (2) Speaker (8Ω
max Output) Impedance)
(3) LF55

Copyright © LG Electronics. Inc. All rights reserved. - 15 - LGE Internal Use Only
Only for training and service purposes

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9. USB S/W Download (7) In terms of FRC version update, below sequence are the
only for 60LF6000-Ux model.
(optional, Service only) (a) When the main sw downloading was finished, if FRC
(1) Put the USB Stick to the USB socket SW version of TV Set is lower than the FRC version
(2) Automatically detecting update file in USB Stick Included in downloading version, FRC verison update
- If your downloaded program version in USB Stick is lower will be started automatically during displaying the below
than that of TV set, it didn’t work. Otherwise USB data is figure.
automatically detected.
(3) Show the message “Copying files from memory”

(b) Be careful to not be off of TV Power.

(c) U dating the FRC is completed, the TV will restrart
automatically.
(d) C heck your updated FRC version on TV set with
(4) Updating is staring. pushing “IN-START” key in service remote controller.
(e) In references, FRC version value shown in TV may
differ from below value.
Refer to the BOM aobut the latest FRC version.

(5) Updating Completed, The TV will restart automatically

(6) If your TV is turned on, check your updated version and
Tool option.
* If downloading version is more high than your TV have, TV * After downloading, TOOL OPTION setting is needed again.
can lost all channel data. In this case, you have to channel (1) Push "IN-START" key in service remote controller.
recover. If all channel data is cleared, you didn’t have a DTV/ (2) Select "Tool Option 1" and Push “OK” button.
ATV test on production line. (3) Punch in the number. (Each model has their number.)

Copyright © LG Electronics. Inc. All rights reserved. - 16 - LGE Internal Use Only
Only for training and service purposes

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1. No video (Main IC Block)

Audio OK

Check stand-by voltage 3.5V NG Check Power connector NG Short check NG

Replace Power board.
P401/P402 5,7,8 pin (24pin/28pin) stand-by voltage 3.5V

OK
NG

Only for training and service purposes

Check stand-by voltage 3.5V Replace
L400,L401,ZD400,C400,C407 L400,L401,ZD400,C400,C407

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OK
NG
Check X-TAL X101 Replace X101

LG Electronics. Inc. All rights reserved.

Check POWER ON signal Low NG Replace IC101
Download software (Main)
P401/P402 1 pin or Main Board

High

- 17 -
Check multi voltage 12V, 24V NG NG NG
Check Power connector Short check
P401/P402 11,12,13,14,15p : 12V Replace Power board.
(24pin/28pin) multi voltage 12V, 24V
P401/P402 18,19,20,21p : 24V

OK
Check Main IC power block
TROUBLESHOOTING

IC404 : 1.5V , Q406 : 3.3V Replace IC404, Q406, IC403

IC403 : 1.1V

LGE Internal Use Only

2. No video (Back-end Block)
Check Audio (Speaker out) Previous page (Main IC block)

Check URSA9 IC power block

IC13403 : 1.5V , IC13401 : 3.3V Replace IC13403, IC13401, IC13402
IC13402 : 1.15V

Only for training and service purposes

OK
NG

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Vx1 power voltage Q405 : 12V Replace Q405

OK
NG NG Replace IC2500
Vx1 output signal Download software (URSA9)
or Main Board

LG Electronics. Inc. All rights reserved.

Check DRV ON signal Low NG

Replace Main Board Check Power Board
P401/P402 2 pin
High
NG

- 18 -
Check Vx1 cable Replace Vx1 cable
OK

Check LCD Module

LGE Internal Use Only

3. Digital / Analog TV Video No signal
Check RF cable & signal

Check Tuner power NG

Replace L3701, L3704
L3701, L3704 : 3.3V

OK
NG Replace Tuner
Check Tuner I2C NG
Replace R3716, R3717, R3738, R3739 or IC101
R3716, R3717, R3738, R3739
or Main Board

Only for training and service purposes

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Check IF signal NG
Replace Tuner
TU3700 6,7 pin
OK

LG Electronics. Inc. All rights reserved.

Replace IC101 or Main Board

- 19 -LGE Internal Use Only

4. AV Video No signal
Check input signal format.

Check AV cable

OK
Check AV Jack CVBS signal NG
Replace AV Jack JK2802
ZD2802

Only for training and service purposes

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Check CVBS signal NG
ZD2802, ZD2803, Replace ZD2802, ZD2803, R2859, R246, C238
R2859, R246, C238

LG Electronics. Inc. All rights reserved.

Replace IC101 or Main Board

- 20 -LGE Internal Use Only

5. Component Video No signal
Check input signal format.

Check Component cable

OK
Check AV Jack CVBS signal NG
Replace AV Jack JK2802
ZD2802, ZD2804, ZD2806

Only for training and service purposes

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Check Component signal Y NG
ZD2802, ZD2803, Replace ZD2802, ZD2803, R2859, R241, C231
R2859, R241, C231

LG Electronics. Inc. All rights reserved.

Check Component signal Pb NG

ZD2804, ZD2805, Replace ZD2804, ZD2805, R2800, R239, C229
R2800, R239, C229

- 21 -
Check Component signal Pr NG
ZD2806, ZD2807, Replace ZD2806, ZD2807, R2801, R243, C233
R2801, R243, C233

Replace IC101 or Main Board

LGE Internal Use Only

6. HDMI Video No signal (HDMI S/W Block)
Check input signal format.

Check HDMI cable

OK
NG
Check X-TAL X3200 Replace X3200

Only for training and service purposes

Check HDMI S/W IC power block NG

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1.1V : IC3205, L3205, L3200,
L3203, Replace IC3205, Q3204
3.3V : Q3204 , L3201, R3214,
L3204, R3221

LG Electronics. Inc. All rights reserved.

OK Replace IC3200
NG Check DDC component NG Replace DDC component NG or Main Board
Check DDC in-start menu HDMI1 : AR3207, AR3201, D3218 HDMI1 : AR3207, AR3201, D3218 or HDMI Jack
HDMI2 : AR3204, AR3200, D3208 HDMI2 : AR3204, AR3200, D3208 HDMI1 : JK3203
OK HDMI2 : JK3200

- 22 -
Check TMDS signal
NG Replace HDMI Jack NG
HDMI1 : JK3203 Replace IC3200
HDMI1 : JK3203
HDMI2 : JK3200 or Main Board
HDMI2 : JK3200
1,3,4,6,7,9,10,12 pin

Next page (URSA9, M1A Block)

LGE Internal Use Only

7. HDMI Video No signal (URSA9, M1A Block)
Replace HPD component Replace IC101

Copyright ©
Check HPD NG HDMI1 : VA3216, R3204, Q3201, NG or Main Board
HDMI1 : JK3203 19 pin R3215, R3213, R3216 or HDMI Jack
HDMI2 : JK3200 19 pin HDMI2 : VA3205, R3202, Q3200, HDMI1 : JK3203
R3205, R3233, R3218 HDMI2 : JK3200
OK

Check URSA9 I2C NG Replace URSA9 I2C component NG Replace URSA9 IC (IC2500)
R216, R217, R146, R147 R216, R217, R146, R147 or Main IC (IC101)
R13235, R13237, R13204, R13219 R13235, R13237, R13204, R13219 or Main Board

Only for training and service purposes

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Check HDMI pattern
NG
IC3200 ↔ IC2500 HDMI pattern Replace Main Board
IC2500 ↔ IC101 HDMI pattern

LG Electronics. Inc. All rights reserved.

Replace URSA9 IC (IC2500)

or Main IC (IC101)
or Main Board

- 23 -LGE Internal Use Only

8. USB No storage
Check USB device

Check USB 5V DCDC IC NG Replace USB 5V DCDC IC

IC405 output voltage : 5V IC405
OK

Check USB 5V OCP IC NG Replace USB 5V OCP IC

Only for training and service purposes

IC406 output voltage : 5V IC406

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Check USB signal NG NG Replace USB Jack (JK700)
Replace R700, R701
R700, R701 or Main IC (IC101)

LG Electronics. Inc. All rights reserved.

Replace Main IC (IC101)

or Main Board

- 24 -LGE Internal Use Only

9. All source Audio
Check the TV Speaker Menu NG

Check AMP IC (IC5600) Power NG Replace AMP power component NG Check Power connector NG
L5600 : 24V L5600 : 24V Replace Power board.
(24pin/28pin)
L5601 : 3.3V L5601 : 3.3V

Only for training and service purposes

Check AMP I2C NG Replace AMP I2C component NG Replace AMP IC (I C5600)

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R141, R144, R5604, R5605 R141, R144, R5604, R5605 or Main IC (IC101)
C5607, C5608 C5607, C5608 or Main Board

LG Electronics. Inc. All rights reserved.

Check I2S signal NG Replace Main IC (IC101)
IC5600 7, 8, 38 pin or Main Board

OK
NG Replace amp output component NG NG
Check amp output signal Replace amp out wafer Replace AMP IC (I C5600)
L5602, L5603, L5604, L5605

- 25 -
P5600 1, 2, 3, 4 pin P5600 or Main Board
C5622, C5623, C5627, C5628
OK
NG
Check speaker connector Replace speaker connector

OK
NG
Check speaker Replace speaker

LGE Internal Use Only

10. Digital / Analog TV No sound
Check RF cable & signal

Check Tuner power NG

Replace L3701, L3704
L3701, L3704 : 3.3V

OK
NG Replace Tuner
Check Tuner I2C NG
Replace R3716, R3717, R3738, R3739 or IC101
R3716, R3717, R3738, R3739
or Main Board

Only for training and service purposes

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Check IF signal NG
Replace Tuner
TU3700 6,7 pin
OK

LG Electronics. Inc. All rights reserved.

Follow procedure
“9. All source audio”

- 26 -LGE Internal Use Only

11. AV No sound
Check AV cable

Check audio signal Replace audio signal component

Only for training and service purposes

L : R2802, C2803, R2810 NG L : R2802, C2803, R2810
R2815, C216 R2815, C216

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R : R2803, C2802, R2811 R : R2803, C2802, R2811
R2816, C219 R2816, C219

LG Electronics. Inc. All rights reserved.

Follow procedure
“9. All source audio”

- 27 -LGE Internal Use Only

12. Component No sound
Check Component cable

Check audio signal Replace audio signal component

Only for training and service purposes

L : R2802, C2803, R2810 NG L : R2802, C2803, R2810
R2815, C216 R2815, C216

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R : R2803, C2802, R2811 R : R2803, C2802, R2811
R2816, C219 R2816, C219

LG Electronics. Inc. All rights reserved.

Follow procedure
“9. All source audio”

- 28 -LGE Internal Use Only

13. HDMI No sound
Check input signal format.

Check HDMI pattern NG

Replace Main Board

Only for training and service purposes

IC2500 ↔ IC101 HDMI pattern

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Replace URSA9 IC (IC2500)
or Main IC (IC101)
or Main Board

LG Electronics. Inc. All rights reserved.

- 29 -LGE Internal Use Only
Copyright ©
X-tal
24MHz

R Embeded
Air/ DDR3 2Gb
E Cable TUNER IF (+/-)
A Digital / Analog Demod

Only for training and service purposes

(Half Nim)
R
(H)
Nand Flash

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(1Gb)

SPI Flash
S SPI
OCP USB (1MB)
USB1(2.0)

LG Electronics. Inc. All rights reserved.

I Boot
1.5A
D RS232C /
E UART M1A
(V) Headphone out
System eeprom
I2C
(256Kb)
HDMI
Rx
MAIN Audio

- 30 -
I2S Out AMP(2ch)
AV/COMP CVBS/YPbPr I2C NTP7515

IR/KEY IR / Joystick SUB

OPTIC SPDIF OUT LVDS ASSY
BLOCK DIAGRAM

(60Hz)
R
E HDMI1.4
A 1920x2160P
R Vx1
(H) (8lane for 60Hz)
HDMI
(16lane for 120Hz)
Tx
4K@60P(6G) / HDCP2.2
HDMI1(HDMI2.0) 4K@60P(3G,even)
URSA9
HDMI S/W HDMI DDR3 1Gb x4
4K@60P(6G) / HDCP2.2 MN864788 4K@60P(3G,odd) Rx
HDMI2(HDMI2.0)

LGE Internal Use Only

EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

910

911
400

900
120
800

521

121
540
LV1

530

350

Stand screw
A10
200

A2
820

Copyright © LG Electronics. Inc. All rights reserved. - 31 - LGE Internal Use Only
Only for training and service purposes

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L14 POWER BLOCK (POWER DETECT 2)
+24V +12V +3.5V_POWER_DET +3.5V_ST
R435
100K
Power_DET +12V
OPT OPT OPT
R457
8.2K
1%
R430
2.7K
1%
R432
0
5% RESET_IC_DIODES(MULTI)
OPT
R438
4.7K RESET_IC_KEC(MULTI)
IC401-*1
Upper 79"
PANEL_POWER TYP 6000mA
IC401 L408 L412
APX803E29 KIC7529M2
R454
VCC RESET 100 5%
3 2 POWER_DET VCC OUT MLB-201209-0120P-N2
3 2
C415 1
R431 C422 1 PANEL_VCC
0.1uF 1.2K GND
16V POWER_DET_RESET 0.1uF GND C425
1% PANEL_FET_AOS(MULTI)
0.1uF Q405
AO4447A
OPT 25V
+24V +3.5V_POWER_DET R436 S_1
1 8
D_4
100K
S_2 D_3
R445 C427 C438 2 7

OPT 10K 10uF 10uF S_3 D_2

OPT OPT 3 6
R451 R452 C439 C440
R427 R458 IC402 16V 16V
27K 0 APX803E29 OPT G
4 5
D_1 2K 2K 10uF 10uF
1% 5% R437 OPT OPT 16V 16V
VCC RESET 100 5%
3 2
R446
OPT OPT 1 PANEL_FET_ROHM(MULTI)
1.8K
C413 R428 GND
Q405-*1
RRH140P03TB
0.1uF 5.1K
16V 1% C S_1 1 8 D_4
R442
10K B Q403
Ready - Dual Power Det Power Detect activity
PANEL_CTL 2N3904S
S_2 2 7 D_3

NPN_KEC(MULTI) S_3 3 6 D_2

R417 E
G 4 5 D_1

Detect Valtage Now is Use Circuit Designator 10K

C
B Q403-*1
Power Detect +3.5V R432, R454-*1, R438 MMBT3904(NXP)
NPN_NXP(MULTI)
E
* Notice Power Detect +12V O R430, R431, R454
- Applying all inch models for LCD L14
- Dual Power Det is used Power Detect +24V R457, R454
for detecting two kinds of voltage

3.3V_FET_AOS(MULTI)
+3.3V_Normal Q406-*1
AO3435
+1.10V_VDDC
+3.5V_ST
S

IC403 +3.3V_NORMAL

+3.5V_ST
L406 TPS5432DDAR [EP]GND
+3.3V_NORMAL CB2012PK501T
G

C418
OPT 0.01uF
3.3V_FET_TOSHIBA(MULTI) C437 C436 C414 C435 BOOT SS R429
1 8
Q406 L410 0.1uF 10uF 10uF 0.1uF 10K

THERMAL
SSM3J332R BLM18PG121SN1D 16V 10V 10V 16V
+1.10V_VDDC VIN EN

9
Vout=1.25*(1+R2/R1)+Iadj*R2
D

+1.5V_DDR 2 7
S

L407 C417
3.6uH 0.1uF
C428 C429 C430 16V PH COMP
G

+3.3V_NORMAL R443 R447 3 6 C416

+1.5V_DDR
10K 22K 2.2uF
10V
0.1uF
16V
22uF
10V
ZD402
5V 3A 0.33uF
OPT R433 16V
TVS_SEMTECH(MULTI) C421 C420 GND VSENSE
ZD401 C424 4 5 2.7K
L409 IC404 L411 22uF 22uF
2.5V 0.1uF 1%
AZ1117EH-ADJTRG1 CB2012PK501T 10V 10V
BLM18PG121SN1D 16V C419 C434
C423 R439
R448 0.039uF 390pF
50V 20K
IN OUT 2.2K R1 50V 50V
270pF 1%
ZD402-*1
ADJ/GND
C426 R449 R453 ZD403
1K R1 0 2.5V C C
10uF R444 R440
10V 1/16W POWER_ON/OFF_1 10K B Q404 B Q404-*1 TVS_KEC(MULTI) R2
1% C431 47K
2N3904S MMBT3904(NXP) 1%
10uF
1.3A R450
200 R2
10V
E
NPN_KEC(MULTI)
E
NPN_NXP(MULTI)
1/16W
1%

Vout=0.808*(1+R1/R2)

+12V
FROM LIPS or POWER B/D
+5V_Normal
PWM_DIM_SYNC

+5V_NORMAL
Q401-*1
PWM_DIM

PNP_NXP(MULTI)
L404 MMBT3906(NXP)
BLM18PG121SN1D +3.3V_NORMAL POWER_28P

1 3
PWR ON 1 2 DRV ON
2
C403 C404 PDIM1 3 4 PDIM2
10uF 0.1uF +3.5V_ST 3.5V 5 6 GND
16V R414 R416
IC405 Q401 0 0 3.5V 7 8 3.5V
R415 PNP_KEC(MULTI) GND GND
BD9D321EFJ [EP] C Q400-*1 2N3906S-RTK PWM_from_MAIN PWM_from_TCON 9 10
10K 12V 12V
B MMBT3904(NXP) 11 12
NPN_NXP(MULTI) 12V 13 14 12V
EN VIN 1 3
1 8 12V 15 16 GND
E
16V R406 GND 24V
THERMAL

0.1uF 10K 2 OPT 17 18

R408 R409 FB BOOT C411 R412 24V 19 20 24V
9

2 7 +3.5V_ST 33K
R404 24V 21 22 GND
R1 120K 6.8K L405 4.7K
POWER_28P GND NC C
1% 1% 3.6uH 23 24
VREG SW OPT URSA_OPT_5R407 33 SCLK GND
3 6 R400 25 26 B
C405 10K C Q400 SIN V_SYNC 33 R413
100pF LPH6050T-3R6N-R R402 27 28 URSA_L/D_VSYNC
50V 10K B 2N3904S R411 33
SS GND C412 URSA_OPT_6POWER_28P POWER_28P E

R410
4
3A 5
22uF
10V
C443
22uF
10V
RL_ON
R401
NPN_KEC(MULTI)

R455
R424
3.9K
C408
18pF
C432
18pF
29
C441
18pF
+3.3V_NORMAL Q402-*1
MMBT3904(NXP)
E OPT OPT OPT NPN_NXP(MULTI)
.

C409 C410 10K 0 P402 +3.5V_ST

22K R420
1uF 2200pF OPT 1K
1% 10V 50V R456
0 R419
R2 100 R426
ZD404-*1
ZD404 10K
C
+3.5V_POWER_DET 5V R425
TVS_SEMTECH(MULTI) POWER_24P B 10K
TVS_KEC(MULTI) INV_CTL
L400
CB2012PK501T E Q402
+3.5V_ST PWR ON 1 2 DRV ON 2N3904S NPN_KEC(MULTI)
ZD400-*1 PDIM1 PDIM2 R423
C407 C400 L401 3 4 PWM1
10uF 1uF ZD400 CB2012PK501T 3.5V GND
10V 10V 5 6 100
2012 1005 5V 3.5V 3.5V
TVS_KEC(MULTI) TVS_SEMTECH(MULTI) 7 8
OPT GND GND OPT
L403 9 10
MLB-201209-0120P-N2 12V 12V R467
+5V_USB +12V 11 12 1K
+3.3V_NORMAL +5V_NORMAL C433 C402 12V 12V
13 14
4.7uF 0.1uF 12V GND
16V 16V 15 16
IC406
GND 17 18 24V
BD2242G 3216 L402
MLB-201209-0120P-N2 24V 24V
+24V 19 20
24V 21 22 GND
VIN VOUT C442 C401
R405 GND NC
4.7K 1 6 4.7uF 0.1uF 23 24
50V 50V
R470
C406 GND ILIM 3216 0
0.1uF 2 5 25
16V
14K

P401
1%

R418

EN OC
USB1_OCD 3 4
1458mA

USB1_CTL

R403
10K

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS M1A_URSA9_UD 2014.04.24
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Power_PD2 04

Copyright ⓒ 2015 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Downloaded
Only for training andfrom www.Manualslib.com manuals search engine
service purposes
USB 3216 CAP(SIDE)

+5V_USB

JK700
ZD700 C703
SD05 C700
3AU04S-305-ZC-(LG)

10uF 10uF
1

5V
OPT 10V 10V
USB DOWN STREAM

OPT
2

SIDE_USB1_DM
R700
2.2
3

SIDE_USB1_DP
OPT OPT R701
C701 C702 2.2
5pF 5pF
4

50V 50V
5

OPT
D700
RCLAMP0502BA

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

Copyright ⓒ 2015 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Downloaded from www.Manualslib.com manuals search engine
Only for training and service purposes
SPDIF

SPDIF OPTIC JACK

+3.3V_NORMAL
5.15 Mstar Circuit Application

SPDIF_OPTIC_SOLTEAM SPDIF_OPTIC_FOXCONN
JK1001 JK1001-*1
JST1223-001 2F01TC1-CLM97-4F

GND GND 1
1

Fiber Optic

VCC VCC 2
2

VINPUT VIN 3
3

SPDIF_OUT
4
4

C1001 C1002
FIX_POLE

SHIELD

OPT 1uF 18pF

10V 50V
SPDIF_OPTIC
ESD Ready

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

R1205 1K 1% R1204 1K 1%

+1.5V_DDR +1.5V_DDR
DDR_EXT

DDR_EXT
C1202 1000pF

A-MVREFDQ A-MVREFCA
1K1%

C1201 0.1uF

C1213 0.1uF

C12141000pF

10uF 10V

C1219

C1220

C1221

C1222

C1223
DDR_EXT

DDR_EXT

0.1uF

0.1uF
C1217

C1218

C1224
DDR_EXT

DDR_EXT

C1216

1uF

1uF
R1202

OPT OPT OPT OPT OPT OPT OPT OPT

OPT

CLose to DDR3 CLose to Saturn7M IC

DDR_1600_1G_HYNIX M1A_256M M1A_128M M1A_256M_AVS+_CHINA M1A_128M_AVS+_CHINA

IC1201 IC101 IC101-*1 IC101-*2 IC101-*3
H5TQ1G63EFR-PBC LGE2134(256M) LGE2133(128M) LGE2136(256M) LGE2135(128M)

EAN61829003
M8 N3 E11 E11 E11 E11
A-MVREFCA VREFCA A0 A-MA0 A-MA0 B_DDR3_A[0] B_DDR3_A[0] B_DDR3_A[0] B_DDR3_A[0]
DDR_1600_1G_SS DDR_1600_2G_HYNIX_OLD DDR_1600_2G_HYNIX_NEW DDR_1600_2G_SS P7 F12 F12 F12 F12
IC1201-*1 IC1201-*2 IC1201-*3 IC1201-*4 A1 A-MA1 A-MA1 B_DDR3_A[1] B_DDR3_A[1] B_DDR3_A[1] B_DDR3_A[1]
P3 D10 D10 D10 D10
K4B1G1646G-BCK0 H5TQ2G63DFR-PBC H5TQ2G63FFR-PBC K4B2G1646Q-BCK0 A2 A-MA2 A-MA2 B_DDR3_A[2] B_DDR3_A[2] B_DDR3_A[2] B_DDR3_A[2]
H1 N2 B10 B10 B10 B10
EAN61836301 EAN61829203 EAN61829204 EAN61848803 A-MVREFDQ VREFDQ A3 A-MA3 A-MA3 B_DDR3_A[3] B_DDR3_A[3] B_DDR3_A[3] B_DDR3_A[3]
N3 M8 N3 M8 N3 M8 N3 M8 P8 E15 E15 E15 E15
P7
A0 VREFCA
P7
A0 VREFCA
P7
A0 VREFCA
P7
A0 VREFCA
A4 A-MA4 A-MA4 B_DDR3_A[4] B_DDR3_A[4] B_DDR3_A[4] B_DDR3_A[4]
P3
A1
P3
A1
P3
A1
P3
A1
DDR_EXT P2 B11 B11 B11 B11
N2
A2
H1 N2
A2
H1 N2
A2
H1 N2
A2
H1 R1203 A5 A-MA5 A-MA5 B_DDR3_A[5] B_DDR3_A[5] B_DDR3_A[5] B_DDR3_A[5]
P8
A3 VREFDQ
P8
A3 VREFDQ
P8
A3 VREFDQ
P8
A3 VREFDQ L8 R8 F14 F14 F14 F14
P2
A4
P2
A4
P2
A4
P2
A4
ZQ A6 A-MA6 A-MA6 B_DDR3_A[6] B_DDR3_A[6] B_DDR3_A[6] B_DDR3_A[6]
R8
A5
L8 R8
A5
L8 R8
A5
L8 R8
A5
L8 240 R2 C11 C11 C11 C11
R2
A6 ZQ
R2
A6 ZQ
R2
A6 ZQ
R2
A6 ZQ +1.5V_DDR A7 A-MA7 A-MA7 B_DDR3_A[7] B_DDR3_A[7] B_DDR3_A[7] B_DDR3_A[7]
T8
A7
T8
A7
T8
A7
T8
A7 1% T8 D14 D14 D14 D14
R3
A8
B2 R3
A8
B2 R3
A8
B2 R3
A8
B2 A8 A-MA8 A-MA8 B_DDR3_A[8] B_DDR3_A[8] B_DDR3_A[8] B_DDR3_A[8]
L7
A9 VDD_1
D9 L7
A9 VDD_1
D9 L7
A9 VDD_1
D9 L7
A9 VDD_1
D9 B2 R3 A12 A12 A12 A12
R7
A10/AP VDD_2
G7 R7
A10/AP VDD_2
G7 R7
A10/AP VDD_2
G7 R7
A10/AP VDD_2
G7 VDD_1 A9 A-MA9 A-MA9 B_DDR3_A[9] B_DDR3_A[9] B_DDR3_A[9] B_DDR3_A[9]
DDR_EXT 10V C1203 D9 L7 F16 F16 F16 F16
A11 VDD_3 A11 VDD_3 A11 VDD_3 A11 VDD_3
N7 K2 N7 K2 N7 K2 N7 K2 10uF A-MA10 A-MA10
T3
A12/BC VDD_4
K8 T3
A12/BC VDD_4
K8 T3
A12/BC VDD_4
K8 T3
A12/BC VDD_4
K8 VDD_2 A10/AP B_DDR3_A[10] B_DDR3_A[10] B_DDR3_A[10] B_DDR3_A[10]
A13 VDD_5
N1
A13 VDD_5
N1
A13 VDD_5
N1
A13 VDD_5
N1
DDR_EXT C1204 0.1uF G7 R7 D13 D13 D13 D13
M7
VDD_6
N9 M7
VDD_6
N9 M7
VDD_6
N9 M7
VDD_6
N9 VDD_3 A11 A-MA11 A-MA11 B_DDR3_A[11] B_DDR3_A[11] B_DDR3_A[11] B_DDR3_A[11]
NC_5 VDD_7
R1
NC_5 VDD_7
R1
NC_5 VDD_7
R1
NC_5 VDD_7
R1
DDR_EXT C1205 0.1uF K2 N7 D15 D15 D15 D15
M2
VDD_8
R9 M2
VDD_8
R9 M2
VDD_8
R9 M2
VDD_8
R9 VDD_4 A12/BC A-MA12 A-MA12 B_DDR3_A[12] B_DDR3_A[12] B_DDR3_A[12] B_DDR3_A[12]
N8
BA0 VDD_9
N8
BA0 VDD_9
N8
BA0 VDD_9
N8
BA0 VDD_9
DDR_EXT C1206 0.1uF K8 T3 C12 C12 C12 C12
M3
BA1
M3
BA1
M3
BA1
M3
BA1
VDD_5 NC_7 A-MA13 A-MA13 B_DDR3_A[13] B_DDR3_A[13] B_DDR3_A[13] B_DDR3_A[13]
BA2
A1
BA2
A1
BA2
A1
BA2
A1
DDR_EXT C1207 0.1uF N1 E13 E13 E13 E13
J7
VDDQ_1
A8 J7
VDDQ_1
A8 J7
VDDQ_1
A8 J7
VDDQ_1
A8 VDD_6 A-MA14 B_DDR3_A[14] B_DDR3_A[14] B_DDR3_A[14] B_DDR3_A[14]
K7
CK VDDQ_2
C1 K7
CK VDDQ_2
C1 K7
CK VDDQ_2
C1 K7
CK VDDQ_2
C1
DDR_EXT C1208 0.1uF N9 M7
K9
CK VDDQ_3
C9 K9
CK VDDQ_3
C9 K9
CK VDDQ_3
C9 K9
CK VDDQ_3
C9 VDD_7 NC_5
CKE VDDQ_4
D2
CKE VDDQ_4
D2
CKE VDDQ_4
D2
CKE VDDQ_4
D2
DDR_EXT C1209 0.1uF R1 A9 A9 A9 A9
L2
VDDQ_5
E9 L2
VDDQ_5
E9 L2
VDDQ_5
E9 L2
VDDQ_5
E9 VDD_8 A-MBA0 B_DDR3_BA[0] B_DDR3_BA[0] B_DDR3_BA[0] B_DDR3_BA[0]
K1
CS VDDQ_6
F1 K1
CS VDDQ_6
F1 K1
CS VDDQ_6
F1 K1
CS VDDQ_6
F1
DDR_EXT C1210 0.1uF R9 M2 D16 D16 D16 D16
ODT VDDQ_7 ODT VDDQ_7 ODT VDDQ_7 ODT VDDQ_7
VDD_9 BA0 A-MBA0 A-MCK A-MBA1 B_DDR3_BA[1] B_DDR3_BA[1] B_DDR3_BA[1] B_DDR3_BA[1]
1%

J3 H2 J3 H2 J3 H2 J3 H2
DDR_EXT DDR_EXT
R1207

K3
RAS VDDQ_8
H9 K3
RAS VDDQ_8
H9 K3
RAS VDDQ_8
H9 K3
RAS VDDQ_8
H9
DDR_EXT C1211 0.1uF N8 A10 A10 A10 A10
L3
CAS VDDQ_9
L3
CAS VDDQ_9
L3
CAS VDDQ_9
L3
CAS VDDQ_9
BA1 A-MBA1 A-MBA2 B_DDR3_BA[2] B_DDR3_BA[2] B_DDR3_BA[2] B_DDR3_BA[2]
WE WE WE WE
C1212 0.1uF M3
56

T2
NC_1
J1
J9 T2
NC_1
J1
J9 T2
NC_1
J1
J9 T2
NC_1
J1
J9
DDR_EXT BA2 A-MBA2 DDR_EXT
RESET NC_2
L1
RESET NC_2
L1
RESET NC_2
L1
RESET NC_2
L1 A1 C1215 C13 C13 C13 C13
NC_3
L9
NC_3
L9
NC_3
L9
NC_3
L9 VDDQ_1 A-MCK B_DDR3_MCLK B_DDR3_MCLK B_DDR3_MCLK B_DDR3_MCLK
A8 J7 B13 B13 B13 B13
1%

NC_4 NC_4 NC_4 NC_4

R1208

F3 T7 F3 T7 F3 T7 F3 T7
G3
DQSL NC_6
G3
DQSL NC_6
G3
DQSL NC_6
G3
DQSL NC_6
VDDQ_2 CK 0.01uF A-MCKB B_DDR3_MCLKZ B_DDR3_MCLKZ B_DDR3_MCLKZ B_DDR3_MCLKZ
DQSL DQSL DQSL DQSL C1 K7 50V E17 E17 E17 E17
A-MCKE
56

C7 A9 C7 A9 C7 A9 C7 A9 VDDQ_3 CK B_DDR3_MCLKE B_DDR3_MCLKE B_DDR3_MCLKE B_DDR3_MCLKE

B7
DQSU VSS_1
B3 B7
DQSU VSS_1
B3 B7
DQSU VSS_1
B3 B7
DQSU VSS_1
B3 C9 K9
DQSU VSS_2
E1
DQSU VSS_2
E1
DQSU VSS_2
E1
DQSU VSS_2
E1 VDDQ_4 CKE A-MCKE
E7
VSS_3
G8 E7
VSS_3
G8 E7
VSS_3
G8 E7
VSS_3
G8 D2 B8 B8 B8 B8
D3
DML VSS_4
J2 D3
DML VSS_4
J2 D3
DML VSS_4
J2 D3
DML VSS_4
J2 VDDQ_5 A-MCKB A-MODT B_DDR3_ODT B_DDR3_ODT B_DDR3_ODT B_DDR3_ODT
DMU VSS_5
J8
DMU VSS_5
J8
DMU VSS_5
J8
DMU VSS_5
J8 E9 L2 C8 C8 C8 C8
E3
VSS_6
M1 E3
VSS_6
M1 E3
VSS_6
M1 E3
VSS_6
M1 VDDQ_6 CS A/B_DDR3_CS A-MRASB B_DDR3_RASZ B_DDR3_RASZ B_DDR3_RASZ B_DDR3_RASZ
F7
DQL0 VSS_7
M9 F7
DQL0 VSS_7
M9 F7
DQL0 VSS_7
M9 F7
DQL0 VSS_7
M9 F1 K1 B9 B9 B9 B9
F2
DQL1 VSS_8
P1 F2
DQL1 VSS_8
P1 F2
DQL1 VSS_8
P1 F2
DQL1 VSS_8
P1 VDDQ_7 ODT A-MODT A-MCASB B_DDR3_CASZ B_DDR3_CASZ B_DDR3_CASZ B_DDR3_CASZ
F8
DQL2 VSS_9
P9 F8
DQL2 VSS_9
P9 F8
DQL2 VSS_9
P9 F8
DQL2 VSS_9
P9 H2 J3 D11 D11 D11 D11
A-MRASB +1.5V_DDR A-MWEB
A-MDQSU
A-MDQSL

H3
DQL3 VSS_10
T1 H3
DQL3 VSS_10
T1 H3
DQL3 VSS_10
T1 H3
DQL3 VSS_10
T1 VDDQ_8 RAS B_DDR3_WEZ B_DDR3_WEZ B_DDR3_WEZ B_DDR3_WEZ
H8
DQL4 VSS_11
T9 H8
DQL4 VSS_11
T9 H8
DQL4 VSS_11
T9 H8
DQL4 VSS_11
T9 H9 K3
G2
DQL5 VSS_12
G2
DQL5 VSS_12
G2
DQL5 VSS_12
G2
DQL5 VSS_12
VDDQ_9 CAS A-MCASB DDR_EXT
H7
DQL6
H7
DQL6
H7
DQL6
H7
DQL6 L3 R1206 F10 F10 F10 F10
WE A-MWEB A-MRESETB B_RESET B_RESET B_RESET B_RESET
A-MDQSUB
A-MDQSLB

DQL7 DQL7 DQL7 DQL7

B1 B1 B1 B1
D7
VSSQ_1
B9 D7
VSSQ_1
B9 D7
VSSQ_1
B9 D7
VSSQ_1
B9 J1
C3
DQU0 VSSQ_2
D1 C3
DQU0 VSSQ_2
D1 C3
DQU0 VSSQ_2
D1 C3
DQU0 VSSQ_2
D1 NC_1 10K
C8
DQU1 VSSQ_3
D8 C8
DQU1 VSSQ_3
D8 C8
DQU1 VSSQ_3
D8 C8
DQU1 VSSQ_3
D8 J9 T2 D12 D12 D12 D12
C2
DQU2 VSSQ_4
E2 C2
DQU2 VSSQ_4
E2 C2
DQU2 VSSQ_4
E2 C2
DQU2 VSSQ_4
E2 NC_2 RESET A-MRESETB A/B_DDR3_CS B_DDR3_CS0 B_DDR3_CS0 B_DDR3_CS0 B_DDR3_CS0
A7
DQU3 VSSQ_5
E8 A7
DQU3 VSSQ_5
E8 A7
DQU3 VSSQ_5
E8 A7
DQU3 VSSQ_5
E8 L1
A2
DQU4 VSSQ_6
F9 A2
DQU4 VSSQ_6
F9 A2
DQU4 VSSQ_6
F9 A2
DQU4 VSSQ_6
F9 NC_3
B8
DQU5 VSSQ_7
G1 B8
DQU5 VSSQ_7
G1 B8
DQU5 VSSQ_7
G1 B8
DQU5 VSSQ_7
G1 L9 A19 A19 A19 A19
A3
DQU6 VSSQ_8
G9 A3
DQU6 VSSQ_8
G9 A3
DQU6 VSSQ_8
G9 A3
DQU6 VSSQ_8
G9 NC_4 B_DDR3_DQSL B_DDR3_DQSL B_DDR3_DQSL B_DDR3_DQSL
DQU7 VSSQ_9 DQU7 VSSQ_9 DQU7 VSSQ_9 DQU7 VSSQ_9 T7 F3 B18 B18 B18 B18
A-MA14 NC_6 DQSL A-MDQSL B_DDR3_DQSU B_DDR3_DQSU B_DDR3_DQSU B_DDR3_DQSU
G3
DQSL A-MDQSLB
C16 C16 C16 C16
A-MDML B_DDR3_DQML B_DDR3_DQML B_DDR3_DQML B_DDR3_DQML
A9 C7 D21 D21 D21 D21
VSS_1 DQSU A-MDQSU A-MDMU B_DDR3_DQMU B_DDR3_DQMU B_DDR3_DQMU B_DDR3_DQMU
B3 B7
VSS_2 DQSU A-MDQSUB
E1 C18 C18 C18 C18
VSS_3 B_DDR3_DQSBL B_DDR3_DQSBL B_DDR3_DQSBL B_DDR3_DQSBL
G8 E7 C17 C17 C17 C17
VSS_4 DML A-MDML B_DDR3_DQSBU B_DDR3_DQSBU B_DDR3_DQSBU B_DDR3_DQSBU
J2 D3
VSS_5 DMU A-MDMU
J8 A20 A20 A20 A20
VSS_6 A-MDQL0 B_DDR3_DQL[0] B_DDR3_DQL[0] B_DDR3_DQL[0] B_DDR3_DQL[0]
M1 E3 A16 A16 A16 A16
VSS_7 DQL0 A-MDQL0 A-MDQL1 B_DDR3_DQL[1] B_DDR3_DQL[1] B_DDR3_DQL[1] B_DDR3_DQL[1]
M9 F7 C19 C19 C19 C19
VSS_8 DQL1 A-MDQL1 A-MDQL2 B_DDR3_DQL[2] B_DDR3_DQL[2] B_DDR3_DQL[2] B_DDR3_DQL[2]
P1 F2 C15 C15 C15 C15
VSS_9 DQL2 A-MDQL2 A-MDQL3 B_DDR3_DQL[3] B_DDR3_DQL[3] B_DDR3_DQL[3] B_DDR3_DQL[3]
P9 F8 C20 C20 C20 C20
VSS_10 DQL3 A-MDQL3 A-MDQL4 B_DDR3_DQL[4] B_DDR3_DQL[4] B_DDR3_DQL[4] B_DDR3_DQL[4]
T1 H3 C14 C14 C14 C14
VSS_11 DQL4 A-MDQL4 A-MDQL5 B_DDR3_DQL[5] B_DDR3_DQL[5] B_DDR3_DQL[5] B_DDR3_DQL[5]
T9 H8 B21 B21 B21 B21
VSS_12 DQL5 A-MDQL5 A-MDQL6 B_DDR3_DQL[6] B_DDR3_DQL[6] B_DDR3_DQL[6] B_DDR3_DQL[6]
G2 B15 B15 B15 B15
DQL6 A-MDQL6 A-MDQL7 B_DDR3_DQL[7] B_DDR3_DQL[7] B_DDR3_DQL[7] B_DDR3_DQL[7]
H7 F18 F18 F18 F18
DQL7 A-MDQL7 A-MDQU0 B_DDR3_DQU[0] B_DDR3_DQU[0] B_DDR3_DQU[0] B_DDR3_DQU[0]
B1 D19 D19 D19 D19
VSSQ_1 A-MDQU1 B_DDR3_DQU[1] B_DDR3_DQU[1] B_DDR3_DQU[1] B_DDR3_DQU[1]
B9 D7 D17 D17 D17 D17
VSSQ_2 DQU0 A-MDQU0 A-MDQU2 B_DDR3_DQU[2] B_DDR3_DQU[2] B_DDR3_DQU[2] B_DDR3_DQU[2]
D1 C3 E21 E21 E21 E21
VSSQ_3 DQU1 A-MDQU1 A-MDQU3 B_DDR3_DQU[3] B_DDR3_DQU[3] B_DDR3_DQU[3] B_DDR3_DQU[3]
D8 C8 E19 E19 E19 E19
VSSQ_4 DQU2 A-MDQU2 A-MDQU4 B_DDR3_DQU[4] B_DDR3_DQU[4] B_DDR3_DQU[4] B_DDR3_DQU[4]
E2 C2 D20 D20 D20 D20
VSSQ_5 DQU3 A-MDQU3 A-MDQU5 B_DDR3_DQU[5] B_DDR3_DQU[5] B_DDR3_DQU[5] B_DDR3_DQU[5]
E8 A7 D18 D18 D18 D18
VSSQ_6 DQU4 A-MDQU4 A-MDQU6 B_DDR3_DQU[6] B_DDR3_DQU[6] B_DDR3_DQU[6] B_DDR3_DQU[6]
F9 A2 F20 F20 F20 F20
VSSQ_7 DQU5 A-MDQU5 A-MDQU7 B_DDR3_DQU[7] B_DDR3_DQU[7] B_DDR3_DQU[7] B_DDR3_DQU[7]
G1 B8
VSSQ_8 DQU6 A-MDQU6 R1209
G9 A3 E9 E9 E9 E9
VSSQ_9 DQU7 A-MDQU7 ZQ ZQ ZQ ZQ
240
1%

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS M1A_URSA_UD 2014.04.24
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 1_DDR 12

+3.5V_ST +3.5V_ST

SPI_FLASH_MACRONIX
OPT IC1300
R1301
+3.5V_ST 4.7K MX25L8006EM2I-12G
C1300
CS# VCC 0.1uF
/SPI_CS 1 8
OPT
R1300
10K SO/SIO1 HOLD#
SPI_SDO 2 7
R1303 0
WP# SCLK
/FLASH_WP 3 6 SPI_SCK
R1302
GND SI/SIO0 33
4 5 SPI_SDI

SPI_FLASH_WINBOND SPI_FLAHS_WINBOND_NEW SPI_FHASH_MACRONIX_NEW

IC1300-*1 IC1300-*2 IC1300-*3
W25Q80BVSSIG W25Q80DVSSIG MX25L8035EM2I-10G

CS VCC CS VCC CS# VCC

1 8 1 8 1 8

DO[IO1] HOLD[IO3] DO[IO1] HOLD[IO3] SO/SIO1 NC/SIO3

2 7 2 7 2 7

%WP[IO2] CLK WP[IO2] CLK WP#/SIO2 SCLK

3 6 3 6 3 6

GND DI[IO0] GND DI[IO0] GND SI/SIO0

4 5 4 5 4 5

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

CI SLOT
+5V_CI_ON
CI_DATA[0-7]
CI TS INPUT
CI_DATA[0-7]

+5V_NORMAL AR1903 33
C1903 FE_TS_DATA[7]
CI_MDI[7]
10uF FE_TS_DATA[6]
10V CI_MDI[6]

FE_TS_DATA[0-7]
R1908 FE_TS_DATA[5]
CI_MDI[5]
10K FE_TS_DATA[4]
CI_SLOT CI_MDI[4]
/CI_CD1 P1900
10125901-115LF
AR1904 33 FE_TS_DATA[3]
R1914 35 1 CI_MDI[3]
100 CI_DATA[3] FE_TS_DATA[2]
36 2 CI_MDI[2] FE_TS_DATA[1]
AR1900 CI_DATA[4]
CI_DATA[0-7]

33 37 3 CI_MDI[1] FE_TS_DATA[0]
CI_DATA[5] R1919
CI_TS_DATA[4] 38 4 10K CI_MDI[0]
CI_DATA[6]
CI_TS_DATA[5] 39 5
CI_DATA[7] FE_TS_DATA[0-7]
CI_TS_DATA[6] 40 6
R1917 R1921 33
CI_TS_DATA[7] 41 7 47 CI_MISTRT FE_TS_SYNC
CI_ADDR[10] /PCM_CE R1922 33
42 8 CI_MIVAL_ERR FE_TS_VAL_ERR
R1910 10K R1923 100
43 9 CI_OE CI_MCLKI FE_TS_CLK
CI_ADDR[11]
CI_IORD 44 10 +5V_NORMAL
CI_ADDR[9]
CI_IOWR 45 11
CI_ADDR[8]
46 12 R1920
CI_ADDR[13] 10K
CI_MDI[0] 47 13
CI_ADDR[14]
CI_MDI[1] 48 14
CI_MDI[2] 49 15 CI_WE
50 16 R1918 100
CI_MDI[3] /PCM_IRQA
51 17

GND
C1901
0.1uF
52
53
18
19
C1904
0.1uF
C1905
0.1uF
CI HOST I/F
CI_MDI[4] 16V
GND
CI_MDI[5] 54 20
+5V_NORMAL CI_ADDR[12]
CI_MDI[6] 55 21 CLOSE TO MSTAR
CI_ADDR[7]
R1900 CI_MDI[7] 56 22 GND +3.3V_NORMAL
10K R1911 10K CI_ADDR[6]
57 23
R1903 CI_ADDR[5]
47 58 24
PCM_RST CI_ADDR[4]
R1904 47 CI_DET
/PCM_WAIT 59 25 IC1902
CLOSE TO MSTAR CI_ADDR[3]
REG 60 26 C1906
R1905 100 CI_ADDR[2]
CI_TS_CLK 61 27 0.1uF
R1906 33 CI_ADDR[1] 1OE CI_BUFFER_NXP(MULTI) VCC 16V
CI_TS_VAL 62 28 1 20
R1907 33 CI_ADDR[0]
CI_TS_SYNC 63 29
CI_DATA[0]
64 30 1A1 2OE
AR1901 33 CI_DATA[1] 2 19
65 31 CI_ADDR[0-14] PCM_A[0]
CI_TS_DATA[0] CI_DATA[2] AR1902 AR1910
66 32 100
CI_TS_DATA[1] 2Y4 1Y1 100
67 33 3 18
CI_TS_DATA[2] CI_ADDR[7] CI_ADDR[0]
68 34
CI_TS_DATA[3] CI_ADDR[6] CI_ADDR[1]
G2 69 G1 CI_ADDR[5] 1A2 2A4 CI_ADDR[2]
PCM_A[1] 4 17 PCM_A[7]
R1912 CI_ADDR[4] CI_ADDR[3]
100
/CI_CD2 2Y3 1Y2
TC74LCX244FT

+5V_NORMAL GND 5 16

GND 1A3 2A3

PCM_A[2] 6 15 PCM_A[6]
C1900
2pF
R1909
50V 2Y2 1Y3
10K GND 7 14
CLOSE TO MSTAR
1A4 2A2
PCM_A[3] 8 13 PCM_A[5]

2Y1 1Y4
CI_MISTRT 9 12
CI_MIVAL_ERR
GND 2A1
10 11 PCM_A[4]
CI_MCLKI

CI DETECT +3.3V_NORMAL
OR_GATE_CI_NXP(MULTI)
IC1900
74LVC1G32GW +3.3V_NORMAL
B 1 5 VCC
/CI_CD2
A 2
/CI_CD1 AR1905 33
GND 3 4 Y R1913 CI_DATA[0] PCM_D[0]
10K CI_DATA[1] PCM_D[1]
CI_DATA[0-7]

CI_DATA[2] PCM_D[2]
R1924 CI_DATA[3] PCM_D[3]
OR_GATE_CI_TOSHIBA(MULTI)
IC1900-*1
0
TOSHIBA ELECTRONICS KOREA CORPORATION CI_DET
IC1902-*1
PCM_D[0-7]

IN_B VCC
1 5
/PCM_CD AR1906 33
R1915 CI_DATA[4] PCM_D[4] 74LCX244FT
IN_A
2 47 CI_DATA[5] PCM_D[5]
GND OUT_Y
3 4 CI_DATA[6] PCM_D[6]
1OE CI_BUFFER_TOSHIBA(MULTI) VCC
CI_DATA[7] PCM_D[7] 1 20

1A1 2OE
2 19
PCM_D[0-7]
CI_DATA[0-7] 2Y4 1Y1
CI POWER ENABLE CONTROL 3 18

1A2 2A4
4 17
AR1908 33
CI_ADDR[8] PCM_A[8] 2Y3 1Y2
IC1901 CI_ADDR[9] PCM_A[9] 5 16
+5V_NORMAL
AP2151WG-7 +5V_CI_ON CI_ADDR[10] PCM_A[10]
L1900 CI_ADDR[11] PCM_A[11] 1A3 2A3
6 15
BLM18PG121SN1D
IN OUT
5 1
2Y2 1Y3
7 14
GND AR1909 33
2 CI_ADDR[12] PCM_A[12]
R1916 1A4 2A2
C1902 8 13
100K CI_ADDR[13] PCM_A[13]
R1902 1uF
100 EN FLG 10V CI_ADDR[14] PCM_A[14]
PCM_5V_CTL 4 3
/PCM_REG 2Y1 1Y4
REG 9 12
R1901
10K
GND 2A1
10 11
AR1907 33
CI_OE /PCM_OE
CI_WE /PCM_WE
CI_IORD /PCM_IORD
CI_IOWR /PCM_IOWR

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

JK2100
RJ45VT-01SN002

1
1
EPHY_TP
ETHERNET

2
2

3
3
EPHY_TN

4
4 EPHY_RP

5
5

6
6
EPHY_RN

7
7

8
8

ETHERNET ETHERNET
C2105 C2104
0.01uF 0.01uF
50V 50V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS M1A_URSA9_UD 2014.04.24
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
LAN 21
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

Input trace widths should be sized to conduct at least 3A

Ouput trace widths should be sized to conduct at least 2A

3A
+12V_LNB

2A LNB_DIODE_SUZHOU(MILTI)
LNB_DIODE_SUZHOU(MULTI)
D2705-*1
40V
D2703-*1
SS2040LL-LG LNB
Max 1.3A
L2702
LPH6050T-150M-R
40V D2705 15uH
LNB_DIODE_ONSEMI(MULTI) LNB_DIODE_KEC(MULTI)
D2703 SMAB34 40V 3.5A

30V
LNB
C2708
LNB LNB LNB LNB 10uF
C2703 C2704 C2705 C2706 25V
0.01uF 10uF 10uF 10uF
50V 25V 25V 25V

close to Boost pin(#1)

A_GND A_GND
A_GND
LNB_DIODE_SUZHOU(MILTI)
D2702-*1 close to VIN pin(#15)
SS2040LL-LG
[EP]GND

LNB
LNB C2709
BOOST

GNDLX
NC_3

NC_2

40V C2707 0.1uF

50V
LX

0.1uF
20

LNB_DIODE_ONSEMI(MULTI)
D2702 VCP 1 15 VIN
close to TUNER MBR230LSFT1G
LNB
THERMAL
GND
LNB_OUT 2 21 14 LNB
30V NC_1 VREG R2703
3 13 36K
LNB
SMAB34

LNB LNB LNB TDI ISET 1/16W 1%

R2702 C2712 LNB_DIODE_KEC(MULTI) 4 IC2701 12
LNB LNB LNB LNB C2713
C2714 C2701 C2702 D2701
2.2K 0.22uF 0.1uF D2704 TDO A8303SESTR-T(4M)TCAP
1W 25V 50V 40V 5 11
18pF 18pF 33pF
10

LNB_DIODE_SUZHOU(MULTI) LNB
6

C2710
D2704-*1 0.1uF
IRQ

SCL

SDA

ADD

TONECTRL

40V LNB
C2711
Close to Tuner 0.22uF
Surge protectioin

A_GND A_GND

R2706
0

LNB LNB
R2704 R2705
33 33

Caution!! need isolated GND

R2701
0
DEMOD_SCL

DEMOD_SDA

LNB_TX

A_GND

Max 1.3A

+12V +12V_LNB

LNB
L2701
BLM18PG121SN1D

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS M1A_URSA9_UD 2014.04.24
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
LNB 27
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

JK2802
PPJ245N2-01
R2811 EU
6E [RD2]E-LUG 10K C2808
COMP2_R_IN
VA2804 R2803 330pF R2816 IC2801 0.1uF
[RD2]O-SPRING 5.6V 470K C2802 12K 50V
5E AZ4580MTR-E1
OPT
R2810 EU
4E [RD2]CONTACT 10K R2831
COMP2_L_IN +3.3V_NORMAL 2.2K OUT1 8 VCC
330pF R2815 DTV/MNT_L_OUT 1
[WH]O-SPRING
VA2803 R2802
C2803 12K EU EU EU
5D 5.6V 470K EU
C2804 R2834 R2844
OPT OPT 33K IN1- 7 OUT2 2.2K
R2817 R2818 10uF R2832 2
[RD1]CONTACT 10K 1K 16V DTV/MNT_R_OUT
4C 470K EU
COMP2_DET R2841 EU
EU IN1+ IN2- 33K C2812
[RD1]O-SPRING VA2816 3 6 OPT 10uF
5C EU R2836
5.6V C2807 10K EU R2843 16V
33pF 470K
OPT R2839
7C [RD1]E-LUG-S VEE 5 IN2+ 10K
4 EU
COMP2_Pr+ C2810
[BL]O-SPRING ZD2806 VA2802 R2801 33pF
5B EU
COMP_ZENER_KEC(MULTI) 5.5V 75 R2835
5.6K EU
[GN/YL]CONTACT ZD2807 OPT SCART1_Lout R2840
4A 5.6K
COMP_ZENER_KEC(MULTI)
SCART1_Rout
330pF 220K
[GN/YL]O-SPRING C2806 R2833
5A EU EU
EU EU
R2842 C2811
220K 330pF
6A [GN/YL]E-LUG

COMP2_Pb+
VA2801 R2800
ZD2804 5.5V 75
COMP_ZENER_KEC(MULTI)
CLOSE TO MSTAR
OPT
ZD2806-*1
COMP_ZENER_ROHM(MULTI) ZD2805 +3.3V_NORMAL CLOSE TO MSTAR
COMP_ZENER_KEC(MULTI)
ZD2807-*1
COMP_ZENER_ROHM(MULTI)

R2812 R2814
ZD2804-*1 1K
COMP_ZENER_ROHM(MULTI) 10K
AV_CVBS_DET
VA2800 OPT
ZD2805-*1 5.6V C2800
COMP_ZENER_ROHM(MULTI) OPT 0.1uF
16V
ZD2802-*1
COMP_ZENER_ROHM(MULTI) COMP2_Y+/AV_CVBS_IN
R2804 R2859
ZD2803-*1 ZD2802 75 75
COMP_ZENER_ROHM(MULTI) COMP_ZENER_KEC(MULTI) 1608 3216
OPT
ZD2803
COMP_ZENER_KEC(MULTI)

SCART_MUTE_NPN_NXP(MULTI) SCART_MUTE_NPN_NXP(MULTI)

Q2802-*1 Q2803-*1
MMBT3904(NXP) MMBT3904(NXP)

FULL SCART +3.3V_NORMAL [SCART AUDIO MUTE] +3.5V_ST

R2819 DTV/MNT_L_OUT SCART_MUTE

10K R2837 SCART_MUTE
2K R2845
R2820 1K SCART_MUTE_NPN_KEC(MULTI) 10K
SC1/COMP1_DET Q2802
VA2815 EU 2N3904S
5.6V R2850 1K
OPT AV2_CVBS_DET
AV2
SCART1_MUTE
SCART_MUTE
DTV/MNT_R_OUT R2838 SCART_MUTE
2K C2809
SCART_MUTE_NPN_KEC(MULTI) 0.1uF
Q2803
SC1/AV2_CVBS_IN 2N3904S
ZD2800-*1 ZD2800 SCART/AV2
AV2
AV2_CVBS_ZENER_ROHM(MULTI) R2857 R2860 C2801
AV2_CVBS_ZENER_KEC(MULTI) 75 75 47pF
AV_DET ZD2801-*1 ZD2801 1608 3216 50V
AV2_CVBS_ZENER_KEC(MULTI) 1% OPT
22 VA2807 AV2_CVBS_ZENER_ROHM(MULTI)
COM_GND 5.5V
ESD_SCART
21
SYNC_IN EU
R2861 AV2
20
SYNC_OUT 10 JK2803
OPT OPT DTV/MNT_VOUT
19 PPJ231-02
SYNC_GND2 VA2808 EU C2815 C2816
VA2814 R2821
18 20V 5.6V 75 68pF 68pF 4
SYNC_GND1 ESD_SCART 50V 50V EU AV2_R_IN_A
R2827
17 22
RGB_IO 5
SC1_FB R2847 AV2_L_IN_A
16
R_OUT 0
SC1_R+/COMP1_Pr+ 7 AV2
15 AV2_CVBS_DET
RGB_GND ESD_SCART
VA2810 R2807
14 75 8 VA2820
R_GND 20V EU 5.6V
R2822 OPT
13 75
D2B_OUT 6 R2848
0
12 EU
G_OUT
11 SC1_G+/COMP1_Y+
D2B_IN VA2811 R2808
10 20V 75
G_GND ESD_SCART EU
9 R2824
ID 15K
SC1_ID SC1/AV2_CVBS_IN
8
B_OUT EU
7 SC1_B+/COMP1_Pb+ R2828
AUDIO_L_IN VA2812 VA2817
20V 3.9K
20V R2805
6 75 ESD_SCART
B_GND ESD_SCART
5
AUDIO_GND
SCART/AV2
4
AUDIO_L_OUT R2826
10K
3 SC1/COMP1_L_IN
AUDIO_R_IN
SCART/AV2

SCART/AV2

2 R2806 R2829
AUDIO_R_OUT VA2813 470K C2818 12K
5.6V 1000pF
1 50V
ESD_SCART/AV2 OPT AV2_L_IN
R2846
0
AV2_L_IN_A AV2
EU SCART/AV2
JK2801 R2825
10K
PSC008-01 SC1/COMP1_R_IN
VA2809
SCART/AV2

SCART/AV2

5.6V C2817
ESD_SCART/AV2 R2809 1000pF R2830
470K 50V 12K
OPT AV2_R_IN
R2849
0
AV2_R_IN_A AV2

AV2
DTV/MNT_L_OUT
EU
VA2806 C2813
5.6V 1000pF
OPT 50V

DTV/MNT_R_OUT
EU
VA2805 C2814
5.6V 1000pF
OPT 50V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

Close to the Main IC

HEAD_PHONE
L3000
5.6uH HEAD_PHONE
HP_LOUT
HEAD_PHONE C3000 OPT C
C3004 E
10uF C3002 HEAD_PHONE
4.7uF R3002 Q3002 B
16V 1000pF 1K Q3004
10V MMBT3904(NXP) MMBT3904(NXP) PHONE_JACK
50V B OPT
OPT JK3000
+3.5V_ST E +3.3V_NORMAL
C PEJ038-3B6
GND 5
E
OPT OPT HEAD_PHONE
Q3001 R3005
10K L 4
OPT MMBT3906(NXP)
C R3001 B
R3000 3.3K
1K B C DETECT 3
SIDE_HP_MUTE HP_DET
Q3000 R3004
MMBT3904(NXP) 1K
E HEAD_PHONE R 1
OPT

HEAD_PHONE
L3001 HEAD_PHONE
5.6uH
HP_ROUT
HEAD_PHONE C3001 OPT HEAD_PHONE
C E
C3005 10uF C3003 R3003 Q3003
4.7uF 16V 1000pF B Q3005
1K MMBT3904(NXP) MMBT3904(NXP)
10V 50V OPT B OPT
E C

Close to the Main IC

RS232C_PHONE
R3006
100

+3.5V_ST
RS232C_PHONE
R3007
100

C3006 OPT
0.33uF ZD3001 OPT
ADUC 20S 02 010L ZD3002
20V ADUC 20S 02 010L
RS232C_PHONE RS232C_PHONE 20V
RS232C_PHONE C3007
IC3001 0.1uF

MAX3232CDR

RS232C_PHONE C1+ VCC

1 16
C3008
0.1uF V+ GND
RS232C_PHONE 2 15
C3009
0.1uF C1- DOUT1
3 14

RS232C_PHONE C2+ RIN1

4 13
C3010 RS232C_PHONE
0.1uF C2- ROUT1 0 R3008
5 12
PM_RXD
RS232C_PHONE
RS232C_PHONE V- DIN1 0 R3009
6 11
PM_TXD
C3011
0.1uF DOUT2 DIN2
7 10

RIN2 ROUT2
8 9

EAN41348201

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

Copyright ⓒ 2015 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Downloaded
Only for training andfrom www.Manualslib.com manuals search engine
service purposes
5V_HDMI_2
VA3216

R3215
1K R3216 C
4.7K Q3201-*1
C B
Q3201 R3213 MMBT3904(NXP)
2N3904S B 1K NPN_NXP(MULTI)
C3240
HDMI2_HPD_MN864788
VA3203

SHIELD P_XOUT
E
OPT

R3204 AR3207 X3200 20pF

R3217

MN864778_RESET
20 100K E 27MHz
4.7K 33 P_VDD33
NPN_KEC(MULTI) X-TAL_1 GND_2
R3241

1/16W
2.2M

OPT 1 4

HDMI_SW_SDA

HDMI_SW_SCL
19 DDC_SDA_HDMI2_MN864788 GND_1 X-TAL_2
HPD TX0SDA 2 3
DDC_SCL_HDMI2_MN864788 P_VDD33 +5V_NORMAL
18

P_XOUT
+5V_POWER C3241

P_XIN
TX0SCL
17 C3201 C3209 P_XIN
DDC/CEC_GND VA3204 VA3207 0.1uF 0.1uF
R3265

R3266

R3267

R3268

TX1SDA 20pF
OPT OPT OPT
1.8K

1.8K

16 OPT
SDA
TX1SCL
15 HDMI_ARC
SCL R3220 0
14

10K
HDMI2_ARC R3269 OPT 0
NC TX0SDA

0
CEC_REMOTE
13 R3270 OPT 0
10K
R3243

10K
R3244

CEC D3202 TX0SCL

12 IP4294CZ10-TBR R3271 OPT 0

R3222

R3223

R3231
CLK- TX1SDA
11 R3272 OPT 0
TX1SCL
CLK_SHIELD 1 10 CK-_HDMI2_MN864788
10
CLK+ 2 9
MOSI/LPSA0
SCLK/LPSA1

9 P_AVDDH33 P_AVDDH11
CH0ALRCLK

SYSCLK/XI

DATA0- 3 8 CK+_HDMI2_MN864788
CH0ABCLK

CH0AMCLK

TX0ARCIN
TX1ARCIN
8 OPT
VDD33_4
VDD11_9
CH0ASD0
CH0ASD1
CH0ASD2
CH0ASD3

VDD33IO

VDD11_8

VDD11_7

VDD33_3

VDD11_6
DATA0_SHIELD 4 7 D0-_HDMI2_MN864788 C3246 10uF10V
TX0SCL
TX1HPD
TX1SDA
TX1SCL
VSS_12

VSS_11

VSS_10

NRESET
VSS_9
NC/XO

HSDA0

HSCL0
NTEST
7
DATA0+ 5 6
[EP]

MISO

C3247 10uF10V
NCS

CEC
6 P_VDD11
D0+_HDMI2_MN864788
NC

DATA1-
P_AVDD33
5
DATA1_SHIELD
D3203 P_AVDD11
4
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
DATA1+ IP4294CZ10-TBR
D1-_HDMI2_MN864788
3 1 10 TX0SDA RX0SCL
DATA2- 1 108 DDC_SCL_HDMI1_MN864788
2 2 9 TX0HPD RX0SDA
DATA2_SHIELD 2 107 DDC_SDA_HDMI1_MN864788
1 3 8
D1+_HDMI2_MN864788 THERMAL
DATA2+ CH1ASD0 3 106 RX1SCL
OPT D2-_HDMI2_MN864788
C3211 10uF10V 145 DDC_SCL_HDMI2_MN864788
4 7 CH1ALRCLK RX1SDA
4 105 DDC_SDA_HDMI2_MN864788
YKF45-7058V 5 6 C3213 10uF10V CH1ABCLK VSS_8
5 104
JK3203 D2+_HDMI2_MN864788
VSS_1 6 103 P0RX2P
HDMI2

HDMI1
D2+_HDMI1_MN864788
VDD11_1 7 102 P0RX2M
D2-_HDMI1_MN864788
P1TX2P 8 101 AVDD11RX0_3 C3249 0.1uF
HDMI_1_RX2+
C3214 0.1uF AVDD11TX_1 9 100 P0RX1P
D1+_HDMI1_MN864788
P1TX2M 10 99 P0RX1M
HDMI_1_RX2- D1-_HDMI1_MN864788
HDMI TX port 1

5V_HDMI_1 C

VA3205 R3205
Q3200-*1
MMBT3904(NXP)
NPN_NXP(MULTI)
B HDMI_1_RX1+
C3218 0.1uF
P1TX1P
AVDD11TX_2
11
12
IC3200 98
97
AVDD11RX0_2
P0RX0P
C3253 0.1uF

D0+_HDMI1_MN864788
E P1TX1M P0RX0M
1K R3218 13 96
HDMI_1_RX1- D0-_HDMI1_MN864788
4.7K
C P1TX0P 14 95 AVDD11RX0_1 C3254 0.1uF
Q3200 R3233 HDMI_1_RX0+
2N3904S B 1K C3219 0.1uF AVDD33TX_1 P0RXCP
HDMI1_HPD_MN864788
VA3201

SHIELD 15 94 CK+_HDMI1_MN864788
R3202

MN864788
OPT

100K
E R3247 P1TX0M 16 93 P0RXCM
20 HDMI_1_RX0- CK-_HDMI1_MN864788
NPN_KEC(MULTI) 4.7K
OPT AR3204 P1TXCP 17 92 AVDD33RX0 C3255 0.1uF
33 HDMI_1_CLK+
19 1/16W
HPD C3220 0.1uF AVDD11TX_3 18 91 VSS_7
18 DDC_SDA_HDMI1_MN864788
+5V_POWER P1TXCM 19 90 P1RX2P
DDC_SCL_HDMI1_MN864788

HDMI2
HDMI_1_CLK- D2+_HDMI2_MN864788
17
DDC/CEC_GND VSS_2 20 89 P1RX2M
VA3209 VA3214 C3203 C3210 D2-_HDMI2_MN864788
16
SDA OPT OPT 0.1uF 0.1uF VDD11_2 21 88 AVDD11RX1_3 C3256 0.1uF
15 OPT OPT
SCL R3219 0 P0TX2P 22 87 P1RX1P
HDMI_0_RX2+ D1+_HDMI2_MN864788
14 HDMI1_ARC HDMI_ARC
NC C3222 0.1uF AVDD11TX_4 23 86 P1RX1M
13
CEC_REMOTE D3204 D1-_HDMI2_MN864788
CEC IP4294CZ10-TBR P0TX2M 24 85 AVDD11RX1_2 C3257 0.1uF
HDMI TX port 0

HDMI_0_RX2-
12
CLK- 1 10 CK-_HDMI1_MN864788 P0TX1P 25 84 P1RX0P
HDMI_0_RX1+ D0+_HDMI2_MN864788
11
CLK_SHIELD 2 9 C3224 0.1uF AVDD11TX_5 26 83 P1RX0M
D0-_HDMI2_MN864788
10
CLK+ 3 8 CK+_HDMI1_MN864788 P0TX1M 27 82 AVDD11RX1_1 C3262 0.1uF
OPT HDMI_0_RX1-
9
DATA0- 4 7 D0-_HDMI1_MN864788 P0TX0P 28 81 P1RXCP
HDMI_0_RX0+ CK+_HDMI2_MN864788
8
DATA0_SHIELD 5 6 C3226 0.1uF AVDD33TX_2 29 80 P1RXCM
CK-_HDMI2_MN864788
7 D0+_HDMI1_MN864788
DATA0+ P0TX0M 30 79 AVDD33RX1 C3266 0.1uF
HDMI_0_RX0-
6
DATA1- D3205 P0TXCP 31 78 VDD11_5 AR3209
HDMI_0_CLK+ P_VDD33
5 47K
DATA1_SHIELD IP4294CZ10-TBR C3227 0.1uF AVDD11TX_6 32 77 RX2SCL 1/16W
4 1 10 D1-_HDMI1_MN864788
DATA1+ P0TXCM 33 76 RX2SDA
2 9 HDMI_0_CLK-
3
DATA2- VSS_3 34 75 RX3SCL
2 3 8 D1+_HDMI1_MN864788
DATA2_SHIELD OPT VDD11_3 35 74 RX3SDA
1 4 7 D2-_HDMI1_MN864788
AR3210
DATA2+ NIRQA1 36 73 RX0P5V 47K
5 6 1/16W
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72

YKF45-7058V D2+_HDMI1_MN864788

JK3200
NIRQA0
VDD33_1
PVDD33
VSS_4
AVDD33RX3
P3RXCM
P3RXCP
AVDD11RX3_1
P3RX0M
P3RX0P
AVDD11RX3_2
P3RX1M
P3RX1P
AVDD11RX3_3
P3RX2M
P3RX2P
VSS_5
AVDD33RX2
P2RXCM
P2RXCP
AVDD11RX2_1
P2RX0M
P2RX0P
AVDD11RX2_2
P2RX1M
P2RX1P
AVDD11RX2_3
P2RX2M
P2RX2P
VSS_6
VDD11_4
NIRQ1
VDD33_2
RX3P5V
RX2P5V
RX1P5V

HDMI1
P_PVDD33
+1.10V_VDDC_MN864778
P_AVDDH11 5V_HDMI_2 5V_HDMI_1
+1.10V_VDDC_MN864778
R3236 R3234
L3205 P_VDD33 10 10
R3914 BLM18PG121SN1D
DDC pull-up 100 R3237 R3235
CEC_REMOTE CEC_REMOTE_S7 47K 47K
C3264
C3272 C3202 4.7uF
22uF 0.33uF 10V
+5V_NORMAL 5V_HDMI_2 5V_HDMI_1 +5V_NORMAL 10V
10uF10V

10uF10V
0.1uF

0.1uF

0.1uF
0.1uF

0.1uF

0.1uF
0.1uF
A1

A2
A1

KDS184 KDS184 MMBD6100 MMBD6100

D3218 D3208 D3218-*1 D3208-*1
C

C3239

C3242

C3243
C

C3234

C3236

C3237

C3238
C

C3233

C3244

C3245

DDC_DIODE_KEC(MULTI) DDC_DIODE_KEC(MULTI) DDC_DIODE_SUZHOU(MULTI) DDC_DIODE_SUZHOU(MULTI)

AR3201

AR3200
1/16W

1/16W
47K

47K

DDC_SDA_HDMI2_MN864788 DDC_SDA_HDMI1_MN864788 +1.10V_VDDC_MN864778 P_VDD11 +1.10V_VDDC_MN864778 P_AVDD11

DDC_SCL_HDMI2_MN864788 DDC_SCL_HDMI1_MN864788
L3200 L3203
BLM18PG121SN1D BLM18PG121SN1D
1000pF

1000pF

1000pF
1000pF

1000pF

4.7uF
0.1uF

C3263
4.7uF

+1.10V_VDDC_MN864778
C3204

C3228

C3229

C3248

C3208

C3250

C3251

C3252

C3259

10V
OPT
OPT

OPT

OPT
OPT

OPT

+12V
TYPICAL 1100mA +1.10V_VDDC_MN864778

L3216
BLM18PG121SN1D HDMI_3.3V P_VDD33 HDMI_3.3V P_AVDD33

L3201 R3214
BLM18PG121SN1D 0
+12V
C3308
0.33uF

0.33uF

0.33uF
0.1uF

0.1uF

4.7uF

10uF IC3205
16V 10K
POWER_ON/OFF_1
R3302 TPS54327DDAR [EP]GND
OPT
R3301
C3205

C3206

C3207

C3216

C3212

C3215

C3217

C3258

C3265

R3303 C3300
10K EN VIN
330K 0.1uF 1 8
R1 OPT 16V
THERMAL

R3304 R3305
3.9K 2.7K VFB VBST C3304
9

2 7
1% 1% 0.1uF L3217
16V 3.6uH
VREG5 SW
3 6
C3301 LPH6050T-3R6N-R
100pF SS GND C3307 C3306
50V
R2
4
3A 5
22uF
10V
22uF
10V
ZD3203
2.5V HDMI_3.3V HDMI_3.3V
R3306

P_AVDDH33 P_PVDD33
14K

C3302 C3303
1%

1uF 3300pF
10V 50V L3204 R3221
BLM18PG121SN1D 0
0.33uF

C3261 0.33uF

C3230 0.33uF

C3231 0.33uF

0.1uF
0.1uF

0.1uF

4.7uF

Switching freq: 700K Vout=0.765*(1+R1/R2)

C3221

C3260
C3223

C3225

C3232

3.3V Power Separation

+3.3V_U_NORMAL +5V_NORMAL HDMI_3.3V

R3208
10K

HDMI3.3_FET_AOS(MULTI)
G
S

AO3438
C3269 Q3204
C3268
100uF 22uF C3235
6.3V 10V 10uF
10V
G
S

NTR4501NT1G
Q3204-*1
HDMI3.3_FET_ONSEMI(MULTI)

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

RS-232C 4PIN

+3.5V_ST P4000
12507WS-04L

R4001
100 VCC
1
PM_TXD
R4000
100 PM_RXD
2
PM_RXD

GND
3

RM_TXD
4

GND

MSTAR DEBUG 4PIN

P4001
JP_GND1

JP_GND2

JP_GND3

JP_GND4

12507WS-04L

3 RGB_DDC_SCL

4 RGB_DDC_SDA

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

Copyright ⓒ 2015 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Downloaded
Only for training andfrom www.Manualslib.com manuals search engine
service purposes
TP for EU

HDMI_ARC HP_ROUT CI_DET EPHY_RP URSA_RESET

DDC_SDA_2 HP_LOUT /CI_CD1 EPHY_TN DEMOD_RESET
DDC_SCL_2 SIDE_HP_MUTE /CI_CD2 EPHY_TP
SPDIF_OUT HP_DET EPHY_RN
AV2_CVBS_DET

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS M1A_URSA9_UD 2014.04.24
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
TP_EU 41
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

+3.5V_ST

R4603 R4604
10K 10K
1% 1%

R4601
100 P4600 OPT
KEY1 P4601
12507WR-10L
C4602 12507WR-08L
0.1uF
16V
R4602 1
100 1
KEY2
C4603 2
0.1uF 2
+3.5V_ST 16V
3
L4600 3
BLM18PG121SN1D
4
4
R4606
+3.5V_ST C4600 C4601 1.8K
0.1uF 1000pF LED_R/BUZZ 5
16V 50V 5
VA4600
OPT
R4600 6
3.3K 6

IR 7
C4604 7
100pF ZD4601
50V 5V 8
OPT 8

9 9

EYE_SENSOR 11
C4605
18pF
50V
R4608 100
HDMI_SW_SCL
OPT

R4609 100
HDMI_SW_SDA
OPT EYE_SENSOR
C4606
R4605 100 18pF
IR_SCL
EYE_SENSOR 50V

R4607 100
IR_SDA
EYE_SENSOR

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

Copyright ⓒ 2015 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Downloaded
Only for training andfrom www.Manualslib.com manuals search engine
service purposes
NAND FLASH MEMORY
<CHIP Config>
IC102 (SPI_SDI, PM_LED, PWM_PM)
H27U1G8F2CTR-BC
LG-NonOS SB51_ExtSPI 3’b000 51boot from SPI
LG-OS HEMCU_ExtSPI 3’b001 MIPS boot from SPI
+3.3V_NORMAL +3.3V_NORMAL +3.5V_ST
NC_1 NC_29
1 48 M1A_256M
NAND_1G_HYNIX(MULTI)
NC_2 NC_28 IC101
2 EAN35669103 47 M1A_128M

NC_3 NC_27 PCM_A[0-7] LGE2134(256M) IC101-*1

LGE2133(128M)
4.7K
4.7K

2.7K

3 46
22
NC_4 NC_26
OPT

OPT

U19 D5
4 45 AR101 T20
LVA4P/TTL_B[0]/HCONV/GPIO170 SAR0/GPIO35
F8
LVA4M/TTL_B[1]/E_O/GPIO171 SAR1/GPIO36
T21 E7
NC_5 I/O7 PCM_A[7] U19 D5 LVA3P/TTL_B[2]/FB/GPIO172 SAR2/GPIO37
R115

R117

R165

T19 E6
5 44 RXA4+ LVA4P/TTL_B[0]/HCONV/GPIO170 SAR0/GPIO35 KEY1 R21
LVA3M/TTL_B[3]/OPT_P/GPIO173 SAR3/GPIO38
D6
T20 F8 R20
LVACKP/TTL_B[4]/MCLK/GPIO174 SAR4/GPIO39
NC_6 I/O6 PCM_A[6] RXA4- LVA4M/TTL_B[1]/E_O/GPIO171 SAR1/GPIO36 KEY2 R19
LVACKM/TTL_B[5]/GCLK/GPIO175
W10
AR103 R107 6 43 T21 E7 P20
LVA2P/TTL_B[6]/GST/GPIO176 GPIO_PM[13]/GPIO20
Y10
22 R109 RXA3+ LVA3P/TTL_B[2]/FB/GPIO172 SAR2/GPIO37 PM_MODEL_OPT_0 LVA2M/TTL_B[7]/POL/GPIO177 GPIO_PM[14]/GPIO21
P3
1K 3.9K R/B I/O5 PCM_A[5] LED_R/BUZZ T19 E6 +3.3V_NORMAL P19
PM_LED/GPIO4
Y3
7 42 RXA3- LVA3M/TTL_B[3]/OPT_P/GPIO173 SAR3/GPIO38 PANEL_CTL N20
LVA1P/TTL_G[0]/EPI0+/GPIO178 GPIO_PM[0]/GPIO7
Y5
R21 D6 N21
LVA1M/TTL_G[1]/EPI0-/GPIO179 PM_SPI_SCZ2/GPIO_PM[10]/GPIO17
W11
/F_RB RE I/O4 PCM_A[4] PM_LED RXACK+ LVACKP/TTL_B[4]/MCLK/GPIO174 SAR4/GPIO39 SCART1_MUTE N19
LVA0P/TTL_G[2]/EPI1+/GPIO180 GPIO_PM[15]/GPIO22
D3
8 41 R20 R123 M21
LVA0M/TTL_G[3]/EPI1-/GPIO181 GPIO_PM[4]/GPIO11
AA3
/PF_OE RXACK- LVACKM/TTL_B[5]/GCLK/GPIO175 10K M20
LVB4P/TTL_G[4]/EPI2+/GPIO182 GPIO_PM[7]/GPIO14
W5
CE NC_25 SPI_SDI DIMMING R19 W10 OPT M19
LVB4M/TTL_G[5]/EPI2-/GPIO183 GPIO_PM[8]/GPIO15
D4
/PF_CE0 9 40 RXA2+ LVA2P/TTL_B[6]/GST/GPIO176 GPIO_PM[13]/GPIO20 URSA_RESET_SoC L20
LVB3P/TTL_G[6]/EPI3+/GPIO184 PWM_PM/GPIO200
L15
4.7K

4.7K

2.7K

P20 Y10 R122 22 LVB3M/TTL_G[7]/EPI3-/GPIO185 PM_UART_TX/GPIO_PM[1]/GPIO8

Y11
NC_7 NC_24 RXA2- LVA2M/TTL_B[7]/POL/GPIO177 GPIO_PM[14]/GPIO21 TCON_I2C_EN L19
PM_UART_RX/GPIO_PM[5]/GPIO12

R108 10 39 C102 R157 100 P3 K20

LVBCKP/TTL_R[0]/EPI4+/GPIO186

R124 10K
10uF
OPT

1K PWM_DIM PWM2 PM_LED/GPIO4 PM_LED K21

LVBCKM/TTL_R[1]/EPI4-/GPIO187
NC_8 NC_23 10V P19 Y3 LVB2P/TTL_R[2]/EPI5+/GPIO188
OPT C101 11 38 RXA1+ LVA1P/TTL_G[0]/EPI0+/GPIO178 GPIO_PM[0]/GPIO7 POWER_DET
K19
J21
LVB2M/TTL_R[3]/EPI5-/GPIO189
R116

R118

R121

N20 Y5 J20
LVB1P/TTL_R[4]/EPI6+/GPIO190
0.1uF VCC_1 VCC_2 RXA1-
R156 OPT 10K LVA1M/TTL_G[1]/EPI0-/GPIO179 PM_SPI_SCZ2/GPIO_PM[10]/GPIO17 AMP_MUTE LVB1M/TTL_R[5]/EPI6-/GPIO191
J19
12 37 R9531_SCL N21 W11 H20
LVB0P/TTL_R[6]/EPI7+/GPIO192

R103 10K RXA0+ LVA0P/TTL_G[2]/EPI1+/GPIO180 GPIO_PM[15]/GPIO22 INV_CTL LVB0M/TTL_R[7]/EPI7-/GPIO193

VSS_1 VSS_2 C103 N19 D3
13 36 0.1uF R9531_SDA RXA0- LVA0M/TTL_G[3]/EPI1-/GPIO181 GPIO_PM[4]/GPIO11 POWER_ON/OFF_1
OPT M21 AA3
NC_9 NC_22 RXB4+ LVB4P/TTL_G[4]/EPI2+/GPIO182 GPIO_PM[7]/GPIO14 RL_ON
+3.3V_NORMAL 14 35 M20 W5
RXB4- LVB4M/TTL_G[5]/EPI2-/GPIO183 GPIO_PM[8]/GPIO15 /FLASH_WP
NC_10 NC_21 M19 D4
R105 15 34 NVRAM_ATMEL(MULTI)
RXB3+ LVB3P/TTL_G[6]/EPI3+/GPIO184 PWM_PM/GPIO200 LED_R/BUZZ M1A_256M_AVS+_CHINA
1K L20 L15 IC101-*2 M1A_128M_AVS+_CHINA
OPT CLE NC_20 IC104 RXB3- LVB3M/TTL_G[7]/EPI3-/GPIO185 PM_UART_TX/GPIO_PM[1]/GPIO8 PM_TXD LGE2136(256M) IC101-*3
16 33 Y11 LGE2135(128M)
AR104
22
AR102 AT24C256C-SSHL-T PM_UART_RX/GPIO_PM[5]/GPIO12 PM_RXD
ALE I/O3 PCM_A[3] +3.3V_NORMAL L19
/PF_CE1 17 32 RXBCK+ LVBCKP/TTL_R[0]/EPI4+/GPIO186 U19 D5
EEPROM K20 T20
LVA4P/TTL_B[0]/HCONV/GPIO170
LVA4M/TTL_B[1]/E_O/GPIO171
SAR0/GPIO35
SAR1/GPIO36
F8
U19
T20
LVA4P/TTL_B[0]/HCONV/GPIO170 SAR0/GPIO35
D5
F8
PF_ALE WE I/O2 PCM_A[2] RXBCK- LVBCKM/TTL_R[1]/EPI4-/GPIO187 T21
LVA3P/TTL_B[2]/FB/GPIO172 SAR2/GPIO37
E7
T21
LVA4M/TTL_B[1]/E_O/GPIO171 SAR1/GPIO36
E7
18 31 A0 VCC K21 T19
LVA3M/TTL_B[3]/OPT_P/GPIO173 SAR3/GPIO38
E6
T19
LVA3P/TTL_B[2]/FB/GPIO172 SAR2/GPIO37
E6
/PF_WE 1 8 RXB2+ LVB2P/TTL_R[2]/EPI5+/GPIO188 R21
LVACKP/TTL_B[4]/MCLK/GPIO174 SAR4/GPIO39
D6
R21
LVA3M/TTL_B[3]/OPT_P/GPIO173 SAR3/GPIO38
D6
WP I/O1 PCM_A[1] K19 R20
LVACKM/TTL_B[5]/GCLK/GPIO175 R20
LVACKP/TTL_B[4]/MCLK/GPIO174 SAR4/GPIO39

/PF_WP 19 30 C105 RXB2- LVB2M/TTL_R[3]/EPI5-/GPIO189 R19

LVA2P/TTL_B[6]/GST/GPIO176 GPIO_PM[13]/GPIO20
W10
R19
LVACKM/TTL_B[5]/GCLK/GPIO175
W10
0.1uF J21 P20
LVA2M/TTL_B[7]/POL/GPIO177 GPIO_PM[14]/GPIO21
Y10
P20
LVA2P/TTL_B[6]/GST/GPIO176 GPIO_PM[13]/GPIO20
Y10
R102 R106 NC_11 I/O0 PCM_A[0] A1 WP RXB1+ LVB1P/TTL_R[4]/EPI6+/GPIO190 PM_LED/GPIO4
P3 LVA2M/TTL_B[7]/POL/GPIO177 GPIO_PM[14]/GPIO21
P3
3.3K 1K 20 29 2 7 J20 P19
LVA1P/TTL_G[0]/EPI0+/GPIO178 GPIO_PM[0]/GPIO7
Y3
P19
PM_LED/GPIO4
Y3
RXB1- LVB1M/TTL_R[5]/EPI6-/GPIO191 N20 Y5 LVA1P/TTL_G[0]/EPI0+/GPIO178 GPIO_PM[0]/GPIO7
NC_12 NC_19 22 J19 N21
LVA1M/TTL_G[1]/EPI0-/GPIO179 PM_SPI_SCZ2/GPIO_PM[10]/GPIO17
LVA0P/TTL_G[2]/EPI1+/GPIO180 GPIO_PM[15]/GPIO22
W11
N20
N21
LVA1M/TTL_G[1]/EPI0-/GPIO179 PM_SPI_SCZ2/GPIO_PM[10]/GPIO17
Y5
W11
21 28 RXB0+ LVB0P/TTL_R[6]/EPI7+/GPIO192 N19
LVA0M/TTL_G[3]/EPI1-/GPIO181 GPIO_PM[4]/GPIO11
D3
N19
LVA0P/TTL_G[2]/EPI1+/GPIO180 GPIO_PM[15]/GPIO22
D3
A2 A0’h SCL H20 M21
LVB4P/TTL_G[4]/EPI2+/GPIO182 GPIO_PM[7]/GPIO14
AA3
M21
LVA0M/TTL_G[3]/EPI1-/GPIO181 GPIO_PM[4]/GPIO11
AA3
NC_13 NC_18 3 6 R111 22 RXB0- LVB0M/TTL_R[7]/EPI7-/GPIO193 M20
LVB4M/TTL_G[5]/EPI2-/GPIO183 GPIO_PM[8]/GPIO15
W5
M20
LVB4P/TTL_G[4]/EPI2+/GPIO182 GPIO_PM[7]/GPIO14
W5
22 27 I2C_SCL M19
LVB3P/TTL_G[6]/EPI3+/GPIO184 PWM_PM/GPIO200
D4
M19
LVB4M/TTL_G[5]/EPI2-/GPIO183 GPIO_PM[8]/GPIO15
D4
L20 L15 LVB3P/TTL_G[6]/EPI3+/GPIO184 PWM_PM/GPIO200
LVB3M/TTL_G[7]/EPI3-/GPIO185 PM_UART_TX/GPIO_PM[1]/GPIO8 L20 L15
NC_14 NC_17 PM_UART_RX/GPIO_PM[5]/GPIO12
Y11 LVB3M/TTL_G[7]/EPI3-/GPIO185 PM_UART_TX/GPIO_PM[1]/GPIO8
Y11
23 26 GND SDA
L19
LVBCKP/TTL_R[0]/EPI4+/GPIO186 L19
PM_UART_RX/GPIO_PM[5]/GPIO12

4 5 R112 22 K20
LVBCKM/TTL_R[1]/EPI4-/GPIO187 K20
LVBCKP/TTL_R[0]/EPI4+/GPIO186
NC_15 NC_16 I2C_SDA K21
LVB2P/TTL_R[2]/EPI5+/GPIO188 K21
LVBCKM/TTL_R[1]/EPI4-/GPIO187
24 25 C104 C106 K19
LVB2M/TTL_R[3]/EPI5-/GPIO189 K19
LVB2P/TTL_R[2]/EPI5+/GPIO188
J21 LVB2M/TTL_R[3]/EPI5-/GPIO189
8pF 8pF J20
LVB1P/TTL_R[4]/EPI6+/GPIO190 J21
LVB1P/TTL_R[4]/EPI6+/GPIO190
LVB1M/TTL_R[5]/EPI6-/GPIO191 J20
OPT OPT J19
H20
LVB0P/TTL_R[6]/EPI7+/GPIO192 J19
LVB1M/TTL_R[5]/EPI6-/GPIO191
LVB0P/TTL_R[6]/EPI7+/GPIO192
LVB0M/TTL_R[7]/EPI7-/GPIO193 H20
EAN61133501 LVB0M/TTL_R[7]/EPI7-/GPIO193

NVRAM_RHOM(MULTI)
NAND_2G_HYNIX(MULTI) NAND_1G_TOSHIBA(MULTI)
IC104-*1
EAN60708703 EAN61508002
BR24G256FJ-3
IC102-*1 IC102-*2
H27U2G8F2DTR-BD TC58NVG0S3HTA00 M1A_256M
A0 VCC IC101
1 8 M1A_128M
LGE2134(256M) from CI SLOT IC101-*1
NC_1 NC_29 NC_1 NC_29 LGE2133(128M)
1 48 1 48
A1 WP
NC_2 NC_28 NC_2 NC_28 2 7 CI_TS_CLK Y1 V10
2 47 2 47
Used net when HDMI Switch not used CI_TS_DATA[0-7] W4
GPIO78 TS0CLK/GPIO92
T14
GPIO79 TS0DATA[0]/GPIO82
NC_3 NC_27 NC_3 NC_27 Y1 V10 TS0DATA[1]/GPIO83
T13

3 46 3 46 A2 SCL 5V_DET_HDMI_4 FRC_FLASH_WP GPIO78 TS0CLK/GPIO92 CI_TS_DATA[0] CI_TS_SYNC K17

I2C_SCKM3/I2C_DDCR_CK/GPIO77 TS0DATA[2]/GPIO84
U13

3 6 W4 T14 J15
I2C_SDAM3/I2C_DDCR_DA/GPIO76 TS0DATA[3]/GPIO85
V15

NC_4 NC_26 NC_4 NC_26 5V_DET_HDMI_2 5V_DET_HDMI_4 GPIO79 TS0DATA[0]/GPIO82 CI_TS_DATA[1] CI_TS_VAL U8
SDAM2/GPIO55 TS0DATA[4]/GPIO86
U12

4 45 4 45 T13 T7
SCKM2/GPIO56 TS0DATA[5]/GPIO87
V13

TS0DATA[1]/GPIO83 CI_TS_DATA[2]
U7
SCKM0/GPIO58 TS0DATA[6]/GPIO88
U14

NC_5 I/O7 NC_5 I/O8 GND SDA R184 22 K17 U13 V7

SDAM0/GPIO59 TS0DATA[7]/GPIO89
T11

5 44 5 44 4 5 I2C_SCL I2C_SCKM3/I2C_DDCR_CK/GPIO77 TS0DATA[2]/GPIO84 CI_TS_DATA[3]

F6
I2S_IN_BCK/GPIO159 TS0SYNC/GPIO91
T12

R183 22 J15 V15 G6

I2S_IN_SD/GPIO160 TS0VALID/GPIO90
V12

NC_6 I/O6 NC_6 I/O7 I2C_SDA I2C_SDAM3/I2C_DDCR_DA/GPIO76 TS0DATA[3]/GPIO85 CI_TS_DATA[4]

AA4
I2C_SCKM1/GPIO80 TS1CLK/GPIO103
Y14

6 43 6 43 R126 0 U8 U12 Y4
I2C_SDAM1/GPIO81 TS1DATA[0]/GPIO93
Y16
URSA_SDA SDAM2/GPIO55 TS0DATA[4]/GPIO86 CI_TS_DATA[5] TS1DATA[1]/GPIO94
AA15

R/B I/O5 RY/BY I/O6 R127 0 T7 V13 J6

ET_TXD[0]/GPIO62 TS1DATA[2]/GPIO95
Y13

7 42 7 42 URSA_SCL SCKM2/GPIO56 TS0DATA[5]/GPIO87 CI_TS_DATA[6]

K6
EXT_TX_CLK/GPIO64 TS1DATA[3]/GPIO96
AA16

EAN62389502 R128 0 U7 U14 TS1DATA[4]/GPIO97

W12

RE I/O4 RE I/O5 HDMI_SW_SCL SCKM0/GPIO58 TS0DATA[6]/GPIO88 CI_TS_DATA[7]

G7 AA13

8 41 8 41 R129 0 V7 T11 Internal demod out I2S_IN_WS/GPIO158 TS1DATA[5]/GPIO98

TS1DATA[6]/GPIO99
W14

HDMI_SW_SDA SDAM0/GPIO59 TS0DATA[7]/GPIO89 J4

ET_COL/GPIO60 TS1DATA[7]/GPIO100
W13

CE NC_25 CE NC_25 T2_OR_CHINA F6 T12 J5

ET_TXD[1]/GPIO61 TS1SYNC/GPIO102
Y15

9 40 9 40 R113 22 AMP_SCL I2S_IN_BCK/GPIO159 TS0SYNC/GPIO91 FE_TS_CLK TS1VALID/GPIO101

W15

DEMOD_SCL G6 V12 H19

LCK/GPIO194
R114 22 AMP_SDA I2S_IN_SD/GPIO160 TS0VALID/GPIO90 FE_TS_DATA[0-7] G20 B3
NC_7 NC_24 NC_7 NC_24 AA4 Y14
LDE/GPIO195 PM_SPI_SCZ1/GPIO_PM[6]/GPIO13
10 39 10 39 DEMOD_SDA G19
LHSYNC/GPIO196 PM_SPI_SCK/GPIO1
A3

T2_OR_CHINA TU_SCL I2C_SCKM1/GPIO80 TS1CLK/GPIO103 FE_TS_DATA[0] FE_TS_SYNC G21

LVSYNC/GPIO197 PM_SPI_SCZ0/GPIO0
A4

NC_8 NC_23 NC_8 NC_23 +3.3V_NORMAL Y4 Y16 PM_SPI_SDI/GPIO2

11 38 11 38 I2C TU_SDA I2C_SDAM1/GPIO81 TS1DATA[0]/GPIO93 FE_TS_DATA[1] FE_TS_VAL_ERR J17

UART2_RX/GPIO69 PM_SPI_SDO/GPIO3
A2
AA15 J16
UART2_TX/GPIO70
VCC_1 VCC_2 VCC_1 VCC_2 TS1DATA[1]/GPIO94 FE_TS_DATA[2]
E8
UART3_TX/GPIO52 RP
B1

12 37 12 37 J6 Y13 D7
UART3_RX/GPIO53 TN
C2

AV_CVBS_DET ET_TXD[0]/GPIO62 TS1DATA[2]/GPIO95 FE_TS_DATA[3]

U6
GPIO46[CTS] TP
C1

VSS_1 VSS_2 VSS_1 VSS_2 K6 AA16 V6

GPIO47[RTS] RN
B2

13 36 13 36 R101 R104 R110 R119 R120 R125 R140 R141 R144 R145 AV2_CVBS_DET EXT_TX_CLK/GPIO64 TS1DATA[3]/GPIO96 FE_TS_DATA[4] FE_TS_DATA[0] K15
UART1_TX/GPIO48
1K 1K 1.8K 1.8K 1.8K 1.8K 1K 1K 2.2K 2.2K R146 R147 W12 L16
UART1_RX/GPIO49 SPDIF_IN/GPIO161
D2

TS1DATA[4]/GPIO97 FE_TS_DATA[0] D1
NC_9 NC_22 NC_9 NC_22 3.3K 3.3K G7 AA13 FE_TS_DATA[5] H5
SPDIF_OUT/GPIO162
14 35 14 35 ET_TX_EN/GPIO63
COMP2_DET I2S_IN_WS/GPIO158 TS1DATA[5]/GPIO98 FE_TS_DATA[6]
K5
ET_RXD[0]/GPIO65 HWRESET
D8

NC_10 NC_21 NC_10 NC_21 W14 K4

ET_MDC/GPIO66 IRIN/GPIO5
E5
G4
15 34 15 34 TS1DATA[6]/GPIO99 FE_TS_DATA[7]
H6
ET_MDIO/GPIO67 DDCA_CK/UART0_RX
URSA_SDA J4 W13 L5
ET_RXD[1]/GPIO68 DDCA_DA/UART0_TX
G5

CLE NC_20 CLE NC_20 URSA_SCL DEMOD_RESET ET_COL/GPIO60 TS1DATA[7]/GPIO100

16 33 16 33 J5 Y15 U17
PCMADR[0]/NF_AD[0]/GPIO130 PWM0/GPIO71
J18

I2C_SDA MODEL_OPT_0 ET_TXD[1]/GPIO61 TS1SYNC/GPIO102 R18

PCMADR[1]/NF_AD[1]/GPIO129 PWM1/GPIO72
K18

ALE I/O3 ALE I/O4 W15 V17

PCMADR[2]/NF_AD[2]/GPIO127 PWM2/GPIO73
K16

17 32 17 32 I2C_SCL TS1VALID/GPIO101 R16

PCMADR[3]/NF_AD[3]/GPIO126 PWM3/GPIO74
L18
H19 U16
PCMADR[4]/NF_AD[4]/GPIO104 PWM4/GPIO75
L17

WE I/O2 WE I/O3 AMP_SDA MODEL_OPT_1 LCK/GPIO194 T17

PCMADR[5]/NF_AD[5]/GPIO106
18 31 18 31 G20 B3 R189 33 W18
PCMADR[6]/NF_AD[6]/GPIO107 NF_ALE/GPIO146
T8

AMP_SCL MODEL_OPT_2 LDE/GPIO195 PM_SPI_SCZ1/GPIO_PM[6]/GPIO13 /SPI_CS U20

PCMADR[7]/NF_AD[7]/GPIO108 NF_CEZ/GPIO142
T9

WP I/O1 WP I/O2 G19 A3 R188 33 Y19

PCMADR[8]/GPIO113 NF_CLE/GPIO141
U9

19 30 19 30 AMP_RESET LHSYNC/GPIO196 PM_SPI_SCK/GPIO1 SPI_SCK AA19

PCMADR[9]/GPIO115 NF_RBZ/GPIO147
U11
R9531_SDA G21 A4 AA20
PCMADR[10]/GPIO119 NF_REZ/GPIO144
V9

NC_11 I/O0 NC_11 I/O1 LVSYNC/GPIO197 PM_SPI_SCZ0/GPIO0 SIDE_HP_MUTE W21

PCMADR[11]/GPIO117 NF_WEZ/GPIO145
U10

20 29 20 29 R9531_SCL C3 V20
PCMADR[12]/GPIO109 NF_WPZ/GPIO199
T10

PM_SPI_SDI/GPIO2 SPI_SDI Y17

PCMADR[13]/GPIO112
NC_12 NC_19 NC_12 NC_19 HDMI_SW_SCL J17 A2 R190 33 V18
PCMADR[14]/GPIO111 IF_AGC
W2

21 28 21 28 HP_DET UART2_RX/GPIO69 PM_SPI_SDO/GPIO3 SPI_SDO V19

PCMCD_N/GPIO135 SIFM
W1

HDMI_SW_SDA J16 W19

PCMCE_N/GPIO120 SIFP
W3

NC_13 NC_18 NC_13 NC_18 SC1/COMP1_DET UART2_TX/GPIO70 U18

PCMDATA[0]/GPIO131 IM
V2

22 27 22 27 IR_SCL R130 0 E8 B1 V16

PCMDATA[1]/GPIO132 IP
V1

IR_SDA UART3_TX/GPIO52 RP EPHY_RP W17

PCMDATA[2]/GPIO133
NC_14 NC_17 NC_14 NC_17 IR_SDA D7 C2 Y20
PCMDATA[3]/GPIO125 XIN
AA2

23 26 23 26 UART3_RX/GPIO53 TN EPHY_TN R15

PCMDATA[4]/GPIO124 XOUT
Y2
U6 C1 AA18
PCMDATA[5]/GPIO123
NC_15 NC_16 NC_15 NC_16 MODEL_OPT_4 GPIO46[CTS] TP EPHY_TP T15
PCMDATA[6]/GPIO122
24 25 24 25 R131 0 V6 B2 Y21
PCMDATA[7]/GPIO121
IR_SCL GPIO47[RTS] RN EPHY_RN W20
PCMIORD_N/GPIO116
K15 V21
PCMIOWR_N/GPIO114
/CI_CD1 UART1_TX/GPIO48 Y18
PCMIRQA_N/GPIO110
L16 D2 T16
PCMOE_N/GPIO118
/CI_CD2 UART1_RX/GPIO49 SPDIF_IN/GPIO161 5V_DET_HDMI_2 R17
PCMREG_N/GPIO128
D1 R192 100 T18
PCM_RESET/GPIO134
+3.3V_NORMAL SPDIF_OUT/GPIO162 SPDIF_OUT W16
PCMWAIT_N/GPIO105
NAND_2G_TOSHIBA(MULTI) H5 SPDIF_OPTIC U15
PCMWE_N/GPIO198
USB1_CTL ET_TX_EN/GPIO63
EAN60991001 R180 K5 D8
10K MODEL_OPT_5 ET_RXD[0]/GPIO65 HWRESET SOC_RESET
IC102-*3 K4 E5
TC58NVG1S3ETA00 R197 0 MODEL_OPT_6 ET_MDC/GPIO66 IRIN/GPIO5 IR
CI_DET H6 G4
R178 22 USB1_OCD ET_MDIO/GPIO67 DDCA_CK/UART0_RX RGB_DDC_SCL
/PCM_CD L5 G5
PCM_A[0-14] ET_RXD[1]/GPIO68 DDCA_DA/UART0_TX RGB_DDC_SDA M1A_256M_AVS+_CHINA M1A_128M_AVS+_CHINA
IC101-*2 IC101-*3
NC_1 NC_29 LGE2136(256M) LGE2135(128M)
1 48 PCM_A[0] U17 J18 R132 0
NC_2 NC_28 PCM_A[1] PCMADR[0]/NF_AD[0]/GPIO130 PWM0/GPIO71 R9531_SCL
2 47 R18 K18 Y1 V10 Y1 V10
PCM_A[2] PCMADR[1]/NF_AD[1]/GPIO129 PWM1/GPIO72 PWM1 W4
GPIO78 TS0CLK/GPIO92
T14 W4
GPIO78 TS0CLK/GPIO92
T14
NC_3 NC_27 V17 K16 GPIO79 TS0DATA[0]/GPIO82
T13
GPIO79 TS0DATA[0]/GPIO82
T13
3 46 PCM_A[3] PCMADR[2]/NF_AD[2]/GPIO127 PWM2/GPIO73 PWM2 K17
TS0DATA[1]/GPIO83
U13 K17
TS0DATA[1]/GPIO83
U13
R16 L18 R133 0 J15
I2C_SCKM3/I2C_DDCR_CK/GPIO77 TS0DATA[2]/GPIO84
V15 J15
I2C_SCKM3/I2C_DDCR_CK/GPIO77 TS0DATA[2]/GPIO84
V15
NC_4 NC_26 PCM_A[4] PCMADR[3]/NF_AD[3]/GPIO126 PWM3/GPIO74 R9531_SDA U8
I2C_SDAM3/I2C_DDCR_DA/GPIO76 TS0DATA[3]/GPIO85
U12 U8
I2C_SDAM3/I2C_DDCR_DA/GPIO76 TS0DATA[3]/GPIO85
U12
4 45 U16 L17 T7
SDAM2/GPIO55 TS0DATA[4]/GPIO86
V13 T7
SDAM2/GPIO55 TS0DATA[4]/GPIO86
V13
PCM_A[5] PCMADR[4]/NF_AD[4]/GPIO104 PWM4/GPIO75 PCM_5V_CTL U7
SCKM2/GPIO56 TS0DATA[5]/GPIO87
U14 U7
SCKM2/GPIO56 TS0DATA[5]/GPIO87
U14
NC_5 I/O8 T17 V7
SCKM0/GPIO58 TS0DATA[6]/GPIO88
T11 V7
SCKM0/GPIO58 TS0DATA[6]/GPIO88
T11
5 44 PCM_A[6] PCMADR[5]/NF_AD[5]/GPIO106 F6
SDAM0/GPIO59 TS0DATA[7]/GPIO89
T12 F6
SDAM0/GPIO59 TS0DATA[7]/GPIO89
T12
W18 T8 +3.3V_NORMAL G6
I2S_IN_BCK/GPIO159 TS0SYNC/GPIO91
V12 G6
I2S_IN_BCK/GPIO159 TS0SYNC/GPIO91
V12
NC_6 I/O7 PCM_A[7] PCMADR[6]/NF_AD[6]/GPIO107 NF_ALE/GPIO146 PF_ALE AA4
I2S_IN_SD/GPIO160 TS0VALID/GPIO90
Y14 AA4
I2S_IN_SD/GPIO160 TS0VALID/GPIO90
Y14
6 43 U20 T9 Y4
I2C_SCKM1/GPIO80 TS1CLK/GPIO103
Y16 Y4
I2C_SCKM1/GPIO80 TS1CLK/GPIO103
Y16
PCM_A[8] PCMADR[7]/NF_AD[7]/GPIO108 NF_CEZ/GPIO142 /PF_CE0 I2C_SDAM1/GPIO81 TS1DATA[0]/GPIO93
AA15
I2C_SDAM1/GPIO81 TS1DATA[0]/GPIO93
AA15
RY/BY I/O6 Y19 U9 IF_AGC J6
TS1DATA[1]/GPIO94
Y13 J6
TS1DATA[1]/GPIO94
Y13
7 42 PCM_A[9] PCMADR[8]/GPIO113 NF_CLE/GPIO141 /PF_CE1 L101 K6
ET_TXD[0]/GPIO62 TS1DATA[2]/GPIO95
AA16 K6
ET_TXD[0]/GPIO62 TS1DATA[2]/GPIO95
AA16
AA19 U11 BLM18PG121SN1D EXT_TX_CLK/GPIO64 TS1DATA[3]/GPIO96
W12
EXT_TX_CLK/GPIO64 TS1DATA[3]/GPIO96
W12
RE I/O5 PCM_A[10] PCMADR[9]/GPIO115 NF_RBZ/GPIO147 /F_RB G7
TS1DATA[4]/GPIO97
AA13 G7
TS1DATA[4]/GPIO97
AA13
8 41 AA20 V9 I2S_IN_WS/GPIO158 TS1DATA[5]/GPIO98
W14
I2S_IN_WS/GPIO158 TS1DATA[5]/GPIO98
W14
PCM_A[11] PCMADR[10]/GPIO119 NF_REZ/GPIO144 /PF_OE IF_AGC IF_AGC J4
TS1DATA[6]/GPIO99
W13 J4
TS1DATA[6]/GPIO99
W13
CE NC_25 W21 U10 R193 C119 J5
ET_COL/GPIO60 TS1DATA[7]/GPIO100
Y15 J5
ET_COL/GPIO60 TS1DATA[7]/GPIO100
Y15
9 40 PCM_A[12] PCMADR[11]/GPIO117 NF_WEZ/GPIO145 /PF_WE 10K 0.1uF ET_TXD[1]/GPIO61 TS1SYNC/GPIO102
W15
ET_TXD[1]/GPIO61 TS1SYNC/GPIO102
W15
V20 T10 IF_AGC H19
TS1VALID/GPIO101
H19
TS1VALID/GPIO101

NC_7 NC_24 PCM_A[13] PCMADR[12]/GPIO109 NF_WPZ/GPIO199 /PF_WP R196 G20

LCK/GPIO194
B3 G20
LCK/GPIO194
B3
10 39 Y17 0 G19
LDE/GPIO195 PM_SPI_SCZ1/GPIO_PM[6]/GPIO13
A3 G19
LDE/GPIO195 PM_SPI_SCZ1/GPIO_PM[6]/GPIO13
A3
PCM_A[14] PCMADR[13]/GPIO112 IF_AGC_MAIN G21
LHSYNC/GPIO196 PM_SPI_SCK/GPIO1
A4 G21
LHSYNC/GPIO196 PM_SPI_SCK/GPIO1
A4
NC_8 NC_23 V18 W2 C120 LVSYNC/GPIO197 PM_SPI_SCZ0/GPIO0
C3
LVSYNC/GPIO197 PM_SPI_SCZ0/GPIO0
C3
11 38 PCMADR[14]/GPIO111 IF_AGC TU_SIF 0.047uF
PM_SPI_SDI/GPIO2 PM_SPI_SDI/GPIO2
0.1uF R198TU_SIF
J17 A2 J17 A2
V19 W1 C115 47 J16
UART2_RX/GPIO69 PM_SPI_SDO/GPIO3
J16
UART2_RX/GPIO69 PM_SPI_SDO/GPIO3

VCC_1 VCC_2 PCM_D[0-7] /PCM_CD PCMCD_N/GPIO135 SIFM 25V E8

UART2_TX/GPIO70
B1 E8
UART2_TX/GPIO70
B1
12 37 W19 W3 C116 0.1uF R199 47 IF_AGC D7
UART3_TX/GPIO52 RP
C2 D7
UART3_TX/GPIO52 RP
C2
/PCM_CE PCMCE_N/GPIO120 SIFP C123 U6
UART3_RX/GPIO53 TN
C1 U6
UART3_RX/GPIO53 TN
C1
VSS_1 VSS_2 PCM_D[0] U18 V2 TU_SIF TU_SIF 1000pF V6
GPIO46[CTS] TP
B2 V6
GPIO46[CTS] TP
B2
13 36 PCMDATA[0]/GPIO131 IM GPIO47[RTS] RN GPIO47[RTS] RN
PCM_D[1] V16 V1 ANALOG SIF TU_SIF K15
L16
UART1_TX/GPIO48
D2
K15
L16
UART1_TX/GPIO48
D2
NC_9 NC_22 PCMDATA[1]/GPIO132 IP UART1_RX/GPIO49 SPDIF_IN/GPIO161 UART1_RX/GPIO49 SPDIF_IN/GPIO161

14 35 PCM_D[2] W17 Close to MSTAR TU_SIF H5

SPDIF_OUT/GPIO162
D1
H5
SPDIF_OUT/GPIO162
D1

PCMDATA[2]/GPIO133 R194-*1 K5
ET_TX_EN/GPIO63
D8 K5
ET_TX_EN/GPIO63
D8
NC_10 NC_21 PCM_D[3] Y20 AA2 R194
0 TUNER_IF_100_ohm K4
ET_RXD[0]/GPIO65 HWRESET
E5 K4
ET_RXD[0]/GPIO65 HWRESET
E5
15 34 PCMDATA[3]/GPIO125 XIN IF_N_MSTAR H6
ET_MDC/GPIO66 IRIN/GPIO5
G4 H6
ET_MDC/GPIO66 IRIN/GPIO5
G4
PCM_D[4] R15 Y2 TUNER_IF_0_ohm IF OPT 100 L5
ET_MDIO/GPIO67 DDCA_CK/UART0_RX
G5 L5
ET_MDIO/GPIO67 DDCA_CK/UART0_RX
G5
CLE NC_20 PCMDATA[4]/GPIO124 XOUT C117 C121 ET_RXD[1]/GPIO68 DDCA_DA/UART0_TX ET_RXD[1]/GPIO68 DDCA_DA/UART0_TX

16 33 PCM_D[5] AA18 0.1uF 100pF DTV_IF U17 J18 U17 J18

PCMDATA[5]/GPIO123 R195 0 R195-*1 R18
PCMADR[0]/NF_AD[0]/GPIO130 PWM0/GPIO71
K18 R18
PCMADR[0]/NF_AD[0]/GPIO130 PWM0/GPIO71
K18
ALE I/O4 PCM_D[6] T15 IF_P_MSTAR TUNER_IF_100_ohm PCMADR[1]/NF_AD[1]/GPIO129 PWM1/GPIO72 PCMADR[1]/NF_AD[1]/GPIO129 PWM1/GPIO72

TUNER_IF_0_ohm IF
V17 K16 V17 K16
17 32 PCMDATA[6]/GPIO122 C118 C122 C124 R16
PCMADR[2]/NF_AD[2]/GPIO127 PWM2/GPIO73
L18 R16
PCMADR[2]/NF_AD[2]/GPIO127 PWM2/GPIO73
L18
PCM_D[7] Y21 0.1uF 33pF 33pF 100 U16
PCMADR[3]/NF_AD[3]/GPIO126 PWM3/GPIO74
L17 U16
PCMADR[3]/NF_AD[3]/GPIO126 PWM3/GPIO74
L17
WE I/O3 PCMDATA[7]/GPIO121 NON_ATSC NON_ATSC T17
PCMADR[4]/NF_AD[4]/GPIO104 PWM4/GPIO75
T17
PCMADR[4]/NF_AD[4]/GPIO104 PWM4/GPIO75

18 31 W20 W18
PCMADR[5]/NF_AD[5]/GPIO106
T8 W18
PCMADR[5]/NF_AD[5]/GPIO106
T8
/PCM_IORD PCMIORD_N/GPIO116 For KR/US models U20
PCMADR[6]/NF_AD[6]/GPIO107 NF_ALE/GPIO146
T9 U20
PCMADR[6]/NF_AD[6]/GPIO107 NF_ALE/GPIO146
T9
WP I/O2 V21 Close to MSTAR Y19
PCMADR[7]/NF_AD[7]/GPIO108 NF_CEZ/GPIO142
U9 Y19
PCMADR[7]/NF_AD[7]/GPIO108 NF_CEZ/GPIO142
U9
19 30 /PCM_IOWR PCMIOWR_N/GPIO114 AA19
PCMADR[8]/GPIO113 NF_CLE/GPIO141
U11 AA19
PCMADR[8]/GPIO113 NF_CLE/GPIO141
U11
Y18 AA20
PCMADR[9]/GPIO115 NF_RBZ/GPIO147
V9 AA20
PCMADR[9]/GPIO115 NF_RBZ/GPIO147
V9
NC_11 I/O1 /PCM_IRQA PCMIRQA_N/GPIO110 W21
PCMADR[10]/GPIO119 NF_REZ/GPIO144
U10 W21
PCMADR[10]/GPIO119 NF_REZ/GPIO144
U10
20 29 T16 V20
PCMADR[11]/GPIO117 NF_WEZ/GPIO145
T10 V20
PCMADR[11]/GPIO117 NF_WEZ/GPIO145
T10
/PCM_OE PCMOE_N/GPIO118 Y17
PCMADR[12]/GPIO109 NF_WPZ/GPIO199
Y17
PCMADR[12]/GPIO109 NF_WPZ/GPIO199
R17 PCMADR[13]/GPIO112 PCMADR[13]/GPIO112
R187

NC_12 NC_19
/PCM_REG
X101 C113 22pF V18 W2 V18 W2
21 28 PCMREG_N/GPIO128 PCMADR[14]/GPIO111 IF_AGC PCMADR[14]/GPIO111 IF_AGC
1M

V19 W1 V19 W1
T18 24MHz C114 22pF W19
PCMCD_N/GPIO135 SIFM
W3 W19
PCMCD_N/GPIO135 SIFM
W3
NC_13 NC_18 PCM_RST PCM_RESET/GPIO134 U18
PCMCE_N/GPIO120 SIFP
V2 U18
PCMCE_N/GPIO120 SIFP
V2
22 27 W16 V16
PCMDATA[0]/GPIO131 IM
V1 V16
PCMDATA[0]/GPIO131 IM
V1
/PCM_WAIT PCMWAIT_N/GPIO105 W17
PCMDATA[1]/GPIO132 IP
W17
PCMDATA[1]/GPIO132 IP

NC_14 NC_17 U15 Y20

PCMDATA[2]/GPIO133
AA2 Y20
PCMDATA[2]/GPIO133
AA2
23 26 /PCM_WE PCMWE_N/GPIO198 R15
PCMDATA[3]/GPIO125 XIN
Y2 R15
PCMDATA[3]/GPIO125 XIN
Y2
PCMDATA[4]/GPIO124 XOUT PCMDATA[4]/GPIO124 XOUT
AA18 AA18
PCMDATA[5]/GPIO123 PCMDATA[5]/GPIO123
NC_15 NC_16 T15
PCMDATA[6]/GPIO122
T15
PCMDATA[6]/GPIO122
24 25 Y21
PCMDATA[7]/GPIO121
Y21
PCMDATA[7]/GPIO121
W20 W20
PCMIORD_N/GPIO116 PCMIORD_N/GPIO116
V21 V21
PCMIOWR_N/GPIO114 PCMIOWR_N/GPIO114
Y18 Y18
PCMIRQA_N/GPIO110 PCMIRQA_N/GPIO110
T16 T16
PCMOE_N/GPIO118 PCMOE_N/GPIO118
R17 R17
PCMREG_N/GPIO128 PCMREG_N/GPIO128
T18 T18
PCM_RESET/GPIO134 PCM_RESET/GPIO134
W16 W16
PCMWAIT_N/GPIO105 PCMWAIT_N/GPIO105
U15 U15
PCMWE_N/GPIO198 PCMWE_N/GPIO198

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

Copyright ⓒ 2015 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Downloaded from www.Manualslib.com manuals search engine
Only for training and service purposes
+3.3V_NORMAL
MODEL OPTION SOC_RESET +3.5V_ST
STby 3.5V Normal Power 3.3V DDR3 1.5V VDDC 1.05V +1.10V_VDDC
MO_M120(UHD120)

+1.10V_VDDC
MO_DVB_T2/C/S2
MO_S/W_EU/AJ
DDR_EXT:256

DDR_EXT:128
1K

L206
1K

MO_S/W_AJ

BLM18PG121SN1D AVDD_NODIE +1.5V_DDR VDDC : 2026mA

+3.3V_NORMAL VDD33
URSA11

+1.10V_VDDC +1.10V_VDDC
OPT

POWER_DET_RESET C289 C286 C252

+3.5V_ST 10uF 0.1uF 0.1uF AVDD_DDR0:55mA
C296 C210 C279
L204 10uF 0.1uF 0.1uF
R291

R222

R221

R206

R208

R211

R226
R290

0.1uF

0.1uF
0.1uF
BLM18PG121SN1D 10V

10uF

0.1uF
10V

1uF
OPT
0.1uF

0.1uF

0.1uF
0.1uF

10V

10V
0.1uF

1uF

1uF
R201 OPT 100 R266 L207
MODEL_OPT_0 470
10V

10V

R202 OPT 100 BLM18PG121SN1D AVDD_DMPLL

MODEL_OPT_1

C275
C248
C207
C254
C278

C228
C266
R203 OPT 100 OPT

10uF

10uF
C288 C205

C277

C280

C283
MODEL_OPT_2
C284
10uF

C204
10uF

C202 C200 10uF 0.1uF

C209

C235

C245

R204 OPT 100

C255

C259

AUD_LRCH 4.7uF 4.7uF

R225 OPT 100 10V 10V
MODEL_OPT_4
R228 OPT 100 L208 AVDD_DDR1:55mA
MODEL_OPT_5 SOC_RESET AVDD_AU33
OPT 100 BLM18PG121SN1D
R230 MODEL_OPT_6
OPT 100
DDR_EXT:128 or NON

DDR_EXT:256 or NON

R229 C201
MO_M120_NON(UHD60)

AUD_LRCK R200 C240 C287 C241

470K 0.1uF 0.1uF 10uF 0.1uF
MO_S/W_NON_AJ
1K
MO_S/W_TW/CN
1K
1K

1K
MO_DVB_T/C
URSA9

R212
R294
R293

R224

R223

R207

R209

R227

+3.5V_ST PM MODEL OPTION

R177
10K PM_MODEL_OPT_0
OPT
PM_MODEL_OPT_0
- HIGH : Non_UHD
R176 - LOW :: UHD
10K
PM_MODEL_OPT_1
MODEL OPTION - Not Use (Ready)
PIN NAME PIN NO. LOW HIGH
PM_model_opt_0 E7 UHD Non_UHD
MODEL_OPT_0 J5 MO_FHD MO_HD
MODEL_OPT_1 H19 MO_S/W_NON_AJ MO_S/W_AJ

MODEL_OPT_2 G20 MO_DVB_T/C MO_DVB_T2/C/S2

MODEL_OPT_3
G19 MO_M120_NON(UDH60) MO_M120(UHD120)
(AUD_LRCH) M1A_256M
IC101 M1A_128M
MODEL_OPT_4 U6 DDR_EXT:256 or NON DDR_EXT : 128 LGE2134(256M)
IC101-*1
LGE2133(128M)

MODEL_OPT_5 K5 MO_S/W_TW/CN MO_S/W_EU/AJ R4 U3

AVDD_AU33 AUVRM

MODEL_OPT_6 K4 DDR_EXT:128 or NON DDR_EXT : 256

L11
L13
AVDD_DDR0_CLK GND_1
A6
A13
AVDD_DDR1_CLK GND_2
R4 U3 M11
AVDD_DDR0_CMD GND_3
A15

MODEL_OPT_7 AVDD_AU33 AVDD_AU33 AUVRM AUVRM K13 A18

L5 URSA9 URSA11 L11 A6 C5

AVDD_DDR1_CMD
AVDD_DDR0_D_1
GND_4
GND_5
B12

(AUD_LRCK) L13
AVDD_DDR0_CLK GND_1
A13
K12
L12
AVDD_DDR0_D_2 GND_6
B14
B16
AVDD_DDR0_D_3 GND_7
AVDD_DDR1_CLK GND_2 C6
AVDD_DDR1_D_1 GND_8
B17
M11 A15 K14
AVDD_DDR1_D_2 GND_9
B19

AVDD_DDR0_CMD GND_3 L14

AVDD_DDR1_D_3 GND_10
B20
K13 A18 B5
AVDD_DRAM_1 GND_11
C9

AVDD_DDR1_CMD GND_4 B6
AVDD_DRAM_2 GND_12
C10

+1.5V_DDR C5 B12 R8
AVDD_DVI_USB_MPLL_1 GND_13
C21

AVDD_DDR0_D_1 GND_5 R9
AVDD_DVI_USB_MPLL_2 GND_14
D9
K12 B14 L7
AVDD_MOD_1 GND_15
E20

AVDD_DDR0_D_2 GND_6 L8
AVDD_MOD_2 GND_16
F9
L12 B16 P8 F11

Memory OPTION C6
AVDD_DDR0_D_3
AVDD_DDR1_D_1
GND_7
GND_8
B17
K9
R5
P11
AVDD_NODIE
AVDD_PLL
AVDD3P3_DMPLL
AVDDL_MOD
GND_17
GND_18
GND_19
GND_20
F13
F15
F17
K14 B19 C7 F19
Memory Auto AVDD_DDR1_D_2 GND_9 M13
DVDD_DDR_1 GND_21
F21
MODEL_OPT_4 MODEL_OPT_6 L14 B20 R6
DVDD_DDR_2 GND_22
G8
INT+EXT Det AVDD_DDR1_D_3 GND_10 A7
DVDD_NODIE
DVDD_RX_1_1
GND_23
GND_24
G9
B5 C9 M12
DVDD_RX_1_2 GND_25
G10

AVDD_DRAM_1 GND_11 B7 G11

128M Only 0 0 0 B6 C10 M14
DVDD_RX_2_1
DVDD_RX_2_2
GND_26
GND_27
G12

AVDD_DRAM_2 GND_12 N11

VDDC_1 GND_28
G13
R8 C21 N12
VDDC_2 GND_29
G14
AVDD_NODIE AVDD_DVI_USB_MPLL_1 GND_13 N13 G15
256M Only 1 0 0 R9 D9 N14
VDDC_3
VDDC_4
GND_30
GND_31
G16

AVDD_DVI_USB_MPLL_2 GND_14 N15

VDDC_5 GND_32
G17
L7 E20 P12
VDDC_6 GND_33
G18
VDD33 AVDD_MOD_1 GND_15 P13 H7
128M+128M 0 1 0 L8 F9 P14
VDDC_7
VDDC_8
GND_34
GND_35
H8

AVDD_MOD_2 GND_16 L9
VDDP GND_36
H9
P8 F11 GND_37
H10
AVDD_NODIE AVDD_NODIE GND_17 AA10 H11
128M+256M 0 0 1 VDD33
K9 F13
AVDD5V_MHL GND_38
GND_39
H12

AVDD_PLL GND_18 GND_40

H13
R5 F15 GND_41
H14
AVDD_DMPLL AVDD3P3_DMPLL GND_19 H15
256M+256M 1 0 1 +1.10V_VDDC P11 F17
GND_42
GND_43
H16

AVDDL_MOD GND_20 GND_44

H17
C7 F19 GND_45
H18
+1.10V_VDDC DVDD_DDR_1 GND_21 GND_46
J7
M13 F21 GND_47
J8

1uFC260 DVDD_DDR_2 GND_22 GND_48

J9
R6 G8 GND_49
J10

DVDD_NODIE GND_23 GND_50

J11
A7 G9 J12

Country Option M12

DVDD_RX_1_1
DVDD_RX_1_2
GND_24
GND_25
G10
GND_51
GND_52
GND_53
GND_54
J13
J14
K8
B7 G11 GND_55
K10

DVDD_RX_2_1 GND_26 K11

MODEL_OPT_1 MODEL_OPT_5 M14 G12
GND_56
GND_57
L10

DVDD_RX_2_2 GND_27 GND_58

M5
N11 G13 GND_59
M7
+1.10V_VDDC VDDC_1 GND_28 GND_60
M8

TW 0 0 N12 G14 GND_61

VDDC_2 GND_29 GND_62

M10
N13 G15 GND_63
N4

VDDC_3 GND_30 GND_64

N5
N14 G16 GND_65
N6

EU 0 1 N15
VDDC_4 GND_31
G17
GND_66
N7
N8
GND_67
VDDC_5 GND_32 GND_68
N9
P12 G18 GND_69
N10

VDDC_6 GND_33 GND_70

CN 1 0 P13 H7 GND_71
P5

VDDC_7 GND_34 GND_72

P6
P14 H8 GND_73
P7

VDDC_8 GND_35 GND_74

P9
L9 H9 GND_75
P10

AJ 1 1 VDD33 VDDP GND_36 GND_76

P15
H10 GND_77
P16

GND_37 GND_78
P17
AA10 H11 GND_79
P18

AVDD5V_MHL GND_38 GND_80

R10
H12 GND_81
R11

GND_39 GND_82
R12
H13 GND_83
R13

M1A_256M GND_40 GND_84

R14
H14 GND_EFUSE
K7

IC101 M1A_128M M1A_256M_AVS+_CHINA M1A_128M_AVS+_CHINA GND_41

H15
LGE2134(256M) IC101-*1 IC101-*2 IC101-*3 GND_42
H16
LGE2133(128M) LGE2136(256M) LGE2135(128M) GND_43
H17 M1A_256M_AVS+_CHINA M1A_128M_AVS+_CHINA
GND_44 IC101-*2 IC101-*3
H18 LGE2136(256M) LGE2135(128M)
HDMI1_ARC M4 T6 M4 T6 M4 T6 GND_45
M4 T6 TU_CVBS W7
ARC0 CVBSOUT1
V5 W7
ARC0 CVBSOUT1
V5 W7
ARC0 CVBSOUT1
V5
J7
HDMI_ARC ARC0 CVBSOUT1 DTV/MNT_VOUT RXC0N CVBS0 RXC0N CVBS0 RXC0N CVBS0 GND_46 R4 U3 R4 U3
C212 1uF W7 V5 0.047uF C236 R244 33 TU_CVBS Y8 U5 Y8 U5 Y8 U5 J8 L11
AVDD_AU33 AUVRM
A6 L11
AVDD_AU33 AUVRM
A6
RXC0N CVBS0 TU_CVBS W8
RXC0P CVBS1
T5 W8
RXC0P CVBS1
T5 W8
RXC0P CVBS1
T5 GND_47 L13
AVDD_DDR0_CLK GND_1
A13 L13
AVDD_DDR0_CLK GND_1
A13
Y8 U5 0.047uF C237SCART/AV2 33 R245 SCART/AV2 +3.3V_NORMAL RXC1N CVBS2 RXC1N CVBS2 RXC1N CVBS2 J9 M11
AVDD_DDR1_CLK GND_2
A15 M11
AVDD_DDR1_CLK GND_2
A15
RXC0P CVBS1 SC1/AV2_CVBS_IN Y9
RXC1P VCOM
V4 Y9
RXC1P VCOM
V4 Y9
RXC1P VCOM
V4 GND_48 K13
AVDD_DDR0_CMD GND_3
A18 K13
AVDD_DDR0_CMD GND_3
A18
W8 T5 0.047uF C238 33 R246 AA9 AA9 AA9 J10 C5
AVDD_DDR1_CMD GND_4
B12 C5
AVDD_DDR1_CMD GND_4
B12
Used net when HDMI Switch used RXC1N CVBS2 COMP2_Y+/AV_CVBS_IN W9
RXC2N
E4 W9
RXC2N
E4 W9
RXC2N
E4 GND_49 K12
AVDD_DDR0_D_1 GND_5
B14 K12
AVDD_DDR0_D_1 GND_5
B14
Y9 V4 0.047uF C239 68 R247 C242 RXC2P I2S_OUT_BCK/GPIO165 RXC2P I2S_OUT_BCK/GPIO165 RXC2P I2S_OUT_BCK/GPIO165 J11 L12
AVDD_DDR0_D_2 GND_6
B16 L12
AVDD_DDR0_D_2 GND_6
B16

MN864778_RESET RXC1P VCOM 1000pF

AA7 F4 AA7 F4 AA7 F4 GND_50 C6
AVDD_DDR0_D_3 GND_7
B17 C6
AVDD_DDR0_D_3 GND_7
B17
AA9 R213 R210 I2S_I/F Y7
RXCCKN I2S_OUT_MCK/GPIO163
F7 Y7
RXCCKN I2S_OUT_MCK/GPIO163
F7 Y7
RXCCKN I2S_OUT_MCK/GPIO163
F7 J12 K14
AVDD_DDR1_D_1 GND_8
B19 K14
AVDD_DDR1_D_1 GND_8
B19
RXC2N 50V Close to MSTAR 10K 10K RXCCKP I2S_OUT_SD/GPIO166 RXCCKP I2S_OUT_SD/GPIO166 RXCCKP I2S_OUT_SD/GPIO166 GND_51 L14
AVDD_DDR1_D_2 GND_9
B20 L14
AVDD_DDR1_D_2 GND_9
B20
HDMI1_HPD_MN864788 W9 E4 OPT OPT OPT N2
CEC/GPIO6 I2S_OUT_WS/GPIO164
F5 N2
CEC/GPIO6 I2S_OUT_WS/GPIO164
F5 N2
CEC/GPIO6 I2S_OUT_WS/GPIO164
F5 J13 B5
AVDD_DDR1_D_3 GND_10
C9 B5
AVDD_DDR1_D_3 GND_10
C9
RXC2P I2S_OUT_BCK/GPIO165 AUD_SCK E3 E3 E3 GND_52 B6
AVDD_DRAM_1 GND_11
C10 B6
AVDD_DRAM_1 GND_11
C10
AA7 F4 DDCDA_CK/GPIO27 DDCDA_CK/GPIO27 DDCDA_CK/GPIO27 J14 R8
AVDD_DRAM_2 GND_12
C21 R8
AVDD_DRAM_2 GND_12
C21
HDMI2_HPD_MN864788 RXCCKN I2S_OUT_MCK/GPIO163 AUD_MASTER_CLK E2 C4 E2 C4 E2 C4
GND_53 AVDD_DVI_USB_MPLL_1 GND_13 AVDD_DVI_USB_MPLL_1 GND_13
DDCDA_DA/GPIO28 USB0_DM DDCDA_DA/GPIO28 USB0_DM DDCDA_DA/GPIO28 USB0_DM R9 D9 R9 D9
Y7 F7 W6 Y12 W6 Y12 W6 Y12 K8 L7
AVDD_DVI_USB_MPLL_2 GND_14
E20 L7
AVDD_DVI_USB_MPLL_2 GND_14
E20
RXCCKP I2S_OUT_SD/GPIO166 AUD_LRCH AA6
DDCDC_CK/GPIO31 USB1_DM
B4 AA6
DDCDC_CK/GPIO31 USB1_DM
B4 AA6
DDCDC_CK/GPIO31 USB1_DM
B4 GND_54 L8
AVDD_MOD_1 GND_15
F9 L8
AVDD_MOD_1 GND_15
F9
N2 F5 DDCDC_DA/GPIO32 USB0_DP DDCDC_DA/GPIO32 USB0_DP DDCDC_DA/GPIO32 USB0_DP K10 P8
AVDD_MOD_2 GND_16
F11 P8
AVDD_MOD_2 GND_16
F11
CEC_REMOTE_S7 CEC/GPIO6 I2S_OUT_WS/GPIO164 AUD_LRCK L4 AA12 L4 AA12 L4 AA12 GND_55 K9
AVDD_NODIE GND_17
F13 K9
AVDD_NODIE GND_17
F13
E3 R216 R218 HOTPLUGA/GPIO23 USB1_DP HOTPLUGA/GPIO23 USB1_DP HOTPLUGA/GPIO23 USB1_DP
Y6 Y6 Y6 K11 R5
AVDD_PLL GND_18
F15 R5
AVDD_PLL GND_18
F15
DDCDA_CK/GPIO27 10K 10K F1
HOTPLUGC/GPIO25
J2 F1
HOTPLUGC/GPIO25
J2 F1
HOTPLUGC/GPIO25
J2 GND_56 P11
AVDD3P3_DMPLL GND_19
F17 P11
AVDD3P3_DMPLL GND_19
F17
E2 C4 OPT OPT C208 RXA0N BIN0M RXA0N BIN0M RXA0N BIN0M L10 C7
AVDDL_MOD GND_20
F19 C7
AVDDL_MOD GND_20
F19
MN864778_RESET DDCDA_DA/GPIO28 USB0_DM WIFI_DM G3 J3 G3 J3 G3 J3 GND_57 M13
DVDD_DDR_1 GND_21
F21 M13
DVDD_DDR_1 GND_21
F21
W6 Y12 15pF G1
RXA0P BIN0P
K3 G1
RXA0P BIN0P
K3 G1
RXA0P BIN0P
K3 M5 R6
DVDD_DDR_2 GND_22
G8 R6
DVDD_DDR_2 GND_22
G8
URSA_RESET_READY DDCDC_CK/GPIO31 USB1_DM SIDE_USB1_DM 50V RXA1N GIN0M RXA1N GIN0M RXA1N GIN0M GND_58 A7
DVDD_NODIE GND_23
G9 A7
DVDD_NODIE GND_23
G9
R295 0 AA6 B4 G2 J1 G2 J1 G2 J1 M7 DVDD_RX_1_1 GND_24 DVDD_RX_1_1 GND_24

L_DIM_EN DDCDC_DA/GPIO32 USB0_DP WIFI_DP OPT H3

RXA1P GIN0P
K2 H3
RXA1P GIN0P
K2 H3
RXA1P GIN0P
K2 GND_59
M12
B7
DVDD_RX_1_2 GND_25
G10
G11
M12
B7
DVDD_RX_1_2 GND_25
G10
G11
L4 AA12 H2
RXA2N RIN0M
K1 H2
RXA2N RIN0M
K1 H2
RXA2N RIN0M
K1
M8 M14
DVDD_RX_2_1 GND_26
G12 M14
DVDD_RX_2_1 GND_26
G12
HDMI1_HPD_MN864788 HOTPLUGA/GPIO23 USB1_DP SIDE_USB1_DP RXA2P RIN0P RXA2P RIN0P RXA2P RIN0P GND_60 DVDD_RX_2_2 GND_27 DVDD_RX_2_2 GND_27
R296 OPT 0
N11 G13 N11 G13
Y6 F3 M6 F3 M6 F3 M6 M9 N12
VDDC_1 GND_28
G14 N12
VDDC_1 GND_28
G14
3D_EN HOTPLUGC/GPIO25 RXACKN HSYNC0 RXACKN HSYNC0 RXACKN HSYNC0 GND_61 VDDC_2 GND_29 VDDC_2 GND_29
Used net when WIFI used F2 L6 F2 L6 F2 L6 N13 G15 N13 G15
HDMI2_HPD_MN864788 F1 J2 EU RXACKP VSYNC0 RXACKP VSYNC0 RXACKP VSYNC0 M10 N14
VDDC_3 GND_30
G16 N14
VDDC_3 GND_30
G16
HDMI_RX0- RXA0N BIN0M C221 0.047uFEU R232 68 GND_62 N15
VDDC_4 GND_31
G17 N15
VDDC_4 GND_31
G17
G3 J3 EU WIFI_DM U4 L2 U4 L2 U4 L2 N4 P12
VDDC_5 GND_32
G18 P12
VDDC_5 GND_32
G18
HDMI_RX0+ RXA0P BIN0P C222 0.047uFEU R233 EU 33 SC1_B+/COMP1_Pb+ T4
EAR_OUTL BIN1M
L3 T4
EAR_OUTL BIN1M
L3 T4
EAR_OUTL BIN1M
L3 GND_63 P13
VDDC_6 GND_33
H7 P13
VDDC_6 GND_33
H7
G1 K3 EAR_OUTR BIN1P EAR_OUTR BIN1P EAR_OUTR BIN1P N5 P14
VDDC_7 GND_34
H8 P14
VDDC_7 GND_34
H8
HDMI_RX1- RXA1N GIN0M C223 0.047uFEU R234 68 WIFI_DP P2 M1 P2 M1 P2 M1 GND_64 L9
VDDC_8 GND_35
H9 L9
VDDC_8 GND_35
H9
G2 J1 EU R2
AUL1 GIN1M
M2 R2
AUL1 GIN1M
M2 R2
AUL1 GIN1M
M2 N6 VDDP GND_36
H10
VDDP GND_36
H10
HDMI_RX1+ RXA1P GIN0P C224 0.047uFEU R235 EU 33 SC1_G+/COMP1_Y+ AUL2 GIN1P AUL2 GIN1P AUL2 GIN1P GND_65 AA10
GND_37
H11 AA10
GND_37
H11
H3 K2 T1 N1 T1 N1 T1 N1 N7 AVDD5V_MHL GND_38 AVDD5V_MHL GND_38
AUL3 RIN1M AUL3 RIN1M AUL3 RIN1M H12 H12
HDMI_RX2- RXA2N RIN0M C225 0.047uFEU R236 EU 68 R3 N3 R3 N3 R3 N3 GND_66 GND_39
H13
GND_39
H13
H2 K1 Used net when TI Amp used R1
AUR1 RIN1P
M3 R1
AUR1 RIN1P
M3 R1
AUR1 RIN1P
M3
N8 GND_40
H14
GND_40
H14
HDMI_RX2+ RXA2P RIN0P C226 0.047uFEU R237 33 SC1_R+/COMP1_Pr+ AUR2 SOGIN1 AUR2 SOGIN1 AUR2 SOGIN1 GND_67 GND_41
H15
GND_41
H15
F3 M6 T3 T3 T3 N9 GND_42
H16
GND_42
H16
HDMI_CLK- RXACKN HSYNC0 SC1_ID AUD_MASTER_CLK U2
AUR3
U2
AUR3
U2
AUR3 GND_68 GND_43
H17
GND_43
H17
F2 L6 AUOUTL0 AUOUTL0 AUOUTL0 N10 GND_44
H18
GND_44
H18
HDMI_CLK+ RXACKP VSYNC0 SC1_FB V3
AUOUTR0
V3
AUOUTR0
V3
AUOUTR0 GND_69 GND_45
J7
GND_45
J7
T2 T2 T2 P4 GND_46
J8
GND_46
J8
AUVAG AUVAG AUVAG GND_70 GND_47 GND_47
H/P OUT U4 L2 P5 GND_48
J9
J10
GND_48
J9
J10
HP_LOUT EAR_OUTL BIN1M C227 0.047uF R238 68 GND_71 GND_49
J11
GND_49
J11
T4 L3 P6 GND_50
J12
GND_50
J12
HP_ROUT EAR_OUTR BIN1P C229 0.047uF R239 33 COMP2_Pb+ GND_72 GND_51
J13
GND_51
J13
P2 M1 P7 GND_52
J14
GND_52
J14
SC1/COMP1_L_IN 2.2uF C214 EU AUL1 GIN1M C230 0.047uF R240 68 GND_73 GND_53
K8
GND_53
K8
R2 M2 P9 GND_54
K10
GND_54
K10
AV2_L_IN C203 AV2 T1 2.2uF AUL2 GIN1P C231 0.047uF R241 33 COMP2_Y+/AV_CVBS_IN GND_74 GND_55
K11
GND_55
K11
N1 P10 GND_56
L10
GND_56
L10
COMP2_L_IN C211 2.2uF C216 AUL3 RIN1M C232 0.047uF R242 68 GND_75 GND_57
M5
GND_57
M5
1000pF R3 N3 P15 GND_58
M7
GND_58
M7
50V SC1/COMP1_R_IN 2.2uF C217 EU R1 AUR1 RIN1P C233 0.047uF R243 33 COMP2_Pr+ GND_76 GND_59
M8
GND_59
M8

ATV_1000P M3 P16 GND_60

M9
GND_60
M9
AV2_R_IN 2.2uF C206 AV2 T3 AUR2 SOGIN1 C234 1000pF GND_77 GND_61
M10
GND_61
M10

OPT P17 GND_62

N4
GND_62
N4
COMP2_R_IN C215 2.2uF C219 AUR3 GND_78 GND_63
N5
GND_63
N5
1000pF U2 P18 GND_64
N6
GND_64
N6
50V SCART1_Lout AUOUTL0 GND_79 GND_65
N7
GND_65
N7

ATV_1000P V3 R10 GND_66

N8
GND_66
N8
SCART1_Rout AUOUTR0 GND_80 GND_67
N9
GND_67
N9
AUDIO OUT T2 R11 GND_68
N10
GND_68
N10
AUVAG GND_81 GND_69
P4
GND_69
P4
C213 C220 R12 GND_70
P5
GND_70
P5
1uF 4.7uF GND_82 GND_71
P6
GND_71
P6
AUVRM R13 GND_72
P7
GND_72
P7

L214 GND_83 GND_73

P9
GND_73
P9

BLM18PG121SN1D R14 GND_74

P10
GND_74
P10
GND_84 GND_75
P15
GND_75
P15
K7 GND_76
P16
GND_76
P16
GND_EFUSE GND_77
P17
GND_77
P17
GND_78 GND_78
P18 P18
GND_79 GND_79
R10 R10
GND_80 GND_80
R11 R11
GND_81 GND_81
R12 R12
GND_82 GND_82
R13 R13
GND_83 GND_83
R14 R14
GND_84 GND_84
K7 K7
GND_EFUSE GND_EFUSE

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

+3.3V_NORMAL
R5606
100
AMP_RESET
1/16W L5602
L5601 C5629
R5615 10uH
4.7K 1000pF
BLM18PG121SN1D SPK_L+
50V
SP-7850_10
50V

AUD_SCK
+24V_AMP
22000pF

R5607
C5609

5.6
+24V +24V_AMP 1/10W R5609
C5622
C5604 0.1uF
C5603 C5615 50V 4.7K
[EP]GND

10uF C5630 390pF

L5600 0.1uF C5610 C5611 50V
VDD_IO
GND_IO

PGND1A

PVDD1A
PVDD1B

10V 0.1uF 4.7uF

UBW2012-121F 16V 10uF 50V
50V
CLK_I

RESET
BST1A

OUT1A

35V 3216
C5621
0.47uF
50V
C5601
AD

0.1uF C5616
390pF
50V 50V
C5623 R5610
R5608 0.1uF
50V 4.7K
SPEAKER_L
5.6
40
39
38
37
36
35
34
33
32
31

1/10W

L5603
NC_1 1 30 OUT1B 10uH
SPK_L-
SP-7850_10
VDD_PLL 2 29 PGND1B C5617
THERMAL 22000pF
NC_2 3 41 28 BST1B 50V
C5605
1uF
10V GND 4 27 VDR1
NC_3 5 IC5600 26 NC_5
C5606
1uF
10V
DVDD 6 NTP7515 25 AGND
SDATA EAN62886102 VDR2
AUD_LRCH 7 24
WCK 0x54 BST2A
C5618
1uF
C5619
1uF
AUD_LRCK 8 23 10V 10V

NC_4 9 DEV_NTP7515 22 PGND2A C5620

22000pF
R5604
AMP_SDA
100 SDA 10 21 OUT2A 50V

R5605
100
11
12
13
14
15
16
17
18
19
20

AMP_SCL
C5607 C5608
33pF 33pF
L5604
50V 50V 10uH
SCL
FAULT
MONITOR_0
MONITOR_1
MONITOR_2
BST2B
PGND2B
OUT2B
PVDD2B
PVDD2A

SPK_R+
SP-7850_10

+3.3V_NORMAL +24V_AMP
R5611
5.6
1/10W C5627 R5613
R5601 0.1uF 4.7K
10K C5631 C5624 C5626 50V
C5614 390pF 0.47uF
R5603 0.1uF 4.7uF 50V 50V
C5613 50V 50V SPEAKER_R
10uF 3216 C5625
C 100 390pF
35V 50V
R5600 C5602 C5628 R5614
B Q5600 C5612
AMP_MUTE 1000pF R5612 0.1uF 4.7K
10K MMBT3904(NXP) 50V 22000pF 5.6 50V
OPT E OPT 1/10W L5605
50V
I2S_AMP

10uH
SPK_R-
SP-7850_10

OPT
R5602
0
POWER_DET
I2S_AMP

WAFER-ANGLE

SPK_L+
4

SPK_L-
3

SPK_R+
2

SPK_R-
1

P5600

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

Copyright ⓒ 2015 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Downloaded from www.Manualslib.com manuals search engine
Only for training and service purposes
L14 TUNER_EU T/C_T2/C/S2_CHINA
TU_I2C Multi option
TU3705 TU3704 TU3706 TU3703 TU3701
TU_I2C_FILTER
TDJK-T301F TDJM-K301F TDJM-G305D TDJM-C401D TDJM-G301D TU_ATSC
C3705-*1
TU_ATSC R3738-*1
R3716-*1 MLG1005SR27JT
1.8K
18pF

TUNER_CSA_H/NIM TUNER_CSA_T2 TUNER_AJ/JA_T2 TUNER_CHINA TUNER_T2/C/S2 +3.3V_LNA TU_ATSC

TU_ATSC
R3717-*1 TU_I2C_FILTER
1.8K R3739-*1
C3707-*1 MLG1005SR27JT
18pF
+3.3V +3.3V +3.3V +3.3V +3.3V
1 1 1 1 1
C3708 C3714
0.1uF
NC NC_1 NC_1 NC_1 NC_1 100pF
50V 16V
2 2 2 2 2 +3.3V_TU
IF_AGC_CSA
R3714-*1 100
DIF_AGC NC_2 NC_2 NC_2 AIF_AGC should be guarded by ground
3 3 3 3 3 C3703 R3714 IF_AGC_MAIN TU_NON_ATSC TU_NON_ATSC
0.1uF 0
16V IF_AGC_NON_CSA R3716 R3717
SCL_RF SCL_RF SCL_RF SCL_RF SCL_RF IF_AGC TU_I2C_NON_FILTER
R3738 33
1K 1K
4 4 4 4 4 TU_SCL

SDA_RF SDA_RF SDA_RF SDA_RF SDA_RF TU_I2C_NON_FILTER

5 5 5 5 5 C3705 C3707
R3739 33
TU_SDA
TU_NON_ATSC_NON_CHINA C3710 C3711 R3726 OPT 0
20pF 20pF 20pF 20pF
DIF[P] NC_3 NC_3 NC_3 AIF[P] R3709
10
TU_NON_ATSC TU_NON_ATSC
TU_NON_ATSC TU_NON_ATSC +3.3V_TU
6 6 6 6 6 IF_P_MSTAR
TU_ATSC
R3709-*1 TU_SIF TU_SIF
DIF[N] NC_4 NC_4 NC_4 AIF[N] R3725
470 R3728
7 7 7 7 7 0
IF_N_MSTAR
82
TU_SIF
TU_NON_ATSC_NON_CHINA
R3710
SIF SIF SIF SIF SIF 10 C3726
E
8 8 8 8 8 Q3700
TU_ATSC 0.1uF R3724 B 2N3906S-RTK
R3710-*1 4.7K
TU_SIF_TR_KEC(MULTI)
CVBS CVBS CVBS CVBS CVBS 16V
TU_SIF
TU_SIF C
9 9 9 9 9 0

close to TUNER
NC_5 NC_5 NC_5 NC_2
10 10 10 10 CHINA
AR3700-*1 47
E
Q3700-*1
A1 B1 +3.3V_RF +3.3V_RF +3.3V_RF +3.3V_RF +3.3V_TU +3.3V_TU B MMBT3906(NXP)
TU_SIF_TR_NXP(MULTI)
A1 B1 11 11 11 11 T2_OR_CHINA
C3718
T2_OR_CHINA
C3722 TU_CVBS TU_CVBS
C
AR3700
100pF 0.1uF 0 R3732 R3735
47 ERROR ERROR ERROR ERROR 50V 16V 1/16W
220 220
12 12 12 12
TU_GND_A

TU_GND_B

FE_TS_ERR CHINA TU_CVBS

AR3701-*1 47 E
FE_TS_CLK
GND_1 GND_1 GND_1 GND_1 FE_TS_SYNC Q3701
SHIELD 13 13 13 13 FE_TS_VAL B 2N3906S-RTK
C TU_CVBS_TR_KEC(MULTI)
T2
MCLK MCLK MCLK MCLK
14 14 14 14 R3731 OPT 0
CHINA
AR3702-*1 47 E TU_CVBS_TR_NXP(MULTI)
SYNC SYNC SYNC SYNC Q3701-*1
15 15 15 15 B MMBT3906(NXP)
TU3700 C
VAILD VAILD VAILD VALID
TDJH-G301D 16 16 16 16
AR3701
0 FE_TS_DATA[0-7]
D0 D0 D0 D0 1/16W
TUNER_T/C 17 17 17 17 FE_TS_DATA[0]
FE_TS_DATA[1]

+3.3V D1 D1 D1 D1 FE_TS_DATA[2]

1 18 18 18 18 FE_TS_DATA[3]

T2
NC_1 D2 D2 D2 D2
2 19 19 19 19
IF_AGC D3 D3 D3 D3
3 20 20 20 20
AR3702
0
SCL_RF D4 D4 D4 D4 1/16W

4 21 21 21 21 FE_TS_DATA[4]
+3.3V_LNA +3.3V_TU +3.3V_NORMAL
FE_TS_DATA[5]

SDA_RF D5 D5 D5 D5 FE_TS_DATA[6]

5 22 22 22 22 FE_TS_DATA[7]

T2 L3701 L3704
IF[P] D6 D6 D6 D6 UBW2012-121F UBW2012-121F

6 23 23 23 23 C3739 C3706 C3730 C3731 C3733 C3738

22uF 0.1uF 22uF 0.1uF 22uF 0.1uF
IF[N] D7 D7 D7 D7 10V 16V 10V 16V 10V 16V

7 24 24 24 24
T2_OR_CHINA
SIF RESET_DEMOD RESET_DEMOD RESET_DEMOD RESET_DEMOD R3719 IC3701
AP7361-Y-13
8 25 25 25 25 10
DEMOD_RESET
+3.3V_TU +1.2V_DEMOD
T2_OR_CHINA T2_OR_CHINA
+3.3V_DEMOD R3723
CVBS +3.3V_DEMOD +3.3V_DEMOD +3.3V_DEMOD +3.3V_DEMODC3716
0.1uF 3.3K EN
1 T2_OR_CHINA 5
OUT

9 26 26 26 26 16V
T2_OR_CHINA
T2_OR_CHINA C3725
C3721 C3723 1uF GND T2_OR_CHINA
SCL_DEMOD SCL_DEMOD SCL_DEMOD SCL_DEMOD T2_OR_CHINA 100pF 0.1uF 10V 2 T2_OR_CHINA R3737
1
27 27 27 27 R3711
C3702
22
DEMOD_SCL
50V 16V
T2_OR_CHINA R3733
12K T2_OR_CHINA
ADJ/NC IN 1% C3737
20pF 3 4 R1
A1 B1 +1.2V_DEMOD +1.2V_DEMOD +1.2V_DEMOD +1.2V_DEMOD 50V
T2_OR_CHINA
+1.2V_DEMOD 10uF
10V
A1 B1 28 28 28 28 C3713 C3729 T2_OR_CHINA
100pF 0.1uF C3732
T2 50V 16V
47 NC_6 NC_6 NC_6 NC_3 R3707 T2_OR_CHINAT2_OR_CHINA
0.1uF
16V
29 29 29 29 0
LNB_TX
TU_GND_A

TU_GND_B

T2_OR_CHINA
SDA_DEMOD SDA_DEMOD SDA_DEMOD SDA_DEMOD T2_OR_CHINA
R3712 22
R3734

SHIELD 30 30 30 30 C3704 DEMOD_SDA

22K
1%
20pF R2
50V
LNB T2_OR_CHINA Vo=0.8*(1+R1/R2)
31 C3709 LNB_OUT
0.1uF
50V GND seperation for CHINA tuner
A1 B1 A1 B1 A1 B1 GND
TU_GND_A

T2_OR_CHINA TU_GND_B
A1 B1 A1 B1 A1 B1 32
TU_KR/US/EU/AJ

TU_KR/US/EU/AJ

TU_KR/US/EU/AJ
TU_KR/US/EU/AJ

TU3700-*1
47 47 47 TU_GND_B
C3701
TDJH-H301F
TU_GND_A

TU_GND_B
TU_GND_A

TU_GND_B

1000pF
R3708

R3713

R3715

R3718

R3720

R3721

C3712
1000pF 630V
TUNER_NTSC
A1 B1 630V TU_GND_B
0

+3.3V CHINA R3740

1 SHIELD SHIELD SHIELD A1 B1 0
NC_1
2
DIF_AGC 47
3
TU_GND_A

TU_GND_B

SCL_RF +3.3V_TU +3.3V_DEMOD

4
T2_OR_CHINA
SDA_RF L3702
5 SHIELD BLM18PG121SN1D
DIF[P]
6
DIF[N] T2_OR_CHINA T2_OR_CHINA
7 T2_OR_CHINA
C3724 C3734 C3727
SIF 0.1uF 10uF 0.1uF
8 16V
10V 16V
CVBS
9

ERROR & VALID PIN

A1 B1
A1 B1 T2_OR_CHINA
47 R3736
FE_TS_VAL 0
FE_TS_VAL_ERR
SHIELD FE_TS_ERR
GPIO must be added.

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

C2106 C2111 C2120 C2128 C2134 C2139 C2143 C2145 C13314 C13315
10uF 10uF 10uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10uF
10V 10V 10V 10V 16V 16V 16V 16V 16V 10V

RXB2- AVDD_PLL 4st Layer

Close to Chip side
L2101
RXB2+ BLM18PG121SN1D

RXB4-

RXB4+
C13317 C2109 C13302 C2151
RXA2- 10uF 0.1uF 0.1uF 10uF
10V 16V 16V 10V
RXA2+

RXA4-

RXA4+
IC2500
LGE7411(URSA9)
IC2500 Close to Chip side
AG2 LGE7411(URSA9) AVDD_MOD
RXB0-
AG1
RB0N 4th Layer
RXB0+ RB0P L2102
AH3 BLM18PG121SN1D
RXB1- RB1N
AH1
RXB1+ RB1P
AH2
RXB2- RB2N
AJ3
RXB2+ RB2P C13316 C2110 C2119 C2127 C2133 C2138 C2142 C13306
AJ2
RXBCK- RBCKN 10uF 10uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
AK2 10V
RXBCK+
AK1
RBCKP
AM17 10V 10V 16V 16V 16V 16V 16V
RXB3- RB3N VX1_0-
AL1 AK17
RXB3+ RB3P VX1_0+
AM2 AL18
RXB4-
AL2
RB4N VX1_1-
AK18 D1
RXB4+ RB4P VX1_1+
AM19
HDMI_0_CLK+ HDMI_RXCP_0
VX1_2-
D3
AL19 HDMI_0_CLK- HDMI_RXCN_0
RXA0-
AK3
RC0N
VX1_2+
VX1_3-
AL20
HDMI_0_RX0+
E3
HDMI_RX0P_0
Close to Chip side
AL3 AM20 D2
RXA0+ RC0P VX1_3+
AK4 AK22 0.1uF C13008 TXDBN7_L HDMI_0_RX0- HDMI_RX0N_0
RXA1- AL4
RC1N VX1_4-
AL21 F3
0.1uF C13009 TXDBP7_L
RXA1+ AM4
RC1P VX1_4+
AK23
HDMI_0_RX1+ HDMI_RX1P_0 VDDC VDDC 4th Layer
RXA2- RC2N VX1_5-
0.1uF C13010 TXDBN6_L E2
AK5 AM22 0.1uF C13011 TXDBP6_L HDMI_0_RX1- HDMI_RX1N_0
RXA2+ AM5
RC2P VX1_5+
AK24 F1
0.1uF C13012 TXDBN5_L
RXACK- AL5
RCCKN VX1_6-
AL23
HDMI_0_RX2+ HDMI_RX2P_0
RXACK+ RCCKP VX1_6+
0.1uF C13013 TXDBP5_L F2
RXA3-
AK6
RC3N VX1_7-
AL25 0.1uF C13014 TXDBN4_L HDMI_0_RX2- HDMI_RX2N_0
AL6 AK25 0.1uF C13015 TXDBP4_L
RXA3+
AK7
RC3P VX1_7+
AM26 C2100 C2101 C2114 C2122 C2132 C2137 C2144 C2146 C2147 C2148 C2149 C13307 C2150 C2107
0.1uF C13016 TXDBN3_L
RXA4- AL7
RC4N VX1_8-
AK26 10uF 10uF 10uF 10uF 10uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10uF 10uF
0.1uF C13017 TXDBP3_L
RXA4+ RC4P VX1_8+ 10V
AL27 0.1uF C13018 TXDBN2_L 10V 10V 10V 10V 10V 10V 16V 16V 16V 16V 16V 16V 10V
VX1_9-
AK27 0.1uF C13019 TXDBP2_L
VX1_9+
AM7 AM28 0.1uF C13020 TXDBN1_L
RD0N VX1_10-
AK8 AL28 0.1uF C13021 TXDBP1_L
RD0P VX1_10+
AM8 AL29 0.1uF C13022 TXDBN0_L AVDDL_MOD
RD1N VX1_11-
AL8 AM29 0.1uF C13023 TXDBP0_L
AK9
AL9
RD1P
RD2N
VX1_11+
VX1_12-
AM31
AL30
0.1uF
0.1uF
C13024
C13025
TXDAN7_L
L2104
4th Layer
Close to Chip side
TXDAP7_L
RD2P VX1_12+ BLM18PG121SN1D
AK10 AL32 0.1uF C13026 TXDAN6_L
AL10
RDCKN VX1_13-
AL31 G1
0.1uF C13027 TXDAP6_L
AM10
RDCKP VX1_13+
AK31
HDMI_1_CLK+ HDMI_RXCP_1
RD3N VX1_14-
0.1uF C13028 TXDAN5_L G3 C2115 C2123 C13311 C13305 C2154
AK11 AK32 0.1uF C13029 TXDAP5_L HDMI_1_CLK- HDMI_RXCN_1 0.1uF 0.1uF 10uF 10uF
AM11
RD3P VX1_14+
AJ30 H3 0.1uF
0.1uF C13030 TXDAN4_L 16V
AL11
RD4N VX1_15-
AJ31
HDMI_1_RX0+ HDMI_RX0P_1 16V 10V 16V 10V
RD4P VX1_15+
0.1uF C13031 TXDAP4_L G2
AH30 0.1uF C13064 TXDAN3_L HDMI_1_RX0- HDMI_RX0N_1
VX1_16-
AH32 J3
0.1uF C13065 TXDAP3_L
AK12
VX1_16+
AG30
HDMI_1_RX1+ HDMI_RX1P_1
RE0N VX1_17-
0.1uF C13066 TXDAN2_L H2
AL12
AK13
RE0P VX1_17+
AG31
AE31
0.1uF
0.1uF
C13067
C13068
TXDAP2_L
TXDAN1_L
HDMI_1_RX1-
J1
HDMI_RX1N_1
AVDDL_DRV
Close to Chip side
AL13
RE1N VX1_18-
AF30
HDMI_1_RX2+ HDMI_RX2P_1
RE1P VX1_18+
0.1uF C13069 TXDAP1_L J2 4th Layer
AM13
RE2N VX1_19-
AD32 0.1uF C13070 TXDAN0_L HDMI_1_RX2- HDMI_RX2N_1
AK14 AE30 L2105
0.1uF C13071 TXDAP0_L BLM18PG121SN1D
RE2P VX1_19+
AM14
RECKN
AL14
RECKP
AK15 AH29 C2116 C2124 C13310 C13304 C2153
RE3N VX1_HTDPN HTPDAn
AL15
RE3P VX1_LOCKN
AG29 0.1uF 0.1uF 10uF 0.1uF 10uF
AK16 16V
RE4N R1938
16V 10V 16V 10V
AL16 10K
RE4P
URSA_TX_HTPD_pulldown

AE2
VBY1_RXM[0]
HDMI_TX_DDC_CLK TP1901
DVDD_DDR Close to Chip side
AE1 HDMI_TX_DDC_SDA TP1902 4th Layer
VBY1_RXP[0]
AD2
VBY1_RXM[1] LOCKAn L2106
AE3 BLM18PG121SN1D
VBY1_RXP[1] R1996 22 N4
AC2
VBY1_RXM[2] HDMI_TX_DDC_CLK HDMITX_SCL
AD3 R1997 22 M4
VBY1_RXP[2] HDMI_TX_DDC_SDA C2117 C2125 C13312 C2152 C13303 C13313
AC3 HDMITX_SDA
AC1
VBY1_RXM[3] +3.3V_U_NORMAL N1 0.1uF 0.1uF 4.7uF 10uF 0.1uF 4.7uF
HDMI OUTPUT to L14

VBY1_RXP[3] HDMI_CLK+ HDMI_TXCP 16V 10V 10V 16V 10V

P1 16V
AB2 HDMI_CLK- HDMI_TXCN
AB1
VBY1_RXM[4] N3
AA2
VBY1_RXP[4] HDMI_RX0+ HDMI_TX0P
VBY1_RXM[5]
N2
AB3 HDMI_RX0- HDMI_TX0N
R1952

Y2
VBY1_RXP[5] M3
Close to Chip side
22

AA3
VBY1_RXM[6] HDMI_RX1+ HDMI_TX1P
VBY1_RXP[6]
M2
19-21/R6C-FR1S1L/3T

Y3 HDMI_RX1- HDMI_TX1N AVDDL_HDMI_TX_RX

VBY1_RXM[7] L1
LED_EVERLIGHT

Y1
HDMI_RX2+ HDMI_TX2P
SML-512UW

LD1900-*1

VBY1_RXP[7]
LED_RHOM
LD1900

L2 L2107
W2
VBY1_RXM[8]
HDMI_RX2- HDMI_TX2N BLM18PG121SN1D
W1 R1939
VBY1_RXP[8] 10K
V2
W3
VBY1_RXM[9] OPT C2118 C2126 C2131 C13309
R1943

VBY1_RXP[9] 0.1uF 0.1uF

U2 0.1uF 10uF
220

VBY1_RXM[10]
V3 16V 16V 16V 10V
VBY1_RXP[10]
U3
VBY1_RXM[11]
U1
VBY1_RXP[11] E Q1901
2N3906S-RTK
GND Connection at Vx1 41pin wafer
B PNP_KEC(MULTI)
AVDDL_LVDSRX
C R12900 0
GND_Vx1_2
E Q1901-*1 OPT L13300
(pin 8)
MMBT3906(NXP) BLM18PG121SN1D

B PNP_NXP(MULTI)

C C13300 C13301 C13308

0.1uF 0.1uF 10uF
R12901 0 16V 16V 10V
GND_Vx1
OPT
(pin 5,11,14)

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

Copyright ⓒ 2015 LG Electronics. Inc. All right reserved. LGE Internal Use Only
Downloaded
Only for training andfrom www.Manualslib.com manuals search engine
service purposes
[51P Vx1
output wafer]
[41P Vx1
DEV_51pin_Wafer
P13000
output wafer]
SP14-11592-01-51Pin
+3.3V_U_NORMAL +3.3V_U_NORMAL DEV_41pin_Wafer
P13001
51
1 SP14-11592-01-41Pin
50
2 TXDAP7_L
49
3 TXDAN7_L
1
48 R13017 R13024
4
+1.8V R13008 10K +1.8V R13022 10K 2
47
5 10K LOCKAn 10K HTPDAn
TXDAP6_L
3
46 R13014 C R13023 C
6 TXDAN6_L 10K 10K
B Q13002 B Q13006 4
45
7 R13025 2N3904S R13020 2N3904S
5 GND_Vx1
44 10K NPN_KEC(MULTI) 10K NPN_KEC(MULTI)
8 TXDAP5_L E E
6 TXDBP11_L
43
9 C C C C
TXDAN5_L R13002 R13021 7 TXDBN11_L
42 100 B Q13001 B Q13002-*1 100 B Q13003 B Q13006-*1
10
2N3904S MMBT3904(NXP) 2N3904S MMBT3904(NXP) 8
41 LOCKn_IN HTPDn_IN GND_Vx1_2
11 NPN_KEC(MULTI) NPN_NXP(MULTI) NPN_KEC(MULTI) NPN_NXP(MULTI)
TXDAP4_L E E E E
9 TXDBP10_L
40
12 C
TXDAN4_L
10 TXDBN10_L
39 C B Q13003-*1
13
MMBT3904(NXP) 11
38 B Q13001-*1
14 TXDAP3_L MMBT3904(NXP) E NPN_NXP(MULTI)
NPN_NXP(MULTI) 12 TXDBP9_L
37
15 E
TXDAN3_L
13 TXDBN9_L
36
16
14
35
17 TXDAP2_L
15 TXDBP8_L
34
18 TXDAN2_L +3.3V_U_NORMAL
L/D_EN(Pin30) 16 TXDBN8_L
33
19 - T-Con L/D Function
R13034 17
32 10K HIGH : Enable
20 TXDAP1_L LOW or NC : Disable
OPT 18
31 +3.3V_U_NORMAL *LGD_120Hz: T240 module (UB98/95,D9) TXDBP7_L
G

21 R13037 0
TXDAN1_L L_DIM_EN 19 TXDBN7_L
30 Non_AUO_Module
22 R13003
20
S

29 10K R13007
23 TXDAP0_L OPT 10K Q13004-*1
Non_AUO_Module 2N7002K 21 TXDBP6_L
28 +3.3V_U_NORMAL TCON_FET_DIODES(MULTI)
24 TXDAN0_L
22 TXDBN6_L
27 TCON_I2C_EN
25
R13004 R13018 23
G

26 10K 4.7K
26 LOCKn_IN LGD_Module
OPT 24
25 R13013 0 R13061 0 TXDBP5_L
27 HTPDn_IN URSA_SCL
S

OPT 25 TXDBN5_L
24 R13011 0 Q13004
28 2N7002KA R1503 0 26
23 Non_INX_Module TCON_FET_KEC(MULTI)
29 R13055 IR_SCL
Non_AUO_Module 27
22 TXDBP4_L
30 33 OPT
L13001
OPT *Pin31(BIT_SEL) 28 TXDBN4_L
21 OPT +3.3V_U_NORMAL
31 HIGH or NC : 10Bit
R13033 10K LOW : 8Bit 29
20 TCON_I2C_EN
32
R13019 30
19 TXDBP3_L
G

33 4.7K
OPT R13062 0 31 TXDBN3_L
18 R13012 0
34 URSA_SDA
32
S

17 R13006 0 *Pin35(PCID) OPT

35 High:PCID enable Q13005
3D_EN 2N7002KA R1506 0 33 TXDBP2_L
16 OPT Low or NC : PCID diable TCON_FET_KEC(MULTI)
36 IR_SDA
R13059 Non_AUO_Module 34
15 TXDBN2_L
37
33 OPT 35
14 R13005 0 +3.3V_U_NORMAL
38
G

LGD_120Hz 36 TXDBP1_L
13
39
R1501 0 37 TXDBN1_L
12 R13044
S

40 PWM_DIM 10K
Q13005-*1 38
11 LGD_60Hz OPT 2N7002K
41 TCON_FET_DIODES(MULTI)
R13016 0 39
10 Data_Format_1 TXDBP0_L
42
LGD_120Hz 40
9 TXDBN0_L
43
R13009 R13010 41
8 0 0
44 R13045
7 10K Data Input Format[1:0] 42
45 LGD_120Hz
6 *Mode 3 (4 Division)
46 - Data Format 0(Pin37) = Low
5 Data Format 1(Pin36) = High
47 +3.3V_U_NORMAL
4 *Mode 2 (2 Division)
48 - Data Format 0(Pin37) = High
3 Data Format 1(Pin36) = Low
49 R13040
2 10K
50 OPT
PANEL_VCC
1
51 R13015 0
Data_Format_0
L13000 LGD_120Hz
52 MLB-201209-0120P-N2
TCON_PWR_Vx1_Wafer R1502 0
PWM_DIM_SYNC R13041
. C13032 C13033 LGD_60Hz 10K
Not Used Net (UB85/95/UC89)
10uF 10uF LGD_120Hz
16V 16V
TXDBP11_L

TXDBN11_L

TXDBP10_L

TXDBN10_L

TXDBP9_L
+1.8V
+3.3V_U_NORMAL TXDBN9_L

TXDBP8_L

IC13000 TXDBN8_L
AZ1117EH-ADJTRG1
GND_Vx1
IN OUT
GND_Vx1_2
ADJ/GND
75
R13036

C13034 C13035
33
R13042

10uF 10uF
10V 10V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

F14 H27 B_DDR3_A[0]

B_DDR3_A[0-15] DDR PHY VREF
A_DDR3_A[0] A_DDR3_A0 B_DDR3_A0
B13 G31 B_DDR3_A[1] +1.5V_U_DDR +1.5V_U_DDR
A_DDR3_A[1] A_DDR3_A1 B_DDR3_A1 U_MVREFCA_A0 U_MVREFCA_A1
E13 G28 B_DDR3_A[2]
A_DDR3_A[2] A_DDR3_A2 B_DDR3_A2
D13 G29 B_DDR3_A[3]
A_DDR3_A[3] A_DDR3_A3 B_DDR3_A3 DDR_VTT_URSA_1
C14 H30 B_DDR3_A[4] URSA9_DDR_SAMSUNG
A_DDR3_A[4] A_DDR3_A4 B_DDR3_A4 R13110 R13120 URSA9_DDR_SAMSUNG
F13 G27 B_DDR3_A[5] 1K
A_DDR3_A[5] A_DDR3_A5 B_DDR3_A5 1%
1K IC2600
A_DDR3_A[6]
C13 G30 B_DDR3_A[6] 1%
K4B1G1646G-BCMA AR13100 AR13102 AR13104 AR13106 AR13108 AR13110 AR13112
IC2700
A_DDR3_A6 B_DDR3_A6
B10 D31 B_DDR3_A[7] U_MVREFCA_A0 100 100 100 100 100 100 100 K4B1G1646G-BCMA
A_DDR3_A[7] A_DDR3_A7 B_DDR3_A7 U_MVREFCA_A1
A12 F32 B_DDR3_A[8]
A_DDR3_A[8] A_DDR3_A8 B_DDR3_A8 R13111 C13202 C13210 R13121 C13222 C13230
C10 D30 B_DDR3_A[9]
1K
A_DDR3_A[9] A_DDR3_A9 B_DDR3_A9 0.1uF 1000pF 1K 0.1uF 1000pF N3 M8
A14 H32 B_DDR3_A[10] 1% 1% A_DDR3_A[0] A0 VREFCA N3 M8
A_DDR3_A[10] A_DDR3_A10 B_DDR3_A10 P7 A_DDR3_A[0] A0 VREFCA
B12 F31 B_DDR3_A[11] A_DDR3_A[1] A1 P7
A_DDR3_A[11] A_DDR3_A11 B_DDR3_A11 P3 A_DDR3_A[1] A1
F15 J27 B_DDR3_A[12] A_DDR3_A[2] A2 P3
A_DDR3_A[12] A_DDR3_A12 B_DDR3_A12 N2 H1 A_DDR3_A[2] A2
C11 E30 B_DDR3_A[13] A_DDR3_A[3] A3 VREFDQ N2 H1
A_DDR3_A[13] A_DDR3_A13 B_DDR3_A13 P8 A_DDR3_A[3] A3 VREFDQ
C12 F30 B_DDR3_A[14] A_DDR3_A[4] A4 P8
A_DDR3_A[14] A_DDR3_A14 B_DDR3_A14 P2 A_DDR3_A[4] A4
D17 L29 B_DDR3_A[15] A_DDR3_A[5] A5 P2
A_DDR3_A[15] A_DDR3_A15 B_DDR3_A15 R8 L8 R13126 240
A_DDR3_A[5] A5
E14 H28 A_DDR3_A[6] A6 ZQ R8 L8 R13134 240
A_DDR3_BA[0] A_DDR3_BA0 B_DDR3_BA0 B_DDR3_BA[0] R2 1%
A_DDR3_A[6] A6 ZQ
B14 H31 A_DDR3_A[7] A7 R2 1% +1.5V_U_DDR
T8 +1.5V_U_DDR A_DDR3_A[7]
A_DDR3_BA[1] A_DDR3_BA1 B_DDR3_BA1 B_DDR3_BA[1] A_DDR3_A[8] A7
E15 J28 A8 T8
A_DDR3_BA[2] A_DDR3_BA2 B_DDR3_BA2 B_DDR3_BA[2] R3 B2 A_DDR3_A[8] A8
A_DDR3_A[9] A9 VDD_1 R3 B2
L7 D9 A_DDR3_A[9] A9 VDD_1
E17 L28 A_DDR3_A[10] A10/AP VDD_2 L7 D9
A_DDR3_RASZ A_DDR3_RASZ B_DDR3_RASZ B_DDR3_RASZ R7 G7 A_DDR3_A[10] A10/AP VDD_2
C17 L30 A_DDR3_A[11] A11 VDD_3 R7 G7
A_DDR3_CASZ A_DDR3_CASZ B_DDR3_CASZ B_DDR3_CASZ N7 K2 A_DDR3_A[11] A11 VDD_3
C16 K30 A_DDR3_A[12] A12/BC VDD_4 N7 K2
A_DDR3_WEZ A_DDR3_WEZ B_DDR3_WEZ B_DDR3_WEZ T3 K8 A_DDR3_A[12] A12/BC VDD_4
F17 L27 A_DDR3_A[13] A13 VDD_5 T3 K8
A_DDR3_ODT A_DDR3_ODT B_DDR3_ODT B_DDR3_ODT N1 A_DDR3_A[13] A13 VDD_5
C15 J30 VDD_6 N1
A_DDR3_CKE A_DDR3_CKE B_DDR3_CKE B_DDR3_CKE M7 N9 A_DDR3_A[14] VDD_6
B11 E31 A_DDR3_A[15] NC_5 VDD_7 M7 N9
A_DDR3_RESET A_DDR3_RESETB B_DDR3_RESETB B_DDR3_RESET R1 A_DDR3_A[15] NC_5 VDD_7
B16 K31 VDD_8 R1
A_DDR3_MCLK A_DDR3_MCLK B_DDR3_MCLK B_DDR3_MCLK +1.5V_U_DDR M2 R9 VDD_8
A16 K32 A_DDR3_BA[0] BA0 VDD_9 M2 R9
A_DDR3_MCLKZ B_DDR3_MCLKZ +1.5V_U_DDR N8
A_DDR3_MCLKZ B_DDR3_MCLKZ U_MVREFCA_B0 U_MVREFCA_B1 A_DDR3_BA[0] BA0 VDD_9
C9 C30 A_DDR3_BA[1] BA1 +1.5V_U_DDR N8
M3 +1.5V_U_DDR
R13123R13122

A_DDR3_CSB1 A_DDR3_CSB1 B_DDR3_CSB1 B_DDR3_CSB1 A_DDR3_MCLK A_DDR3_BA[1] BA1

A9 C32 A_DDR3_BA[2] BA2 M3
56

A_DDR3_CSB2 A_DDR3_CSB2 B_DDR3_CSB2 B_DDR3_CSB2 C13233 A1 A_DDR3_BA[2] BA2

VDDQ_1 A1
A_DDR3_DQ[0-15] B_DDR3_DQ[0-15] R13108 0.01uF J7 A8 VDDQ_1
R13118
56

A_DDR3_DQ[0] D23 U29 B_DDR3_DQ[0] CK VDDQ_2 J7 A8

1K 1K K7 C1
A_DDR3_DQ0 B_DDR3_DQ0 A_DDR3_MCLK CK VDDQ_2
A_DDR3_DQ[1] A19 N32 B_DDR3_DQ[1] 1% 1% A_DDR3_MCLKZ CK VDDQ_3 K7 C1
A_DDR3_DQ1 B_DDR3_DQ1 K9 C9 A_DDR3_MCLKZ CK VDDQ_3
A_DDR3_DQ[2] E22 T28 B_DDR3_DQ[2] A_DDR3_CKE CKE VDDQ_4 K9 C9
A_DDR3_DQ2 B_DDR3_DQ2 D2 A_DDR3_CKE CKE VDDQ_4
A_DDR3_DQ[3] B18 M31 B_DDR3_DQ[3] VDDQ_5 D2
A_DDR3_DQ3 B_DDR3_DQ3 L2 E9 VDDQ_5
A_DDR3_DQ[4] C23 U30 B_DDR3_DQ[4] R13109 C13201 C13209 R13119 C13221 C13229 A_DDR3_CSB1 CS VDDQ_6 L2 E9
A_DDR3_DQ4 B_DDR3_DQ4 1K 0.1uF 1000pF 1K K1 F1 A_DDR3_CSB2 CS VDDQ_6
A_DDR3_DQ[5] C18 M30 B_DDR3_DQ[5] 0.1uF 1000pF A_DDR3_ODT ODT VDDQ_7 K1 F1
1% 1% J3 H2
A_DDR3_DQ5 B_DDR3_DQ5 A_DDR3_ODT ODT VDDQ_7
A_DDR3_DQ[6] B22 T31 B_DDR3_DQ[6] A_DDR3_RASZ RAS VDDQ_8 J3 H2
A_DDR3_DQ6 B_DDR3_DQ6 K3 H9 A_DDR3_RASZ RAS VDDQ_8
A_DDR3_DQ[7] A18 M32 B_DDR3_DQ[7] A_DDR3_CASZ CAS VDDQ_9 K3 H9
A_DDR3_DQ7 B_DDR3_DQ7 L3 A_DDR3_CASZ CAS VDDQ_9
A_DDR3_DQ[8] E19 N28 B_DDR3_DQ[8] A_DDR3_WEZ WE L3
A_DDR3_DQ8 B_DDR3_DQ8 J1 A_DDR3_WEZ WE
A_DDR3_DQ[9] B21 R31 B_DDR3_DQ[9] NC_1 J1
A_DDR3_DQ9 B_DDR3_DQ9 T2 J9 NC_1
A_DDR3_DQ[10] F18 M27 B_DDR3_DQ[10] A_DDR3_RESET RESET NC_2 T2 J9
A_DDR3_DQ10 B_DDR3_DQ10 L1 A_DDR3_RESET RESET NC_2
A_DDR3_DQ[11] C22 T30 B_DDR3_DQ[11] NC_3 L1
A_DDR3_DQ11 B_DDR3_DQ11 L9 NC_3
A_DDR3_DQ[12] D20 P29 B_DDR3_DQ[12] NC_4 L9
A_DDR3_DQ12 B_DDR3_DQ12 F3 T7 NC_4
A_DDR3_DQ[13] F22 T27 B_DDR3_DQ[13] A_DDR3_DQS0 DQSL NC_6 A_DDR3_A[14] F3 T7
A_DDR3_DQ13 B_DDR3_DQ13 G3 A_DDR3_DQS2 DQSL NC_6 A_DDR3_A[14]
A_DDR3_DQ[14] E18 M28 B_DDR3_DQ[14] A_DDR3_DQS0B DQSL G3
A_DDR3_DQ14 B_DDR3_DQ14 A_DDR3_DQS2B DQSL
A_DDR3_DQ[15] D22 T29 B_DDR3_DQ[15]
A_DDR3_DQ15 B_DDR3_DQ15 C7 A9
B19 N31 A_DDR3_DQS1 DQSU VSS_1 C7 A9
A_DDR3_DM0 A_DDR3_DM0 B_DDR3_DM0 B_DDR3_DM0 B7 B3 A_DDR3_DQS3 DQSU VSS_1
E21 R28 A_DDR3_DQS1B DQSU VSS_2 B7 B3
A_DDR3_DM1 A_DDR3_DM1 B_DDR3_DM1 B_DDR3_DM1 E1 A_DDR3_DQS3B DQSU VSS_2
VSS_3 E1
E7 G8 VSS_3
A21 R32 A_DDR3_DM0 DML VSS_4 E7 G8
A_DDR3_DQS0 A_DDR3_DQS0 B_DDR3_DQS0 B_DDR3_DQS0 D3 J2 A_DDR3_DM2 DML VSS_4
B20 P31 A_DDR3_DM1 DMU VSS_5 D3 J2
A_DDR3_DQS0B A_DDR3_DQS0B B_DDR3_DQS0B B_DDR3_DQS0B J8 A_DDR3_DM3 DMU VSS_5
C20 P30 A_DDR3_DQ[0-15] VSS_6 J8
A_DDR3_DQS1 A_DDR3_DQS1 B_DDR3_DQS1 B_DDR3_DQS1
A_DDR3_DQ[0] E3 M1 A_DDR3_DQ[16-31] VSS_6
C19 N30 DQL0 VSS_7 A_DDR3_DQ[16] E3 M1
A_DDR3_DQS1B A_DDR3_DQS1B B_DDR3_DQS1B B_DDR3_DQS1B
A_DDR3_DQ[1] F7 M9 DQL0 VSS_7
DQL1 VSS_8 A_DDR3_DQ[17] F7 M9
A_DDR3_DQ[16-31] B_DDR3_DQ[16-31]
A_DDR3_DQ[2] F2 P1 DQL1 VSS_8
A_DDR3_DQ[16] B27 AA31 B_DDR3_DQ[16] DQL2 VSS_9 A_DDR3_DQ[18] F2 P1
A_DDR3_DQ16 B_DDR3_DQ16
A_DDR3_DQ[3] F8 P9 DQL2 VSS_9
A_DDR3_DQ[17] A24 V32 B_DDR3_DQ[17] DQL3 VSS_10 A_DDR3_DQ[19] F8 P9
A_DDR3_DQ17 B_DDR3_DQ17
A_DDR3_DQ[4] H3 T1 DQL3 VSS_10
A_DDR3_DQ[18] C27 AA30 B_DDR3_DQ[18] DQL4 VSS_11 A_DDR3_DQ[20] H3 T1
A_DDR3_DQ18 B_DDR3_DQ18
A_DDR3_DQ[5] H8 T9 DQL4 VSS_11
A_DDR3_DQ[19] C24 V30 B_DDR3_DQ[19] DQL5 VSS_12 A_DDR3_DQ[21] H8 T9
A_DDR3_DQ19 B_DDR3_DQ19
A_DDR3_DQ[6] G2 DQL5 VSS_12
A_DDR3_DQ[20] A28 AB32 B_DDR3_DQ[20] DQL6 A_DDR3_DQ[22] G2
A_DDR3_DQ20 B_DDR3_DQ20
A_DDR3_DQ[7] H7 DQL6
A_DDR3_DQ[21] E24 V28 B_DDR3_DQ[21] DQL7 A_DDR3_DQ[23] H7
A_DDR3_DQ21 B_DDR3_DQ21 +1.5V_U_DDR A_DDR3_CKE B1 DQL7
A_DDR3_DQ[22] B28 AB31 B_DDR3_DQ[22] VSSQ_1 B1
A_DDR3_DQ22 B_DDR3_DQ22
A_DDR3_DQ[8] D7 B9 VSSQ_1
A_DDR3_DQ[23] B23 U31 B_DDR3_DQ[23] R13112 DQU0 VSSQ_2 A_DDR3_DQ[24] D7 B9
A_DDR3_DQ23 B_DDR3_DQ23
R13102
1K
A_DDR3_DQ[9] C3 D1 DQU0 VSSQ_2
1K DQU1 VSSQ_3
A_DDR3_DQ[24] D25 W29 B_DDR3_DQ[24] A_DDR3_DQ[25] C3 D1
A_DDR3_DQ24 B_DDR3_DQ24
A_DDR3_DQ[10] C8 D8 DQU1 VSSQ_3
A_DDR3_DQ[25] E27 AA28 B_DDR3_DQ[25] A_DDR3_RESET DQU2 VSSQ_4 A_DDR3_DQ[26] C8 D8
A_DDR3_DQ25 B_DDR3_DQ25
A_DDR3_DQ[11] C2 E2 DQU2 VSSQ_4
A_DDR3_DQ[26] C25 W30 B_DDR3_DQ[26] DQU3 VSSQ_5 A_DDR3_DQ[27] C2 E2
A_DDR3_DQ26 B_DDR3_DQ26
A_DDR3_DQ[12] A7 E8 DQU3 VSSQ_5
A_DDR3_DQ[27] D28 AB29 B_DDR3_DQ[27] DQU4 VSSQ_6 A_DDR3_DQ[28] A7 E8
A_DDR3_DQ27 B_DDR3_DQ27
A_DDR3_DQ[13] A2 F9 DQU4 VSSQ_6
A_DDR3_DQ[28] E26 Y28 B_DDR3_DQ[28] URSA9_DDR_NANYA URSA9_DDR_NANYA URSA9_DDR_NANYA URSA9_DDR_NANYA DQU5 VSSQ_7 A_DDR3_DQ[29] A2 F9
A_DDR3_DQ28 B_DDR3_DQ28 IC2700-*1 IC2800-*1 A_DDR3_DQ[14] B8 G1 DQU5 VSSQ_7
IC2600-*1 IC2900-*1 DQU6 VSSQ_8
A_DDR3_DQ[29] E28 AB28 B_DDR3_DQ[29]
NT5CB64M16FP-EK NT5CB64M16FP-EK A_DDR3_DQ[30] B8 G1
A_DDR3_DQ29 B_DDR3_DQ29 NT5CB64M16FP-EK NT5CB64M16FP-EK A_DDR3_DQ[15] A3 G9 DQU6 VSSQ_8
A_DDR3_DQ[30] E25 W28 B_DDR3_DQ[30] DQU7 VSSQ_9 A_DDR3_DQ[31] A3 G9
A_DDR3_DQ30 B_DDR3_DQ30 DQU7 VSSQ_9
A_DDR3_DQ[31] C28 AB30 B_DDR3_DQ[31]
N3 M8 N3 M8
N3 M8 N3 M8
A_DDR3_DQ31 B_DDR3_DQ31 +1.5V_U_DDR B_DDR3_CKE A0 VREFCA P7
A0 VREFCA
P7
A0 VREFCA A0 VREFCA
B24 V31 P7 A1 A1 P7
A_DDR3_DM2 A_DDR3_DM2 B_DDR3_DM2 B_DDR3_DM2 A1 P3 P3 A1
P3 P3
B26 Y31 A2 N2
A2
H1 N2
A2
H1 A2
R13113 N2 H1 N2 H1
A_DDR3_DM3 A_DDR3_DM3 B_DDR3_DM3 B_DDR3_DM3 A3 VREFDQ P8
A3 VREFDQ
P8
A3 VREFDQ A3 VREFDQ
R13103 1K P8 P8
A4 A4 A4 A4
1K P2 P2 P2 P2
B25 W31 A5 R8
A5
L8 R8
A5
L8 A5
R8 L8 R8 L8
A_DDR3_DQS2 A_DDR3_DQS2 B_DDR3_DQS2 B_DDR3_DQS2 A6 ZQ R2
A6 ZQ
R2
A6 ZQ A6 ZQ
A25 W32 B_DDR3_RESET R2
A7 A7
R2
A_DDR3_DQS2B A_DDR3_DQS2B B_DDR3_DQS2B B_DDR3_DQS2B A7 T8 T8 A7
T8 T8
D26 Y29 A8 R3
A8
B2 R3
A8
B2 A8
R3 B2 R3 B2
A_DDR3_DQS3 A_DDR3_DQS3 B_DDR3_DQS3 B_DDR3_DQS3 A9 VDD_1 L7
A9 VDD_1
D9 L7
A9 VDD_1
D9 A9 VDD_1
C26 Y30 L7 D9 A10/AP VDD_2 A10/AP VDD_2
L7 D9
A_DDR3_DQS3B A_DDR3_DQS3B B_DDR3_DQS3B B_DDR3_DQS3B A10/AP VDD_2 R7 G7 R7 G7 A10/AP VDD_2
R7 G7 R7 G7
A11 VDD_3 A11 VDD_3 A11 VDD_3 A11 VDD_3
N7 K2 N7 K2 N7 K2 N7 K2
A12/BC VDD_4 A12/BC VDD_4 A12/BC VDD_4 A12/BC VDD_4
T3 K8 T3 K8 T3 K8 T3 K8
NC_6 VDD_5 NC_6 VDD_5 NC_6 VDD_5 NC_6 VDD_5
N1 N1 N1 N1
VDD_6 VDD_6 VDD_6 VDD_6
M7 N9 M7 N9 M7 N9 M7 N9
NC_5 VDD_7 NC_5 VDD_7 NC_5 VDD_7 NC_5 VDD_7
R1 R1 R1 R1
VDD_8 VDD_8 VDD_8 VDD_8
M2 R9 M2 R9 M2 R9 M2 R9
BA0 VDD_9 BA0 VDD_9 BA0 VDD_9 BA0 VDD_9
N8 N8 N8 N8
BA1 BA1 BA1 BA1
M3 M3 M3 M3
BA2 BA2 BA2 BA2
A1 A1 A1 A1
* DDR_VTT VDDQ_1 J7
VDDQ_1
A8 J7
VDDQ_1
A8 VDDQ_1
J7 A8 J7 A8
CK VDDQ_2 CK VDDQ_2 CK VDDQ_2 CK VDDQ_2
K7 C1 K7 C1 K7 C1 K7 C1
CK VDDQ_3 CK VDDQ_3 CK VDDQ_3 CK VDDQ_3
K9 C9 K9 C9 K9 C9 K9 C9
CKE VDDQ_4 CKE VDDQ_4 CKE VDDQ_4 CKE VDDQ_4
D2 D2 D2 D2
+1.5V_U_DDR +3.3V_U_NORMAL VDDQ_5 VDDQ_5
VDDQ_5 L2 E9 L2 E9 VDDQ_5 DDR_VTT_URSA_0
L2 E9 L2 E9
CS VDDQ_6 CS VDDQ_6 CS VDDQ_6 CS VDDQ_6
K1 F1 K1 F1 K1 F1 K1 F1
IC13101 ODT VDDQ_7 ODT VDDQ_7 ODT VDDQ_7 ODT VDDQ_7 URSA9_DDR_SAMSUNG
J3 H2 J3 H2 J3 H2 J3 H2
AP2303MPTR-G1 [EP] RAS VDDQ_8 RAS VDDQ_8 RAS VDDQ_8 RAS VDDQ_8
K3 H9 K3 H9 K3 H9 K3 H9 IC2900
CIS21J121

CAS VDDQ_9 CAS VDDQ_9

CAS VDDQ_9 L3 L3 CAS VDDQ_9 URSA9_DDR_SAMSUNG
L13104

L3 L3 AR13101 AR13103 AR13105 AR13107 AR13109 AR13111 AR13113

C13119
VIN
1 8
NC_3 10uF
WE
J1
WE
NC_1
J1
WE
NC_1
J1 WE
J1
100 100 100 100 100 100 100 K4B1G1646G-BCMA
C13114 10V T2
NC_1
J9 T2 J9 T2 J9 T2
NC_1
J9 IC2800 U_MVREFCA_B1
THERMAL

RESET NC_2 RESET NC_2 RESET NC_2 RESET NC_2

10uF L1 L1
GND NC_2 L1
NC_3 NC_3
L1
K4B1G1646G-BCMA
9

10V 2 7 NC_3 L9 L9 NC_3

DDR_VTT_URSA L9 L9
NC_4 F3
NC_4
T7 F3
NC_4
T7 NC_4 U_MVREFCA_B0
R13101 F3 T7
DQSL NC_7 DQSL NC_7 F3 T7 N3 M8
VREFEN VCNTL DQSL NC_7 G3 G3 DQSL NC_7
10K
3 6 G3
DQSL DQSL
G3 B_DDR3_A[0] A0 VREFCA
DQSL DQSL P7
CIS21J121

1/16W B_DDR3_A[1]
L13101

1% C7 A9 C7 A9 C7 A9 C7 A9 N3 M8 A1
VOUT NC_1 DQSU VSS_1 DQSU VSS_1 P3
4 5 B7
DQSU VSS_1
B3 B7 B3 B7 B3 B7
DQSU VSS_1
B3 B_DDR3_A[0] A0 VREFCA B_DDR3_A[2] A2
DQSU VSS_2 DQSU VSS_2
E1
DQSU VSS_2
E1 DQSU VSS_2 P7 N2 H1
E1 E1 B_DDR3_A[1]
VSS_3 E7
VSS_3
G8 E7
VSS_3
G8 VSS_3 A1 B_DDR3_A[3] A3 VREFDQ
E7 G8
DML VSS_4 DML VSS_4 E7 G8 P3 P8
D3
DML VSS_4
J2 D3 J2 D3 J2 D3
DML VSS_4
J2 B_DDR3_A[2] A2 B_DDR3_A[4] A4
DMU VSS_5 DMU VSS_5
J8
DMU VSS_5
J8 DMU VSS_5 N2 H1 P2
J8 J8 B_DDR3_A[3]
C13110 C13111 C13113
VSS_6 E3
VSS_6
M1 E3
VSS_6
M1 VSS_6 A3 VREFDQ B_DDR3_A[5] A5
10uF 10uF 10uF E3 M1
DQL0 VSS_7 DQL0 VSS_7 E3 M1 P8 R8 L8 R13135 240
R13104

10V 10V 10V

C13118 F7
DQL0 VSS_7
M9 F7 M9 F7 M9 F7
DQL0 VSS_7
M9 B_DDR3_A[4] A4 B_DDR3_A[6] A6 ZQ
1%
1/16W

10K

0.1uF
DQL1 VSS_8 F2
DQL1 VSS_8
P1 F2
DQL1 VSS_8
P1 DQL1 VSS_8 P2 R2 1%
F2 P1 F2 P1 B_DDR3_A[5]
16V DQL2 VSS_9 F8
DQL2 VSS_9
P9 F8
DQL2 VSS_9
P9 DQL2 VSS_9 A5 B_DDR3_A[7] A7 +1.5V_U_DDR
F8 P9
DQL3 VSS_10 DQL3 VSS_10 F8 P9 R8 L8 R13127 240
T8
H3
DQL3 VSS_10
T1 H3 T1 H3 T1 H3
DQL3 VSS_10
T1 B_DDR3_A[6] A6 ZQ B_DDR3_A[8] A8
DQL4 VSS_11 H8
DQL4 VSS_11
T9 H8
DQL4 VSS_11
T9 DQL4 VSS_11 R2 1%
R3 B2
H8 T9 H8 T9 B_DDR3_A[7]
DQL5 VSS_12 G2
DQL5 VSS_12
G2
DQL5 VSS_12 DQL5 VSS_12 A7 +1.5V_U_DDR B_DDR3_A[9] A9 VDD_1
G2
DQL6 DQL6
G2 T8 L7 D9
H7
DQL6 H7 H7 H7
DQL6 B_DDR3_A[8] A8 B_DDR3_A[10] A10/AP VDD_2
DQL7 DQL7
B1
DQL7
B1 DQL7 R3 B2 R7 G7
B1 B1 B_DDR3_A[9]
VSSQ_1 D7
VSSQ_1
B9 D7
VSSQ_1
B9 VSSQ_1 A9 VDD_1 B_DDR3_A[11] A11 VDD_3
D7 B9
DQU0 VSSQ_2 DQU0 VSSQ_2 D7 B9 L7 D9 N7 K2
C3
DQU0 VSSQ_2
D1 C3 D1 C3 D1 C3
DQU0 VSSQ_2
D1 B_DDR3_A[10] A10/AP VDD_2 B_DDR3_A[12] A12/BC VDD_4
DQU1 VSSQ_3 C8
DQU1 VSSQ_3
D8 C8
DQU1 VSSQ_3
D8 DQU1 VSSQ_3 R7 G7 T3 K8
C8 D8 C8 D8 B_DDR3_A[11]
DQU2 VSSQ_4 C2
DQU2 VSSQ_4
E2 C2
DQU2 VSSQ_4
E2 DQU2 VSSQ_4 A11 VDD_3 B_DDR3_A[13] A13 VDD_5
C2 E2
DQU3 VSSQ_5 DQU3 VSSQ_5 C2 E2 N7 K2 N1
A7
DQU3 VSSQ_5
E8 A7 E8 A7 E8 A7
DQU3 VSSQ_5
E8 B_DDR3_A[12] A12/BC VDD_4 B_DDR3_A[14] VDD_6
DQU4 VSSQ_6 A2
DQU4 VSSQ_6
F9 A2
DQU4 VSSQ_6
F9 DQU4 VSSQ_6 T3 K8 M7 N9
A2 F9 A2 F9 B_DDR3_A[13]
DDR_VTT_URSA DQU5 VSSQ_7 B8
DQU5 VSSQ_7
G1 B8
DQU5 VSSQ_7
G1 DQU5 VSSQ_7 A13 VDD_5 B_DDR3_A[15] NC_5 VDD_7
DDR_VTT_URSA_0 B8 G1
DQU6 VSSQ_8 DQU6 VSSQ_8 B8 G1 N1 R1
L13102 DQU6 VSSQ_8 A3 G9 A3 G9 DQU6 VSSQ_8 VDD_6
A3 G9
DQU7 VSSQ_9 DQU7 VSSQ_9 A3 G9
M7 N9 VDD_8
BLM18PG121SN1D DQU7 VSSQ_9 DQU7 VSSQ_9 M2 R9
B_DDR3_A[15] NC_5 VDD_7 B_DDR3_BA[0] BA0 VDD_9
R1 N8 +1.5V_U_DDR
C13181 C13179 C13189 C13151
VDD_8 B_DDR3_BA[1] BA1
C13105 M2 R9 M3
1uF 0.1uF 0.1uF 0.1uF
10V 16V 16V 16V
0.1uF B_DDR3_BA[0] BA0 VDD_9 B_DDR3_BA[2] BA2
16V N8 A1
B_DDR3_BA[1] BA1 VDDQ_1
M3 +1.5V_U_DDR
R13125R13124

B_DDR3_MCLK J7 A8
B_DDR3_BA[2] BA2 B_DDR3_MCLK CK VDDQ_2
56

C13234 A1 K7 C1
VDDQ_1 B_DDR3_MCLKZ CK VDDQ_3
0.01uF J7 A8 K9 C9
56

DDR_VTT_URSA DDR_VTT_URSA_1 CK VDDQ_2 B_DDR3_CKE CKE VDDQ_4

L13103 K7 C1 D2
BLM18PG121SN1D B_DDR3_MCLKZ CK VDDQ_3 VDDQ_5
K9 C9 L2 E9
B_DDR3_CKE CKE VDDQ_4 B_DDR3_CSB2 CS VDDQ_6
D2 K1 F1
C13112 C13132 C13158 C13174 C13106 VDDQ_5 B_DDR3_ODT ODT VDDQ_7
1uF 0.1uF 0.1uF 0.1uF 0.1uF L2 E9 J3 H2
10V 16V 16V 16V 16V B_DDR3_CSB1 CS VDDQ_6 B_DDR3_RASZ RAS VDDQ_8
K1 F1 K3 H9
B_DDR3_ODT ODT VDDQ_7 B_DDR3_CASZ CAS VDDQ_9
J3 H2 L3
B_DDR3_RASZ RAS VDDQ_8 B_DDR3_WEZ WE
K3 H9 J1
B_DDR3_CASZ CAS VDDQ_9 NC_1
L3 T2 J9
B_DDR3_WEZ WE B_DDR3_RESET RESET NC_2
J1 L1
NC_1 NC_3
T2 J9 L9
B_DDR3_RESET RESET NC_2 NC_4
L1 F3 T7
NC_3 B_DDR3_DQS2 DQSL NC_6 B_DDR3_A[14]
L9 G3
NC_4 B_DDR3_DQS2B DQSL
F3 T7
Decap removed B_DDR3_DQS0
G3
DQSL NC_6 B_DDR3_A[14]
C7 A9
B_DDR3_DQS0B DQSL B_DDR3_DQS3 DQSU VSS_1
B7 B3
C7 A9 B_DDR3_DQS3B DQSU VSS_2
E1
B_DDR3_DQS1 DQSU VSS_1 VSS_3
B7 B3 E7 G8
B_DDR3_DQS1B DQSU VSS_2 B_DDR3_DM2 DML VSS_4
E1 D3 J2
VSS_3 B_DDR3_DM3 DMU VSS_5
E7 G8 J8
B_DDR3_DM0 DML VSS_4 B_DDR3_DQ[16-31] VSS_6
D3 J2 B_DDR3_DQ[16] E3 M1
B_DDR3_DM1 DMU VSS_5 DQL0 VSS_7
J8 B_DDR3_DQ[17] F7 M9
B_DDR3_DQ[0-15] VSS_6 DQL1 VSS_8
B_DDR3_DQ[0] E3 M1 B_DDR3_DQ[18] F2 P1
DQL0 VSS_7 DQL2 VSS_9
B_DDR3_DQ[1] F7 M9 B_DDR3_DQ[19] F8 P9
DQL1 VSS_8 DQL3 VSS_10
B_DDR3_DQ[2] F2 P1 B_DDR3_DQ[20] H3 T1
DQL2 VSS_9 DQL4 VSS_11
+1.5V_U_DDR B_DDR3_DQ[3] F8 P9 B_DDR3_DQ[21] H8 T9
DQL3 VSS_10 DQL5 VSS_12
Close to DDR Power pin B_DDR3_DQ[4] H3 T1 B_DDR3_DQ[22] G2
DQL4 VSS_11 DQL6
B_DDR3_DQ[5] H8 T9 B_DDR3_DQ[23] H7
DQL5 VSS_12 DQL7
B_DDR3_DQ[6] G2 B1
DQL6 VSSQ_1
B_DDR3_DQ[7] H7 B_DDR3_DQ[24] D7 B9
C13104 C13109 C13117 C13128 C13137 C13146 C13156 C13164 C13172 C13178 C13186 C13194 C13198 C13206 C13214 C13218 C13226 DQL7
B1 DQU0 VSSQ_2
B_DDR3_DQ[25] C3 D1
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 1uF 0.1uF 0.1uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 1uF B_DDR3_DQ[8] D7
VSSQ_1
B9 DQU1 VSSQ_3
B_DDR3_DQ[26] C8 D8
16V 16V 16V 16V 16V 16V 16V 16V 10V 16V 16V 10V 16V 16V 16V 16V 10V B_DDR3_DQ[9] C3
DQU0 VSSQ_2
D1 DQU2 VSSQ_4
B_DDR3_DQ[27] C2 E2
DQU1 VSSQ_3 DQU3 VSSQ_5
B_DDR3_DQ[10] C8 D8 B_DDR3_DQ[28] A7 E8
DQU2 VSSQ_4 DQU4 VSSQ_6
B_DDR3_DQ[11] C2 E2 B_DDR3_DQ[29] A2 F9
DQU3 VSSQ_5 DQU5 VSSQ_7
B_DDR3_DQ[12] A7 E8 B_DDR3_DQ[30] B8 G1
DQU4 VSSQ_6 DQU6 VSSQ_8
B_DDR3_DQ[13] A2 F9 B_DDR3_DQ[31] A3 G9
DQU5 VSSQ_7 DQU7 VSSQ_9
B_DDR3_DQ[14] B8 G1
DQU6 VSSQ_8
B_DDR3_DQ[15] A3 G9
+1.5V_U_DDR DQU7 VSSQ_9
Close to DDR Power pin

C13102 C13107 C13115 C13126 C13135 C13144 C13154 C13162 C13170 C13176 C13184 C13192 C13196 C13204 C13212 C13216 C13224 C13232 C13100 C13101
0.1uF 0.1uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 1uF 0.1uF 0.1uF 0.1uF 10uF 10uF
16V 16V 10V 16V 16V 16V 16V 10V 16V 16V 16V 16V 16V 16V 10V 16V 16V 16V 10V 10V

4th layer

+1.5V_U_DDR
Close to DDR Power pin
Decap removed

C13103 C13108 C13116

0.1uF 0.1uF 0.1uF
16V 16V 16V

+1.5V_U_DDR
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
Close to DDR Power pin SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
Decap removed FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
C13195 ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
0.1uF THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
16V
M1A_URSA9_UD 2014.04.24
4th layer

URSA9_DDR 131

URSA Option

URSA_BIT0_1
LGD_Module
Div_BIT1_1
Div_BIT0_1

R13210 10K

R13212 10K

R13213 10K

R13245 10K
R13451 10K

R13208 10K
R13457 10K

R13453 10K
R13459 10K

Release
R13455 10K
OPT

OPT
Clock for URSA9 URSA Reset

OPT

OPT
+3.3V_U_NORMAL
C13236

URSA_BIT1_1

URSA_BIT2_1
URSA_RX_LVDS
URSA_OPT_6

SW13201 +3.3V_U_NORMAL
8pF
50V

URSA_OPT_5
1 2 BIT [1/0] Module Division
X-TAL_1

URSA_OPT_4
XIN_URSA C13238
GND_1

Div_BIT0
1uF R13215
0/0 Non Division
Division Type
3 4 10V 10K 0/1 2 Division Div_BIT1
OPT 1/0 4 Division
R13220

URSA_OPT_0
URSA_RESET 1/1 8 Division Rx Interface
2

X13201
24MHz

URSA_OPT_1
1M

Module Type
C13237

BIT [2/1/0] Tx Lane URSA_BIT0

Tx Lane
URSA_RESET_SoC
R13218 URSA_BIT1
3

4
8pF
50V

0 0/0/0 4K@120 (16lane)

470K
X-TAL_2

GND_2

URSA_BIT2
1N4148W

R13221 0/0/1 4k@60 (8lane)

OPT

OPT URSA_RX_Vx1
D13201

OPT
XO_URSA 0/1/0 5k@120 (20lane)

URSA_BIT0_0

URSA_BIT1_0

URSA_BIT2_0
10K

10K
10K

10K
Div_BIT1_0
100V

Div_BIT0_0

R13452 10K
URSA_RESET_READY

R13454 10K
0/1/1 OLED ULTRA HD

R13458 10K

R13456 10K

10K
OS_Module
R13460 10K

Reserved
0

Reserved

Debug

R13249
1/0/0 FHD@120 (4lane)

R13214
R13209

R13247
R13242

R13211
1/0/1 FHD@60 (2lane)
OPT
1/1/0 Reserved

1/1/1 Reserved

OPT
P13204
12507WS-04L
IC2500
LGE7411(URSA9) OPT
R13230 33
1
URSA9_PQ_DEBUG

URSA_L/D_VSYNC

2
+3.3V_U_NORMAL AF29 AG25
URSA_RESET RESET I2C_HSC_SDA/VSYNC_LIKE2 OPT
IC13201-*1 AH25 R13461 33
3
W25Q32FVSSIG URSA9_PQ_DEBUG I2C_HSC_SCL/VSYNC_LIKE3 URSA_OPT_6
R3
R13250

P13202 XIN_URSA XTALO OPT

R13462 33
CS VCC
12507WS-04L R4 AH28 4
SPI Flash 1 8 URSA_OPT_5
10K

XO_URSA XTALI SPI1_CK/PWM2/GPIO58 URSA_OPT_0

DO[IO1] HOLD_OR_RESET[IO3] AJ27 Module Division OPT
2 7 Div_BIT0 5
SPI1_DI/PWM3/GPIO59
WP[IO2] CLK
1 SDA2_+3.3V_URSA 33 R13204 AJ24 AJ29
3 6 I2CS_SDA SPI2_CK/PWM0/GPIO56 Div_BIT1 +3.3V_U_NORMAL
R13251 AH24 AF27
GND DI[IO0] 33 SCL2_+3.3V_URSA I2CS_SCL SPI2_DI/PWM1/GPIO57 URSA_OPT_4
4 5 2 33 R13219 AG28 OPT
SPI3_CK/DIM10/GPIO54 URSA_OPT_5 R13226
URSA9_PQ_DEBUG AH26 AH27 10K
URSA_FLASH_WINDBOND(MULTI) 3 I2CM_SDA SPI3_DI/DIM11/GPIO55 URSA_OPT_6
AG24 AG27 R13225 33
+3.3V_U_NORMAL R13252 I2CM_SCL/VSYNC_LIKE1 SPI4_CK/DIM8/GPIO52 3D_EN
33 AG26 R13224 33 OPT
4 R13228
IC13201 URSA9_PQ_DEBUG B4
SPI4_DI/DIM9/GPIO53
OPT
L_DIM_EN
10K

MX25L3235E 5 C13240
0.1uF A4
GPIO[0][UART2_TX]
AF28
16V GPIO[1][UART2_RX] VSYNC_LIKE/PWM5/GPIO40 URSA_L/D_VSYNC
URSA9_PQ_DEBUG
URSA9_SYS_DEBUG

CS VCC C13235 B5
1 8 0.1uF GPIO[2][UART1_TX]
SPI_CZ URSA_FLASH_MX(MULTI) 16V +3.3V_U_NORMAL
URSA9_SYS_DEBUG R13255 A5 AG23 +3.3V_U_NORMAL
33 GPIO[3][UART1_RX] DIM0/GPIO[32] DIM0
R13253

P13203
Change pin from A5 to C4
AG20
R13246 SO/SIO1 HOLD/SIO3 12507WS-04L URSA9_SYS_DEBUG DIM1/GPIO[33] DIM1 OPT
33 2 7 AH23 R13233
10K

SPI_DO DIM2/GPIO[34] DIM2 10K

10K R13450 +3.3V_U_NORMAL AD28 AH20
1 SPI_CZ SPI_CZ DIM3/GPIO[35]
1K WP/SIO2 SCLK AD30 AG21
R13205 3 6 SPI_CK SPI_CK DIM4/GPIO[36] URSA_OPT_1
FLASH_WP_URSA 1K SPI_CK AR13200 AC31 AH22 R13234
URSA_BIT0 10K
OPT 2 SPI_DI 33 SPI_DI DIM5/GPIO[37]
OPT AD29 AG22
GND SI/SIO0 R13231 SPI_DO SPI_DO DIM6/GPIO[38] URSA_BIT1
R13222 1K 4 5 SPI_DI 3 AH21
URSA_BIT2
FRC_FLASH_WP OPT DIM7/GPIO[39]
33 R13243 AE28
R13001 4 INT_R21/GPIO[41]
TCON_I2C_EN OPT 33 R13223 AE27
10K URSA9_SYS_DEBUG 10K INT_R20/GPIO[42]
OPT 5 A3
C13239 R13232 GPIO43/TCON0
0.1uF B3
16V OPT GPIO44/TCON1
A2
R13254 GPIO45/TCON2
33 C4 C3
IRE GPIO46/TCON3
URSA9_SYS_DEBUG B2
GPIO47/TCON4
URSA9 UART1_RX B1
GPIO48/TCON5
C2
GPIO49/TCON6
AC27 C1
GND_1 GPIO50/TCON7
AD27
GND_2
AG4
GPIO[18]/TCON8
A7 AG5
NC_1 GPIO[19]/TCON9
B6 AH4
Chip Config NC_2 GPIO[20]/TCON10 DDC_SCL_2

Debugging for URSA9 B7

C5
NC_3 GPIO[21]/TCON11
AH5
AH6
DDC_SDA_2
Used net when HDMI SWITCH not used
Debug/ISP ADDR NC_4 GPIO[22]/TCON12 HPD2
Slave (Debug Port:0XB4,ISP:0X98) C6 AJ4 DDC_SCL_2
NC_5 GPIO[23]/TCON13
CHIP_CONF:{DIM2,DIM1,DIM0} C7 AJ5 DDC_SDA_2

CHIP_CONF=3’d7:111:boot from SPI Flash I2C_S Port NC_6 GPIO24/TCON14 HPD2

D4 AJ6
NC_7 GPIO25/TCON15 DDC_SCL_4
P13201 D5
12507WS-04L NC_8 DDC_SDA_4
D6 AH16
WAFER-STRAIGHT Data_Format_1
URSA_DEBUG
NC_9 GPIO[4]
+3.3V_U_NORMAL
D7 AG16
DIM0 1 SW13002 NC_10 GPIO[5] Data_Format_0
JS2235S E4 Y5
NC_11 GPIO[6] DDC_SCL_4
OPT 10K E5 Y4
2
NC_12 GPIO[7] DDC_SDA_4
10K R13207 URSA_SCL 1 6 URSA_SDA E6 AB4
DIM1 R13217 33 R13235 R13237 NC_13 GPIO[8]
R13203 3 SCL2_+3.3V_DB NON_URSA_SLIDE_SW(MP) 0 0 NON_URSA_SLIDE_SW(MP) E7 AB5
OPT 10K URSA_DEBUG
SCL2_+3.3V_URSA 2 5 SDA2_+3.3V_URSA NC_14 GPIO[9] OPT
R13238 URSA_SLIDE_SW(DEBUG) R13240
F4 AG17 R13239 33 R13229 R13236
R13216 33 0 0 NC_15 GPIO[10]/PWM_DIM_IN[0] OPT 100K
4 SDA2_+3.3V_DB 100K
10K R13206 URSA_DEBUG
OPT
3 4
OPT F5 AH17 R13241 33
SCL2_+3.3V_DB SDA2_+3.3V_DB NC_16 GPIO[11]/PWM_DIM_IN[1]
R13202 DIM2 5 M5 AG18 10K R13227
NC_17 GPIO[12] URSA_RX_Vx1_HTPDn
OPT 10K M6 AJ20 10K R13244
NC_18 GPIO[13] URSA_RX_Vx1_HTPDn
M7 AH18 URSA9_Vx1_RX_HTPD_GPIO
10K R13248 NC_19 GPIO[14] URSA9_CONNECT
R13201 N5 AG19
NC_20 GPIO[15] URSA_LOCK_O
R7 AH19
NC_21 GPIO[16] URSA_LOCK_V
P7 AJ21 Not Used Net (UB85/95/UC89)
NC_22 GPIO[17] FLASH_WP_URSA
N7 URSA9_CONNECT
NC_23 URSA_LOCK_O
N6
NC_24 URSA_LOCK_V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

D18 D24
A8 T13 VSS_285 VSS_389
VSS_81 VSS_186 G18 F24
B8 R13 VSS_286 VSS_390
VSS_82 VSS_187 H18 G24
C8 P13 VSS_287 VSS_391
VSS_83 VSS_188 J18 H24
D8 N13 VSS_288 VSS_392
VSS_84 VSS_189 L18 J24
E8 M13 VSS_289 VSS_393
VSS_85 VSS_190 N18 K24
F8 U13 VSS_290 VSS_394
VSS_86 VSS_191 P18 L24
G8 V13 VSS_291 VSS_395
VSS_87 VSS_192 R18 M24
H8 W13 VSS_292 VSS_396
VSS_88 VSS_193 T18 N24
J8 Y13 VSS_293 VSS_397
VSS_89 VSS_194 U18 P24
K8 AA13 VSS_294 VSS_398
IC2500 L8
VSS_90 VSS_195
AB13
V18 R24
VSS_295 VSS_399
LGE7411(URSA9) M8
VSS_91 VSS_196
AD13
W18 T24
VSS_296 VSS_400
VSS_92 VSS_197 Y18 U24
VDDC N8 AE13 VSS_297 VSS_401
VSS_93 VSS_198 AA18 V24
P8 AF13 VSS_298 VSS_402
A6 K1 VSS_94 VSS_199 AB18 W24
R8 AG13 VSS_299 VSS_403
VDDC_1 VSS_1 VSS_95 VSS_200 AE18 Y24
M9 T1 T8 AH13 VSS_300
VDDC_2 VSS_2 VSS_404
M10 K2 VSS_96 VSS_201 AF18 AA24
U8 AJ13 VSS_301 VSS_405
VDDC_3 VSS_3 VSS_97 VSS_202 AJ18 AB24
M11 P2 V8 G14 VSS_302
VDDC_4 VSS_4 VSS_406
N9 T2 VSS_98 VSS_203 F19 AC24
W8 H14 VSS_303 VSS_407
VDDC_5 VSS_5 VSS_99 VSS_204 G19 AD24
N10 AF2 Y8 J14 VSS_304
VDDC_6 VSS_6 VSS_408
N11 K3 VSS_100 VSS_205 H19 AE24
AA8 K14 VSS_305 VSS_409
VDDC_7 VSS_7 VSS_101 VSS_206 J19 AF24
P9 T3 L14 VSS_306
VDDC_8 VSS_8 VSS_410
P10 AF3 VSS_207 K19
AC8 P14 VSS_307
VDDC_9 VSS_9 VSS_102 VSS_208 L19 AL24
P11 AG3 AD8 R14 VSS_308
VDDC_10 VSS_10 VSS_411
R9 G4 VSS_103 VSS_209 N19 F25
AE8 T14 VSS_309 VSS_412
VDDC_11 VSS_11 VSS_104 VSS_210 P19 G25
R10 H4 AF8 U14 VSS_310
VDDC_12 VSS_12 VSS_413
R11 J4 VSS_105 VSS_211 R19 H25
AG8 V14 VSS_311 VSS_414
VDDC_13 VSS_13 VSS_106 VSS_212 T19 J25
T9 K4 AH8 W14 VSS_312
VDDC_14 VSS_14 VSS_415
T10 P4 VSS_107 VSS_213 U19 K25
AJ8 Y14 VSS_313 VSS_416
VDDC_15 VSS_15 VSS_108 VSS_214 V19 L25
T11 T4 B9 AA14 VSS_314
VDDC_16 VSS_16 VSS_417
U9 U4 VSS_109 VSS_215 W19 M25
D9 AB14 VSS_315 VSS_418
VDDC_17 VSS_17 VSS_110 VSS_216 Y19 N25
U10 V4 E9 AE14 VSS_316
VDDC_18 VSS_18 VSS_419
U11 W4 VSS_111 VSS_217 AB19 P25
F9 AF14 VSS_317 VSS_420
VDDC_19 VSS_19 VSS_112 VSS_218 AC19 R25
V9 AA4 G9 AG14 VSS_318
VDDC_20 VSS_20 VSS_421
V10 AC4 VSS_113 VSS_219 AD19 T25
H9 AH14 VSS_319 VSS_422
VDDC_21 VSS_21 VSS_114 VSS_220 AE19 U25
V11 AD4 J9 AJ14 VSS_320
VDDC_22 VSS_22 VSS_423
W9 AE4 VSS_115 VSS_221 AF19 V25
K9 A15 VSS_321 VSS_424
VDDC_23 VSS_23 VSS_116 VSS_222 AK19 W25
W10 AF4 L9 B15 VSS_322
VDDC_24 VSS_24 VSS_425
W11 G5 VSS_117 VSS_223 A20 Y25
D15 VSS_323 VSS_426
VDDC_25 VSS_25 VSS_224 E20 AA25
Y9 H5 VSS_324
VDDC_26 VSS_26 VSS_427
J5 F20 AB25
AD9 G15 VSS_325 VSS_428
VSS_27 VSS_118 VSS_225 G20 AC25
K5 AE9 H15 VSS_326 VSS_429
AVDDL_HDMI_TX_RX VSS_28 VSS_119 VSS_226 H20 AD25
L5 AF9 J15 VSS_327 VSS_430
VSS_29 VSS_120 VSS_227 J20 AE25
AG9 K15 VSS_328 VSS_431
L3 P5 VSS_121 VSS_228 L20 AF25
AH9 L15 VSS_329 VSS_432
AVDDL_HDMITX_1 VSS_30 VSS_122 VSS_229 N20 AM25
AVDDL_LVDSRX L4 R5 AJ9 M15 VSS_330
AVDDL_HDMITX_2 VSS_31 VSS_433
AA9 T5 VSS_123 VSS_230 P20 A26
N15 VSS_331 VSS_434
AVDDL_RX_1 VSS_32 VSS_231 R20 F26
AA10 U5 D10 P15 VSS_332
AVDDL_RX_2 VSS_33 VSS_435
AB9 V5 VSS_124 VSS_232 T20 G26
E10 R15 VSS_333 VSS_436
AVDDL_RX_3 VSS_34 VSS_125 VSS_233 U20 H26
F10 T15 VSS_334 VSS_437
Y10 W5 VSS_126 VSS_234 V20 J26
G10 U15 VSS_335 VSS_438
AVDDL_DVI_1 VSS_35 VSS_127 VSS_235 W20 K26
Y11 AA5 H10 V15 VSS_336
AVDDL_DVI_2 VSS_36 VSS_439
DVDD_DDR AC5 VSS_128 VSS_236 AE20 L26
J10 W15 VSS_337 VSS_440
VSS_37 VSS_129 VSS_237 AF20 M26
M14 AD5 K10 Y15 VSS_338
DVDD_DDR_1 VSS_38 VSS_441
N14 AE5 VSS_130 VSS_238 AK20 N26
L10 AA15 VSS_339 VSS_442
AVDDL_MOD DVDD_DDR_2 VSS_39 VSS_131 VSS_239 P26
AF5 AB10 AE15 VSS_443
VSS_40 VSS_132 VSS_240 D21 R26
Y20 F6 AC10 AF15 VSS_340
AVDDL_MOD_1 VSS_41 VSS_444
Y21 G6 VSS_133 VSS_241 F21 T26
AD10 AG15 VSS_341 VSS_445
AVDDL_MOD_2 VSS_42 VSS_134 VSS_242 G21 U26
Y22 H6 AE10 AH15 VSS_342
AVDDL_MOD_3 VSS_43 VSS_446
AA19 J6 VSS_135 VSS_243 H21 V26
AF10 AJ15 VSS_343 VSS_447
AVDDL_MOD_4 VSS_44 VSS_136 VSS_244 J21 W26
AA20 K6 AG10 E16 VSS_344
AVDDL_DRV AVDDL_MOD_5 VSS_45 VSS_448
AA21 L6 VSS_137 VSS_245 K21 Y26
AH10 F16 VSS_345 VSS_449
AVDDL_DRV_1 VSS_46 VSS_138 VSS_246 L21 AA26
AA22 AJ10 G16 VSS_346
AVDDL_DRV_2 VSS_450
AB20 P6 VSS_139 VSS_247 T21 AB26
A11 H16 VSS_347 VSS_451
AVDDL_DRV_3 VSS_47 VSS_140 VSS_248 U21 AC26
AB21 R6 D11 J16 VSS_348
AVDDL_DRV_4 VSS_48 VSS_452
AB22 T6 VSS_141 VSS_249 V21 AD26
E11 VSS_349 VSS_453
AVDDL_DRV_5 VSS_49 VSS_142 W21 AE26
U6 F11 L16 VSS_350 VSS_454
AVDD_MOD VSS_50 VSS_143 VSS_250 AE21 AF26
AC20 V6 G11 N16 VSS_351
AVDD_MOD_1 VSS_51 VSS_455
AC21 W6 VSS_144 VSS_251 AF21 AJ26
H11 P16 VSS_352 VSS_456
AVDD_MOD_2 VSS_52 VSS_145 VSS_252 AK21 AL26
AD21 Y6 J11 R16 VSS_353
AVDD_MOD_3 VSS_53 VSS_457
AD20 AA6 VSS_146 VSS_253 D27
K11 T16 VSS_458
AVDD_MOD_LDO VSS_54 VSS_147 VSS_254 F27
VDDP AB6 L11 U16 VSS_459
VSS_55 VSS_148 VSS_255 K27
AC18 AC6 AA11 V16
VDDP_1 VSS_56 VSS_460
AD17 AD6 VSS_149 VSS_256 G22 N27
AB11 W16 VSS_354 VSS_461
VDDP_2 VSS_57 VSS_150 VSS_257 H22 P27
AD18 AE6 AC11 Y16 VSS_355
VDDP_3 VSS_58 VSS_462
AF6 VSS_151 VSS_258 J22 R27
AE11 AA16 VSS_356 VSS_463
VSS_59 VSS_152 VSS_259 U27
AD11 AG6 AF11 AE16
AVDD_DVI_1 VSS_60 VSS_464
AD12 VSS_153 VSS_260 L22 V27
AG11 AF16 VSS_357 VSS_465
AVDD_DVI_2 VSS_154 VSS_261 M22 W27
AC12 F7 AH11 VSS_358
AVDD_HDMITX_1 VSS_61 VSS_466
AC13 G7 VSS_155 T22 Y27
AJ11 VSS_359 VSS_467
AVDD_HDMITX_2 VSS_62 VSS_156 U22 AA27
AD15 H7 AJ16 VSS_360
AVDD_RX_1 VSS_63 VSS_468
AC16 J7 VSS_262 V22 AB27
D12 AM16 VSS_361 VSS_469
AVDD_RX_2 VSS_64 VSS_157 VSS_263 W22
AC17 K7 E12 A17 VSS_362
AVDD_RX_3 VSS_65 VSS_158 VSS_264 AC22 F28
AD16 L7 F12 B17 VSS_363
AVDD_RX_4 VSS_66 VSS_470
VSS_159 VSS_265 AD22 K28
AVDD_PLL G12 G17 VSS_364 VSS_471
AD14 VSS_160 VSS_266 AE22 P28
H12 H17 VSS_365 VSS_472
AVDD_XTAL VSS_161 VSS_267 AF22 U28
AC14 J12 J17 VSS_366
AVDD_PLL_1 VSS_473
AC15 T7 VSS_162 VSS_268 AL22 AC28
+1.5V_U_DDR K12 K17 VSS_367 VSS_474
AVDD_PLL_2 VSS_67 VSS_163 VSS_269 AK28
M18 U7 L12 L17
AVDD_DDR0_1 VSS_68 VSS_475
M19 V7 VSS_164 VSS_270 A29
M12 N17 VSS_476
AVDD_DDR0_2 VSS_69 VSS_165 VSS_271 A23 C29
M20 W7 N12 P17
AVDD_DDR0_3 VSS_70 VSS_368 VSS_477
M21 Y7 VSS_166 VSS_272 E23 D29
P12 R17 VSS_369 VSS_478
AVDD_DDR0_4 VSS_71 VSS_167 VSS_273 F23 E29
M16 AA7 R12 T17
AVDD_DDR0_5 VSS_72 VSS_370 VSS_479
M17 AB7 VSS_168 VSS_274 G23 F29
T12 U17 VSS_371 VSS_480
AVDD_DDR0_6 VSS_73 VSS_169 VSS_275 H23 J29
AC7 U12 V17 VSS_372 VSS_481
VSS_74 VSS_170 VSS_276 J23 M29
P21 AD7 V12 W17 VSS_373
AVDD_DDR1_1 VSS_75 VSS_482
R21 AE7 VSS_171 VSS_277 K23 R29
W12 Y17 VSS_374 VSS_483
AVDD_DDR1_2 VSS_76 VSS_172 VSS_278 V29
P22 AF7 Y12 AA17
AVDD_DDR1_3 VSS_77 VSS_484
R22 AG7 VSS_173 VSS_279 M23 AA29
AA12 AB17 VSS_375 VSS_485
AVDD_DDR1_4 VSS_78 VSS_174 VSS_280 AC29
N21 AH7 AB12 AE17
AVDD_DDR1_5 VSS_79 VSS_486
N22 AJ7 VSS_175 VSS_281 P23 AK29
AE12 AF17 VSS_376 VSS_487
AVDD_DDR1_6 VSS_80 VSS_176 VSS_282 A30
AF12 VSS_488
VSS_177 T23 B30
AG12 VSS_377 VSS_489
VSS_178 V23 AC30
AH12 AJ17 VSS_378 VSS_490
VSS_179 VSS_283 W23 AK30
AJ12 AL17 VSS_379 VSS_491
VSS_180 VSS_284 Y23 AM30
VSS_380 VSS_492
AA23 A31
VSS_381 VSS_493
AB23 B31
G13 VSS_382 VSS_494
VSS_181 AC23 C31
H13 VSS_383 VSS_495
VSS_182 AD23 J31
J13 VSS_384 VSS_496
VSS_183 AE23 L31
K13 VSS_385 VSS_497
VSS_184 AF23 AD31
L13 VSS_386 VSS_498
VSS_185 AJ23 AF31
VSS_387 VSS_499
AM23 AH31
VSS_388 VSS_500
B32
VSS_501
E32
VSS_502
J32
VSS_503
L32
VSS_504
P32
VSS_505
U32
VSS_506
Y32
VSS_507

AE32
VSS_508
AG32
VSS_509

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

+12V

+1.5V URSA DDR +1.15V URSA9 Core

+1.5V_U_DDR

L13411 POWER_ON/OFF_1
BLM18PG121SN1D

R13404
10K
C13443 C13410
10uF 0.1uF R13407

R13408
4.87K

1/16W
16V 39K
IC13403
R13424 R1

1%
BD9D321EFJ [EP] 1/16W
10K 5%

1%
1/16W

91K
R13406
C13403

R13411R13409
[EP]

GND2

GND1

NC_3

TRIP
EN VIN

1/16W 1/16W
1 8 1000pF

240 5.1K
VO
16V 50V R2

1%
1/16W

27K
R13405
THERMAL

R13410
0.1uF

1%
1/16W

20K
R13421 R13422 FB BOOT C13447

24
9

2 7 +3.3V_U_NORMAL
RF 1 23 FB
R1

1%
18K 3.6K L13412
1% 1% 2.2uH R13425 THERMAL
VREG SW 10K PGOOD 2 29 22 GND
3 6 +12V
C13444
100pF VLS5045EXT-2R2N 0 R13401 EN 3 21 MODE
50V 16V
SS GND 0.1uF IC13402
4
3A 5 C13448
22uF
C13449
22uF
ZD13401 R13403 VBST 4
TPS53513RVER
20 VREG L13402
1/16W

10V 10V 2.5V 10K

R13423 C13405 NC_1 VDD
OPT R13426 5 19
4.7

22K C13445 C13446 OPT C13402 R13400

1uF 2200pF 2K SW_1 NC_2
1% 6 18
10V 50V
0.1uF 1/16W C13407 C13409
SW_2 7 17 VIN_3 C13408
R2 16V 5% 1uF 10uF
VDDC 10uF
10V 16V
L13403 SW_3 8 16 VIN_2 16V
Vout=0.765*(1+R1/R2)=1.516V 1.0uH
SW_4 9
8A 15 VIN_1
R13402

14
1/10W
3.3

D13400

C13400 C13401 C13411

C13406
PGND_1

PGND_2

PGND_3

PGND_4

PGND_5
22uF 22uF 22uF
30V

2200pF
ZD13400

50V
2.5V

OPT

C13404
470pF
50V

+12V

+3.3V URSA +3.3V_U_NORMAL

L13401 Vout=0.6*(1+R1/R2)
BLM18PG121SN1D +3.3V_NORMAL

C13412 C13413
10uF 0.1uF
16V
IC13401
R13415
BD9D321EFJ [EP]
10K

EN VIN
1 8
16V
THERMAL

0.1uF
R13412 R13413 FB BOOT C13417
9

2 7
R1 68K 6.8K L13404
1% 1% 2.2uH
VREG SW
3 6
C13414
100pF VLS5045EXT-2R2N
50V
SS GND
4
3A 5 C13418
22uF
C13419
22uF D13401
1/16W

10V 10V 5V
R13414
22K C13415 C13416 TVS_SEMTECH(MULTI)
1uF 2200pF
1% 10V 50V

R2 D13401-*1

TVS_KEC(MULTI)

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

2
PANEL_VCC

3
L13409
MLB-201209-0120P-N2
4

L13410
5
MLB-201209-0120P-N2
6 C13434 C13435 C13440 C13442
10uF 0.1uF 10uF 0.1uF
16V 25V 16V 25V
OPT

SMD bottom Gasket 10.5T

OPT OPT OPT OPT OPT OPT
GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H
M13000 M13001 M13002 M13003 M13004 M13005
MDS62110225 MDS62110225 MDS62110225 MDS62110225 MDS62110225 MDS62110225

OPT SMD_GASKET OPT OPT SMD_GASKET

GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H GASKET_8.0X6.0X10.5H
M13006 M13007 M13008 M13009 M13010
MDS62110225 MDS62110225 MDS62110225 MDS62110225 MDS62110225

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS M1A_URSA9_UD 2014.04.24
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
T-CON POWER 141
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

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49 Uf 6700

Uploaded by

49 Uf 6700

Uploaded by

Internal Use Only

North/Latin America http://aic.lgservice.com

MODEL : 49UF6700 49UF6700-UC

P/NO : MFL68682506 (1503-REV00) Printed in Korea

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SAFETY PRECAUTIONS ......................................................................... 3

SERVICING PRECAUTIONS .................................................................... 4

ADJUSTMENT INSTRUCTION .............................................................. 10

BLOCK DIAGRAM .................................................................................. 30

EXPLODED VIEW ................................................................................... 31

SCHEMATIC CIRCUIT DIAGRAM ............................................ APPENDIX

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IMPORTANT SAFETY NOTICE

General Guidance Leakage Current Hot Check (See below Figure)

Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed

Leakage Current Cold Check(Antenna Cold Check)

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Fuse and Conventional Resistor

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1) Temperature : 25 ºC ± 5 ºC, (77 ± 9 ºF), CST : 40±5 ºC

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3.2. Final assembly adjustment 4.2.3. Download method

3.3. Appendix ※ Caution) When EDID Download, must remove RGB/HDMI

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▪ HDMI1 (E6 , DD) - HDMI DEEP COLOR OFF

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▪ HDMI2 (A0 , E3) - HDMI DEEP COLOR ON

▪ HDMI2 (E6 , C4) - HDMI DEEP COLOR OFF

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** (Aging chamber) LGD Cell

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7. AUDIO output check

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(b) Be careful to not be off of TV Power.

(5) Updating Completed, The TV will restart automatically

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Check stand-by voltage 3.5V NG Check Power connector NG Short check NG

Only for training and service purposes

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LG Electronics. Inc. All rights reserved.

IC404 : 1.5V , Q406 : 3.3V Replace IC404, Q406, IC403

LGE Internal Use Only

Check URSA9 IC power block

Only for training and service purposes

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LG Electronics. Inc. All rights reserved.

Check DRV ON signal Low NG

Check LCD Module

LGE Internal Use Only

Check Tuner power NG

Only for training and service purposes

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LG Electronics. Inc. All rights reserved.

- 19 -LGE Internal Use Only

Only for training and service purposes

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LG Electronics. Inc. All rights reserved.

Replace IC101 or Main Board

- 20 -LGE Internal Use Only

Check Component cable

Only for training and service purposes

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LG Electronics. Inc. All rights reserved.

Check Component signal Pb NG

Replace IC101 or Main Board

LGE Internal Use Only

Check HDMI cable

Only for training and service purposes

Check HDMI S/W IC power block NG

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3.3. Appendix ※ Caution) When EDID Download, must remove RGB/HDMI

** (Aging chamber) LGD Cell