EC8791-Embedded and Real Time Systems UNITS NOTES
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DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
EC8791 EMBEDDED AND REAL TIME SYSTEMS LTPC3003
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Objectives:
To Understand the concept of embedded system design and analysis.
To learn the architecture of ARM processor.
To learn the Programming of ARM processor
To Expose the basic concepts of embedded programming.
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To Learn real time operating systems
UNIT I INTRODUCTION TO EMBEDDED SYSTEM DESIGN
Complex systems and microprocessors– Embedded system design process –Design example:
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Model train controller- Design methodologies- Design flows - Requirement Analysis –
Specifications-System analysis and architecture design – Quality Assurance techniques -
Designing with computing platforms – consumer electronics architecture – platform-level
performance analysis. pa
UNIT II ARM PROCESSOR AND PERIPHERALS
ARM Architecture Versions – ARM Architecture – Instruction Set – Stacks and Subroutines –
Features of the LPC 214X Family – Peripherals – The Timer Unit – Pulse Width Modulation
Unit – UART – Block Diagram of ARM9 and ARM Cortex M3 MCU.
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UNIT III EMBEDDED PROGRAMMING
Components for embedded programs- Models of programs- Assembly, linking and loading –
compilation techniques- Program level performance analysis – Software performance
optimization – Program level energy and power analysis and optimization – Analysis and
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optimization of program size- Program validation and testing.
UNIT IV REAL TIME SYSTEMS
Structure of a Real Time System –– Estimating program run times – Task Assignment and
Scheduling – Fault Tolerance Techniques – Reliability, Evaluation – Clock Synchronisation..
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UNIT V PROCESSES AND OPERATING SYSTEMS
Introduction – Multiple tasks and multiple processes – Multirate systems- Preemptive realtime
operating systems- Priority based scheduling- Interprocess communication mechanisms –
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Evaluating operating system performance- power optimization strategies for processes –
Example Real time operating systems-POSIX-Windows CE. - Distributed embedded systems –
MPSoCs and shared memory multiprocessors. – Design Example - Audio player, Engine control
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unit – Video accelerator.
TOTAL : 45 PERIODS
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Course Outcomes:
At the end of the course, the student will be able to:
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Summarize Architecture and programming of ARM processor.
Applying the concepts of embedded systems and its features.
Analyze various Real Time Operating system is used in Embedded System.
Design the flow &Techniques to develop Software for embedded system networks.
Analyze Real-time applications using embedded System Products.
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TEXT BOOK:
1. Marilyn Wolf, “Computers as Components - Principles of Embedded Computing System
Design”, Third Edition “Morgan Kaufmann Publisher (An imprint from Elsevier), 2012.
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(UNIT I, II, III, V)
2. Jane W.S.Liu,‖ Real Time Systems‖, Pearson Education, Third Indian Reprint, 2003.(UNIT
IV) pa
REFERENCES:
1. Lyla B.Das, ―Embedded Systems : An Integrated Approach‖ Pearson Education, 2013.
2. Jonathan W.Valvano, “Embedded Microcomputer Systems Real Time Interfacing”, Third
Edition Cengage Learning, 2012.
3. David. E. Simon, “An Embedded Software Primer”, 1st Edition, Fifth Impression, Addison-
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Wesley Professional, 2007.
4. Raymond J.A. Buhr, Donald L.Bailey, “An Introduction to Real-Time Systems- From Design
to Networking with C/C++”, Prentice Hall, 1999.
5. C.M. Krishna, Kang G. Shin, “Real-Time Systems”, International Editions, Mc Graw Hill 1997
6. K.V.K.K.Prasad, “Embedded Real-Time Systems: Concepts, Design & Programming”, Dream
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Tech Press, 2005.
7. Sriram V Iyer, Pankaj Gupta, “Embedded Real Time Systems Programming”, Tata Mc Graw
Hill, 2004.
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1. Wayne Wolf, “Computers as Components – Principles of
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Embedded Computing System Design”, Third Edition “Morgan
Kaufmann Publisher (An imprint from Elsevier), 2012.
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UNIT I
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INTRODUCTION TO EMBEDDEDSYSTEM DESIGN
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Complex systems and microprocessors– Embedded system design process
–Design example: Model train controller- Design methodologies- Design
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flows - Requirement Analysis – Specifications-System analysis and
architecture design – Quality Assurance techniques - Designing with
computing platforms – consumer electronics architecture – platform-
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level performance analysis.
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Introduction--Embedded Systems
Introduction
An Embedded system is an electronic system that has a software and is
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embedded in computer hardware.
It is a system which has collection of components used to execute a task
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according to a program or commands given to it.
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Examples Microwave ovens, Washing machine, Telephone answering
machine system, Elevator controller system, Printers, Automobiles,
Cameras, etc.
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Components of Embedded system
Microprocessor
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Memory Unit(RAM,ROM)
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Input unit(Keyboard,mouse,scanner)
Output unit(pinters,video monitor)
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Networking unit(Ethernet card)
I/O units(modem)
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Real Time Operating System
ystem--RTOS
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Real-Time Operating System (RTOS) is an operating system (OS)
intended to serve real-time applications that process data as it comes
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in, typically without buffer delays.
It schedules their working and execution by following a plan to control
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the latencies and to meet the dead lines.
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Modeling and evaluation of a real-time scheduling system concern is
on the analysis of the algorithm capability to meet a process deadline.
A deadline is defined as the time required for a task to be processed.
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Classification of Embedded system
1. Small scale Embedded system(8/16bit microcontroller)
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2. Medium Scale Embedded system (16/32bit microcontroller,
more tools like simulator, debugger)
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3. Sophisticated Embedded system (configurable processor and PAL)
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Embedded designer-
designer-skills
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Designer has a knowledge in the followings field,
Microcontrollers, Data comm., motors, sensors, measurements ,C
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programming, RTOS programming.
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1) COMPLEX SYSTEMS AND MICROPROCESSORS
Embedded(+)computer system
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Embedded system is a complex system
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It is any device that includes a programmable computer but is not
itself intended to be a general-purpose computer.
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History of Embedded computer system
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Computers have been embedded into applications since the earliest days of
computing.
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In 1940s and 1950sWhirlwind, designed a first computer to support real-time
operation for controlling an aircraft simulator.
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In 1970s The first microprocessor( Intel 4004) was designed for an embedded
application (Calculator), provided basic arithmetic functions.
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In 1972s The first handheld calculator (HP-35 ) was to perform
transcendental functions , so it used several chips to implement the CPU,
rather than a single-chip microprocessor.
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Designer faced critical problems to design a digital circuits to perform
operations like trigonometric functions using calculator.
But ,Automobile designers started making use of the microprocessor for to
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control the engine by determining when spark plugs fire, controlling the
fuel/air mixture
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Levels of Microprocessor
1. 8-bit microcontroller for low-cost applications and includes on-board
memory and I/O devices.
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2. 16-bit microcontroller used for more sophisticated applications that may
require either longer word lengths or off-chip I/O and memory.
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3. 32-bit RISC microprocessor offers very high performance for
computation-intensive applications.
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Microprocessor Uses/Applications
Microwave oven has at least one microprocessor to control oven operation
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Thermostat systems, which change the temperature level at various times during
the day
The modern camera is a prime example of the powerful features that can be
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added under microprocessor control.
Digital television makes extensive use of embedded processors.
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Embedded Computing Applications
Ex
ExBMW 850i Brake and Stability Control System
The BMW 850i was introduced with a sophisticated system for controlling the
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wheels of the car.
Which uses An antilock brake system (ABS) and An automatic stability
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control (ASC +T) system.
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1. An antilock brake system (ABS)
Reduces skidding by pumping the brakes.
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It is used to temporarily release the brake on a wheel when it rotates
too slowly—when a wheel stops turning, the car starts skidding and
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becomes hard to control.
It sits between the hydraulic pump, which provides power to the
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brakes.
It uses sensors on each wheel to measure the speed of the wheel.
The wheel speeds are used by the ABS system to determine how to vary
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the hydraulic fluid pressure to prevent the wheels from skidding.
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2. An automatic stability control (ASC +T) system
It is used to control the engine power and the brake to improve the car’s
stability during maneuvers.
It controls four different systems: throttle, ignition timing, differential
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brake, and (on automatic transmission cars) gear shifting.
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It can be turned off by the driver, which can be important when
operating with tire snow chains.
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It has control unit has two microprocessors , one of which concentrates
on logic-relevant components and the other on performance-specific
components.
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The ABS and ASC+ T must clearly communicate because the ASC+ T
interacts with the brake system.
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Characteristics of Embedded Computing
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Applications
1. Complex algorithms-The microprocessor that controls an automobile engine
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must perform complicated filtering functions to optimize the performance of
the car while minimizing pollution and fuel utilization.
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2. User interface-The moving maps in Global Positioning System (GPS)
navigation are good examples of user interfaces.
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3. Real time-Embedded computing systems have to perform in real time—if the
data is not ready by a certain deadline,the system breaks. In some cases, failure
to meet a deadline or missing a deadline does not create safety problems but
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does create unhappy customers
4. Multirate-Multimedia applications are examples of multirate behavior.
The audio and video portions of a multimedia stream run at very different
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rates, but they must remain closely synchronized. Failure to meet a deadline
on either the audio or video portions spoils the perception of the entire
presentation.
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5. Manufacturing cost- It is depends on the type of microprocessor used, the
amount of memory required, and the types of I/O devices.
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6. Power and energy-Power consumption directly affects the cost of the
hardware, since a larger power supply may be necessary.
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7. Energy consumption affects battery life, which is important in many
applications, as well as heat consumption, which can be important even in
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desktop applications.
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Why Use Microprocessors?
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Microprocessors are a very efficient way to implement digital systems.
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It make it easier to design families of products with various feature at
different price points
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It can be extended to provide new features to keep up with rapidly
changing markets.
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It executes program very efficiently
It make their CPU run very fast
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Implementing several function on a single processor
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Why not use PCs for all embedded
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computing?
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Real time performance is very less in PC because of
different architecture.
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It increases the complexity and price of components due to
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broad mix of computing requirements.
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Challenges in Embedded Computing System Design
1. How much hardware do we need?
To meet performance deadlines and manufacturing cost constraints, the choice of
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Hardware is important.
Too much hardware and it becomes too expensive.
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2. How do we meet deadlines?
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To speed up the hardware so that the program runs faster. But the system more
expensive.
It is also entirely possible that increasing the CPU clock rate may not make
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enough difference to execution time, since the program’s speed may be limited by
the memory system.
3. How do we minimize power consumption?
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In battery-powered applications, power consumption is extremely important.
In non-battery applications, excessive power consumption can increase heat
dissipation.
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Careful design is required to slow down the noncritical parts of the machine for
power consumption while still meeting necessary performance goals.
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4) How do we design for upgradability?
The hardware platform may be used over several product generations,or for
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several different versions ,able to add features by changing software.
4.1) Complex testing: Run a real machine in order to generate the proper data.
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Testing of an embedded computer from the machine in which it is embedded.
4.2) Limited observability and controllabilityNo keyboard and screens, in real-
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time applications we may not be able to easily stop the system to see what is
going on inside and to affect the system’s operation.
4.3) Restricted development environments:
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We generally compile code on one type of machine, such as a PC, and
download it onto the embedded system.
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To debug the code, we must usually rely on programs that run on the PC or
workstation and then look inside the embedded system.
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Performance in Embedded Computing
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Embedded system designers have to set their goal —their program must meet its
deadline.
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Performance Analysis
1. CPU: The CPU clearly influences the behavior of the program, particularly when
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the CPU is a pipelined processor with a cache.
2. Platform: The platform includes the bus and I/O devices. The platform
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components that surround the CPU are responsible for feeding the CPU and can
dramatically affect its performance.
3. Program: Programs are very large and the CPU sees only a small window of the
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program at a time. We must consider the structure of the entire program to
determine its overall behavior.
4. Task: We generally run several programs simultaneously on a CPU, creating a
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multitasking system. The tasks interact with each other in ways that have profound
implications for performance.
5. Multiprocessor: Many embedded systems have more than one processor—they
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may include multiple programmable CPUs as well as accelerators. Once again, the
interaction between these processors adds yet more complexity to the analysis of
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overall system performance.
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2)EMBEDDED SYSTEM DESIGN PROCESS
Design process has two objectives as follows.
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1. It will give us an introduction to the various steps in embedded system
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design.
2. Design methodology
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I. Design to ensure that we have done everything we need to do, such as
optimizing performance or performing functional tests.
II. It allows us to develop computer-aided design tools.
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III. A design methodology makes it much easier for members of a design
team to communicate.
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Levels of abstraction in the design process.
1)Requirements
•It can be classified in to functional or nonfunctional
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1.1)Functional Requirements
•Gather an informal description from the customers.
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•Refine the requirements into a specification that contains
enough information to design the system architecture.
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•Ex:Sample Requirements form
•NameGiving a name to the project
PurposeBrief one- or two-line description of what the system
is supposed to do.
Mechanical inputs?
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•Inputs& Outputs Analog electronic signals? Digital data?
•Functions detailed description of what the system does
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Performance computations must be performed within a
certain time frame
•Manufacturing cost cost of the hardware components.
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Power how much power the system can consume
Physical size and weight indication of the physical size
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of the system
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1.2) Non-Functional Requirements
Performance depends upon approximate time to perform a user-
level function and also operation must be completed within deadline.
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CostManufacturing cost includes the cost of components and
assembly.
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• Nonrecurring engineering (NRE) costs include the personnel and other
costs of designing the
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system
Physical Size and WeightThe final system can vary depending upon
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the application.
Power ConsumptionPower can be specified in the requirements stage
in terms of battery life.
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2)SPECIFICATION
The specification must be carefully written so that it accurately reflects the
customer’s requirements.
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It can be clearly followed during design.
3) Architecture Design
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The architecture is a plan for the overall structure of the system.
It is in the form block diagram that shows a major operation and data flow.
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4) Designing Hardware and Software Components
The architectural description tells us what components we need include both
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hardware—FPGAs, boards & software modules
5)System Integration
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Only after the components are built, putting them together and seeing a
working system.
Bugs are found during system integration, and good planning can help us find
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the bugs quickly.
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Embedded system Design Example
GPS moving map
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Design Process Steps
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1. Requirements analysis of a GPS moving map
The moving map is a handheld device that displays for the user a map of the
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terrain around the user’s current position.
The map display changes as the user and the map device change position.
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The moving map obtains its position from the GPS, a satellite-based navigation
system.
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Name GPS moving map
Purpose Consumer-grade moving map for driving use
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Inputs Power button, two control buttons
Outputs Back-lit LCD display 400 600
Functions Uses 5-receiver GPS system; three user-selectable
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resolutions;always displays current latitude and
longitude
Performance Updates screen within 0.25 seconds upon movement
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Manufacturing cost $30
Power 100mW
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Physical size and No more than 2”X 6, ” 12 ounces
weight
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Design Process Steps
2) FunctionalityThis system is designed for highway driving and similar uses.
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The system should show major roads and other landmarks available in
standard topographic databases.
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3)User interfaceThe screen should have at least 400X600 pixel resolution. The
device should be controlled by no more than 3 buttons.
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A menu system should pop up on the screen when buttons are
pressed to allow the user to make selections to control the system.
4)Performance The map should scroll smoothly.
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Upon power-up, a display should take no more than 1sec to appear.
The system should be able to verify its position and display the
current map within 15 s.
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5)Cost The selling cost of the unit should be no more than $100.
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6)Physical size and weightThe device should fit comfortably in the palm of the
hand.
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7) Power consumption The device run for at least 8 hrs on 4 AA batteries.
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8) specification
1. Data received from the GPS satellite constellation.
2. Map data.
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3. User interface.
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4. Operations that must be performed to satisfy customer requests.
5. Background actions required to keep the system running, such as
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operating the GPS receiver.
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Block Diagram
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Hardware architecture
•one central CPU surrounded by
memory and I/O devices.
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• It used two memories: a frame buffer
for the pixels to be displayed and a
separate program/data memory for
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general use by the CPU.
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Software architecture
•Timer to control when we read the buttons
on the user interface and render data onto
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the screen.
•Units in the software block diagram will be
executed in the hardware block diagram and
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when operations will be performed in time.
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3)FORMALISM FOR SYSTEM DESIGN
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UML(Unified Modeling Language) is an object-oriented modeling language
used to capture all these design tasks.
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It encourages the design to be described as a number of interacting objects,
rather than blocks of code.
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objects will correspond to real pieces of software or hardware in the system.
It allows a system to be described in a way that closely models real-world
objects and their interactions.
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Classification of descriptor
3.1)Structural Description
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3.2)Behavioral Description
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3.1)Structural Description
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It gives basic components of the system and designers can learn how to
describe these components in terms of object.
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3.1.1) OBJECT in UML NOTATION
An object includes a set of attributes that define its internal state.
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An object describing a display (CRT screen) is shown in UML notation in
Figure.
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The object has a unique name, and a member of a class.
The name is underlined to show that this is a description of an object and not
of a class.
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The text in the folded-corner page icon is a note.
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An object in UML notation
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3.1.2)CLASS IN UML NOTATION
All objects derived from the same
class have the same characteristics,
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but attributes may have different
values.
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It also defines the operations that
determine how the object interacts
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with the rest of the world.
It defines both the interface for a
particular type of object and that
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object’s implementation.
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Relationships between objects and classes
1. Association occurs between objects that communicate with each other but
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have no ownership relationship between them.
2. Aggregation describes a complex object made of smaller objects.
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3. Composition It is a type of aggregation in which the owner does not allow
access to the component objects.
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4. Generalization allows us to define one class in terms of another.
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Derived classes as a form of generalization in UML
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•A derived class is defined to include all the
attributes of its base class.
• Display is the base class and BW display and
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color map display are the two derived classes.
•BW display represents black and white display.
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Multiple inheritance in UML
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•UML allows to define multiple inheritance, in which a class is derived from more
than one base class.
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•Multimedia display class by combining the Display class with a Speaker class for
sound.
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•The derived class inherits all the attributes and operations of both its base classes,
Display and Speaker.
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•
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Links and Association
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A link describes a relationship between objects and association is to
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link as class is to object.
Links used to make to stand associations capture type information
about these links.
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The association is drawn as a line between the two labeled with the
name of the association, namely, contains.
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3.2)Behavioral Description
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Behavior of an operation is specified by a state machine.
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These state machines will not rely on the operation of a clock.
Changes from one state to another are triggered by the occurrence of
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events.
The event may generated from the outside or inside of the system.
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Signal, call, and time-out events in UML.
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Signal is an asynchronous occurrence.
It is defined in UML by an object that is labeled as a <<signal>>.
Signal may have parameters that are passed to the signal’s receiver.
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Call event follows the model of a procedure call in a programming
language.
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Time-out event causes the machine to leave a state after a certain
amount of time.
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The label tm(time-value) on the edge gives the amount of time after
which the transition occurs.
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It is implemented with an external timer.
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State Machine specification in UML
The start and stop states are special states which organize the flow of the state
machine.
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The states in the state machine represent different operations.
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Conditional transitions out of states based on inputs or results of some
computation.
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An unconditional transition to the next state.
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Sequence diagram in UML
Sequence diagram is similar to a hardware timing diagram, although the time
flows vertically in a sequence diagram, whereas time typically flows horizontally
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in a timing diagram.
It is designed to show particular choice of events—it is not convenient for
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showing a number of mutually exclusive possibilities.
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4) Design:Model Train Controller
In order to learn how to use UML to model systems specify a simple system
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(Ex: model train controller)
The user sends messages to the train with a control box attached to the tracks.
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The control box may have controls such as a throttle, emergency stop button,
and so on.
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The train Rx its electrical power from the two rails of the track.
CONSOLE
Each packet includes an address so that the console can control several trains
on the same track.
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The packet also includes an error correction code (ECC) to guard against
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transmission errors.
This is a one-way communication system—the model train cannot send
commands back to the user.
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Model Train Control system
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REQUIREMENTS
The console shall be able to control up to eight trains on a single track.
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The speed of each train controllable by a throttle to at least 63 different
levels in each direction (forward and reverse).
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There shall be an inertia control to adjust the speed of train.
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There shall be an emergency stop button.
An error detection scheme will be used to transmit messages.
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Requirements:Chart Format
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Name Model train controller
Purpose Control speed of up to eight model trains
Inputs Throttle, inertia setting, emergency stop, train
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number
Outputs Train control signals
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Functions Set engine speed based upon inertia settings;
respond
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Performance Can update train speed at least 10 times per second
Manufacturing cost $50
Power 10W
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Physical size and weight Console should be comfortable for two
hands,approximatesize of standard
keyboard;
weight 2 pounds
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Digital Command Control (DCC)
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Standard S-9.1 how bits are encoded on the rails for transmission.
Standard S-9.2 defines the packets that carry information.
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The signal encoding system should not interfere with power transmission
Data signal should not change the DC value of the rails.
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Bits are encoded in the time between transitions.
Bit 0 is at least 100 s while bit 1 is nominally 58 s.
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Packet Formation in DCC
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The basic packet format is given by
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P preamble, which is a sequence of at least 10 1 bits.
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S packet start bit. It is a 0 bit.
A address is 8 bits long. The addresses 00000000, 11111110, and 11111111 are
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reserved.
s data byte start bit, which, like the packet start bit, is a 0.
D data byte includes 8 bits. A data byte may contain an address, instruction,
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data, or error correction information.
E packet end bit, which is a 1 bit.
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Baseline packet
The minimum packet that must be accepted by all DCC implementations.
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It has three data bytes.
Address data byte gives the intended receiver of the packet
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Instruction data byte provides a basic instruction
Error correction data byte is used to detect and correct transmission errors.
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Date byte
Bits 0–3 provide a 4-bit speed value.
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Bit 4 has an additional speed bit.
Bit 5 gives direction, with 1 for forward and 0 for reverse.
Bits 6-7 are set at 01 provides speed and direction.
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Conceptual Specification
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Conceptual specification allows us to understand the system a little better.
A train control system turns commands into packets.
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A command comes from the command unit while a packet is transmitted over the
rails.
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Commands and packets may not be generated in a 1-to-1 ratio
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UML collaboration diagram for train
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controller system
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The command unit and receiver are each represented by objects.
The command unit sends a sequence of packets to the train’s receiver, as
illustrated by the arrow messages as 1..n.
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Those messages are of course carried over the track.
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UML class diagram for the train controller
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Basic characteristics of UML classes
Console class describes the command unit’s front panel, which contains
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the analog knobs and hardware to interface to the digital parts of the system.
Formatter class includes behaviors that know how to read the panel knobs and creates a
bit stream for the required message.
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Transmitter class interfaces to analog electronics to send the message along the track
Knobs* describes the actual analog knobs, buttons, and levers on the control panel.
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Sender* describes the analog electronics that send bits along the track.
Receiver class knows how to turn the analog signals on the track into digital form.
Controller class includes behaviors that interpret the commands and figures out how to
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control the motor.
Motor interface class defines how to generate the analog signals required to control the
motor.
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Detector* detects analog signals on the track and converts them into digital form.
Pulser* turns digital commands into the analog signals required to control the motor
speed.
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Detailed Specification
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•The Panel has three knobs
• train number (which train is currently
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being controlled).
•speed (which can be positive or negative),
and inertia.
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•It also has one button for emergency-
stop.
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•When we change the train number
setting, to reset the other controls to the
proper values for that train.
• so that the previous train’s control
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settings are not used to change the current
train’s settings.
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Class diagram for panel
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•The Panel class defines a behavior for each of the controls on the panel.
• The new-settings behavior uses the set-knobs behavior of the Knobs*
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•Change the knobs settings whenever the train number setting is changed.
•The Motor-interface defines an attribute for speed that can be set by other
classes.
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Class diagram for the Transmitter and Receiver
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•They provide the software interface to the physical devices that send
and receive bits along the track.
•The Transmitter provides a behavior message that can be sent
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• The Receiver class provides a read-cmd behavior to read a message off
the tracks.
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Class diagram for Formatter
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The formatter holds the current control settings for all of the trains.
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The send-command serves as the interface to the transmitter.
The operate function performs the basic actions for the object.
The panel-active behavior returns true whenever the panel’s values do not
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correspond to the current values
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Class diagram for Controller
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•The Controller’s operate behavior must execute several behaviors to
determine the nature of the message.
•Once the speed command has been parsed, it must send a sequence of
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commands to the motor to smoothly change the train’s speed.
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Sequences diagram for transmitting a
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control input
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Sequence diagram
specify the interface
between more than one
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classes.
Its detailed operations
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and what ways its going
to operate
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1.4DESIGN METHODOLOGIES
Design of Embedded system is not an easy task.
The main goal of a design process is to create a product that does something useful.
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Typical specifications for a product are functionality , manufacturing cost, performance and
power consumption.
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Design process has several important goals as follows
Time-to-market
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Customers always want new features.
The product that comes out first can win the market, even setting customer preferences for
future generations of the product.
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Design cost
Consumer products are very cost sensitive, and it is distinct from manufacturing cost.
Design costs can dominate manufacturing costs.
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Design costs can also be important for high-volume consumer devices when time-to-market
pressures cause teams to swell in size.
Quality
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Customers want their products fast and cheap.
Correctness, reliability, and usability must be explicitly addressed from the beginning of the
design job to obtain a high-quality product at the end
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1.5Design flows
A design flow is a sequence of steps to be followed during a design.
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Some of the steps can be performed by tools and other steps can be performed by hand.
Types of Software development models
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1. Waterfall model
2. Spiral model
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3. Successive refinement development model
4. Hierarchical design model
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1.5.1)Waterfall model
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The waterfall development model consists of five major phases.
Requirements analysis determines the basic characteristics of the system.
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Architecture designIt decomposes the functionality into major components
CodingIt implements the pieces and integrates them.
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TestingIt detemines bugs.
Maintenance It entails deployment in the field, bug fixes,and upgrades.
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The waterfall model makes work flow information from higher levels of abstraction to
more detailed design steps.
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1.5.2)Spiral model
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The spiral model assumes that several versions of the
system will be built.
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Each level of design, the designers go through
requirements,construction,and testing phases.
At later stages when more complete versions of the
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system are constructed.
Each phase requires more work, widening the design
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spiral.
The first cycles at the top of the spiral are very small
and short.
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The final cycles at the spiral’s bottom add detail
learned from the earlier cycles of the spiral.
The spiral model is more realistic than the waterfall
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model because multiple iterations needed to
complete a design.
But too many spirals may take long time required for
design.
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1.5.3)Successive refinement design model
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In this approach, the system is built several times.
A first system is used as a rough prototype.
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Embedded computing systems are involved the design of hardware/software project.
Front-end activities are specification and architecture and also includes hardware and
software aspects.
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Back-end activities includes integration and testing.
Middle activitiesincludes hardware and software development.
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1.5.4)Hierarchical design flow
Many complex embedded systems are built of smaller designs.
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The complete system may require the design of significant software
components.
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It has many levels of abstraction to design flows for individual components.
The implementation phase contains a complete flow from specification
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through testing.
Each flow will probably be handled by separate people or teams.
The teams must rely on each other’s results.
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The component teams take their requirements from team handling the next
higher level of abstraction.
The higher-level team relies on the quality of design and testing performed by
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the component team.
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1.5.5) Concurrent engineering
Reduced design time is an important goal for concurrent engineering.
It eliminate “over-the-wall” design steps, one designer performs an isolated task and then
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throws the result to the next designer.
Concurrent engineering efforts are comprised of several elements.
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Cross-functional teams include members from various disciplines ( manufacturing,
hardware and software design, marketing)
Concurrent product realize the process activities .
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Designing various subsystems simultaneously, is reducing design time.
Integrated project managementensures that someone is responsible for the entire project.
Early and continual supplier make the best use of suppliers’ capabilities.
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Early and continual customer ensure that the product meets customers’ needs.
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Concurrent Engineering Applied to Telephone Systems
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1. Benchmarking They compared themselves to competitors and found that it took
them 30% longer to introduce a new product than their best competitors.
2. Breakthrough improvement.
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Increased partnership between design and manufacturing.
Continued existence of the basic organization of design labs and manufacturing.
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Support of managers at least two levels above the working level.
3. Characterization of the current process.
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Too many design and manufacturing tasks were performed sequentially.
4. Create the target process The core team created a model for the new development
process.
5. Verify the new process test the new process.
6.
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Implement across the product lineThis activity required training of personnel,
documentation of the new standards and procedures, and improvements to information
systems.
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7. Measure results and improvePerformance of the new design was measured.
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1.6REQUIREMENTS ANALYSIS
RequirementsIt is a informal descriptions of what the customer wants.
A functional requirement states what the system must do.
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A nonfunctional requirementIt can be physical size, cost, power consumption, design
time, reliability, and so on.
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Requirements of tests
CorrectnessRequirements should not mistakenly describe what the customer wants.
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UnambiguousnessRequirements document should be clear and have only one plain
language interpretation.
Completeness Requirements all should be included.
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Verifiability cost-effective way to ensure that each requirement is satisfied in the final
product.
ConsistencyOne requirement should not contradict another requirement.
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ModifiabilityThe requirements document should be structured so that it can be
modified to meet changing requirements without losing consistency.
TraceabilityAble to trace forward /backward from the requirements.
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1.7)SPECIFICATIONS
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SpecificationsIt is a detailed
descriptions of the system that can
be used to create the architecture.
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Control-oriented specification languages
SDL specifications include states,
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actions, and both conditional and
unconditional transitions between
states.
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SDL is an event-oriented state
machine model.
State chart has some important
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concepts.
State charts allow states to be
grouped together to show common
functionality.
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Basic groupings(OR)
State machine specifies that the machine goes to state s4 from any of s1, s2, or s3 when
they receive the input i2.
The State chart denotes this commonality by drawing an OR state around s1, s2, and s3 .
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Single transition out of the OR state s123 specifies that the machine goes to s4 when it
receives the i2 input while in any state included in s123.
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Multiple ways to get into s123 (via s1 or s2), and transitions between states within the OR
state (from s1 to s3 or s2 to s3).
The OR state is simply a tool for specifying some of the transitions relating to these
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states.
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Basic groupings(AND)
In the State chart, the AND state sab is decomposed into two components, sa and sb.
When the machine enters the AND state, it simultaneously inhabits the state s1 of
component sa and the state s3 of component sb.
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When it enters sab, the complete state of the machine requires examining both sa and sb.
State s1-3 in the State chart machine having its sa component in s1 and its sb component in
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s3.
When exit from cluster states go to s5 only when in the traditional specification, we are in
state s2-4 and receive input r.
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1.7.1)Advanced specifications
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It ensure the correctness and safety of this system.
Ex Traffic Alert and Collision Avoidance System(TCAS)
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It is a collision avoidance system for aircraft.
TCAS unit in an aircraft keeps track of the position of other nearby aircraft.
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It uses pre-recorded voice (“DESCEND!) commands for mid-air collision.
TCAS makes sophisticated decisions in real time and is clearly safety critical.
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It must detect as many potential collision events as possible .
It must generate a few false alarms ,at extreme maneuvers in potentially dangerous.
TCAS-II specification(RSML Language) Transition states
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Collision Avoidance system
The system has Power-off and Power-on states .
In the power on state, the system may be in Standby or Fully operational mode.
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In the Fully operational mode, three components are operating in parallel, as specified
by the AND state.
The own aircraft subsystem to keep track of up to 30 other aircraft.
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Subsystem to keep track of up to 15 Mode S ground stations, which provide radar
information.
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1.8SYSTEM ANALYSIS AND ARCHITECTURE DESIGN
The CRC card methodology analyze and understanding the overall structure of a complex
system.
CRC cards
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Classes define the logical groupings of data and functionality.
Responsibilities describe what the classes do.
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Collaborators are the other classes with which a given class works.
It has space to write down the class name, its responsibilities and collaborators, and other
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information.
Layout of CRC card
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A class may represent a real-world object of the system.
A class has both an internal state and a functional interface.
The functional interface describes the class’s capabilities.
The responsibility set is describing that functional interface.
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The collaborators of a class are simply the classes that it talks or calls upon to help it do its
work.
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CRC card Analysis Process
1. Develop an initial list of classesWrite down the class name and functions of it.
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2. Write an initial list of responsibilities and collaborators.
3. Create some usage scenariosdescribe what the system does.
4. Walk through the scenariosEach person on the team represents one or more classes.
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5. Refine the classes, responsibilities, and collaborators make changes to the CRC cards.
6. Add class relationships subclass and super-class can be added to the cards.
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Ex:Elevator system
1. One passenger requests a car on a floor, gets in the car when it arrives, requests
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another floor, and gets out when the car reaches that floor.
2. One passenger requests a car on a floor, gets in the car when it arrives, and
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requests the floor that the car is currently on.
3. A second passenger requests a car while another passenger is riding in the
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elevator.
4. Two people push floor buttons on different floors at the same time.
5. Two people push car control buttons in different cars at the same time.
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1.9) Quality Assurance techniques(QA
techniques(QA))
The quality assurance (QA) process is vital for the delivery of a satisfactory system.
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International Standards Organization (ISO) has created a set of quality standards known as
ISO 9000.
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It was created to apply to a broad range of industries, including limited to embedded
hardware and software.
ISO 9000 quality management parameters
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Process is crucialKnowing what steps are to be followed to create a high-quality product.
Documentation is importanthelps internal quality monitoring groups to ensure that the
required processes and helps outside groups understand the processes and how they are
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being implemented.
Communication is important people should understand not only their specific tasks but
also how their jobs can affect overall system quality.
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Capability Maturity Model (CMM)
It is used to measuring the quality of an organization’s software development.
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1. InitialA poorly organized process, with very few well-defined processes.
Success of a project depends on the efforts of individuals, not the organization
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itself.
2. Repeatable provides basic tracking mechanisms to understand cost,
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scheduling .
3. DefinedThe management and engineering processes are documented and
standardized.
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4. Manageddetailed measurements of the development process and product
quality.
5. Optimizingfeedback from detailed measurements is used to continually
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improve the organization’s processes.
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Verifying the specificationDiscovering bugs early is crucial because it prevents bugs
from being released to customers, minimizes design costs, and reduces design time.
Validation of specificationscreating the requirements, including correctness,
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completeness, consistency, and so on
Design reviews
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The review leader coordinates the pre-meeting activities, the design review itself,
and the post-meeting follow-up.
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The reviewer records the minutes of the meeting so that designers and others know
which problems need to be fixed.
The review audience studies the component.
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1.10 DESIGNING WITH COMPUTING PLATFORM
1.10.1 System Architecture
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The architecture of an embedded computing system includes both hardware
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and software elements
HARDWARE
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CPU The choice of the CPU is one of the most important, but it can be
considered the software that will execute on the machine.
Bus The choice of a bus is closely tied to that of a CPU,bus can handle the
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traffic.
MemorySelection depends total size and speed of the memory will play a
large part in determining system performance.
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Input and output devices Dependig upon the system requirements
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SOFTWARE
Run Time components
It is a critical part of the platform.
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An operating system is required to control CPU and its multiple
processes .
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A file system is used in many embedded systems to organize internal
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data and interface with other systems
Support components
It is a complex hardware platform.
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Without proper code development and operating system, the hardware
itself is useless.
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ARM evaluation board
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1.10.2)The PC as a Platform
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CPU provides basic computational facilities.
RAM is used for program storage.
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ROMholds the boot program.
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DMAcontroller provides DMA capabilities.
Timers used by the operating system for a variety of purposes.
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High-speed busconnected to the CPU bus through a bridge, allows
fast devices to communicate with the rest of the system.
low-speed bus provides an inexpensive way to connect simpler
devices.
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1.10.3 Development Environments
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Development process used to make a complete design
of the system.
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It guides the developers how to design a system .
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An embedded computing system has CPU ,memory, I/O
devices.
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Development of embedded system have both hardware&
software.
The software development on a PC or workstation known
as a host.
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•The host and target are frequently connected by a USB link.
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•The target must include a small amount of software to talk to the host
system.
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Functions of Host system
Load programs into the target
Start and stop program execution on the target
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Examine memory and CPU registers.
Cross-Compiler
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Compiler kind of software that translate one form of pgm to another form of
pgm.
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Cross Compileris a compiler that runs on one type of machine but generates
code for another
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After compilation, the executable code is downloaded to the embedded system
by a serial link.
A PC or workstation offers a programming environment .
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But one problem with this approach emerges when debugging code talks to I/O
devices.
Testbench program can be built to help debug the embedded code.
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It may also take the output values and compare them against expected values.
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1.10.4Debugging Techniques
It is the process of checking errors and correcting those errors.
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It can be done by compiling and executing the code on a PC or workstation.
It can be performed by both H/W and S/W sides.
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Software debugging tools
1. Serial Port tool
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It will perform the debugging process from the initial state of embedded system
design.
It can be used not only for development debugging but also for diagnosing
problems in the field.
2. Breakpoints tool
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user to specify an address at which the program’s execution is to break.
When the PC reaches that address, control is returned to the monitor program.
From the monitor program, the user can examine and/or modify CPU registers,
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Breakpoint is a location in memory at which a program stops executing and
returns to the debugging tool or monitor program.
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To establish a breakpoint at location 0x40c in some ARM code, replaced the branch
(B) instruction with a subroutine call (BL) to the breakpoint handling routine
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Hardware debugging tools
Hardware can be deployed to give a clearer view on what is happening when the
system is running.
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1. Microprocessor In-Circuit Emulator (ICE)
It is a specialized hardware tool that can help debug software in a working
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embedded system.
In-circuit emulator is a special version of the microprocessor that allows its
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internal registers to be read out when it is stopped
2. Logic Analyer
The analyzer can sample many different signals simultaneously but can display
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only 0, 1, or changing values for each.
The logic analyzer records the values on the signals into an internal memory
and then displays the results on a display once the memory is full.
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Architecture of a logic analyzer
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Data modes of logic analyzer
State modes
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State mode represent different ways of sampling the values.
It uses the own clock to control sampling
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It samples each signal only one per clock cycle.
It has less memory to store a given number of system clock.
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Timing modes
Timing mode uses an internal clock that is fast enough to take several samples
per clock period in a typical system.
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1.10.5)Debugging Challenges
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Logical errors in software can be hard to track down and it will create
many problems in real time code.
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Real-time programs are required to finish their work within a certain
amount of time.
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Run time pgm run too long, they can create very unexpected behavior.
Missing of Deadline makes debugging process as difficult.
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1.11 Consumer Electronic Architecture
Consumer electronic refers to any device containing an electronic circuit board
that is intended for eneryday use by individuals.
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EgTV,cameras,digital cameras,calculators,DVDs,audio devices,smart phones
etc..,
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1.11..1)Functional Requirements
1. Multimedia
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The media may be audio, still images, or video.
These multimedia objects are generally stored in compressed form and must be
uncompressed to be played .
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Eg multimedia compression standards (MP3,Dolby Digital(TM))
audio; JPEG for still images; MPEG-2, MPEG-4, H.264, etc. for video.
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2. Data storage and management People want to select what multimedia objects
they save or play, data storage goes hand-in-hand with multimedia capture and
display. Many devices provide PC-compatible file systems so that data can be
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3. Communications Communications may be relatively simple, such as a USB
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and another is Ethernet port or a cellular telephone link.
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1.11.2)Non-Functional Requirements
Many devices are battery-operated, which means that they must operate under
strict energy budgets.
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Battery(75mW) support not only the processors but also the display, radio,
etc.
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Consumer electronics must also be very inexpensive but provide very high
performance.
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Use case for playing multimedia
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use case for selecting and playing a multimedia object (audio clip, a picture,etc.).
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Selecting an object makes use of both the user interface and the file system.
Playing also makes use of the file system as well as the decoding subsystem and
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I/O subsystem.
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Use case of synchronizing with a host
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system
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use case for connecting to a client.
The connection may be either over a local connection like USB or over the
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Internet.
Some operations may be performed locally on the client device
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most of the work is done on the host system while the connection is
established
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1.11.3)Functional architecture of
Consumer Electronics Device(CED)
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It is a two-processor architecture.
If more computation is required, more DSPs and CPUs may be added.
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The RISC-CPU runs the operating system, runs the user interface, maintains
the file system, etc.
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DSP it is a programmable one, which performs signal processing.
Operating system runs on the CPU must maintain processes and the file
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system.
Depending on the complexity of the device, the operating system may not need
to create tasks dynamically.
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If all tasks can be created using initialization code, the operating system can be
made smaller and simpler.
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1.11.4 Flash File Systems
Many consumer electronics devices use flash memory for mass storage.
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Flash memory is a type of semiconductor memory ,unlike DRAM or
SRAM, provides permanent storage.
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Values are stored in the flash memory cell as electric charge using a
specialized capacitor that can store the charge for years.
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The file system of a device is typically shared with a PC.
Standard file systemhas two layers.bottom layer handles physical
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reads and writes on the storage device and the top layer provides a
logical view of the file system.
Flash file systemimposes an intermediate layer that allows the logical-
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to-physical mapping of files to be changed.
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1.12 Platform-
Platform-Level Performance Analysis
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System-Level Performance involves much more than the CPU.
To move data from memory to the CPU to process it. To get the data from
memory to the CPU we must.
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1. Read from the memory.
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2. Transfer over the bus to the cache.
3. Transfer from the cache to the CPU.
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The performance of the system based on Bandwidth of the system.
We can increase bandwidth in two ways:
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1) By increasing the clock rate of the bus
2) By increasing the amount of data transferred per clock cycle.
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For example, bus to carry four bytes or 32 bits per transfer, we would reduce
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the transfer time to 0.058 s. If we also increase the bus clock rate to 2 MHz,
then we would reduce the transfer time to 0.029 s ,which is within our time
budget for the transfer.
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tbus cycle counts
Tbus cycles.
pbus clock period
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1.12.1Parallelism
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Direct memory access is a example of parallelism.
DMA was designed to off-load memory transfers from the CPU.
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The CPU can do other useful work while the DMA transfer is running.
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.c
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UNIT II
.c
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ARM PROCESSOR AND PERIPHERALS
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ARM Architecture Versions – ARM Architecture – Instruction Set
– Stacks and Subroutines – Features of the LPC 214X Family –
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Peripherals – The Timer Unit – Pulse Width Modulation Unit –
UART – Block Diagram of ARM9 and ARM Cortex M3 MCU.
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2.1 ARM Architecture Versions
The ARM processor is a Reduced Instruction Set
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Computer (RISC).
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The first ARM processor was developed at Acorn
Computers Limited, of Cambridge, England, between
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October 1983 and April 1985. It is very simple
architecture.
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At that time, and until the formation of Advanced
RISC Machines Limited (which later was renamed
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simply ARM Limited) in 1990, ARM stood for Acorn
RISC Machine
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Second, both ARM ISA and pipeline design are aimed
to minimize the energy consumption.
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Third, the ARM architecture is highly modular only
mandatory component of ARM processor is the integer
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pipeline, others are optional. This gives more
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flexibility in application dependent architecture
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Revision Example core ISA Enhancement
implementation
ARM v1 ARM1 •First ARM Processor
•26bit addressing
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ARMv2 ARM2 •32bit multiplier
•32bit coprocessor
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support
ARMv2a ARM3 •On chip cache
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•Atomic swap instruction
•Coprocessor 15 for cache
management
ARMv3
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ARM6 and ARM7DI •32 bit addressing
•Separate cpsr (current
Program status
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register)and spsr
(Saved program status
register)
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•New modes undefined
instruction and abort
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•MMU support(Memory
Management Unit)
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ARMv3M ARM7M Signed and un signed
long multiply
instruction
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ARMv4 Strong ARM •load store instructions
for signed half
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words/bytes
•Reserve SWI(software
interrupt) space fro
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architecturally define
operations.
•26 bit addressing mode
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no longer supported
ARMv4T ARM7TDMI and ARM9T •Thumb
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ARMV5TE ARM9E AND ARM10E •Superset of ARM
•Enhanced multiply
instructions
•Extra DSP type
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instruction
•Faster multiply
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instruction
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ARM V5tej ARM7EJ & ARM926EJ Java Acceleration
ARMv6 ARM11 •Improved Multiprocessor
instructions
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•Unaligned and Mixed
endian data handling
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ARM processor Features
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Terms Extention
X Family or series
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Y Memory Management
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Z Cache
T 16bit thumb decoder
D Jtag Debugger
M
I jin Fast multiplier
Embedded In circuit Emulator
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E Enhanced Instruction for DSP
J Jazelle
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F Vector floating point unit
S Synthesizable version
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ARM 7family
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ARM7 core has a von neumann style architecture
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ARM7 TDMI is first processor introduced in 1995 by
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ARM
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It provide a very good performance to power ratio
ARM7TDMI-S has the synthesizable
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ARM720T is the most fexible member of ARM7 family
because it include MMU. MMU handle both platforms
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Linux and windows
It having unified 8k cache and vector table are
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relocated depend on the priority
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ARM7EJS processor, also synthesizable. Its having five
stage pipeline and execute ARMv5TEJ instruction
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This version only support java acceleration.
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ARM9 family
The ARM9 family was announced in 1997
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ARM9 has five stage pipeline and high clock
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frequencies
Memory have been redesign Harvard architecture
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ARM9 process includes cache and MMU
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Operating system requiring virtual memory support
ETM (Embedded Trace Macrocell) which allows a
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developer to trace instruction and data execution in
real time operation. So that debugging is done during
the critical time segments.
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ARM946E-S include TCM, cache and MPU. The size
of the TCM and cache are configurable
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The processor is designed for the embedded control
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application that require deterministic real time
response
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ARM926EJ-S synthesizable processor core, announced
in 2000
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It a java enable device such as 3G phones and personal
digital assistant
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ARM10 FAMILY
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The ARM10 announced in 1997 was designed for
performance
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It extended version of 6 stage pipeline
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Vector floating point unit which adds a seventh stage
to the ARM10 pipeline
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VFP combined with IEEE 754.1985 floating point
ARM1020 E it includes E instruction. it having cache,
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VFP and MMU
ARM1026EJ-S is similar to ARM926EJ-S . But ARM10 is
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ARM11
ARM1136J-S, announced in 2003 was designed for high
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performance and power efficient applications
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ARM1136J-S was the first processor to execute
architecture ARMv6 instructions
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It has eight pipeline stages with load and store
arithmetic pipeline.
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ARMv6 instruction are single instruction with
multiple data extensions for media processing.
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2.2 ARM PROCESSORS
ARM Processor can be divided into three types
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ARM classic processor
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ARM Embedded Processor
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ARM Application processor
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ARM classic processor
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ARM Embedded Processor
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ARM Application processor
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2.3 ARM ARCHITECTURE
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The architecture has evolved over time, and starting
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with cortex series of cores, three profiles are,
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Application Profile Cortex- A series
Real time profile- Cortex- R series
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Microcontroller profile-Cortex –M series
2.3.1 Arm Features
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A load-store architecture,
Fixed-length 32-bit instructions
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3-Address instruction formats.
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It has 32 bit architecture but it supports to 16bit and 8
bit data types also
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A wide choice of development tools and simulation
models for leading EDA (Electronic Design
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Automation) environments and excellent debug
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support
ARM uses a Intelligent Memory Manager (IEM). It
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implements advanced algorithms to optimally balance
processor workload and power consumption.IEM work
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with operating system and mobile OS
ARM uses AHB (AMBA Advanced High performance
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Bus) interface. AMBA is open source specification for
on chip interconnection
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Byte organizations with an ARM word
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2.3.2 ARM ARCHITECTURE
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ARM core is functional units connected by data buses.
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Arrow represents the flow of data.
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Lines represent buses.
Boxes represent either operation unit or storage area
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Design of ARM is simple and Programmer’s design.
Power Saving design module.
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Flexible design for different application with simple
changes
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Instruction Pipeline and Read Data Register are 32 bit
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ARM instructions have two registers:
Rm, Rn- source register
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Rd-destination register.
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Address bus line A(31:0) and data in lines DATA (31:0)
to store the data into the register.
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Address Register holds the address of next instruction
/ data to be fetched
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Address Incrementer the address register value to
appropriate amount to point the next instruction/ data
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It contains 31 Register bank, each register are 32 bit
registers and also contains 6 status registers each of 32
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2.3.3CPU Modes of ARM:
User mode: It is used for programs and applications.
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It is a only non privileged mode.
System Mode: It is a special version of user mode. It
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allows the full read write access to the CPSR.
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Supervisor Mode: it is privileged mode it enters
whenever the processor get reset or SWI instruction is
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executed. In this mode OS kernel operates in.
Abort Mode: It occurs when there is a failed attempt
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to access the memory. This mode is entered when
prefetch abort and data abort exception occurs.
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Undefined mode: it is used when the processor
encountered an instruction that is undefined or not
supported by the implementation. It is a privileged
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mode.
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Interrupt Mode : It is a privileged mode. When the
processor accepts the IRQ it occurs.
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Fast Interrupt Mode : It is a privileged mode. When
the processor accepts the IRQ it occurs.
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HYP Mode: This mode introduced in the ARMV-7A
fir cortex- A15 processor to providing hardware
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virtualization support.
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The Current Program Status
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Register (CPSR)
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It gives the status of ALU result for every execution
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The CPSR is used in user-level programs to store the
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condition code bits.
Example, to record the result of a comparison
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operation and to control whether or not a conditional
branch is taken
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N: Negative; the last ALU operation which changed the
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flags produced a negative result
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Z: Zero; the last ALU operation which changed the flags
produced a zero result (every bit of the 32-bit result was
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zero).
C: Carry; the last ALU operation which changed the flags
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generated a carry-out, either as a result of an arithmetic
operation in the ALU or from the shifter.
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V: oVerflow; the last arithmetic ALU operation which
changed the flags generated an overflow into the sign
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bit.
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ARM Data Instruction
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.c
Example Program:
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int a,b,c, X;
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X= a+b-c;
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.c
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2.4 ARM INSTRUCTION SET
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Types of instruction set
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Data Processing Instructions
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Branch Instructions
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Load Store Instructions
Software interrupt Instructions
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Program Status Register Instructions
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DATA PROCESSING INSTRUCTIONS:
Move instruction
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Arithmetic instruction
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Logical instruction
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Comparison instruction
Multiply instruction
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Move instruction
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MOV operand2
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MVN NOT operand2
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MOVS – Update In Status Reg
Syntax:
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<Operation>{<cond>}{S} Rd, Operand2
Examples:
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MOV r0, r1
MOVS r2, #10
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The Barrel Shifter
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The ARM doesn’t have actual shift instructions.
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Instead it has a barrel shifter which provides a
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mechanism to carry out shifts as part of other
instructions.
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Barrel Shifter - Left Shift
Shifts left by the specified amount (multiplies by
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powers of two)
e.g.
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LSL #5 = multiply by 32
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Barrel Shifter - Left Shift
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Logical Shift Left (LSL)
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CF Destination 0
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Barrel Shifter - Right Shifts
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Logical Shift Right
Logical Shift Right
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•Shifts right by the
specified amount (divides ...0 Destination CF
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by powers of two) e.g.
LSR #5 = divide by 32
Arithmetic Shift Right
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•Shifts right (divides by
powers of two) and Destination CF
preserves the sign bit, for
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Sign bit shifted in
2's complement
operations. e.g.
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ASR #5 = divide by 32
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Barrel Shifter - Rotations
Rotate Right (ROR)
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Rotate Right
• Similar to an ASR but the
bits wrap around as they
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leave the LSB and appear as Destination CF
the MSB.
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e.g. ROR #5
• Note the last bit rotated is
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also used as the Carry Out.
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Rotate Right Extended Rotate Right through Carry
(RRX)
• This operation uses the
Destination
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CF
CPSR C flag as a 33rd bit.
• Rotates right by 1 bit.
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Encoded as ROR #0.
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Arithmetic instruction
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example
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ADD r0, r1, r2
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R0 = R1 + R2
SUB r5, r3, #10
R5 = R3 − 10
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RSB r2, r5, #0xFF00
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R2 = 0xFF00 − R5
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Logical instruction
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Comparison instruction
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Multiply instruction
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2. Branch Instructions
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3.Load Store Instructions
Single register transfer
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Single register load store
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addressing mode
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Multiple Register Transfer
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Swap instruction
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Software interrupt Instructions
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Program Status Register
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Instructions
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Coprocessor Instruction
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2.5 Stack and subroutine
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Stack and subroutine
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Calling A subroutine
Parameter passing
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Software delay
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2.6 Features of the LPC 214x family
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.c
The LPC2148 is a 16 bit or 32 bit ARM7 family based
microcontroller and available in a small LQFP64
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package.
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ISP (in system programming) or IAP (in application
programming) using on-chip boot loader software.
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On-chip static RAM is 8 kB-40 kB, on-chip flash
memory is 32 kB-512 kB, the wide interface is 128 bit,
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or accelerator allows 60 MHz high-speed operation.
It takes 400 milliseconds time for erasing the data in
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full chip and 1 millisecond time for 256 bytes of
programming.
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Embedded Trace interfaces and Embedded ICE RT
offers real-time debugging with high-speed tracing of
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instruction execution and on-chip Real Monitor
software.
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It has 2 kB of endpoint RAM and USB 2.0 full speed
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device controller. Furthermore, this microcontroller
offers 8kB on-chip RAM nearby to USB with DMA.
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One or two 10-bit ADCs offer 6 or 14 analogs i/ps with
low conversion time as 2.44 μs/ channel.
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Only 10 bit DAC offers changeable analog o/p.
External event counter/32 bit timers-2, PWM unit, &
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watchdog.
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Low power RTC (real time clock) & 32 kHz clock
input.
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Several serial interfaces like two 16C550 UARTs, two
I2C-buses with 400 kbit/s speed.5 volts tolerant quick
general purpose Input/output pins in a small LQFP64
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package.
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Outside interrupt pins-21.60 MHz of utmost CPU
CLK-clock obtainable from the programmable-on-chip
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phase locked loop by resolving time is 100 μs.
The incorporated oscillator on the chip will work by an
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exterior crystal that ranges from 1 MHz-25 MHz
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The modes for power-conserving mainly comprise idle
& power down.
For extra power optimization, there are individual
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enable or disable of peripheral functions and
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peripheral CLK scaling.
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2.7 PERIPHERALS:
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Embedded systems that interacts with the outside
world, needs some peripheral device. A peripheral
device performs input and output functions for the
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chip by connecting to other devices or sensors that are
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off chip.
Each peripheral device performs one function from
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outside of chip. Peripheral range is from simple serial
communication to complex 802.11 wireless devices.
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All ARM peripherals are memory mapped. It has set of
addressed registers. This address registers used to
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select the exact peripheral device address
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Controllers-Specialized peripherals for higher level functionality. Its two
types are,
Memory controllers.
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Interrupt controllers.
Memory controllers:
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Connect different types of memory to the processor bus.
On- power-up a memory controller is configured in hardware to allow
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the certain memory devices to be active.
Some memory devices must be set up by software.
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Interrupt controllers:
When a peripheral device requires a attention it raises the interrupt to
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the processor.
The interrupt controller provides the programmable governing policy
that allows the software to determine which peripheral device can
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interrupt the processor at specific time. This is done by bits in the
interrupt controller register.
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Two types of interrupt controllers for ARM:
The Standard interrupt controller.
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The Vector interrupt controller (VIC).
The Standard interrupt controller:
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It sends the interrupt signal to the processor core, when an external
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device requests servicing.
It can be programmed to ignore or mask other individual device or set
of devices.
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The interrupt handler determines which device requires to servicing by
reading a device bitmap register in the interrupt controller.
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The Vector interrupt controller (VIC):
It is powerful than Standard interrupt controller. It has prioritizes
interrupts. So determination of which device caused the interrupt is
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simple.
The VIC only allows an interrupt signal to the core if the new higher
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The ARM core data flow model:
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Software abstraction layers
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executing on hardware
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2.9 The Timer Unit
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Register Associated with timer
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in LPC2148
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Prescale register (PR)
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Prescaler Counter register (PC)
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Timer counter register(TC)
Ttimer control register(TCR)
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Conter control register(CTCR)
Match control Register (MCR)
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Interrupt Register(IR)
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Timer 0 register
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1. T0IR(Timer 0 interrupt Register)
1.
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2.T0TCR(Timer 0 Timer Control Register)
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3.T0CTCR(Timer 0 counter control register)
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4. T0TC(Timer 0 Timer Counter)
5.T0PR(Timer 0 Prescale Register)
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6.T0PC(Timer 0 prescale counter register)
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7.T0MR0-T0MR3(Timer0 Match Register)
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8.T0MCR(Timer0 Match Control Register)
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2.10 UART
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UART
Universal Asynchronous Receiver/Transmitter
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UART in LPC2148 ARM 7 Micro controller
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Register Associated with UART
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in LPC2148
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UART0 Receiver Buffer Register(U0RBR)
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UART0 Transmit Holding Register(U0THR)
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UART0 Divisor Latch Register (U0DLL and U0DLM)
Determine the baud rate generator (U0DLL /
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U0DLM). (0x00:00x01)
UART0 Fractional divider register (U0FDR)
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It is used for prescale for the baud rate
Both Multiply and Division can be done in prescale
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Bit 0 – 3 used for prescale divisor value for baurd rate
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Bit 4 -7 used multiplier value
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UART0 Interrupt Enable Register(U0IER)
0 bit- RBR (Receiver buffer Register)interrupt
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1 bit- Interrupt enable register
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2 bit- Rx line status register
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8 bit – End of auto baud rate interrupt
9 bit- auto baud time out interrupt
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U0LCR (UART0 Line Control Register)
Bit 1:0 - Word Length Select
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00 = 5-bit character length
01 = 6-bit character length
10 = 7-bit character length
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11 = 8-bit character length
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Bit 2 - Number of Stop Bits
0 = 1 stop bit
1 = 2 stop bits
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Bit 3 - Parity Enable
0 = Disable parity generation and checking
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1 = Enable parity generation and checking
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Bit 5:4 - Parity Select
00 = Odd Parity
01 = Even Parity
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10 = Forced “1” Stick Parity
11 = Forced “0” Stick Parity
Bit 6 - Break Control
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0= Disable break transmission
1 = Enable break transmission
Bit 7 - Divisor Latch Access Bit (DLAB)
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0 = Disable access to Divisor Latches
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1 = Enable access to Divisor Latches
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U0LSR (UART0 Line Status
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Register)
It provides status information on UART0 RX and TX blocks.
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Bit 0 - Receiver Data Ready
0 = U0RBR is empty
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1 = U0RBR contains valid data
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Bit 1 - Overrun Error
0 = Overrun error status inactive
1 = Overrun error status active
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This bit is cleared when U0LSR is read.
Bit 2 - Parity Error
0 = Parity error status inactive
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1 = Parity error status active
This bit is cleared when U0LSR is read.
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Bit 3 - Framing Error
0 = Framing error status inactive
1 = Framing error status active
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This bit is cleared when U0LSR is read.
Bit 4 - Break Interrupt
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0 = Break interrupt status inactive
1 = Break interrupt status active
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This bit is cleared when U0LSR is read.
Bit 5 - Transmitter Holding Register Empty
0 = U0THR has valid data
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1 = U0THR empty
Bit 6 - Transmitter Empty
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0 = U0THR and/or U0TSR contains valid data
1 = U0THR and U0TSR empty
Bit 7 - Error in RX FIFO (RXFE)
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0 = U0RBR contains no UART0 RX errors
1 = U0RBR contains at least one UART0 RX error
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This bit is cleared when U0LSR is read
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U0TER (UART0 Transmit Enable
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Register)
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The U0TER enables implementation of software flow control. When
TXEn=1, UART0 transmitter will keep sending data as long as they are
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available. As soon as TXEn becomes 0, UART0 transmission will stop.
Software implementing software-handshaking can clear this bit when
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it receives an XOFF character (DC3). Software can set this bit again
when it receives an XON (DC1) character.
Bit 7 : TXEN
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0 = Transmission disabled
1 = Transmission enabled
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If this bit is cleared to 0 while a character is being sent, the
transmission of that character is completed, but no further characters
are sent until this bit is set again
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.c
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2.11 Block Diagram of ARM9
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ARM9TDMI
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ARM940T Cached Processor
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Comparision between ARM9TDMI and
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ARM7TDMI
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Pipeline Process
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DATA FLOW
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COMPARISION SUMMARY
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2.9 Pulse Width Modulation(PWM)
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LPC 2148
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It consist of 32 timer /counter ie PWMTC
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Counter count the cycles of peripheral clock(PCLK)
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It having 32bit prescale register (PWMPR)
It having 7 matching register (PWMR0-PWMR06)
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6 different pwm signal in single edge controlled pwm
or 3 different pwm signal in double edge controlled
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pwm
Match register will match and then it will reset the
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timer/counter or stop.
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.c
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PWM Registers
1.PWMIR (PWM Interrupt Register)
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•It has 7 interrupt bits corresponding to the 7 PWM match registers.
•If an interrupt is generated, then the corresponding bit in this register becomes HIGH.
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•Otherwise the bit will be LOW.
•Writing a 1 to a bit in this register clears that interrupt.
•Writing a 0 has no effect.
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2. PWMTCR (PWM Timer Control Register)
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It is an 8-bit register.
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It is used to control the operation of the PWM Timer Counter.
Bit 0 – Counter Enable
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When 1, PWM Timer Counter and Prescale Counter are enabled.
When 0, the counters are disabled.
Bit 1 – Counter Reset
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When 1, the PWM Timer Counter and PWM Prescale Counter are synchronously
reset on next positive edge of PCLK.
Counter remains reset until this bit is returned to 0.
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Bit 3 – PWM Enable
This bit always needs to be 1 for PWM operation. Otherwise PWM will operate as a
normal timer.
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When 1, PWM mode is enabled and the shadow registers operate along with match
registers.
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A write to a match register will have no effect as long as corresponding bit in
PWMLER is not set.
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3. PWMTC (PWM Timer Counter)
It is a 32-bit register.
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It is incremented when the PWM Prescale Counter (PWMPC) reaches
its terminal count.
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4. PWMPR (PWM Prescale Register)
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It is a 32-bit register.
It holds the maximum value of the Prescale Counter.
5. PWMPC (PWM Prescale Counter)
It is a 32-bit register.
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It controls the division of PCLK by some constant value before it is
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applied to the PWM Timer Counter.
It is incremented on every PCLK.
When it reaches the value in PWM Prescale Register, the PWM Timer
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Counter is incremented and PWM Prescale Counter is reset on next
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PCLK.
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6. PWMMR0-PWMMR6 (PWM Match Registers)
These are 32-bit registers.
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The values stored in these registers are continuously
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compared with the PWM Timer Counter value.
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When the two values are equal, the timer can be reset
or stop or an interrupt may be generated.
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The PWMMCR controls what action should be taken
on a match.
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7. PWMMCR (PWM Match Control Register)
It is a 32-bit register.
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It controls what action is to be taken on a match
between the PWM Match Registers and PWM Timer
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Counter.
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Bit 0 – PWMMR0I (PWM Match register 0 interrupt)
0 = This interrupt is disabled
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1 = Interrupt on PWMMR0. An interrupt is generated when PWMMR0 matches the value
in PWMTC
Bit 1 – PWMMR0R (PWM Match register 0 reset)
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0 = This feature is disabled
1 = Reset on PWMMR0. The PWMTC will be reset if PWMMR0 matches it
Bit 2 – PWMMR0S (PWM Match register 0 stop)
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0 = This feature is disabled
1 = Stop on PWMMR0. The PWMTC and PWMPC is stopped and Counter Enable bit in
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PWMTCR is set to 0 if PWMMR0 matches PWMTC
PWMMR1, PWMMR2, PWMMR3, PWMMR4, PWMMR5 and PWMMR6 has same
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Bit 2 – PWMSEL2
0 = Single edge controlled mode for PWM2
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1 = Double edge controlled mode for PWM2
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All other PWMSEL bits have similar operation as
PWMSEL2 above.
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Bit 10 – PWMENA2
0 = PWM2 output disabled
1 = PWM2 output enabled
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All other PWMENA bits have similar operation as
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PWMENA2 above.
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9. PWMLER (PWM Latch Enable Register)
It is an 8-bit register.
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It is used to control the update of the PWM Match Registers when they
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are used for PWM generation.
When a value is written to a PWM Match Register while the timer is in
PWM mode, the value is held in the shadow register. The contents of
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the shadow register are transferred to the PWM Match Register when
the timer resets (PWM Match 0 event occurs) and if the corresponding
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bit in PWMLER is set.
Bit 6 – Enable PWM Match 6 Latch
Writing a 1 to this bit allows the last written value to PWMMR6 to
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become effective when timer next is reset by the PWM match event.
Similar description as that of Bit 6 for the remaining bits.
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Steps for PWM generation
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Reset and disable PWM counter using PWMTCR
Load prescale value according to need of application in the PWMPR
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Load PWMMR0 with a value corresponding to the time period of your
PWM wave
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Load any one of the remaining six match registers (two of the
remaining six match registers for double edge controlled PWM) with
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the ON duration of the PWM cycle. (PWM will be generated on PWM
pin corresponding to the match register you load the value with).
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Load PWMMCR with a value based on the action to be taken in the
event of a match between match register and PWM timer counter.
Enable PWM match latch for the match registers used with the help of
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PWMLER
Select the type of PWM wave (single edge or double edge controlled)
and which PWMs to be enabled using PWMPCR
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Enable PWM and PWM counter using PWMTCR
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2.12 Block diagram of ARM CORTEX M3 MCU
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INTNMI- Non-maskable interrupt
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INTISR[239:0]- External interrupt signals
SLEEPING- Indicates that the Cortex-M3 clock can be
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stopped.
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SLEEPDEEP - Indicates that the Cortex-M3 clock can be
stopped
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WIC - Wake-up Interrupt Controller
NVIC- Nested Vectored Interrupt Controller
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ETM- Embedded Trace Macrocell
The ETM is an optional debug component that enables
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reconstruction of program execution. The ETM is
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designed to be a high-speed, low-power debug tool
that only supports instruction trace
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MPU- Memory Protection Unit
The MPU provides full support for:
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protection regions
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overlapping protection regions, with ascending
region priority:
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— 7 = highest priority
— 0 = lowest priority.
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access permissions
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exporting memory attributes to the system.
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FPB-Flash Patch and Breakpoint
unit to implement breakpoints and code patches.
DWT -Data Watchpoint and Trace () unit to
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implement watchpoints, trigger resources, and system
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profiling.
ITM- Instrumentation Trace Macrocell for application-
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driven trace source that supports printf style
debugging.
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TPIU- Trace Port Interface Unit
it is an optional component that acts as a bridge
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between the on-chip trace data from the Embedded
Trace Macrocell (ETM) and the Instrumentation Trace
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Macrocell(ITM), with separate IDs, to a data stream,
encapsulating IDs where required, that is then captured
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by a Trace Port Analyzer (TPA).
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SW/SWJ-DP - SW-DP or SWJ-DP debug port
interfaces.
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The debug port provides debug access to all registers
and memory in the system, including the processor
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registers.
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The SW/SWJ-DP might not be present in the
production device if no debug functionality is present
in the implementation.
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.c
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UNIT III
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EMBEDDED PROGRAMMING
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Syllabus
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Components for embedded programs- Models of
programs- Assembly, linking and loading –
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compilation techniques- Program level performance
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analysis – Software performance optimization –
Program level energy and power analysis and
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optimization – Analysis and optimization of program
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size- Program validation and testing
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1. COMPONENTS FOR EMBEDDED PROGRAMS
• Embedded components are given by State machine, Circular buffer, and the
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Queue.
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1.1)STATE MACHINE
• The reaction of most systems can be characterized in terms of the input received
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and the current state of the system.
• The finite-state machine style of describing the reactive system’s behavior..
•
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Finite-state machines are usually first encountered in the context of hardware
design.
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software state machine
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seat, belt, timer
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case BELTED:
#define IDLE 0 if (!seat) state = IDLE; /* person left */
#define SEATED 1
else if (!belt) state = SEATED; /* person
#define BELTED 2
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still
#define BUZZER 3
switch (state) { /* check the current state in seat */
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*/ break;
case IDLE: case BUZZER:
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if (seat) { state = SEATED;
if (belt) state = BELTED; /* belt is on—
timer_on = TRUE; }
turn off
/* default case is self-loop */
break;
case SEATED: jin buzzer */
else if (!seat) state = IDLE; /* no one in
if (belt) state = BELTED; /* won't hear the seat—turn off buzzer */
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buzzer */ break;
else if (timer) state = BUZZER; /* didn't
put on }
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belt in time */
/* default is self-loop */
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break;
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1.2)Stream-Oriented Programming and Circular Buffers
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• The circular buffer is a data structure that handle streaming
data in an efficient way.
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• Size of the window does not change.
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• Fixed-size buffer to hold the current data.
• To avoid constantly copying data within the buffer, move the
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head of the buffer in time.
• The buffer points to the location at which the next sample will
be placed. jin
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• Every time add a sample, automatically overwrite the oldest
sample, which is the one that needs to be thrown out.
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• When the pointer gets to the end of the buffer, it wraps around
to the top.
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Circular buffer for streaming data.
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1.3 QUEUES
• Queues are also used in signal processing and event
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processing.
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• Queues are used whenever data may arrive and depart at
somewhat unpredictable times or when variable amounts of
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data may arrive.
• A queue is often referred to as an Elastic buffer.
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2.MODELS OF PROGRAMS
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• Programs are collection of instructions to execute a specified
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task.
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• Models for programs are more general than source code.
• source code can’t be used directly because of different type s
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such as assembly language,C code.
• Single model to describe all of them.
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• control/data flow graph (CDFG)it is the fundamental model
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for programs
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2.1 DATA FLOW GRAPH
• A data flow graph is a model of a program with no conditionals.
• In a high-level programming language, a code segment with no
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conditionals have only one entry and exit point—is known as a basic
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block.
A basic block in C
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An extended data flow graph for our sample basic block
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•The basic block in single-assignment form
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•Round nodesdenote operators
•Square nodesdenote values.
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•The value nodes may be either inputs(a,b)
or variables(w,x1).
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Standard data flow graph for our sample basic
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block
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2.2. Control/Data Flow Graphs(CDFG)
• A CDFG uses a data flow graph as an element,adding
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constructs to describe control.
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CDFG having following two types of nodes.
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1. Decision nodesused to describe the control in a sequential
program
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• Data flow nodes encapsulates a complete data flow graph
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to represent a data.
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C code and its CDFG
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if (cond1)
basic_block_1( );
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else
basic_block_2();
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basic_block_3( );
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switch (test1) {
case c1: basic_block_4( ); break;
case c2: basic_block_5( ); break;
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case c3: basic_block_6( ): break;
}
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•Rectangular nodesrepresent the basic blocks.
•Diamond-shaped nodes represent the conditionals.
•Label node’s condition
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•Edges are labeled with the possible outcomes of
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evaluating the condition
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CDFG for a while loop
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while (a < b) {
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a5proc1(a,b);
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b5proc2(a,b);
}
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CDFG for a while loop
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while (a < b) {
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a5proc1(a,b);
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b5proc2(a,b);
}
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3. ASSEMBLY, LINKING AND LOADING
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•Assembly and linking last steps in the compilation process
•They convert list of instructions into an image of the program’s
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bits in memory.
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•Loading puts the program in memory so that it can be
executed.
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• Compilers used to create the instruction-level program in to
assembly language code.
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• Assembler’s used to translate symbolic assembly language
statements into bit-level representations of instructions known
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as object code and also translating labels into addresses.
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• Linker determining the addresses of instructions.
• Loader load the program into memory for execution.
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• Absolute addresses Assembler assumes that the starting
address of the ALP has been specified by the programmer.
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• Relative addresses specifying at the start of the file address
is to be computed later.
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3.1 Assemblers
• Assembler Translating assembly code into object code also
.c
assembler must translate opcodes and format the bits in each
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instruction, and translate labels into addresses.
• Labels it is an abstraction provided by the assembler.
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• Labelsknow the locations of instructions and data.
Label processing requires making two passes
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1. first pass scans the code to determine the address of each label.
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2. second pass assembles the instructions using the label values
computed in the first pass.
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EXAMPLE
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CODE SYMBOL TABLE
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3.2)LINKING
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• A linker allows a program to be stitched together out of several smaller
pieces.
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• The linker operates on the object files and links between files.
• Some labels will be both defined and used in the same file.
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• Other labels will be defined in a single file but used elsewhere .
• The place in the file where a label is defined is known as an entry point.
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• The place in the file where the label is used is called an external reference.
Phases of linker
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• First Phaseit determines the address of the start of each object file
• Second Phasethe loader merges all symbol tables from the object files
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into a single,large table.
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4. PROGRAM-LEVEL PERFORMANCE ANALYSIS
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• The techniques we use to analyze program execution time are
also helpful in analyzing properties such as power consumption.
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• The CPU executes the entire program at the rate we desire.
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• The execution time of a program often varies with the input data
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values.
• The cache has a major effect on program performance.
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• Cache’s behavior depends in part on the data values input to the
program.
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• The execution time of an instruction in a pipeline depends not
only on that instruction but on the instructions around it in the
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pipeline.
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Execution time of a program
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4.1. Program Performance Measuring techniques
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1. Simulator
• It runs on a PC, takes as input an executable for the
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microprocessor along with input data, and simulates the program.
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2. Timer
• It is can be used to measure performance of executing sections of
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code.
• The length of the program that can be measured is limited by the
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accuracy of the timer.
3. Logic analyzer
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• It is used to measure the start and stop times of a code segment.
• The length of code that can be measured is limited by the size of
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the logic analyzer’s buffer.
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4.2)Types of performance Parameters
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1. Average-case execution time
• This is the typical execution time we would expect for typical data.
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2. Worst-case execution time
• The longest time that the program can spend on any input sequence is
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clearly important for systems that must meet deadlines.
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3. Best-case execution time
• This measure can be important in multi-rate real-time systems.
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4.3) Elements of Program Performance
•Execution time =Program path +Instruction timing
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•Program path It is the sequence of instructions executed by the program.
•Instruction timingIt is determined based on the sequence of instructions
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traced by the program path.
•Not all instructions take the same amount of time.
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•The execution time of an instruction may depend on operand values.
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4.4)Measurement-Driven Performance Analysis
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• To measure the program’s performance need CPU or its simulator .
• Measuring program performance combination of determination of
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the execution path and the timing of that path.
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• program trace record of the execution path of a program.
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Cycle-Accurate Simulator
• It can determine the exact number of clock cycles required for
execution.
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• It is built with detailed knowledge of how the processor works .
• It is slower than the processor itself, but a variety of techniques can
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be used to make them surprisingly fast.
• It has a complete model of the processor, including the cache.
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• It can provide information about why the program runs too slowly.
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5. SOFTWARE PERFORMANCE OPTIMIZATION
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5.1)Loop Optimizations-Loops are important targets for optimization
because programs with loops tend to spend a lot of time executing
.c
those loops.
•
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Code motion
• Induction variable elimination
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• Strength reduction
Code motion
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• It can move unnecessary code out of a loop.
• If a computation’s result does not depend on operations performed
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in the loop body,thenwe can safely move it out of the loop.
for (i = 0; i < N*M; i++)
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{
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z[i] = a[i] + b[i];
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Code motion in a loop
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•The loop bound computation is performed on every iteration during
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the loop test, even though the result never changes.
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•We can avoid N X M- 1 unnecessary executions of this statement by
moving it before the loop.
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Induction variable elimination
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• It is a variable whose value is derived from the loop iteration variable’s value.
• The compiler often introduces induction variables to help it implement the
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loop.
• Properly transformed able to eliminate some variables and apply strength
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reduction to others.
•
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A nested loop is a good example of the use of induction variables.
for (i = 0; i < N; i++)
for (j = 0; j < M; j++)
•
z[i][j] = b[i][j];
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The compiler uses induction variables to help it address the arrays. Let us
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rewrite the loop in C using induction variables and pointers
for (i = 0; i < N; i++)
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for (j = 0; j < M; j++) {
zbinduct = i*M + j;
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*(zptr + zbinduct) = *(bptr + zbinduct);
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}
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Strength reduction
• It reduce the cost of a loop iteration.
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Consider the following assignment
y = x * 2;
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• In integer arithmetic, we can use a left shift rather than a
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multiplication by 2
• If the shift is faster than the multiply, then perform the substitution.
• This optimization can often be used with induction variables because
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loops are often indexed with simple expressions.
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5.2 Cache Optimizations
• A loop nest is a set of loops, one inside the other.
• Loop nests occur when we process arrays.
.c
• A large body of techniques has been developed for optimizing loop
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nests.
• Rewriting a loop nest changes the order in which array elements are
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accessed.
• This can expose new parallelism opportunities that can be exploited
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by later stages of the compiler, and it can also improve cache
performance.
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6. PROGRAM-LEVEL ENERGY AND POWER
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ANALYSIS AND OPTIMIZATION
.c
• Power consumption is a important design metric for battery-
powered systems.
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• It is increasingly important in systems that run off the power grid.
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• Fast chips run hot, and controlling power consumption is an
important element of increasing reliability and reducing system cost.
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Power consumption reduction techniques.
• To replace the algorithms with others that consume less power.
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• By optimizing memory accesses ,able to significantly reduce power.
• To turn off the subsystems of CPU, chips in the system, in order to
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save power.
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Measuring energy consumption for a piece of code
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Program’s energy consumption how
much energy the program consumes.
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To measure power consumption for an
instruction or a small code fragment.
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It is used to executes the code under test
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over and over in a loop.
By measuring the current flowing into the
CPU,we are measuring the power
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consumption of the complete loop,
including both the body and other code.
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By separately measuring the power
consumption of a loop with no body.
we can calculate the power consumption
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of the loop body code as the difference b/w the
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full loop and the bare loop energy cost of an
instruction.
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List of the factors contribution for energy consumption of the
program.
• Energy consumption varies somewhat from instruction to instruction.
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• The sequence of instructions has some influence.
• The opcode and the locations of the operands also matter.
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Steps to Improve Energy Consumption
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• Try to use registers efficiently(r4)
• Analyze cache behavior to find major cache conflicts.
•
•
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Make use of page mode accesses in the memory system whenever possible.
Moderate loop unrolling eliminates some loop control overhead. when the
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loop is unrolled too much, power increases.
• Software pipelining reducing the average energy per instruction.
• Eliminating recursive procedure calls where possible saves power by getting
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• Tail recursion can often be eliminated, some compilers do this
automatically.
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7. ANALYSIS AND OPTIMIZATION OF PROGRAM SIZE
• Memory size of a program is determined by the size of its data and instructions.
• Both must be considered to minimize program size.
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• Data provide an opportunity to minimizing the size of program.
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• Data buffers can be reused at several different points in program, which reduces
program size.
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• Some times inefficient programs keep several copies of data, identifying and
eliminating duplications can lead to significant memory savings.
• Minimizing the size of the instruction text and reducing the number of
•
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instructions in a program which reduces program size
Proper instruction selection may reduce code size.
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• Special compilation modes produce the program in terms of the dense
instruction set.
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• Program size of course varies with the type of program, but programs using the
dense instruction set are often 70 to 80% of the size of the standard instruction
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8. PROGRAM VALIDATION AND
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TESTING
• Complex systems need testing to ensure the working behavior of the
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systems.
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• Software Testingused to generate a comprehensive set of tests to
ensure that our system works properly.
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• The testing problem is divided into sub-problems and analyze each sub
problem.
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Types of testing strategies
1. White/Clear-box Testing generate tests ,based on the program
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structure.
2. Black-box Testing generate tests ,without looking at the internal
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8.1 Clear box testing
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• Testingrequires the control/data flow graph of a program’s source
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code.
• To test the program exercise both its control and data operations.
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• To execute and evaluate the tests control the variables in the
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program and observe the results .
The following three things to be followed during a test
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1. Provide the program with inputs for the test.
2. Execute the program to perform the test.
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3. Examine the outputs to determine whether the test was successful.
• Execution PathTo test the program by forcing the program to
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execute along chosen paths. ( giving it inputs that it to take the
appropriate branches)
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Graph Theory
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•It help us get a quantitative handle on the different paths required.
•Undirected graph-form any path through the graph from combinations of basis
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paths.
•Incidence matrix contains each row and column represents a node.
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•1 is entered for each node pair connected by an edge.
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Cyclomatic Complexity
• It is a software metric tool.
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• Used to measure the control complexity of a program.
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M = e – n + 2p.
• e number of edges in the flow graph
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• n number of nodes in the flow graph
• p number of components in the graph
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Types of Clear Box test strategy
1. Branch testing
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2. Domain testing
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3. Data flow testing
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8.1.1 Branch testing
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• This strategy requires the true and false branches of a
conditional.
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• Every simple condition in the conditional’s expression to be
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tested at least once.
if ((x == good_pointer) && (x->field1 == 3))
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{ printf("got the value\n"); }
The bad code we actually wrote
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if ((x = good_pointer) && (x->field1 == 3))
{ printf("got the value\n"); }
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8.1.2 Domain testing
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• It concentrates on linear-inequalities.
• The program should use for the test is j <= i + 1
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• We test the inequality with three test points
• Two on the boundary of the valid region
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• Third outside the region but between the i values of the other
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two points.
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8.1.3 Data flow testing
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• It use of def-use analysis (definition-use analysis).
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• It selects paths that have some relationship to the program’s
function.
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• Compilers which use def-use analysis for Optimization.
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• A variable’s value is defined when an assignment is made to the
variable.
• It is used when it appears on the right side of an assignment.
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8.2)Block Box Testing
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• Black-box tests are generated without knowledge of the code being
tested.
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• It have a low probability of finding all the bugs in a program.
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• We can’t test every possible input combination, but some rules help
us select reasonable sets of inputs.
1. Random Tests
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• Random values are generated with a given inputs.
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• The expected values are computed first, and then the test inputs are
applied.
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2. Regression Tests
• When tests are created during earlier or previous versions of the
system.
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• Those tests should be saved apply to the later versions of the
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system.
• It simply exercise current version of the code and possibly exercise
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different bugs.
• In digital signal processing systems Signal processing algorithms
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are implemented to save hardware costs.
• Data sets can be generated for the numerical accuracy of the
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system.
• These tests can often be generated from the original formulas
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UNIT IV
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REAL TIME SYSTEMS
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Structure of a Real Time System - Estimating program run
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times – Task Assignment and Scheduling – Fault Tolerance
Techniques – Reliability, Evaluation – Clock
Synchronisation.
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Operating System
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An Operating System performs all the basic tasks like
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managing file, process, and memory.
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Thus operating system acts as manager of all the
resources, i.e. resource manager.
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Thus operating system becomes an interface between
user and machine.
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Types of Operating Systems
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Batch Operating System
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Time-Sharing Operating Systems
Distributed Operating System
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Network Operating System
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Real-Time Operating System
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1. Batch Operating System
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Time-Sharing Operating
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Systems
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Distributed Operating System
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Network Operating System
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Real-Time Operating System
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These types of OSs serves the real-time systems. The
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time interval required to process and respond to
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inputs is very small. This time interval is
called response time.
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Real-time systems are used when there are time
requirements are very strict like missile systems, air
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traffic control systems, robots etc
Two types of Real-Time Operating System which
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are as follows:
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Hard Real-Time Systems:
Soft Real-Time Systems:
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Hard Real-Time Systems:
These OSs are meant for the applications where time
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constraints are very strict and even the shortest
possible delay is not acceptable.
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These systems are built for saving life like automatic
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parachutes or air bags which are required to be readily
available in case of any accident.
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Virtual memory is almost never found in these
systems.
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Soft Real-Time Systems:
These OSs are for applications where for time-
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constraint is less strict.
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4.1) Structure of a Real Time
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System
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4.2 Estimating Program Run
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Times
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Real time system meet deadlines, it is important to be
able to accurately estimate program run times.
.c
Estimating the executing time of any given program is
a very difficult task
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It depend on the following factors
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Source code
Compiler-Mapping should be depend on the compiler
used.
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Machine architecture
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Operating system
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Analysis of a source code
L1: a = b x c;
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L2: b = d + e;
L3: d = a – f;
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Example 2
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Schematic of a timing estimation system
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Accounting of Pipeline
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Two Stage pipeline
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Cache Memory
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Virtual Memory
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.c
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4.3 Task Assignment and
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Scheduling
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A Task requires some execution time on a processor
.c
Also a task may required certain amount of memory or
access to a bus
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Sometimes a resource must be exclusively held by a
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task
In other cases resource may be exclusive or non
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exclusive depending on the operation to be performed
on it
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Release Time
A task is a time at which all the data that are required to
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begin executing the Task are available
Deadline
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The deadline is the time by which the task must complete its
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execution
The deadline must be hard or soft
Task are classified as
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Periodic
Sporadic
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Aperiodic
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Periodic
A task ti is periodic if it is released periodically.
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say every pi seconds pi is called the period of task Ti
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Sporadic Task
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Sporadic task is a not periodic task, but may be invoked at irregular
interval
Sporadic tasks are characterized by an upper bound on the rate at
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which they may be invoked
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APeriodic Task
Tasks to be those tasks which are not periodic and which also have no
upper bound on their invocation rate
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Task Assignment / Schedule
All task starts after the release time and complete before
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their deadline
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A schedule may be
Precomputed(Offline scheduling)
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Dynamically(Online Scheduling)
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Precomputed
Advance the operation with specification of periodic tasks will be
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run and slots for the sporadic / aperiodic tasks in the event that
they are involved.
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Dynamically
Tasks are scheduled as they arrive in the system
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The algorithm used in online scheduling must be fast
and it takes to meet their deadlines is clearly useless
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Two types priority algorithms are used
Static priority algorithm
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Dynamic priority algorithm
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Static priority algorithm
Static priority algorithm assume that the task priority does not
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change within a mode
Example Rate monotonic algorithm
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Dynamic priority algorithm
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algorithm assume that the task priority can change within a time
Example Earliest Deadline First (EDF)algorthim
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Classical uni-processor Scheduling Algorthim
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Example for Rate monotonic scheduling
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UNIT V
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PROCESSES AND OPERATING SYSTEMS
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Introduction – Multiple tasks and multiple processes – Multirate
systems- Preemptive real-time operating systems- Priority based
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scheduling- Interprocess communication mechanisms – Evaluating
operating system performance- power optimization strategies for
processes – Example Real time operating systems-POSIX-Windows-
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CE. Distributed embedded systems – MPSoCs and shared memory
multiprocessors. – Design Example - Audio player, Engine control unit
– Video accelerator.
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5.1)INTRODUCTION
Simple applications can be programmed on a microprocessor by writing a single
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piece of code.
But for a complex application, multiple operations must be performed at widely
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varying times.
Two fundamental abstractions that allow us to build complex applications on
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microprocessors.
1. Process defines the state of an executing program
2. operating system (OS)provides the mechanism for switching execution
between the processes.
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5.2)MULTIPLE TASKS AND MULTIPLE
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PROCESSES
Systems which are capable of performing multiprocessing known as multiple
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processor system.
Multiprocessor system can execute multiple processes simultaneously with the
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help of multiple CPU.
Multi-
Multi-tasking
tasking
The ability of an operating system to hold multiple processes
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in memory and switch the processor for executing one process.
5.2.1)Tasks and Processes
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Task is nothing but different parts of functionality in a single system.
Eg-Mobile Phones
When designing a telephone answering machine, we can define recording a
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phone call ,answering a call and operating the user’s control panel as distinct
tasks, at different rates.
Each application in a system is called a task.
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5.2.2)Process
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A process is a single execution of a program.
If we run the same program two different times, we have created two
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different processes.
Each process has its own state that includes not only its registers but all
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of its memory.
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In some OSs, the memory management unit is used to keep each
process in a separate address space.
In others, particularly lightweight RTOSs, the processes run in the
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same address space.
Processes that share the same address space are often called threads.
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This device is connected to serial ports on both ends.
The input to the box is an uncompressed stream of bytes.
The box emits a compressed string of bits, based on a compression table.
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Ex: compress data being sent to a modem.
The program’s need to receive and send data at different rates
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EgThe program may emit 2 bits for the first byte and then 7 bits for the
second byte— will obviously find itself reflected in the structure of the code.
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if we spend too much time in packaging and emitting output characters,we
may drop an input character.
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5.2.3)Asynchronous input
Ex:A control panel on a machine provides a different type of rate.
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The control panel of the compression box include a compression mode button
that disables or enables compression, so that the input text is passed through
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unchanged when compression is disabled.
Sampling the button’s state too slowly machine will miss a button
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depression entirely.
Sampling it too frequently the machine will do incorrectly compress data.
To solve this problem every n times the compression loop is executed.
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5.3.1)Multi--rate Systems
5.3.1)Multi
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In operating system implementing code for satisfies timing requirements is
more complex when multiple rates of computation must be handled.
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Multirate embedded computing systemsEx: automobile engines, printers,
and cell phones.
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In all these systems, certain operations must be executed periodically with its
own rate.
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EgAutomotive engine control
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The simplest automotive engine controllers, such as the ignition controller for a
basic motorcycle engine, perform only one task—timing the firing of the spark
plug, which takes the place of a mechanical distributor.
Spark Plug
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The spark plug must be fired at a certain point in the combustion cycle.
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Microcontroller
Using a microcontroller that senses the engine crankshaft position allows the
spark timing to vary with engine speed.
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Firing the spark plug is a periodic process.
Engine controller
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Automobile engine controllers use additional sensors, including the gas pedal
position and an oxygen sensor used to control emissions.
They also use a multimode control scheme. one mode may be used for engine
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warm-up, another for cruise, and yet another for climbing steep hills.
The engine controller takes a variety of inputs that determine the state of the
engine.
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It then controls two basic engine parameters: the spark plug firings and the
fuel/air mixture.
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Task performed by engine controller unit
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5.3.1)Timing Requirements on Processes
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Processes can have several different types of timing requirements based on the
application.
The timing requirements on a set of processes strongly depends on the type of
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scheduling.
A scheduling policy must define the timing requirements that it uses to
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determine whether a schedule is valid.
1. Release time
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The time at which the process becomes ready to execute.
simpler systems the process may become ready at the beginning of the period.
sophisticated systems set the release time at the arrival time of certain data, at
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a time after the start of the period.
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2. Deadline
specifies when a computation must be finished.
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The deadline for an a periodic process is generally measured from the release
time or initiation time.
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The deadline for a periodic process may occur at the end of the period.
The period of a process is the time between successive executions.
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The process’s rate is the inverse of its period.
In a Multi rate system, each process executes at its own distinct rate.
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Example definitions of release times and deadlines
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A sequence of processes with a high initiation rate
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•In this case, the initiation interval is equal to one fourth of the period.
•It is possible for a process to have an initiation rate less than the period even in
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single-CPU systems.
•If the process execution time is less than the period, it may be possible to initiate
multiple copies of a program at slightly offset times.
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Data dependencies among processes
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•The data dependencies define a partial ordering on process execution.
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•P1 and P2 can execute in any order but must both complete before P3, and P3
must complete before P4.
•All processes must finish before the end of the period.
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Directed Acyclic Graph (DAG)
•It is a directed graph that contains no cycles.
•The data dependencies must form a directed acyclic graph.
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•A set of processes with data dependencies is known as a task graph.
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Communication among processes at different rates
(MPEG audio/Video)
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•The system decoder process demultiplexes the audio and video data and
distributes it to the appropriate processes.
•Missing Deadline
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•Missing deadline in a multimedia system may cause an audio or video glitch.
•The system can be designed to take a variety of actions when a deadline is
missed.
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5.3.2)CPU Metrics
CPU metrics are described by initiation time and completion time.
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Initiation timeIt is the time at which a process actually starts executing on
the CPU.
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Completion timeIt is the time at which the process finishes its work.
The CPU time of process i is called Ci .
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The CPU time is not equal to the completion time minus initiation time.
The total CPU time consumed by a set of processes is
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The simplest and most direct measure is utilization.
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5.3.3)Process State and Scheduling
The first job of the OS is to determine that process runs next.
The work of choosing the order of running processes is known as scheduling.
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There three basic scheduling ,such as waiting, ready and executing.
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A process goes into the waiting state when it needs data that it has finished all its work for
the current period.
A process goes into the ready state when it receives its required data, when it enters
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a new period.
Finally a process can go into the executing state only when it has all its data, is ready to
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5.3.4)Scheduling Policies
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A scheduling policy defines how processes are selected for promotion from the
ready state to the running state.
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SchedulingAllocate time for execution of the processes in a system .
For periodic processes, the length of time that must be considered is the hyper period,
which is the least-common multiple of the periods of all the processes.
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Unrolled schedule The complete schedule for the least-common multiple of the
periods.
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Types of scheduling
1. Cyclostatic scheduling or Time Division Multiple Access scheduling
Schedule is divided into equal-sized time slots over an interval equal to the length of the
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hyperperiod H. (run in the same time slot)
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Two factors affect this scheduling
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The fraction of each time slot that is used for useful work.
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2)Round Robin-scheduling
Uses the same hyper period as does cyclostatic.
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It also evaluates the processes in order.
If a process does not have any useful work to do, the scheduler moves on to the next
process in order to fill the time slot with useful work.
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All three processes execute during the first hyperperiod.
During the second one, P1 has no useful work and is skipped so P3 is directly move on to
the next process.
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Scheduling overhead
The execution time required to choose the next execution process, which is incurred in
addition to any context switching overhead.
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To calculate the utilization of CPU
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5.4)Preemptive Real-
Real-Time Operating
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Systems(RTOS)
A pre emptive OS solves the fundamental problem in multitasking system.
.c
It executes processes based upon timing requirements provided by the system designer.
To meet timing constraints accurately is to build a preemptive OS and to use priorities to
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control what process runs at any given time.
5.4.1) Preemption
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Preemption is an alternative to the C function call to control execution.
To be able to take full advantage of the timer, change the process as something more than
a function call.
Break the assumptions of our high-level programming language.
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Create new routines that allow us to jump from one subroutine to another at any point in
the program.
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The timer, will allow us to move between functions whenever necessary based upon the
system’s timing constraints.
5.4.2) Kernel
It is the part of the OS that determines what process is running.
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The kernel is activated periodically by the timer.
It determines what process will run next and causes that process to run.
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5.4.3) Priorities
Based on the priorities kernel can do the processes sequentially.
which ones actually want to execute and select the highest priority process that is ready
to run.
.c
This mechanism is both flexible and fast.
The priority is a non-negative integer value.
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•When the system begins execution,P2 is the only ready process, so it is selected for execution.
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•At T=15, P1 becomes ready; it preempts P2 because p1 has a higher priority, so it execute
immediately
•P3’s data arrive at time 18, it has lowest priority.
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•P2 is still ready and has higher priority than P3.
•Only after both P1 and P2 finish can P3 execute
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5.4.4) Context Switching
To understand the basics of a context switch, let’s assume that the set of tasks is
in steady state.
.c
Everything has been initialized, the OS is running, and we are ready for a timer
interrupt.
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This diagram shows the application tasks, the hardware timer, and all the
functions in the kernel that are involved in the context switch.
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vPreemptiveTick() it is called when the timer ticks.
portSAVE_CONTEXT() swaps out the current task context.
vTaskSwitchContext ( ) chooses a new task.
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portRESTORE_CONTEXT() swaps in the new context
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5.5) PRIORITY-
PRIORITY-BASED SCHEDULING
Operating system is to allocate resources in the computing system based on
the priority.
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After assigning priorities, the OS takes care of the rest by choosing the highest-
priority ready process.
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There are two major ways to assign priorities.
Static priorities that do not change during execution
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Dynamic priorities that do change during execution
Types of scheduling process
1. Rate-Monotonic Scheduling
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2. Earliest-Deadline-First Scheduling
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5.5.1)
.5.1)RRate
ate--Monotonic Scheduling(
cheduling(RMS
RMS))
Rate-monotonic scheduling (RMS) is one of the first scheduling policies
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developed for real-time systems.
RMS is a static scheduling policy.
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It assigns fixed priorities are sufficient to efficiently schedule the processes in
many situations.
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RMS is known as rate-monotonic analysis (RMA), as summarized below.
All processes run periodically on a single CPU.
Context switching time is ignored.
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There are no data dependencies between processes.
The execution time for a process is constant.
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All deadlines are at the ends of their periods.
The highest-priority ready process is always selected for execution.
Priorities are assigned by rank order of period, with the process with the
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shortest period being assigned the highest priority.
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Example-Rate-monotonic scheduling
set of processes and their characteristics
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According to RMA Assign highest priority for least execution period.
Hence P1 the highest priority, P2 the middle priority,and P3 the lowest priority.
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First execute P1 then P2 and finally P3.(T1>T2>T3)
After assigning priorities, construct a time line equal in length to hyper period, which is 12
in this case.
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Every 4 time intervals P1 executes 1 units.(Execution time intervals for
P1 0-4,4-8,8-12)
Every 6 time intervals P2 executes 2 units. .(Execution time intervals
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for P2 0-6,6-12)
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Every 12 intervals P3 executes 3 units. .(Execution time intervals for P3
0-12)
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Time interval from 10-12 no scheduling available because no process
will be available for execution. All process are executed already.
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P1 is the highest-priority process, it can start to execute immediately.
After one time unit, P1 finishes and goes out of the ready state until the start of its next
period.
At time 1, P2 starts executing as the highest-priority ready process.
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At time 3, P2 finishes and P3 starts executing.
P1’s next iteration starts at time 4, at which point it interrupts P3.
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P3 gets one more time unit of execution between the second iterations of P1 and P2, but
P3 does not get to finish until after the third iteration of P1.
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Consider the following different set of execution times.
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In this case, Even though each process alone has an execution time significantly less than
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its period, combinations of processes can require more than 100% of the available CPU
cycles.
During one 12 time-unit interval, we must execute P1 -3 times, requiring 6 units of CPU
time; P2 twice, costing 6 units and P3 one time, costing 3 units.
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The total of 6 + 6 + 3 = 15 units of CPU time is more than the 12 time units available,
clearly exceeding the available CPU capacity(12units).
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RMA priority assignment analysis
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Response time The time at which the process finishes.
Critical instantThe instant during execution at which the task has the largest response
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time.
Let the periods and computation times of two processes P1 and P2 be τ1, τ2 and T1, T2,
with τ 1 < τ 2.
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let P1 have the higher priority. In the worst case we then execute P2 once during its period
and as many iterations of P1 as fit in the same interval.
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Since there are τ2/ τ1 iterations of P1 during a single period of P2.
The required constraint on CPU time, ignoring context switching overhead, is
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we give higher priority to P2, then execute all of P2 and all of P1 in one of P1’s periods in
the worst case.
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Total CPU utilization for a set of n tasks is
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5.5.2)EEarliest
5.5.2) arliest--Deadline
eadline--First Scheduling(EDF
Scheduling(EDF))
Earliest deadline first (EDF) is a dynamic priority scheme.
It changes process priorities during execution based on initiation times.
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As a result, it can achieve higher CPU utilizations than RMS.
The EDF policy is also very simple.
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It assigns priorities in order of deadline.
Assign highest priority to a process who has Earliest deadline.
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Assign lowest priority to a process who has farthest deadline.
After assigning scheduling procedure, the highest-priority process is chosen for
execution.
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Consider the following Example
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Hyper-period is 60
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Dead line Table
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There is one time slot left at t= 30, giving a CPU utilization of 59/60.
EDF can achieve 100% utilization
RMS vs. EDF
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Ex:Priority inversion
Low-priority process blocks execution of a higher priority process by keeping hold
of its resource.
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Consider a system with two processes
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Higher-priority P1 and the lower-priority P2.
Each uses the microprocessor bus to communicate to peripherals.
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When P2 executes, it requests the bus from the operating system and receives it.
If P1 becomes ready while P2 is using the bus, the OS will preempt P2 for P1,
leaving P2 with control of the bus.
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When P1 requests the bus, it will be denied the bus, since P2 already owns it.
Unless P1 has a way to take the bus from P2, the two processes may deadlock.
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Eg:Data dependencies and scheduling
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Data dependencies imply that certain combinations of processes can never occur. Consider the
simple example.
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We know that P1 and P2 cannot execute at the same time, since P1 must finish before P2 can
begin.
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P3 has a higher priority, it will not preempt both P1 and P2 in a single iteration.
If P3 preempts P1, then P3 will complete before P2 begins.
if P3 preempts P2, then it will not interfere with P1 in that iteration.
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Because we know that some combinations of processes cannot be ready at the same time,
worst-case CPU requirements are less than would be required if all processes could be ready
simultaneously.
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5.5)Inter--process communication mechanisms
5.5)Inter
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It is provided by the operating system as part of the process abstraction.
Blocking Communication The process goes into the waiting state until it receives a
response
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Non-blocking CommunicationIt allows a process to continue execution after
sending the communication.
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Types of inter-process communication
1. Shared Memory Communication
2. Message Passing
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3. Signals
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5.5.1) Shared Memory Communication
The communication between inter-process is used by bus-based system.
CPU and an I/O device, communicate through a shared memory location.
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The software on the CPU has been designed to know the address of the shared location.
The shared location has also been loaded into the proper register of the I/O device.
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If CPU wants to send data to the device, it writes to the shared location.
The I/O device then reads the data from that location.
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The read and write operations are standard and can be encapsulated in a procedural
interface.
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CPU and the I/O device want to communicate through a shared memory block.
There must be a flag that tells the CPU when the data from the I/O device is ready.
The flag value of 0 when the data are not ready and 1 when the data are ready.
If the flag is used only by the CPU, then the flag can be implemented using a standard
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memory write operation.
If the same flag is used for bidirectional signaling between the CPU and the I/O device,
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care must be taken.
Consider the following scenario to call flag
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1. CPU reads the flag location and sees that it is 0.
2. I/O device reads the flag location and sees that it is 0.
3. CPU sets the flag location to 1 and writes data to the shared location.
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4. I/O device erroneously sets the flag to 1 and overwrites the data left by the CPU.
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Ex: Elastic buffers as shared memory
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The text compressor is a good example of a shared memory.
The text compressor uses the CPU to compress incoming text, which is then sent on a
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serial line by a UART.
The input data arrive at a constant rate and are easy to manage.
But the output data are consumed at a variable rate, these data require an elastic buffer.
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The CPU and output UART share a memory area—the CPU writes compressed characters
into the buffer and the UART removes them as necessary to fill the serial line.
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Because the number of bits in the buffer changes constantly, the compression and
transmission processes need additional size information.
CPU writes at one end of the buffer and the UART reads at the other end.
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The only challenge is to make sure that the UART does not overrun the buffer.
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5.5.2) Message Passing
Here each communicating entity has its own message send/receive unit.
The message is not stored on the communications link, but rather at the senders/ receivers
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at the end points.
Ex:Home control system
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It has one microcontroller per household device—lamp, thermostat, faucet, appliance.
The devices must communicate relatively infrequently.
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Their physical separation is large enough that we would not naturally think of them as
sharing a central pool of memory.
Passing communication packets among the devices is a natural way to describe
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coordination between these devices.
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5.5.3) Signals
Generally signal communication used in Unix .
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A signal is analogous to an interrupt, but it is entirely a software creation.
A signal is generated by a process and transmitted to another process by the OS.
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A UML signal is actually a generalization of the Unix signal.
Unix signal carries no parameters other than a condition code.
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UML signal is an object, carry parameters as object attributes.
The sigbehavior( ) behavior of the class is responsible for throwing the signal,
as indicated by<<send>>.
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The signal object is indicated by the <<signal>>
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5.6)Evaluating operating system performance
Analysis of scheduling policies is made by the following 4 assumptions
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Assumed that context switches require zero time. Although it is often
reasonable to neglect context switch time when it is much smaller than the
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process execution time, context switching can add significant delay in some
cases.
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We have largely ignored interrupts. The latency from when an interrupt is
requested to when the device’s service is complete is a critical parameter of real
time performance.
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We have assumed that we know the execution time of the processes.
We probably determined worst-case or best-case times for the processes in
isolation.
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5.6.1)Context switching time
It depends on following factors
The amount of CPU context that must be saved.
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Scheduler execution time.
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5.6.2)Interrupt latency
Interrupt latency It is the duration of time from the assertion of a device interrupt to
the completion of the device’s requested operation.
Interrupt latency is critical because data may be lost when an interrupt is not serviced in
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a timely fashion.
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A task is interrupted by a device.
The interrupt goes to the kernel, which may need to finish a protected operation.
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Once the kernel can process the interrupt, it calls the interrupt service routine (ISR),
which performs the required operations on the device.
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Once the ISR is done, the task can resume execution.
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Several factors in both hardware and software affect interrupt latency:
The processor interrupt latency
The execution time of the interrupt handler
Delays due to RTOS scheduling
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RTOS delay the execution of an interrupt handler in two ways.
Critical sections and interrupt latency
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Critical sections in the kernel will prevent the RTOS from taking interrupts.
Some operating systems have very long critical sections that disable interrupt handling for
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very long periods.
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If a device interrupts during a critical section, that critical section must finish before the
kernel can handle the interrupt.
The longer the critical section, the greater the potential delay.
Critical sections are one important source of scheduling jitter because a device may
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interrupt at different points in the execution of processes and hit critical sections at
different points.
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Interrupt priorities and interrupt latency
A higher-priority interrupt may delay a lower-priority interrupt.
A hardware interrupt handler runs as part of the kernel, not as a user thread.
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The priorities for interrupts are determined by hardware.
Any interrupt handler preempts all user threads because interrupts are part of the CPU’s
fundamental operation.
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We can reduce the effects of hardware preemption by dividing interrupt handling into
two different pieces of code.
Interrupt service handler (ISH) performs the minimal operations required to
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respond to the device.
Interrupt service routine (ISR) Performs updating user buffers or other more
complex operation.
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RTOS performance evaluation tools
Some RTOSs provide simulators or other tools that allow us to view the
operation of the processes,context switching time, interrupt response time,
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and other overheads.
Windows CE provides several performance analysis tools
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An instrumentation routine in the kernel that measures both interrupt service
routine and interrupt service thread latency.
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OS Bench measures the timing of operating system tasks such as critical
section access, signals, and so on
Kernel Tracker provides a graphical user interface for RTOS events.
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5.7)Power optimization strategies for processes
A power management policy is a strategy for determining when to perform
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certain power management operations.
The system can be designed based on the static and dynamic power
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management mechanisms.
Power saving straegies
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Avoiding a power-down mode can cost unnecessary power.
Powering down too soon can cause severe performance penalties.
Re-entering run mode typically costs a considerable amount of time.
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A straightforward method is to power up the system when a request is received.
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Predictive shutdown
The goal is to predict when the next request will be made and to start the
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system just before that time, saving the requestor the start-up time.
Make guesses about activity patterns based on a probabilistic model of
expected behavior.
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This can cause two types of problems
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The requestor may have to wait for an activity period.
In the worst case,the requestor may not make a deadline due to the delay
incurred by system
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An L-
L-shaped usage distribution
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A very simple technique is to use fixed times.
If the system does not receive inputs during an interval of length Ton, it shuts down.
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Powered-down system waits for a period Toff before returning to the power-on mode.
In this distribution, the idle period after a long active period is usually very short, and the
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length of the idle period after a short active period is uniformly distributed.
Based on this distribution, shutdown when the active period length was below a threshold,
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putting the system in the vertical portion of the L distribution.
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Advanced Configuration and Power Interface (ACPI)
It is an open industry standard for power management services.
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It is designed to be compatible with a wide variety of OSs.
A decision module determines power management actions.
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ACPI supports the following five basic global power states.
1. G3, the mechanical off state, in which the system consumes no power.
2. G2, the soft off state, which requires a full OS reboot to restore the machine to
working condition. This state has four sub-states:
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S1, a low wake-up latency state with no loss of system context
S2, a low wake-up latency state with a loss of CPU and system cache state
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S3, a low wake-up latency state in which all system state except for main
memory is lost.
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S4, the lowest-power sleeping state, in which all devices are turned off.
3. G1, the sleeping state, in which the system appears to be off.
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4. G0, the working state, in which the system is fully usable.
5. The legacy state, in which the system does not comply with ACPI.
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5.8)Example Real time operating systems
5.8.1)POSIX
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POSIX is a Unix operating system created by a standards organization.
POSIX-compliant operating systems are source-code compatible.
ul
Application can be compiled and run without modification on a new POSIX
platform.
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It has been extended to support real time requirements.
Many RTOSs are POSIX-compliant and it serves as a good model for basic
RTOS techniques.
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The Linux operating system has a platform for embedded computing.
Linux is a POSIX-compliant operating system that is available as open source.
Linux was not originally designed for real-time operation .
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Some versions of Linux may exhibit long interrupt latencies,
To improve interrupt latency,A dual-kernel approach uses a specialized kernel,
the co-kernel, for real-time processes and the standard kernel for non-real-
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Process in POSIX
A new process is created by making a copy of an existing process.
The copying process creates two different processes both running the same code.
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The complex task is to ensuring that one process runs the code intended for the new process
while the other process continues the work of the old process .
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Scheduling in POSIX
A process makes a copy of itself by calling the fork() function.
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That function causes the operating system to create a new process (the child process) which is
a nearly exact copy of the process that called fork() (the parent process).
They both share the same code and the same data values with one exception, the return value
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of fork().
The parent process is returned the process ID number of the child process, while the child
process gets a return value of 0.
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We can therefore test the return value of fork() to determine which process is the child
childid = fork();
if (childid == 0) { /* must be the child */
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/* do child process here */
}
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execv() function takes as argument the name of the file that holds the child’s
code and the array of arguments.
It overlays the process with the new code and starts executing it from the
main() function.
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In the absence of an error, execv() should never return.
The code that follows the call to perror() and exit(), take care of the case where
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execv() fails and returns to the parent process.
The exit() function is a C function that is used to leave a process
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childid = fork();
if (childid == 0) { /* must be the child */
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execv(“mychild”,childargs);
perror(“execv”);
exit(1);
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}
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The wait functions not only return the child process’s status, in many
implementations of POSIX they make sure that the child’s resources .
The parent stuff() function performs the work of the parent function.
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childid = fork();
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if (childid == 0) { /* must be the child */
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execv(“mychild”,childargs);
perror(“execl”);
exit(1);
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}
else { /* is the parent */
parent_stuff(); /* execute parent functionality */
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wait(&cstatus);
exit(0);
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}
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The POSIX process model
Each POSIX process runs in its own address space and cannot directly access the
data or code.
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Real-time scheduling in POSIX
POSIX supports real-time scheduling in the POSIX_PRIORITY_SCHEDULING
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resource.
POSIX supports Rate-monotonic scheduling in the SCHED_FIFO scheduling
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policy.
It is a strict priority-based scheduling scheme in which a process runs until it is
preempted or terminates.
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The term FIFO simply refers processes run in first-come first-served order.
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POSIX semaphores
POSIX supports semaphores and also supports a direct shared memory mechanism.
POSIX supports counting semaphores in the _POSIX_SEMAPHORES option.
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A counting semaphore allows more than one process access to a resource at a time.
If the semaphore allows up to N resources, then it will not block until N processes have
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simultaneously passed the semaphore;
The blocked process can resume only after one of the processes has given up its
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semaphore.
When the semaphore value is 0, the process must wait until another process gives up the
semaphore and increments the count.
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POSIX pipes
Parent process uses the pipe() function to create a pipe to talk to a child.
Each end of a pipe appears to the programs as a file.
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The pipe() function returns an array of file descriptors, the first for the write end and the
second for the read end.
POSIX also supports message queues under the _POSIX_MESSAGE_PASSING facility..
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5.8.2)Windows CE
Windows CE is designed to run on multiple hardware platforms and
instruction set architectures.
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It supports devices such as smart phones, electronic instruments etc..,
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Applications run under the shell and its user interface.
The Win32 APIs manage access to the operating system.
OEM Adaption Layer (OAL) provides an interface to the hardware and software
architecture.
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OAL provides services such as a real-time clock, power management, interrupts, and a
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debugging interface.
A Board Support Package (BSP) for a particular hardware platform includes the OAL and
drivers.
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Memory Space
It support for virtual memory with a flat 32-bit virtual address space.
A virtual address can be statically mapped into main memory for key kernel-mode code.
An address can also be dynamically mapped, which is used for all user-mode and some
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kernel-mode code.
Flash as well as magnetic disk can be used as a backing store
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The top 1 GB is reserved for system elements such as DLLs, memory mapped files, and
shared system heap.
The bottom 1 GB holds user elements such as code, data, stack, and heap.
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User address space in windows CE
Threads are defined by executable files while drivers are defined by
dynamically-linked libraries (DLLs).
A process can run multiple threads.
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Threads in different processes run in different execution
environments.
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Threads are scheduled directly by the operating system.
Threads may be launched by a process or a device driver.
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A driver may be loaded into the operating system or a process.
Drivers can create threads to handle interrupts
Each thread is assigned an integer priority.
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0 is the highest priority and 255 is the lowest priority.
Priorities 248 through 255 are used for non-real-time threads .
The operating system maintains a queue of ready processes at each
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Execution of a thread can also be blocked by a higher-priority thread.
Tasks may be scheduled using either of two policies: a thread runs until the end
of its quantum; or a thread runs until a higher-priority thread is ready to run.
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Within each priority level, round-robin scheduling is used.
WinCE supports priority inheritance.
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When priorities become inverted, the kernel temporarily boosts the priority of
the lower-priority thread to ensure that it can complete and release its
resources.
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Kernel will apply priority inheritance to only one level.
If a thread that suffers from priority inversion in turn causes priority inversion
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for another thread, the kernel will not apply priority inheritance to solve the
nested priority inversion.
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Sequence diagram for an interrupt
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Interrupt handling is divided among three entities
The interrupt service handler (ISH) is a kernel service that provides the first
response to the interrupt.
The ISH selects an interrupt service routine (ISR) to handle the interrupt.
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The ISR in turn calls an interrupt service thread (IST) which performs most of
the work required to handle the interrupt.
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The IST runs in the OAL and so can be interrupted by a higher-priority
interrupt.
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ISRdetermines which IST to use to handle the interrupt and requests the
kernel to schedule that thread.
The ISH then performs its work and signals the application about the updated
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device status as appropriate.
kernel-mode and user-mode drivers use the same API.
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5.9) Distributed Embedded Systems (DES)
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It is a collection of hardware and software and its communication.
It also has many control system performance.
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Processing Element (PE)is a basic unit of DES.
It allows the network to communicate.
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PE is an instruction set processor such as DSP,CPU and Microcontroller.
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Network abstractions
Networks are complex systems.
It provide high-level services such as data transmission from the other
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components in the system.
ISO has developed a seven-layer model for networks known as Open Systems
Interconnection (OSI) models.
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5.9.1)OSI model layers
Physical layer defines the basic properties of the
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interface between systems, including the physical
connections, electrical properties & basic procedures
for exchanging bits.
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Data link layer used for error detection and control
across a single link.
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Network layer defines the basic end-to-end data
transmission service.
Transport layer defines connection-oriented
services that ensure that data are delivered in the
proper order .
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Session layer provides mechanisms for controlling
the interaction of end-user services across a network,
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such as data grouping and checkpointing.
Presentation layer layer defines data exchange
formats
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Application layer provides the application interface
between the network and end-user programs.
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5.9.2)C
5.9.2) Controller Area Network
etwork(CAN)
(CAN)Bus
Bus
It was designed for automotive electronics
and was first used in production cars in 1991.
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It uses bit-serial transmission.
CAN can run at rates of 1 Mbps over a twisted
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pair connection of 40 meters.
An optical link can also be used.
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4.7.2.1)Physical-electrical organization of a CAN
bus
Each node in the CAN bus has its own
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electrical drivers and receivers that connect
the node to the bus in wired-AND fashion.
When all nodes are transmitting 1s, the bus is
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said to be in the recessive state.
when a node transmits a 0s, the bus is in the
dominant state.
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5.9.2.2)Data Frame
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Arbitration field The first field in the packet contains the packet’s destination address 11 bits
Remote Transmission Request (RTR) bit is set to 0 if the data frame is used to request data
from the destination identifier.
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When RTR = 1, the packet is used to write data to the destination identifier.
Control field 4-bit length for the data field with a 1 in between.
Data field0 to 64 bytes, depending on the value given in the control field.
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CRC It is sent after the data field for error detection.
Acknowledge field identifier signal whether the frame was correctly received.( sender puts a
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bit (1) in the ACK slot , if the receiver detected an error, it put (0) value)
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Arbitration
It uses a technique known as Carrier Sense Multiple Access with Arbitration on Message
Priority (CSMA/AMP).
When a node hears a dominant bit in the identifier when it tries to send a recessive bit, it
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stops transmitting.
By the end of the arbitration field, only one transmitter will be left.
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The identifier field acts as a priority identifier, with the all-0 having the highest priority
Error handling
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An error frame can be generated by any node that detects an error on the bus.
Upon detecting an error, a node interrupts the current transmission.
Error flag field followed by an error delimiter field of 8 recessive bits.
transmission can resume.
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Error delimiter field allows the bus to return to the quiescent state so that data frame
Overload frame signals that a node is overloaded and will not be able to handle the next
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message. Hence the node can delay the transmission of the next frame .
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5.9.2.3)Architecture of a CAN controller
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The controller implements the physical and data link layers.
CAN does not need network layer services to establish end-to-end
connections.
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The protocol control block is responsible for determining when to send
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messages, when a message must be resent and when a message should
be received.
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5.9.3) I2C bus
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I2C bus used to link microcontrollers
into systems.
I2C is designed to be low cost, easy to
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implement, and of moderate speed (up to
100kbps for the standard bus and up to
400 kbps for the extended bus).
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Serial data line (SDL) for data
transmission.
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Serial clock line (SCL) indicates when
valid data are on the data line.
Every node in the network is connected to
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both SCL and SDL.
Some nodes may act as bus masters .
Other nodes may act as slaves that only
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5.9.3.1)Electrical interface to the I2C bus
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Both bus lines are defined by an electrical signal.
Both bus signals use open collector/open drain
circuits.
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The open collector/open drain circuitry allows a slave
device to stretch a clock signal during a read.
The master is responsible for generating the SCL
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clock.
The slave can stretch the low period of the clock.
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It is a multi master bus so different devices may act
as the master at various times.
Master drives both SCL and SDL when it is sending
data.
high.
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When the bus is idle, both SCL and SDL remain
When two devices try to drive either SCL or SDL ,
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the open collector/open drain circuitry prevents
errors.
Each master device make sure that it is not
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5.9.3.2)Format of an I2C address transmission
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Every I2C device has an separate address.
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A device address is 7 bits and 1 bit for read/write data.
The address 0000000 ,which can be used to signal all devices simultaneously.
The address 11110XX is reserved for the extended 10-bit addressing scheme.
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5.9.3.3)Bus transactions on the I2C bus
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When a master wants to write a slave, it transmits the slave’s address followed by the data.
When a master send a read request with the slave’s address and the slave transmit the data.
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Transmission address has 7-bit and 1 bit for data direction.( 0 for writing from the master to
the slave and 1 for reading from the slave to the master)
A bus transaction is initiated by a start signal and completed with an end signal.
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A start is signaled by leaving the SCL high and sending a 1 to 0 transition on SDL.
A stop is signaled by setting the SCL high and sending a 0 to 1 transition on SDL.
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5.9.3.4)State transition graph for an I2C bus master
Starts and stops must be paired.
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A master can write and then read by sending a start after the data transmission, followed
by another address transmission and then more data.
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5.9.3.5)Transmitting a byte on the I2C bus
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The transmission starts when SDL is pulled low while SCL remains high.
The clock is pulled low to initiate the data transfer.
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At each bit, the clock goes high while the data line assumes its proper value of 0 or 1.
An acknowledgment is sent at the end of every 8-bit transmission, whether it is an
address or data.
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After acknowledgment, the SDL goes from low to high while the SCL is high, signaling
the stop condition.
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5.9.3.6)I2C
5.9.3.6) I2C interface in a microcontroller
System has a 1-bit hardware interface with routines for byte-level functions.
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I2C device used to generates the clock and data.
Application code calls routines to send an address, data byte, and also generates the SCL
,SDL and acknowledges.
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Timers is used to control the length of bits on the bus.
When Interrupts used in master mode, polled I/O may be acceptable.
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If no other pending tasks can be performed, because masters initiate their own transfers.
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5.9.4)ETHERNET
It is widely used as a local area network for general-purpose computing.
It is also used as a network for embedded computing.
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It is particularly useful when PCs are used as platforms, making it possible to use
standard components, and when the network does not have to meet real-time
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requirements.
It is a bus with a single signal path.
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It supports both twisted pair and coaxial cable.
Ethernet nodes are not synchronized, if two nodes decide to transmit at the same
time,the message will be ruined.
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5.9.4.1)Ethernet CSMA/CD algorithm
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A node that has a message waits for the
bus to become silent and then starts
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transmitting.
It simultaneously listens, and if it hears
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another transmission that interferes with
its transmission, it stops transmitting and
waits to retransmit.
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The waiting time is random, but weighted
by an exponential function of the number
of times the message has been aborted
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5.9.4.2)Ethernet--Packet format
5.9.4.2)Ethernet
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Preamble 56-bit of alternating 1 and 0 bits, allowing devices on the network
to easily synchronize their receiver clocks.
SFD8-bit ,indicates the beginning of the Ethernet frame
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Physical or MAC addresses destination and the source( 48-bit length)
Length data payloadThe minimum payload is 42 octets
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5.9.5)IINTERNET PROTOCOL(
5.9.5) ROTOCOL(IP
IP))
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It is the fundamental protocol on the Internet.
It provides connection orientded, packet-based
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communication.
It transmits packet over different networks from
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source to destination.
It allows data to flow seamlessly from one end user to
another.
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When node A wants to send data to node B, the data
pass through several layers of the protocol stack to
get to the Internet Protocol.
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IP creates packets for routing to the destination,
which are then sent to the data link and physical
layers.
A packet may go through many routers to get to its
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destination.
IP works at the network layer does not
guarantee that a packet is delivered to its
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It supports best-effort routing packets packets
that do arrive may come out of order.
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5.9.5.1)IP packet structure
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Version it ia s 4-bit field.used to identify v4 or v6.
Header Length (HL)It is a 4 bits, field.Indicates the length of the header.
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Service Typeit is a 8 bit field ,used to specify the type of service.
Total lengthIncluding header and data payload is 65,535 bytes.
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Identification identifying the group of fragments of a single IP datagram.
Flags bit 0 Reserved.
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bit 1: Don't Fragment (DF)
bit 2: More Fragments (MF)
Fragment Offset It is 13 bits long , specifies the offset of a particular fragment relative to
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the beginning of the original unfragmented IP datagram
Time To Live (TTL)It is a 8 bit wide, indicates th datagram's lifetime
Protocol protocol used in the data portion of the IP datagram
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Header Checksum(16 bit) used for error-checking of the header
Source address Sender packet address(32-bits size)
Destination address Receiver packet address(32-bits size)
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5.9.5.1) Transmission Control Protocol(
rotocol(TCP
TCP))
It provides a connection-oriented service.
It ensures that data arrive in the appropriate order.
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It uses an acknowledgment protocol to ensure that packets arrive.
TCP is used to provide File Transport Protocol (FTP) for batch file transfers.
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Hypertext Transport Protocol (HTTP) for World Wide Web service.
Simple Mail Transfer Protocol (SMTP) for email.
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Telnet for virtual terminals.
User Datagram Protocol (UDP), is used to provide connection-less services.
Simple Network Management Protocol (SNMP) provides the network management services.
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5.10) MPSoCs and shared memory
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multiprocessors
Shared memory processors are well-suited to applications that require a large amount
of data to be processed(Signal processing systems )
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Most MPSoCs are shared memory systems.
Shared memory allows for processors to communicate with varying patterns.
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If the pattern of communication is very fixed and if the processing of different steps is
performed in different units, then a networked multiprocessor may be most appropriate.
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If one processing element is used for several different steps, then shared memory also
allows the required flexibility in communication.
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5.10.1)Heterogeneous shared memory multiprocessors
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Many high-performance embedded platforms are heterogeneous multiprocessors.
Different processing elements (PE)perform different functions.
PEs may be programmable processors with different instruction sets or specialized
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accelerators.
Processors with different instruction sets can perform different tasks faster and using less
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energy.
Accelerators provide even faster and lower-power operation for a narrow range of
functions.
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5.10.2)Accelerators
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It is the important processing element for embedded multiprocessors.
It can provide large performance increases for applications with computational kernels .
It can also provide critical speedups for low-latency I/O functions.
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CPU(host) accelerator is attached to the CPU bus.
CPU talks to the accelerator through data and control registers in the accelerator.
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Control registers allow the CPU to monitor the accelerator’s operation and to give the
accelerator commands.
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The CPU and accelerator may also communicate via shared memory.
The accelerator operate on a large volume of data with efficient data in memory.
Accelerator read and write memory directly .
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The CPU and accelerator use synchronization mechanisms to ensure that they do not
destroy each other’s data.
An accelerator is not a co-processor.
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A co-processor is connected to the internals of the CPU and processes instructions.
An accelerator interacts with the CPU through the programming model interface.
It does not execute instructions.
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CPU and accelerators performs computations for specification.
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CPU accelerators in a system
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5.10.2)Accelerator Performance Analysis
The speed factor of accelerator will depend on the following factors.
Single threadedCPU is in idle state while the accelerator runs.
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MultithreadedCPU do some useful work in parallel with accelerator.
Blocking CPU’s scheduler block other operations wait for the accelerator call to
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complete.
Non-blocking CPU’s run some other work parallel with accelerator.
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Data dependencies allow P2 and P3 to run independently on the CPU.
P2 relies on the results of the A1 process that is implemented by the accelerator.
Single-threaded CPU blocks to wait for the accelerator to return the results of its
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computation.t, it doesn’t matter whether P2 or P3 runs next on the CPU.
Multithreaded CPU continues to do useful work while the accelerator runs, so the CPU
can start P3 just after starting the accelerator and finish the task earlier.
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5.10.3)Components of execution time for an accelerator
Execution time of a accelerator depends on the
time required to execute the accelerator’s
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function.
It also depends on the time required to get the
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data into the accelerator and back out of it.
Accelerator will read all its input data, perform
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the required computation,and write all its results.
Total execution time given as
tacccel=tx+tin+tout
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tx execution time of the accelerator
Tin times required for reading the required
variables
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tout- times required for writing the required
variables
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5.10.4)System Architecture Framework
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Architectural design depends on the application.
An accelerator can be considered from two angles.
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Accelerator core functionality
Accelerator interface to the CPU bus.
The accelerator core typically operates off internal
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registers.
Requirement of number of registers is an important
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design decision.
Main memory accesses will probably take multiple
clock cycles.
Status registers used to test the accelerator’s state and
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to perform basic operations(starting, stopping, and
resetting the accelerator)
A register file in the accelerator acts as a buffer between
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main memory and the accelerator core.
Read unit can read the accelerator’s requirements and
load the registers with the next required data.
Write unit can send recently completed values to main
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5.10.5)cache problem in an accelerated system
CPU cache can cause problems for
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accelerators.
1. The CPU reads location S.
2. The accelerator writes S.
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3. The CPU again reads S.
If the CPU has cached location S ,the
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program will not see the value of S
written by the accelerator. It will instead
get the old value of S stored in the cache.
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To avoid this problem, the CPU’s cache
must update the cache by setting cache
entry is invalid.
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5.10.6)Scheduling and allocation
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Designing a distributed embedded system, depends upon the scheduling and allocation
of resources.
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We must schedule operations in time, including communication on the network and
computations on the processing elements.
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The scheduling of operations on the PEs and the communications between the PEs are
linked.
If one PE finishes its computations too late, it may interfere with another communication
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on the network as it tries to send its result to the PE that needs it.
This is bad for both the PE that needs the result and the other PEs whose communication
is interfered with.
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We must allocate computations to the processing elements.
The allocation of computations to the PEs determines what communications are
required—if a value computed on one PE is needed on another PE, it must be
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transmitted over the network.
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We can specify the system as a task graph. However, different processes may end up on
different processing elements. Here is a task graph
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We have labeled the data transmissions on each arc ,We want to execute the task on the
platform below.
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The platform has two processing elements and a single bus connecting both PEs. Here
are the process speeds:
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As an initial design, let us allocate P1 and P2 to M1 and P3 to M2This schedule shows
what happens on all the processing elements and the network.
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The schedule has length 19. The d1 message is sent between the processes internal to
P1 and does not appear on the bus.
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Let’s try a different allocation. P1 on M1 and P2 and P3 on M2. This makes P2 run more
slowly. Here is the new schedule:.
The length of this schedule is 18, or one time unit less than the other schedule. The
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increased computation time of P2 is more than made up for by being able to transmit a
shorter message on the bus. If we had not taken communication into account when
analyzing total execution time, we could have made the wrong choice of which processes
to put on the same processing element.
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5.11) Audio player/MP3 Player
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5.11.1)Operation and requirements
MP3 players use either flash memory or disk drives to store music.
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It performs the following functions such as audio storage, audio decompression, and
user interface.
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Audio compression It is a lossy process. The coder eliminates certain features of the audio
stream so that the result can be encoded in fewer bits.
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Audio decompression The incoming bit stream has been encoded using a Huffman style
code, which must be decoded.
Masking One tone can be masked by another if the tones are sufficiently close in frequency.
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Audio compression standards
Layer 1 (MP1) uses a lossless compression of sub bands and simple masking model.
Layer 2 (MP2) uses a more advanced masking model.
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Layer 3 (MP3) performs additional processing to provide lower bit rates.
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5.11.2)MPEG Layer 1 encoder
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Filter bank splits the signal into a set of 32 sub-
bands that are equally spaced in the frequency
domain and together cover the entire frequency
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range of the audio.
EncoderIt reduce the bit rate for the audio
signals.
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Quantizer scales each sub-band( fits within 6
bits ), then quantizes based upon the current scale
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factor for that sub-band.
Masking model It is driven by a separate Fast
Fourier transform (FFT), the filter bank could be
used for masking, a separate FFT provides better
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results.
The masking model chooses the scale factors for
the sub-bands, which can change along with the
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audio stream.
Multiplexer output of the encoder passes along
all the required data.
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MPEG Layer 1 data frame format
A frame carries the basic MPEG data, error correction codes, and additional information.
After disassembling the data frame, the data are un-scaled and inverse quantized to
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produce sample streams for the sub-band.
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5.11.3)MPEG Layer 1 decoder
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•After disassembling the data frame, the data are un-
scaled and inverse quantized to produce sample
streams for the sub-band.
•An inverse filter bank then reassembles the sub-bands
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into the uncompressed signal.
User interface MP3 player is simple both the
physical size and power consumption of the device.
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Many players provide only a simple display and a few
buttons.
File system
system player generally must be compatible
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with PCs. CD/MP3 players used compact discs that had
been created on PCs.
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5.11.4)Requirements
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5.11.5) Specification
The File ID class is an abstraction of a file in the flash file system.
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The controller class provides the method that operates the player.
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5.11.6) State diagram for file display and selection
This specification assumes that all files are in the root directory and that all files are
playable audio.
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5.11.7) State diagram for Audio Playback
It refers to sending the samples to the audio system.
Playback and reading the next data frame must be overlapped to ensure continuous operation.
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The details of playback depend on the hardware platform selected, but will probably involve a
DMA transfer.
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5.11.8) System architecture
The audio controller includes two processors.
The 32-bit RISC processor is used to perform system control and audio decoding.
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The 16-bit DSP is used to perform audio effects such as equalization.
The memory controller can be interfaced to several different types of memory.
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Flash memory can be used for data or code storage.
DRAM can be used to handle temporary disruptions of the CD data stream.
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The audio interface unit puts out audio in formats that can be used by A/D converters.
General- purpose I/O pins can be used to decode buttons, run displays.
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5.11.9) Component design and testing
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The audio output system should be tested separately from the compression system.
Testing of audio decompression requires sample audio files.
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The standard file system can either implement in a DOS FAT or a new file system.
While a non-standard file system may be easier to implement on the device, it also
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requires software to create the file system.
The file system and user interface can be tested independently .
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5.11.10) System integration and debugging
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It ensure that audio plays smoothly and without interruption.
Any file access and audio output that operate concurrently should be separately tested,
ideally using an easily recognizable test signal.
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5.12)Engine Control Unit
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This unit controls the operation of a
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fuel-injected engine based on
several measurements taken from
the running engine.
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5.12.1)Operation and
Requirements
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The throttle is the command input.
The engine measures throttle,
RPM, intake air volume, and other
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variables.
The engine controller computes
injector pulse width and spark.
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5.12.2)Requirements
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5.12.3)Specification
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The engine controller must deal with processes at different rates
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ΔNE and ΔT to represent the change in RPM and throttle position.
Controller computes two output signals, injector pulse width PW and spark advance
angle S.
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S=k2X ΔNE-k3VS
The controller then applies corrections to these initial values
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If intake air temperature (THA) increases during engine warm-up, the controller reduces
the injection duration.
If the throttle opens, the controller temporarily increases the injection frequency.
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Controller adjusts duration up or down based upon readings from the exhaust oxygen
sensor (OX).
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5.12.4)System architecture
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The two major processes, pulse-
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width and advance-angle,
compute the control parameters
for the spark plugs and injectors.
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Control parameters rely on
changes in some of the input
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signals.
Physical sensor classes used to
compute these values.
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Each change must be updated at
the variable’s sampling rate.
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5.12.5)State diagram for throttle position sensing
Throttle sensing, which saves both the
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current value and change in value of
the throttle.
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5.12.6)State diagram for injector pulse
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width
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In each case, the value is computed
in two stages, first an initial value
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followed by a correction.
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State diagram for spark advance angle
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5.12.7)Component design and testing
Various tasks must be coded to satisfy the requirements of RTOS processes.
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Variables that are maintained across task execution, such as the change-of-state
variables, must be allocated and saved in appropriate memory locations.
Some of the output variables depend on changes in state, these tasks should be tested
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with multiple input variable sequences to ensure that both the basic and adjustment
calculations are performed correctly.
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5.12.8)System integration and testing
Engines generate huge amounts of electrical noise that can cripple digital electronics.
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They also operate over very wide temperature ranges.
1. hot during engine operation,
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2. potentially very cold before the engine is started.
Any testing performed on an actual engine must be conducted using an engine
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controller that has been designed to withstand the harsh environment of the engine
compartment.
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5.13)Video Accelerator
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It is a hardware circuits on a display adapter that speed up fill motion video.
Primary video accelerator functions are color space conversion, which converts YUV to RGB.
Hardware scaling is used to enlarge the image to full screen and double buffering which
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moves the frames into the frame buffer faster.
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Video compression
•MPEG-2 forms the basis for U.S. HDTV
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broadcasting.
• This compression uses several
component algorithms together in a
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feedback loop.
•Discrete cosine transform (DCT) used in
JPEG and MPEG-2.
•DCT used a block of pixels which is
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quantized for lossy compression.
•Variable-length coderassign number of
bits required to represent the block.
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5.13.1)Block motion Estimation
MPEG uses motion to encode one frame in
terms of another.
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Block motion estimationsome frames are
sent as modified forms of other frames
During encoding, the frame is divided into
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macro blocks.
Encoder uses the encoding information to
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recreate the lossily-encoded picture, compares
it to the original frame, and generates an error
signal.
Decoder keep recently decoded frames in
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memory so that it can retrieve the pixel values
of macro-blocks.
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5.13.2).Concept of Block motion estimation
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To find the best match between regions in the two frames.
Divide the current frame into 16 x 16 macro blocks.
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For every macro block in the frame, to find the region in the previous frame that most
closely matches the macro block.
Measure similarity using the following sum-of-differences measure
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M(i,j) intensity of the macro block at pixel i,j,
S(i,j) intensity of the search region
N size of the macro block in one dimension
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<ox, oy>offset between the macro block and search region
We choose the macro block position relative to the search area that gives us the smallest
value for this metric.
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The offset at this chosen position describes a vector from the search area center to the
macro block's center that is called the motion vector.
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5.13.3)Algorithm and requirements
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C code for a single search, which assumes that the search region does not extend past the
boundary of the frame.
.c
The arithmetic on each pixel is simple, but we have to process a lot of pixels.
If MBSIZE is 16 and SEARCHSIZE is 8, and remembering that the search distance in each
dimension is 8 + 1 + 8, then we must perform
ul
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5.13.4)Requirements
om
.c
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5.13.5)Specification
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Specification for the system is relatively straightforward because the algorithm is simple.
The following classes used to describe basic data types in the system motion vector,
.c
macro block, search area.
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5.13.6)Sequence Diagram
.c
The accelerator provides a behavior
compute-mv() that performs the block
motion estimation algorithm.
ul
After initiating the behavior, the accelerator
reads the search area and macro block from
pa
the PC, after computing the motion vector,
it returns it to the PC.
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5.13.7)Architecture
om
The macro block has 16 x16 = 256.
The search area has (8 + 8 + 1 + 8 + 8)2 =
1,089 pixels.
.c
FPGA probably will not have enough
memory to hold 1,089 (8-bit )values.
ul
The machine has two memories, one for
the macro block and another for the
search memories.
pa
It has 16 processing elements that
perform the difference calculation on a
pair of pixels.
jin
Comparator sums them up and selects
the best value to find the motion vector.
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5.13.8)System testing
om
Testing video algorithms requires a large amount of data.
.c
we are designing only a motion estimation accelerator and not a complete video
compressor, it is probably easiest to use images, not video, for test data.
ul
use standard video tools to extract a few frames from a digitized video and store them in
JPEG format.
pa
Open source for JPEG encoders and decoders is available.
These programs can be modified to read JPEG images and put out pixels in the format
required by your accelerator.
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