COURSE STRUCTURE AND SYLLABUS

For

M. Tech

VLSI SYSTEM DESIGN

(Applicable for batches admitted from 2019-2020)

PRAGATI ENGINEERING COLLEGE

(Autonomous)
Permanently Affiliated to JNT University Kakinada and Approved by AICTE, New Delhi,
Accredited by NAAC with “A” Grade
Recognized by UGC 2(f) and 12(b) under UGC act, 1956
1-378, ADB Road, Surampalem – 533 437, Near Peddapuram, E.G.Dist., A.P.
 PRAGATI ENGINEERING COLLEGE: SURAMPALEM
(Autonomous)

VLSI SYSTEM DESIGN

I Semester

Sub Code Name of the Subject L P C

19041T01 Digital System Design 3 3
19041T02 VLSI Technology and Design 3 3
19041T03 CMOS Analog IC Design 3 3
Elective I 3 3
19041D01 1. Digital Design using HDL
19041D02 2. Advanced Operating Systems
19041D03 3. Soft Computing Techniques
Elective II 3 3
19041D04 1. CPLD and FPGA Architectures and
Applications
19041D05 2. Advanced Computer Architecture
19041D06 3. Hardware Software Co-Design
Laboratory - 4 2
16041L01 VLSI Laboratory-I
Total 17

II Semester

Sub Code Name of the Subject L P C

19042T04 CMOS Mixed Signal Circuit Design 3 3
19042T05 CMOS Digital IC Design 3 3
19042T06 Low Power VLSI Design 3 3
Elective III 3 3
19042D07 1. CAD for VLSI
19042D08 2. DSP Processors & Architectures
19042D09 3. VLSI Signal Processing
Elective IV 3 3
19042D10 1. System on Chip Design
19042D11 2. Optimization Techniques in VLSI Design
19042D12 3. Semiconductor Memory Design and Testing
Laboratory - 4 2
19042L02 VLSI Laboratory-II
Total 17
 PRAGATI ENGINEERING COLLEGE: SURAMPALEM
(Autonomous)

III Semester

Sub Code Name of the Subject L P C

19043T07 Embedded System Design 3 3

19043T08 Testing and Testability 3 3

Comprehensive Viva-Voce -- -- 3
19043C01
19043S01 Seminar – I 2
19043P01 Project Work Part - I 6
Total 17

IV Semester

Sub Code Name of the Subject L P C

19044S02 Seminar – II 2
19044P02 Project Work Part - II 15
Total 17

The project will be evaluated at the end of the IV Semester

 DIGITAL SYSTEM DESIGN
I M. Tech I Semester
Course Category Professional Core Course Code 19041T01
Course Type Theory L-T-P-C 3-0-0-3
Prerequisites Internal Assessment 40
Semester End Examination 60
Total Marks 100

COURSE OUTCOMES
Cognitive
Upon successful completion of the course, the student will be able to:
Level
Analyse various Minimization Procedures for minimizing Switching
CO1 K4
functions and Camp Algorithms.
CO2 Design PLD’s & PLA by using Minimization and Folding Algorithms K3

CO3 Design the Large-Scale Digital Systems K3

Analyse the Fault Diagnosis in Combinational Circuits.
CO4 K4

CO5 Discuss the Fault Diagnosis in Sequential Circuits and its Experiments. K2
K1: Remember, K2: Understand, K3: Apply, K4: Analyze, K5: Evaluate, K6: Create.

Contribution of Course Outcomes towards achievement of Program

Outcomes (1 – Low, 2 - Medium, 3 – High)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 2
CO2 3 2 2
CO3 3 1 3
CO4 3 3
CO5 3 1 1

COURSE CONTENT
Minimization Procedures and CAMP Algorithm: Review on minimization of switching
functions using tabular methods, k-map, QM algorithm, CAMP-I algorithm, Phase-I:
Determination of Adjacencies, DA, CSC, SSMs and EPCs,, CAMP-I algorithm, Phase-II:
UNIT I
Passport checking, Determination of SPC, CAMP-II algorithm: Determination of solution
cube, Cube based operations, determination of selected cubes are wholly within the given
switching function or not, Introduction to cube based algorithms.
PLA Design, Minimization and Folding Algorithms: Introduction to PLDs, basic
configurations and advantages of PLDs, PLA-Introduction, Block diagram of PLA, size of
UNIT II
PLA, PLA design aspects, PLA minimization algorithm(IISc algorithm), PLA folding
algorithm(COMPACT algorithm)-Illustration of algorithms with suitable examples.
Design of Large Scale Digital Systems: Algorithmic state machine charts-
Introduction, Derivation of SM Charts, Realization of SM Chart, control
UNIT III implementation, control unit design, data processor design, ROM design, PAL
design aspects, digital system design approaches using CPLDs, FPGAs and
ASICs.
 Fault Diagnosis in Combinational Circuits: Faults classes and models, fault diagnosis and
testing, fault detection test, test generation, testing process, obtaining a minimal complete test
UNIT IV set, circuit under test methods- Path sensitization method, Boolean difference method,
properties of Boolean differences, Kohavi algorithm, faults in PLAs, DFT schemes, built in
self-test.
Fault Diagnosis in Sequential Circuits: Fault detection and location in sequential
circuits, circuit test approach, initial state identification, Haming experiments,
UNIT V
synchronizing experiments, machine identification, distinguishing experiment,
adaptive distinguishing experiments.

TEXT BOOKS
Logic Design Theory-N. N. Biswas, PHI,1993.
1.

2. Switching and Finite Automata Theory-Z. Kohavi , 2nd Edition, 2001,TMH

3. Digital system Design usingPLDd-Lala,2003

REFERENCE BOOKS
1. Fundamentals of Logic Design – Charles H. Roth, 5th Ed., CengageLearning.
Digital Systems Testing and Testable Design – Miron Abramovici, Melvin A. Breuer and Arthur
2.
D. Friedman- John Wiley & SonsInc,2003
WEB RESOURCES
 VLSI TECHNOLOGY ANDDESIGN
I M. Tech I Semester
Course Category Professional Core Course Code 19041T02
Course Type Theory L-T-P-C 3-0-0-3
Prerequisites MOSFET
Internal Assessment 40
construction and
Semester End Examination 60
working,
Total Marks 100
combinational

COURSE OUTCOMES
Cognitive
Upon successful completion of the course, the student will be able to:
Level
Demonstrate IC design rules, parameters and design techniques of
CO1 K3
combinational and sequential systems
Illustrate fabrication processes of NMOS, PMOS, CMOS and outline VLSI
CO2 K2
design issues
CO3 Infer electrical properties and scaling of MOS circuits K3
Analyze switch, gate logic and clocked sequential circuits, design ALU
CO4 K3
subsystem
Summarize floor planning, Architecture -RT design, Low power
CO5 K3
architectures and their testing, chip design methodologies
K1: Remember, K2: Understand, K3: Apply, K4: Analyze, K5: Evaluate, K6: Create.

Contribution of Course Outcomes towards achievement of Program

Outcomes (1 – Low, 2 - Medium, 3 – High)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 2 3
CO2 3 2
CO3 3 2
CO4 3 2 2
CO5 3 2

COURSE CONTENT
VLSI Technology: Fundamentals and applications, IC production process, semiconductor
processes, design rules and process parameters, layout techniques and process parameters.
UNIT I VLSI Design: Electronic design automation concept, ASIC and FPGA design flows, SOC
designs, design technologies: combinational design techniques, sequential design techniques,
state machine logic design techniques and design issues
CMOS VLSI Design: MOS Technology and fabrication process of pMOS, nMOS, CMOS
and BiCMOS technologies, comparison of different processes.
Building Blocks of a VLSI circuit: Computer architecture, memory
UNIT II
architectures, communication interfaces, mixed signal interfaces.
VLSI Design Issues: Design process, design for testability, technology options, power
calculations, package selection, clock mechanisms, mixed signal design.
Basic electrical properties of MOS and BiCMOS circuits, MOS and BiCMOS circuit design
UNIT III processes, Basic circuit concepts, scaling of MOS circuits-qualitatitive and quantitative
analysis with proper illustrations and necessary derivations of expressions.
 Subsystem Design and Layout: Some architectural issues, switch logic, gate logic, examples
of structured design (combinational logic), some clocked sequential circuits, other system
UNIT IV considerations.
Subsystem Design Processes: Some general considerations and an illustration of design
processes, design of an ALU subsystem.
Floor Planning: Introduction, Floor planning methods, off-chip connections.
Architecture Design: Introduction, Register-Transfer design, high-level synthesis,
UNIT V
architectures for low power, architecture testing.
Chip Design: Introduction and design methodologies.

TEXT BOOKS
Essentials of VLSI Circuits and Systems, K. Eshraghian, Douglas A. Pucknell, SholehEshraghian,
1.
2005, PHI Publications.
2. Modern VLSI Design-Wayne Wolf, 3rd Ed., 1997, Pearson Education.

3. VLSI Design-Dr.K.V.K.K.Prasad, KattulaShyamala, Kogent Learning Solutions Inc

REFERENCE BOOKS
1. VLSI Design Technologies for Analog and Digital Circuits
2. Introduction to VLSI Systems: A Logic

3. Principals of CMOS VLSI Design-N.H.E Weste

WEB RESOURCES

1. https://nptel.ac.in/courses/117101058/3

2. https://nptel.ac.in/courses/117106093/1
 CMOS ANALOG IC DESIGN
I M. Tech I Semester
Course Category Professional Core Course Code 19041T03
Course Type Theory L-T-P-C 3-0-0-3
Prerequisites Internal Assessment 40
Semester End Examination 60
Total Marks 100

COURSE OUTCOMES
Cognitive
Upon successful completion of the course, the student will be able to:
Level
CO1 Understand the basic parameters of MOS transistor and different models K3
Understand the basic theory of MOS transistors and Different
CO2 K2
characteristics’
CO3 Study the Different application of C-MOS transistor K3

CO4 Design the Op-Amps and its application using C-MOS transistor K3

CO5 Learn the basics theory of open loop comparators. K3

K1: Remember, K2: Understand, K3: Apply, K4: Analyze, K5: Evaluate, K6: Create.

Contribution of Course Outcomes towards achievement of Program

Outcomes (1 – Low, 2 - Medium, 3 – High)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
2 2 2 1 0 0 0 0 0 0 0
CO1
3
CO2 2 3 2 2 2 0 0 0 0 0 0 0
CO3 3 2 3 2 2 0 0 0 0 0 0 0
CO4 2 2 2 2 1 0 0 0 0 0 0 0
CO5 3 2 2 2 2 0 0 1 0 0 0 0

COURSE CONTENT
MOS Devices and Modeling The MOS Transistor, Passive Components-Capacitor & Resistor,
Integrated circuit Layout, CMOS Device Modeling - Simple MOS Large-Signal Model, Other
UNIT I
Model Parameters, Small-Signal Model for the MOS Transistor, Computer Simulation
Models, Sub-threshold MOS Model.

Analog CMOS Sub-Circuits MOS Switch, MOS Diode, MOS Active Resistor, Current Sinks
UNIT II and Sources, Current Mirrors-Current mirror with Beta Helper, Degeneration, Cascode current
Mirror and Wilson Current Mirror, Current and Voltage References, Band gap Reference.
CMOS Amplifiers Inverters, Differential Amplifiers, Cascode Amplifiers, Current
UNIT III
Amplifiers, Output Amplifiers, High Gain Amplifiers Architectures.
CMOS Operational Amplifiers Design of CMOS Op Amps, Compensation of Op Amps,
UNIT IV Design of Two- Stage Op Amps, Power-Supply Rejection Ratio of Two-Stage Op Amps,
Cascode Op Amps, Measurement Techniques of OPAMP.
 Comparators Characterization of Comparator, Two-Stage, Open-Loop Comparators, Other
UNIT V Open-Loop Comparators, Improving the Performance of Open-Loop Comparators, Discrete-
Time Comparators.

TEXT BOOKS
CMOS Analog Circuit Design - Philip E. Allen and Douglas R. Holberg, Oxford University Press,
1.
International Second Edition/Indian Edition, 2010
Analysis and Design of Analog Integrated Circuits- Paul R. Gray, PaulJ. Hurst, S. Lewis and R. G.
2.
Meyer, Wiley India, Fifth Edition, 2010.
REFERENCE BOOKS
1. Analog Integrated Circuit Design- David A.Johns, Ken Martin, Wiley Student Edn, 2013.
2. Design of Analog CMOS Integrated Circuits- Behzad Razavi, TMH Edition.

3. CMOS: Circuit Design, Layout and Simulation- Baker, Li and Boyce, PHI

WEB RESOURCES
 DIGITAL DESIGN USING HDL
I M. Tech I Semester
Course Category Professional Core Course Code 19041D01
Course Type Theory L-T-P-C 3-0-0-3
Prerequisites Internal Assessment 40
Semester End Examination 60
Total Marks 100

COURSE OUTCOMES
Cognitive
Upon successful completion of the course, the student will be able to:
Level
CO1 Design the digital circuits using VHDL and Verilog HDL models. K3

CO2 Discuss Combinational and Sequential logic Circuit Design. K2

Design Digital circuits using Verilog HDL Behavioural modelling and
CO3 K3
compare styles of it.
CO4 Describe the Synthesis of Digital logic Circuit Design and sequential circuits K3

CO5 Implement the Testing of Digital Logic Circuits using CAD Tools. K3
K1: Remember, K2: Understand, K3: Apply, K4: Analyze, K5: Evaluate, K6: Create.

Contribution of Course Outcomes towards achievement of Program

Outcomes (1 – Low, 2 - Medium, 3 – High)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 3 3 1
CO2 3 3 2 1
CO3 3 3 2 1
CO4 3 3 2 1
CO5 3 3 1 1

COURSE CONTENT
Digital Logic Design using VHDL Introduction, designing with VHDL, design entry methods,
logic synthesis , entities , architecture , packages and configurations, types of models: dataflow
, behavioral , structural, signals vs. variables, generics, data types, concurrent vs. sequential
statements , loops and program controls.
UNIT I
Digital Logic Design using Verilog HDL Introduction, Verilog Data types and Operators,
Binary data manipulation, Combinational and Sequential logic design, Structural Models of
Combinational Logic, Logic Simulation, Design Verification and Test Methodology,
Propagation Delay, Truth Table models using Verilog.
Combinational Logic Circuit Design using VHDL Combinational circuits building blocks:
Multiplexers, Decoders , Encoders , Code converters, Arithmetic comparison circuits , VHDL
for combinational circuits , Adders-Half Adder, Full Adder, Ripple-Carry Adder, Carry Look-
Ahead Adder, Subtraction, Multiplication.
UNIT II
Sequential Logic Circuit Design using VHDL Flip-flops, registers & counters, synchronous
sequential circuits: Basic design steps, Mealy State model, Design of FSM using CAD tools,
Serial Adder Example, State Minimization, Design of Counter using sequential Circuit
approach
 Digital Logic Circuit Design Examples using Verilog HDLBehavioral modeling , Data types,
Boolean-Equation-Based behavioral models of combinational logics , Propagation delay and
continuous assignments, latches and level-sensitive circuits in Verilog, Cyclic behavioral
models of flip-flops and latches and Edge detection, comparison of styles for behavioral
UNIT III
model; Behavioral model, Multiplexers, Encoders and Decoders, Counters, Shift Registers,
Register files, Dataflow models of a linear feedback shift register, Machines with multi cycle
operations, ASM and ASMD charts for behavioral modeling, Design examples, Keypad
scanner and encoder.
Synthesis of Digital Logic Circuit Design Introduction to Synthesis, Synthesis of
UNIT IV combinational logic, Synthesis of sequential logic with latches and flip-flops, Synthesis of
Explicit and Implicit State Machines, Registers and counters.
Testing of Digital Logic Circuits and CAD Tools Testing of logic circuits, fault model,
complexity of a test set, path-sensitization, circuits with tree structure, random tests, testing of
UNIT V
sequential circuits, built in self test, printed circuit boards, computer aided design tools,
synthesis, physical design.

TEXT BOOKS
Stephen Brown & Zvonko Vranesic, “Fundamentals of Digital logic design with VHDL”, Tata
1.
McGraw Hill,2nd edition
Michael D. Ciletti, “Advanced digital design with the Verilog HDL”, Eastern economy edition,
2.
PHI
REFERENCE BOOKS
Stephen Brown & Zvonko Vranesic, “Fundamentals of Digital logic with Verilog design”, Tata
1.
McGraw Hill,2nd edition
2. Bhaskar, “VHDL Primer”,3rd Edition, PHI Publications

Ian Grout, “Digital systems design with FPGAs and CPLDs”, Elsevier Publications.
3.

WEB RESOURCES
 ADVANCED OPERATING SYSTEMS
I M. Tech I Semester
Course Category Professional Core Course Code 19041D02
Course Type Theory L-T-P-C 3-0-0-3
Prerequisites Internal Assessment 40
Operating Systems Semester End Examination 60
Total Marks 100

COURSE OUTCOMES
Cognitive
Upon successful completion of the course, the student will be able to:
Level
Understand the concepts of I/O function, Interrupts & Memory hierarchy in
CO1 K2
operating systems.
CO2 Interpret the concept of Unix & Linux in operating systems. K4

CO3 Perceive the concept of Pipes, FIFOs, Message queues & Semaphores. K4
Interpret the concept of ATM networks, Client - Server model, Remote procedure
CO4 call and Group communication. K2

Perceive the concept of Clock synchronization, Bully algorithm, Ring algorithm,

CO5 Deadlock in distributed systems. K3

K1: Remember, K2: Understand, K3: Apply, K4: Analyze, K5: Evaluate, K6: Create.

Contribution of Course Outcomes towards achievement of Program

Outcomes (1 – Low, 2 - Medium, 3 – High)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 1 1 1 1 2 1 2
CO2 1 1 1 1 2 1 2
CO3 1 1 1 1 2 1 2
CO4 1 1 1 1 2 1 2
CO5 1 1 1 1 2 1 2

COURSE CONTENT

Introduction to Operating Systems: Overview of computer system hardware, Instruction

UNIT I execution, I/O function, Interrupts, Memory hierarchy, I/O Communication techniques,
Operating system objectives and functions, Evaluation of operating System

Introduction to UNIX and LINUX: Basic Commands & Command Arguments, Standard
UNIT II
Input, Output, Input / Output Redirection, Filters and Editors, Shells and Operations

System Calls: System calls and related file structures, Input / Output, Process creation &
termination. Inter Process Communication: Introduction, File and record locking, Client
UNIT III
– Server example, Pipes, FIFOs, Streams & Messages, Name Spaces, Systems V IPC,
Message queues, Semaphores, Shared Memory, Sockets & TLI.
Introduction to Distributed Systems: Goals of distributed system, Hardware and software
UNIT IV
concepts, Design issues. Communication in Distributed Systems: Layered protocols, ATM
 networks, Client - Server model, Remote procedure call and Group communication.

Synchronization in Distributed Systems: Clock synchronization, Mutual exclusion, E-tech

algorithms, Bully algorithm, Ring algorithm, Atomic transactions Deadlocks :Dead lock in
UNIT V
distributed systems, Distributed dead lock prevention and distributed dead lock detection.

TEXT BOOKS

1. The Design of the UNIX Operating Systems – Maurice J. Bach, 1986, PHI.

2. Distributed Operating System - Andrew. S. Tanenbaum, 1994, PHI

3. The Complete Reference LINUX – Richard Peterson, 4th Ed., McGraw – Hill

REFERENCE BOOKS
1. Operating Systems: Internal and Design Principles -Stallings, 6th Ed., PE.
2. Modern Operating Systems - Andrew S Tanenbaum, 3rd Ed., PE.
Operating System Principles - Abraham Silberchatz, Peter B. Galvin, Greg Gagne, 7th Ed., John
3. Wiley

4. UNIX User Guide – Ritchie & Yates

5. UNIX Network Programming - W.Richard Stevens, 1998, PHI

WEB RESOURCES

1. https://nptel.ac.in/courses/106106157/15

2. https://nptel.ac.in/courses/106106157/13

3. https://nptel.ac.in/courses/106106168
 SOFT COMPUTING TECHNIQUES
I M. Tech I Semester
Course Category Professional Core Course Code 19041D03
Course Type Theory L-T-P-C 3-0-0-3
Prerequisites Artificial Internal Assessment 40
Intelligence Semester End Examination 60
Total Marks 100

COURSE OUTCOMES
Cognitive
Upon successful completion of the course, the student will be able to:
Level
Identify and describe soft computing techniques and their roles in building
CO1 K3
intelligent machines
To familiarize with neural networks and learning methods for neural
CO2 K2
networks
CO3 To introduce the ideas of fuzzy sets, fuzzy logic and fuzzy inference system K3

CO4 Analyze the genetic algorithms to combinatorial optimization problems K3

CO5 Apply neural networks to pattern classification and regression problems K3

K1: Remember, K2: Understand, K3: Apply, K4: Analyze, K5: Evaluate, K6: Create.
Contribution of Course Outcomes towards achievement of Program
Outcomes (1 – Low, 2 - Medium, 3 – High)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 1 1
CO2 3 1 1 1
CO3 3 1 1 1
CO4 3 1 1 1
CO5 3 1 1 1

COURSE CONTENT

Introduction: Approaches to intelligent control, Architecture for intelligent control, Symbolic

UNIT I reasoning system, Rule-based systems, the AI approach, Knowledge representation - Expert
systems.
Artificial Neural Networks: Concept of Artificial Neural Networks and its basic
mathematical model, McCulloch-Pitts neuron model, simple perceptron, Adaline and
Madaline, Feed-forward Multilayer Perceptron, Learning and Training the neural network,
UNIT II
Data Processing: Scaling, Fourier transformation, principal-component analysis and wavelet
transformations, Hopfield network, Self-organizing network and Recurrent network, Neural
Network based controller.
Fuzzy Logic System: Introduction to crisp sets and fuzzy sets, basic fuzzy set operation and
approximate reasoning, Introduction to fuzzy logic modeling and control, Fuzzification,
UNIT III inferencing and defuzzification, Fuzzy knowledge and rule bases, Fuzzy modeling and
control schemes for nonlinear systems, Self-organizing fuzzy logic control, Fuzzy logic
control for nonlinear time delay system
 Genetic Algorithm: Basic concept of Genetic algorithm and detail algorithmic steps,
Adjustment of free parameters, Solution of typical control problems using genetic algorithm,
UNIT IV
Concept on some other search techniques like Tabu search and anD-colony search techniques
for solving optimization problems.
Applications: GA application to power system optimisation problem, Case studies:
Identification and control of linear and nonlinear dynamic systems using MATLAB-Neural
UNIT V Network toolbox, Stability analysis of Neural-Network interconnection systems,
Implementation of fuzzy logic controller using MATLAB fuzzy-logic toolbox, Stability
analysis of fuzzy control systems

TEXT BOOKS

1. Introduction to Artificial Neural Systems - Jacek.M.Zurada, Jaico Publishing House, 1999

2. Neural Networks and Fuzzy Systems - Kosko, B., Prentice-Hall of India Pvt. Ltd., 1994

REFERENCE BOOKS
Fuzzy Sets, Uncertainty and Information - Klir G.J. &Folger T.A., Prentice-Hall of India Pvt. Ltd.,
1.
1993
2. Fuzzy Set Theory and Its Applications - Zimmerman H.J. Kluwer Academic Publishers, 1994

3. Introduction to Fuzzy Control - Driankov, Hellendroon, Narosa Publishers

4. Artificial Neural Networks - Dr. B. Yagananarayana, 1999, PHI, New Delhi

Elements of Artificial Neural Networks - KishanMehrotra, Chelkuri K. Mohan, Sanjay Ranka,

5.
Penram International
6. Artificial Neural Network –Simon Haykin, 2nd Ed., Pearson Education

Introduction Neural Networks Using MATLAB 6.0 - S.N. Shivanandam, S. Sumati, S. N.

7.
Deepa,1/e, TMH, New Delhi
WEB RESOURCES

1. https://nptel.ac.in/courses/106105173/

2. https://nptel.ac.in/courses/106105173/2

3. https://nptel.ac.in/courses/106105173/14

4. https://nptel.ac.in/courses/106105173/16

5. https://nptel.ac.in/courses/106105173/34
 CPLD AND FPGA ARCHITECURES AND APPLICATIONS
I M. Tech I Semester
Course Category Professional Core Course Code 19041D04
Course Type Theory L-T-P-C 3-0-0-3
Prerequisites Internal Assessment 40
VLSI Semester End Examination 60
Total Marks 100

COURSE OUTCOMES
Cognitive
Upon successful completion of the course, the student will be able to:
Level
CO1 understand the concepts of various PLAs and PLDs. K3

CO2 understandFPGA Programming Technologies and its applications. K2

analyze SRAM Programmable FPGAs and the architectures of Xilinx
CO3 K3
XC2000, XC3000 and XC4000
CO4 analyze the architectures of Actel ACT1, ACT2 and ACT3. K3

CO5 understand concepts of various Design Applications General Design Issues. K3

K1: Remember, K2: Understand, K3: Apply, K4: Analyze, K5: Evaluate, K6: Create.
Contribution of Course Outcomes towards achievement of Program
Outcomes (1 – Low, 2 - Medium, 3 – High)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 3 2
CO2 3 3 3
CO3 3 2 3
CO4 3 3 3
CO5 3 2 3

COURSE CONTENT
Introduction to Programmable Logic Devices Introduction, Simple Programmable Logic
Devices – Read Only Memories, Programmable Logic Arrays, Programmable Array Logic,
UNIT I Programmable Logic Devices/ Generic Array Logic; Complex Programmable Logic Devices –
Architecture of Xilinx Cool Runner XCR3064XL CPLD, CPLD Implementation of a Parallel
Adder with Accumulation.
Field Programmable Gate Arrays Organization of FPGAs, FPGA Programming
Technologies, Programmable Logic Block Architectures, Programmable Interconnects,
UNIT II
Programmable I/O blocks in FPGAs, Dedicated Specialized Components of FPGAs,
Applications of FPGAs
SRAM Programmable FPGAs Introduction, Programming Technology, Device Architecture,
UNIT III
The Xilinx XC2000, XC3000 and XC4000 Architectures.
Anti-Fuse Programmed FPGAs Introduction, Programming Technology, Device Architecture,
UNIT IV
The Actel ACT1, ACT2 and ACT3 Architectures.
 Design Applications General Design Issues, Counter Examples, A Fast Video Controller, A
UNIT V Position Tracker for a Robot Manipulator, A Fast DMA Controller, Designing Counters with
ACT devices, Designing Adders and Accumulators with the ACT Architecture.

TEXT BOOKS
Field Programmable Gate Array Technology - Stephen M. Trimberger, Springer International
1.
Edition.
2. Digital Systems Design - Charles H. Roth Jr, Lizy Kurian John, Cengage Learning.

REFERENCE BOOKS
1. Field Programmable Gate Arrays - John V. Oldfield, Richard C. Dorf, Wiley India
Digital Design Using Field Programmable Gate Arrays - Pak K. Chan/ Samiha Mourad, Pearson
2.
Low Price Edition
3. Digital Systems Design with FPGAs and CPLDs - Ian Grout, Elsevier, Newnes

4. FPGA based System Design - Wayne Wolf, Prentice Hall Modern Semiconductor Design Series

WEB RESOURCES

1. https://www.youtube.com/watch?v=2c5dQrqhfn0

2. https://www.youtube.com/watch?v=uEVmdvBo_lk

3. https://www.youtube.com/watch?v=gCAYY0fHPq4
 ADVANCED COMPUTER ARCHITECTURE
I M. Tech I Semester
Course Category Professional Core Course Code 19041D05
Course Type Theory L-T-P-C 3-0-0-3
Prerequisites Internal Assessment 40
Basics of advanced
Semester End Examination 60
computer architeture
Total Marks 100

COURSE OUTCOMES
Cognitive
Upon successful completion of the course, the student will be able to:
Level
Discuss the organisation of computer-based systems and how a range of
CO1 design choices are influenced by applications K3

Understand different processor architectures and system-level design

CO2 processes. K2

Understand the components and operation of a memory hierarchy and the

CO3 range of performance issues influencing its design. K3

Understand the organisation and operation of current generation parallel

CO4 computer systems, including multiprocessor and multicore systems. K3

Develop systems programming skills in the content of computer system

CO5 design and organisation. K3

K1: Remember, K2: Understand, K3: Apply, K4: Analyze, K5: Evaluate, K6: Create.
Contribution of Course Outcomes towards achievement of Program
Outcomes (1 – Low, 2 - Medium, 3 – High)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 2 2 2 2 2 0 0 0 2 0 0 1
CO2 2 3 2 3 2 0 0 0 1 0 0 2
CO3 2 2 2 3 2 0 0 0 1 0 0 1
CO4 2 3 2 2 3 0 0 0 1 0 0 1
CO5 3 2 3 2 2 0 0 1 1 0 0 1

COURSE CONTENT
Fundamentals of Computer Design Fundamentals of Computer design, Changing faces of
computing and task of computer designer, Technology trends, Cost price and their trends,
UNIT I measuring and reporting performance, Quantitative principles of computer design,
Amdahl‟slaw. Instruction set principles and examples- Introduction, classifying instruction
set- memory addressing- type and size of operands, Operations in the instruction set.
 Pipelines Introduction, basic RISC instruction set, Simple implementation of RISC instruction
set, Classic five stage pipe lined RISC processor, Basic performance issues in pipelining,
UNIT II
Pipeline hazards, Reducing pipeline branch penalties. Memory Hierarchy Design Introduction,
review of ABC of cache, Cache performance, Reducing cache miss penalty, Virtual memory.
Instruction Level Parallelism (ILP)-The Hardware Approach Instruction-Level parallelism,
Dynamic scheduling, Dynamic scheduling using Tomasulo‟s approach, Branch prediction,
UNIT III High performance instruction delivery- Hardware based speculation. ILP Software Approach
Basic compiler level techniques, Static branch prediction, VLIW approach, Exploiting ILP,
Parallelism at compile time, Cross cutting issues - Hardware verses Software.
Multi Processors and Thread Level Parallelism Multi Processors and Thread level Parallelism-
UNIT IV Introduction, Characteristics of application domain, Systematic shared memory architecture,
Distributed shared – Memory architecture, Synchronization.
Inter Connection and Networks Introduction, Interconnection network media, Practical issues
UNIT V in interconnecting networks, Examples of inter connection, Cluster, Designing of clusters.
Intel Architecture Intel IA-64 ILP in embedded and mobile markets Fallacies and pit falls.

TEXT BOOKS
John L. Hennessy, David A. Patterson - Computer Architecture: A Quantitative Approach, 3rd
1.
Edition, An Imprint of Elsevier,2002
2.

REFERENCE BOOKS
John P. Shen and Miikko H. Lipasti - Modern Processor Design : Fundamentals of Super
1.
ScalarProcessors,2013
2. Computer Architecture and Parallel Processing - Kai Hwang, Faye A.Brigs., MC Graw Hill,1984

Advanced Computer Architecture - A Design Space Approach -Dezso Sima, Terence Fountain,
3.
Peter Kacsuk , PearsonEd,1997
WEB RESOURCES

1. http://scitechconnect.elsevier.com/category/computer-science/

2. https://www.sztaki.hu/en/science/departments/lpds

3. http://www.ecs.umass.edu/ece/koren/arith/

4. https://onlinelibrary.wiley.com/doi/full/10.1002/9780470050118.ecse071

5.
 HARDWARE SOFTWARE CO-DESIGN
I M. Tech I Semester
Course Category Professional Core Course Code 19041D06
Course Type Theory L-T-P-C 3-0-0-3
Prerequisites Internal Assessment 40
Semester End Examination 60
Total Marks 100

COURSE OUTCOMES
Cognitive
Upon successful completion of the course, the student will be able to:
Level
acquire the knowledge about system specification and modeling.
CO1 K2
learn the formulation of partitioning the hardware and software
CO2 K2
analyze about the hardware and software integration
CO3 K2
study the hardware design languages and its components
CO4 K2
formulate the design specification and module creation
CO5 K2
K1: Remember, K2: Understand, K3: Apply, K4: Analyze, K5: Evaluate, K6: Create.
Contribution of Course Outcomes towards achievement of Program
Outcomes (1 – Low, 2 - Medium, 3 – High)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 2 1 1
CO2 3 2 2 1
CO3 3 3 2 1
CO4 3 2 1 1
CO5 3 3 3 1

COURSE CONTENT
Co- Design Issues: Co- Design Models, Architectures, Languages, A Generic Co-design
Methodology.
UNIT I
Co- Synthesis Algorithms: Hardware software synthesis algorithms: hardware – software
partitioning distributed system co-synthesis.
Prototyping and Emulation: Prototyping and emulation techniques, prototyping and
emulation environments, future developments in emulation and prototyping architecture
specialization techniques, system communication infrastructure
UNIT II Target Architectures: Architecture Specialization techniques, System Communication
infrastructure, Target Architecture and Application System classes, Architecture for control
dominated systems (8051-Architectures for High performance control), Architecture for Data
dominated systems (ADSP21060, TMS320C60), Mixed Systems.
Compilation Techniques and Tools for Embedded Processor Architectures: Modern
UNIT III embedded architectures, embedded software development needs, compilation technologies,
practical consideration in a compiler development environment.
Design Specification and Verification: Design, co-design, the codesign computational model,
UNIT IV concurrency coordinating concurrent computations, interfacing components, design
verification, implementation verification, verification tools, interface verification
 Languages for System – Level Specification and Design-I: System level specification, design
representation for system level synthesis, system level specification languages.
UNIT V
Languages for System – Level Specification and Design-II: Heterogeneous specifications and
multi language co-simulation, the cosyma system and lycos system.

TEXT BOOKS
Hardware / Software Co- Design Principles and Practice – JorgenStaunstrup, Wayne Wolf – 2009,
1.
Springer.
Hardware / Software Co- Design - Giovanni De Micheli, Mariagiovanna Sami, 2002, Kluwer
2.
Academic Publishers
REFERENCE BOOKS
A Practical Introduction to Hardware/Software Co-design -Patrick R. Schaumont -
1.
2010 – Springer Publications.
2.

WEB RESOURCES
 VLSI Design Laboratory -I
I M. Tech I Semester
Course Category Professional Core Course Code 16041L01
Course Type Laboratory L-T-P-C 4-0-0-2
Prerequisites Internal Assessment 40
Semester End Examination 60
Total Marks 100

 The students are required to design the logic circuit to perform the following
experiments using necessary simulator (Xilinx ISE Simulator/ Mentor Graphics
Questa Simulator) to verify the logical /functional operation and to perform the
analysis with appropriate
 synthesizer (Xilinx ISE Synthesizer/Mentor Graphics Precision RTL) and then
verify the implemented logic with different hardware modules/kits (CPLD/ FPGA
kits).
 The students are required to acquire the knowledge in both the Platforms (Xilinx
and Mentor graphics) by perform at least FIVE experiments on each Platform.
List of Experiments:
1. Realization of Logic gates.
2. Parity Encoder.
3. Random Counter
4. Single Port Synchronous RAM.
5. Synchronous FIFO.
6. ALU.
7. UART Model.
8. Dual Port Asynchronous RAM.
9. Fire Detection and Control System using Combinational Logic circuits.
10. Traffic Light Controller using Sequential Logic circuits
11. Pattern Detection using Moore Machine.
12. Finite State Machine(FSM) based logic circuit.
Lab Requirements:
Software:
Xilinx ISE Suite 13.2 Version, Mentor Graphics-Questa Simulator, Mento Graphics-
Precision RTL
Hardware:
Personal Computer with necessary peripherals, configuration and operating System
and relevant VLSI (CPLD/FPGA) hardware Kits.
 CMOS MIXED SIGNAL CIRCUIT DESIGN
I M. Tech II Semester
Course Category Professional Core Course Code 19042T04
Course Type Theory L-T-P-C 3-0-0-3
Prerequisites Internal Assessment 40
VLSI design and
Semester End Examination 60
Analog VLSI Design
Total Marks 100

COURSE OUTCOMES
Cognitive
Upon successful completion of the course, the student will be able to:
Level
CO1 Understand the Switched capacitors Circuits and Operation and Analysis K3

CO2 Understand the Operation and Analysis of PLLS K2

CO3 To know Data Converter Fundamentals, Nyquist Rate D/A Converters K3

CO4 To explain Data Converter Fundamentals, Nyquist Rate A/D Converters K3

CO5 To analyze the Oversampling Converters and Continuous-Time Filters K3

K1: Remember, K2: Understand, K3: Apply, K4: Analyze, K5: Evaluate, K6: Create.
Contribution of Course Outcomes towards achievement of Program
Outcomes (1 – Low, 2 - Medium, 3 – High)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 1 1 1
CO2 3 1 1 1
CO3 3 1 1 1
CO4 3 1 1 1
CO5 3 1 1 1

COURSE CONTENT

Switched Capacitor Circuits Introduction to Switched Capacitor circuits- basic building

UNIT I blocks, Operation and Analysis, Non-ideal effects in switched capacitor circuits, Switched
capacitor integrators first order filters, Switch sharing, biquad filters.

Phased Lock Loop (PLL) Basic PLL topology, Dynamics of simple PLL, Charge pump
PLLs-Lock acquisition, Phase/Frequency detector and charge pump, Basic charge pump PLL,
UNIT II
Non-ideal effects in PLLs PFD/CP non-idealities, Jitter in PLLs, Delay locked loops,
applications
Data Converter Fundamentals DC and dynamic specifications, Quantization noise, Nyquist
UNIT III rate D/A converters- Decoder based converters, Binary-Scaled converters, Thermometer-code
converters, Hybrid converters
Nyquist Rate A/D Converters Successive approximation converters, Flash converter, Two-step
UNIT IV A/D converters, Interpolating A/D converters, Folding A/D converters, Pipelined A/D
converters, Time interleaved converters.
Oversampling Converters Noise shaping modulators, Decimating filters and interpolating
UNIT V filters, Higher order modulators, Delta sigma modulators with multibit quantizers, Delta
sigma D/A
TEXT BOOKS
Design of Analog CMOS Integrated Circuits- Behzad Razavi, TMH Edition,2002
1.
CMOS Analog Circuit Design - Philip E. Allen and Douglas R. Holberg, Oxford University Press,
2.
International Second Edition/Indian Edition,2010
3. Analog Integrated Circuit Design- David A. Johns,Ken Martin, Wiley Student Edition,2013

REFERENCE BOOKS
CMOS Integrated Analog-to- Digital and Digital-to-Analog convertersRudy Van De Plassche,
1.
Kluwer Academic Publishers,2003
2. Understanding Delta-Sigma Data converters-Richard Schreier, Wiley Interscience, 2005

3. CMOS Mixed-Signal Circuit Design - R. Jacob Baker, Wiley Interscience,2009

WEB RESOURCES
https://www.youtube.com/watch?v=PhTU4pbWMEQ&list=PLLDC70psjvq5vtrb0EdII4xIKA15ec-
1.
Ij&index=10&t=0s
https://www.youtube.com/watch?v=7xVSL93ZZq8&list=PLLDC70psjvq5vtrb0EdII4xIKA15ec-
2.
Ij&index=15
https://www.youtube.com/watch?v=WjtUpOPEljQ&list=PLLDC70psjvq5vtrb0EdII4xIKA15ec-
3.
Ij&index=20
 CMOS DIGITAL IC DESIGN
I M. Tech II Semester
Course Category Professional Core Course Code 19042T05
Course Type Theory L-T-P-C 3-0-0-3
Prerequisites Basic knowledge in Internal Assessment 40
VLSI and Mos Semester End Examination 60
transistors concepts Total Marks 100

COURSE OUTCOMES
Cognitive
Upon successful completion of the course, the student will be able to:
Level
Remember the basic concepts of NMOS logic and inverter devices used in
CO1 K3
portable consumer devices
Understand the design of transmission gated used to implement analog
CO2 K2
switches and multiplexers
Apply the MOS logic and concept of flip flops for sequential circuits used
CO3 K3
temporary storage of data or delay signals
Analyze dynamic logic circuits used in temporary storage of signal using
CO4 K3
various load capacitances.
CO5 Compare different type of memory devices used for storage K3
K1: Remember, K2: Understand, K3: Apply, K4: Analyze, K5: Evaluate, K6: Create.

Contribution of Course Outcomes towards achievement of Program

Outcomes (1 – Low, 2 - Medium, 3 – High)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 2 2 2 1 2 1 2 1
CO2 1 1 3 1 2 1 2 2
CO3 1 2 3 2 2 1 2 1
CO4 2 2 2 1 2 1 2 2
CO5 1 2 3 1 1 1 2 1

COURSE CONTENT

MOS Design Pseudo NMOS Logic – Inverter, Inverter threshold voltage, Output high voltage,
UNIT I Output Low voltage, Gain at gate threshold voltage, Transient response, Rise time, Fall time,
Pseudo NMOS logic gates, Transistor equivalency, CMOS Inverter logic.

Combinational MOS Logic Circuits: MOS logic circuits with NMOS loads, Primitive
CMOS logic gates – NOR & NAND gate, Complex Logic circuits design – Realizing
UNIT II
Boolean expressions using NMOS gates and CMOS gates , AOI and OIA gates, CMOS
full adder, CMOS transmission gates, Designing with Transmission gates.
Sequential MOS Logic Circuits Behaviour of bistable elements, SR Latch, Clocked latch and
UNIT III
flip flop circuits, CMOS D latch and edge triggered flip-flop
Dynamic Logic Circuits Basic principle, Voltage Bootstrapping, Synchronous dynamic pass
UNIT IV transistor circuits, Dynamic CMOS transmission gate logic, High performance Dynamic
CMOS circuits.
 Semiconductor MemoriesTypes, RAM array organization, DRAM – Types, Operation,
UNIT V Leakage currents in DRAM cell and refresh operation, SRAM operation Leakage currents in
SRAM cells, Flash Memory-NOR flash and NAND flash.

TEXT BOOKS

1. Digital Integrated Circuit Design – Ken Martin, Oxford University Press, 2011.
CMOS Digital Integrated Circuits Analysis and Design – Sung-Mo Kang, Yusuf Leblebici, TMH,
2.
3rd Ed., 2011.
REFERENCE BOOKS
Introduction to VLSI Systems: A Logic, Circuit and System Perspective – Ming-BO Lin, CRC
1.
Press, 2011
Digital Integrated Circuits – A Design Perspective, Jan M. Rabaey, Anantha Chandrakasan,
2.
Borivoje Nikolic, 2nd Ed., PHI
WEB RESOURCES
 LOW POWER VLSI DESIGN
I M. Tech II Semester
Course Category Professional Core Course Code 19042T06
Course Type Theory L-T-P-C 3-0-0-3
Prerequisites Internal Assessment 40
Semester End Examination 60
Total Marks 100

COURSE OUTCOMES
Cognitive
Upon successful completion of the course, the student will be able to:
Level
CO1 Understand the basic concept of VLSI technologies K3

CO2 Study the Architectural Level Approach for MOS Transistor K2

CO3 Design the Adder circuit using CMOS technologies K3

CO4 Design the Different multiplier algorithm K3

CO5 Understand the basic concept of Memory technologies. K3

K1: Remember, K2: Understand, K3: Apply, K4: Analyze, K5: Evaluate, K6: Create.
Contribution of Course Outcomes towards achievement of Program
Outcomes (1 – Low, 2 - Medium, 3 – High)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
2 2 2 1 0 0 0 0 0 0 0
CO1
3
CO2 2 3 2 2 2 0 0 0 0 0 0 0
CO3 3 2 3 2 2 0 0 0 0 0 0 0
CO4 2 2 2 2 1 0 0 0 0 0 0 0
CO5 3 2 2 2 2 0 0 1 0 0 0 0

COURSE CONTENT
Fundamentals of Low Power VLSI Design Need for Low Power Circuit Design, Sources of
Power Dissipation – Switching Power Dissipation, Short Circuit Power Dissipation, Leakage
UNIT I Power Dissipation, Glitching Power Dissipation, Short Channel Effects –Drain Induced
Barrier Lowering and Punch Through, Surface Scattering, Velocity Saturation, Impact
Ionization, Hot Electron Effect.
Low-Power Design Approaches Low-Power Design through Voltage Scaling – VTCMOS
circuits, MTCMOS circuits, Architectural Level Approach –Pipelining and Parallel Processing
UNIT II
Approaches. Switched Capacitance Minimization Approaches System Level Measures,
Circuit Level Measures, Mask level Measures.
Low-Voltage Low-Power Adders Introduction, Standard Adder Cells, CMOS Adder‟s
Architectures – Ripple Carry Adders, Carry Look-Ahead Adders, Carry Select Adders, Carry
UNIT III
Save Adders, Low-Voltage Low Power Design Techniques –Trends of Technology and
Power Supply Voltage, Low-Voltage Low-Power Logic Styles.
Low-Voltage Low-Power Multipliers Introduction, Overview of Multiplication, Types of
UNIT IV Multiplier Architectures, Braun Multiplier, Baugh-Wooley Multiplier, Booth Multiplier,
Introduction to Wallace Tree Multiplier.
 Low-Voltage Low-Power Memories Basics of ROM, Low-Power ROM Technology, Future
Trend and Development of ROMs, Basics of SRAM, Memory Cell, Precharge and
UNIT V
Equalization Circuit, Low-Power SRAM Technologies, Basics of DRAM, Self-Refresh
Circuit, Future Trend and Development of DRAM.

TEXT BOOKS
CMOS Digital Integrated Circuits – Analysis and Design – Sung-Mo Kang, Yusuf Leblebici,
1.
TMH, 2011
Low-Voltage, Low-Power VLSI Subsystems – Kiat-Seng Yeo, Kaushik Roy, TMH
2.
Professional Engineering.
REFERENCE BOOKS
1. Low Power CMOS Design –Anantha Chandrakasan, IEEE Press/Wiley International, 1998
Low Power CMOS VLSI Circuit Design – Kaushik Roy, Sharat C. Prasad, John Wiley & Sons,
2.
2000
3. Practical Low Power Digital VLSI Design – Gary K. Yeap, Kluwer Academic Press, 2002

Low Power CMOS VLSI Circuit Design – A. Bellamour, M. I. Elamasri, Kluwer Academic Press,
4.
1995
WEB RESOURCES

1.
2.
3.

4.

5.
 CAD FOR VLSI
I M. Tech II Semester
Course Category Professional Core Course Code 19042D07
Course Type Theory (Elective-III) L-T-P-C 3-0-0-3
Prerequisites Internal Assessment 40
ECAD Semester End Examination 60
Total Marks 100

COURSE OUTCOMES
Cognitive
Upon successful completion of the course, the student will be able to:
Level
CO1 understand the trends in physical and VLSI design cycles. K3
analyze the partitioning, floor planning, pin assignment andplacement.
CO2 K2

CO3 understand various routing and routing algorithms. K3

CO4 apply partitioning and routing for various models. K3

CO5 understand concepts of chip input and output circuits. K3

K1: Remember, K2: Understand, K3: Apply, K4: Analyze, K5: Evaluate, K6: Create.
Contribution of Course Outcomes towards achievement of Program
Outcomes (1 – Low, 2 - Medium, 3 – High)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 3 3
CO2 3 3 2
CO3 3 2 3
CO4 3 3 3
CO5 3 3 2

COURSE CONTENT

VLSI Physical Design Automation : VLSI Design Cycle, New Trends in VLSI Design
UNIT I Cycle, Physical Design Cycle, New Trends in Physical Design Cycle, Design Styles, System
Packaging Styles;
Partitioning, Floor Planning, Pin Assignment and Placement:Partitioning – Problem
formulation, Classification of Partitioning algorithms, Kernighan-Lin Algorithm, Simulated
Annealing, Floor Planning – Problem formulation, Classification of floor planning
UNIT II algorithms, constraint based floor planning, Rectangular Dualization, Pin Assignment –
Problem formulation, Classification of pin assignment algorithms, General and channel Pin
assignments, Placement – Problem formulation, Classification of placement algorithms,
Partitioning based placement algorithms
Global Routing and DetailedRouting :Global Routing – Problem formulation, Classification
UNIT III of global routing algorithms, Maze routing algorithms, Detailed Routing – Problem
formulation, Classification of routing algorithms, Single layer routing algorithms
Physical Design Automation of FPGAs and MCMs:FPGA Technologies, Physical Design
UNIT IV cycle for FPGAs, Partitioning, Routing – Routing Algorithm for the Non-Segmented model,
Routing Algorithms for the Segmented Model;
 Introduction to MCM Technologies, MCM Physical Design Cycle

ESD Protection, Input Circuits, Output Circuits and L (di/dt) noise, On-chip clock
UNIT V Generation and
Distribution, Latch-up and its prevention

TEXT BOOKS
Algorithms for VLSI Physical Design Automation by NaveedShervani, 3rd Edition, 2005,
1.
Springer International Edition
CMOS Digital Integrated Circuits Analysis and Design – Sung-Mo Kang, Yusuf Leblebici, TMH,
2.
3rd Ed., 2011
REFERENCE BOOKS
VLSI Physical Design Automation-Theory and Practice by Sadiq M Sait, Habib Youssef, World
1.
Scientific
Algorithms for VLSI Design Automation, S. H. Gerez, 1999, Wiley student Edition, John Wiley
2.
and Sons (Asia) Pvt. Ltd
3. VLSI Physical Design Automation by Sung Kyu Lim, Springer International Edition

WEB RESOURCES

1. https://www.youtube.com/watch?v=zOkxhERkWy0

2. https://www.youtube.com/watch?v=jZ6LAcHmvng

3. https://www.youtube.com/watch?v=rck5O8DnWlg

4.

5.
 DIGITAL SIGNAL PROCESSORS & ARCHITECTURS
I M. Tech II Semester
Course Category Professional Core Course Code 19042D08

Course Type Theory (Elective-III) L-T-P-C 3-0-0-3

Prerequisites Basics Of Digital
Internal Assessment 40
Signal processors &
Semester End Examination 60
Architectures
Total Marks 100

COURSE OUTCOMES
Cognitive
Upon successful completion of the course, the student will be able to:
Level
Learn to represent real world signals in digital format and understand
CO1 K3
transform-domain (Fourier and z-transforms) representation of the signals
Know to apply the linear systems approach to signal processing problems
CO2 K2
using high-level programming language
CO3 Learn the basic architecture of microprocessors and digital signal processors K3

CO4 Provide the basic knowledge of different DSP Processors K3

Interfacing Memory and I/O Peripherals to different Programmable DSP
CO5 K3
Devices
K1: Remember, K2: Understand, K3: Apply, K4: Analyze, K5: Evaluate, K6: Create.
Contribution of Course Outcomes towards achievement of Program
Outcomes (1 – Low, 2 - Medium, 3 – High)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
2 2 2 1 0 0 0 1 0 0 1
CO1
3
CO2 2 3 2 2 2 0 0 0 1 0 0 2
CO3 3 2 3 2 2 0 0 0 1 0 0 1
CO4 2 2 2 2 1 0 0 0 1 0 0 1
CO5 3 2 2 2 2 0 0 1 0 0 0 1

COURSE CONTENT
Introduction to Digital Signal Processing Introduction, a Digital signal processing system, the
sampling process, discrete time sequences.
Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT), Linear time- invariant
UNIT I systems, Digital filters, Decimation and interpolation. Computational Accuracy in DSP
Implementations Number formats for signals and coefficients in DSP systems, Dynamic
Range and Precision, Sources of error in DSP implementations, A/D Conversion errors, DSP
Computational errors, D/A Conversion Errors, Compensating filter
Architectures for Programmable DSP Devices Basic Architectural features, DSP
Computational Building Blocks, Bus Architecture and Memory, Data Addressing
UNIT II
Capabilities, Address Generation UNIT, Programmability and Program Execution, Speed
Issues, Features for External interfacing
Programmable Digital Signal Processors Commercial Digital signal processing Devices, Data
UNIT III
Addressing modes of TMS320C54XX DSPs, Data Addressing modes of TMS320C54XX
 Processors, Memory space of TMS320C54XX Processors, Program Control, TMS320C54XX
Instructions and Programming, On-Chip Peripherals, Interrupts of TMS320C54XX
Processors, Pipeline Operation of TMS320C54XX Processors
Analog Devices Family of DSP Devices Analog Devices Family of DSP Devices – ALU and
MAC block diagram, Shifter Instruction, Base Architecture of ADSP 2100, ADSP- 2181 high
performance Processor. Introduction to Black fin Processor - The Black fin Processor,
UNIT IV
Introduction to Micro Signal Architecture, Overview of Hardware Processing Units and
Register files, Address Arithmetic Unit, Control Unit, Bus Architecture and Memory, Basic
Peripherals
Interfacing Memory and I/O Peripherals to Programmable DSP Devices Memory space
UNIT V organization, External bus interfacing signals, Memory interface, Parallel I/O interface,
Programmed I/O, Interrupts and I/O, Direct memory access (DMA).

TEXT BOOKS

1. Digital Signal Processing – Avtar Singh and S. Srinivasan, Thomson Publications, 2004
A Practical Approach To Digital Signal Processing - K Padmanabhan, R. Vijayarajeswaran,
2.
Ananthi. S, New Age International, 2006/2009
Embedded Signal Processing with the Micro Signal Architecture: Woon-Seng Gan, Sen M. Kuo,
3.
Wiley-IEEE Press, 2007
REFERENCE BOOKS
Digital Signal Processors, Architecture, Programming and ApplicationsB. Venkataramani and M.
1.
Bhaskar, 2002, TMH.
2. DSP Processor Fundamentals, Architectures & Features – Lapsley et al. 2000, S. Chand & Co

Digital Signal Processing Applications Using the ADSP-2100 Family by The Applications
3.
Engineering Staff of Analog Devices, DSP Division, Edited by Amy Mar, PHI
The Scientist and Engineer‟s Guide to Digital Signal Processing by Steven W. Smith, Ph.D.,
4.
California Technical Publishing, ISBN 0-9660176-3-3, 1997
WEB RESOURCES

1. https://www.arm.com/resources/education/online-courses/digital-signal-processing

2. https://electronicsforu.com/resources/cool-stuff-misc/8-free-digital-signal-processing-ebooks

3. https://www.analog.com/en/design-center/landing-pages/001/beginners-guide-to-dsp.html

4. http://users.ece.utexas.edu/~bevans/hp-dsp-seminar/

5.
 VLSI SIGNAL PROCESSING
I M. Tech II Semester
Course Category Professional Core Course Code 19042D09
Course Type Theory (Elective-III) L-T-P-C 3-0-0-3
Prerequisites Internal Assessment 40
Semester End Examination 60
Total Marks 100

COURSE OUTCOMES
Cognitive
Upon successful completion of the course, the student will be able to:
Level
CO1 Design Low Power IIR Filter Using Pipelining And Parallel Processing K3

CO2 Analyze Folding Techniques For Area Reduction K2

CO3 Understand VLSI Design Methodology For Signal Processing Systems K3

CO4 Understand VLSI Algorithms And Architectures For DSP. K3

Implement Basic Architectures For DSP Using CAD Tools
CO5 K3
K1: Remember, K2: Understand, K3: Apply, K4: Analyze, K5: Evaluate, K6: Create.
Contribution of Course Outcomes towards achievement of Program
Outcomes (1 – Low, 2 - Medium, 3 – High)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 2 3 2 1 0 0 0 0 0 0 0 1
CO2 2 3 3 0 0 0 0 0 0 0 0 1
CO3 2 3 3 0 0 0 0 0 0 0 0 0
CO4 2 3 2 0 0 0 0 0 0 0 0 0
CO5 2 2 2 0 0 0 0 0 0 0 0 0

COURSE CONTENT
Introduction to DSPTypical DSP algorithms, DSP algorithms benefits, Representation of DSP
algorithms Pipelining and Parallel Processing Introduction, Pipelining of FIR Digital filters,
UNIT I
Parallel Processing, Pipelining and Parallel Processing for Low Power Retiming Introduction
– Definitions and Properties – Solving System of Inequalities – Retiming Techniques
Folding: Introduction -Folding Transform - Register minimization Techniques – Register
minimization in folded architectures – folding of multi rate systems Unfolding: Introduction –
UNIT II
An Algorithm for Unfolding – Properties of Unfolding – critical Path, Unfolding and
Retiming – Applications of Unfolding
Systolic Architecture Design Introduction – Systolic Array Design Methodology – FIR
UNIT III Systolic Arrays – Selection of Scheduling Vector – Matrix Multiplication and 2D Systolic
Array Design – Systolic Design for Space Representations contain Delays
Fast Convolution Introduction – Cook-Toom Algorithm – Wino gard algorithm – Iterated
UNIT IV
Convolution – Cyclic Convolution – Design of Fast Convolution algorithm by Inspection
 Low Power Design Scaling Vs Power Consumption –Power Analysis, Power Reduction
techniques – Power Estimation Approaches Programmable DSP: Evaluation of
UNIT V
Programmable Digital Signal Processors, DSP Processors for Mobile and Wireless
Communications, Processors for Multimedia Signal Processing

TEXT BOOKS
VLSI Digital Signal Processing- System Design and Implementation – Keshab K. Parhi, 1998,
1.
Wiley InterScience
VLSI and Modern Signal Processing – Kung S. Y, H. J. While House, T. Kailath, 1985,
2.
PrenticeHall
REFERENCE BOOKS
Design of Analog – Digital VLSI Circuits for Telecommunications and Signal Processing – Jose
1.
E. France, Yannis Tsividis, 1994, Prentice Hall
2. VLSI Digital Signal Processing – Medisetti V. K, 1995, IEEE Press (NY),USA

WEB RESOURCES

1. https://www.slideshare.net/krishna602/ds-p-algorithms-02

2. https://www.semanticscholar.org/paper/Folding-and-Register-Minimization-Transformation

3. https://www.oreilly.com/library/view/vlsi-digital-signal/9780471241867/sec-7.2.html

4. https://www.scribd.com/doc/58450407/COOK-TOOM-ALGORITHM

5. https://ieeexplore.ieee.org/document/860100
 SYSTEM ON CHIP DESIGN
I M. Tech II Semester
Course Category Professional Core Course Code 19042D10

Course Type Theory (Elective-IV) L-T-P-C 3-0-0-3

Prerequisites Internal Assessment 40
Basics of chip design Semester End Examination 60
Total Marks 100

COURSE OUTCOMES
Cognitive
Upon successful completion of the course, the student will be able to:
Level
CO1 Able to understand System Architecture. K3

CO2 Able to unnderstand Basic concepts in Processor Architecture. K2

CO3 Able to understand SOC Memory System. K3

CO4 Able to understand Customization and Configuration. K3

CO5 Able to understand Design and evaluation . K3

K1: Remember, K2: Understand, K3: Apply, K4: Analyze, K5: Evaluate, K6: Create.
Contribution of Course Outcomes towards achievement of Program
Outcomes (1 – Low, 2 - Medium, 3 – High)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 2 3 2 2 2 1 0 0 1 2 1 1
CO2 2 2 2 3 2 2 0 0 1 2 1 1
CO3 3 3 2 2 3 1 0 0 1 1 1 1
CO4 2 2 2 2 2 1 0 0 0 2 1 1
CO5 2 3 2 2 2 2 0 0 1 1 1 1

COURSE CONTENT

Introduction to the System Approach: System Architecture, Components of the system,

UNIT I Hardware & Software, Processor Architectures, Memory and Addressing. System level
interconnection, An approach for SOC Design, System Architecture and Complexity

Processors: Introduction , Processor Selection for SOC, Basic concepts in Processor

Architecture, Basic concepts in Processor Micro Architecture, Basic elements in Instruction
UNIT II
handling. Buffers: minimizing Pipeline Delays, Branches, More Robust Processors, Vector
Processors and Vector Instructions extensions, VLIW Processors, Superscalar Processors
Memory Design for SOC: Overview of SOC external memory, Internal Memory, Size,
Scratchpads and Cache memory, Cache Organization, Cache data, Write Policies, Strategies
UNIT III for line replacement at miss time, Types of Cache, Split – I, and D – Caches, Multilevel
Caches, Virtual to real translation , SOC Memory System, Models of Simple Processor –
memory interaction
 Interconnect Customization and Configuration: Inter Connect Architectures, Bus: Basic
Architectures, SOC Standard Buses , Analytic Bus Models, Using the Bus model, Effects of
Bus transactions and contention time. SOC Customization: An overview, Customizing
UNIT IV
Instruction Processor, Reconfiguration Technologies, Mapping design onto Reconfigurable
devices, Instance- Specific design, Customizable Soft Processor, Reconfiguration - overhead
analysis and trade-off analysis on reconfigurable Parallelism

Application Studies / Case Studies: SOC Design approach, AES algorithms, Design and
UNIT V
evaluation, Image compression – JPEG compression

TEXT BOOKS
Computer System Design System-on-Chip - Michael J. Flynn and Wayne Luk, WileyIndia
1.
Pvt.Ltd,2011
2. ARM System on Chip Architecture – Steve Furber –2nd Ed., 2000, Addison Wesley Professional

REFERENCE BOOKS
1. Design of System on a Chip: Devices and Components – Ricardo Reis, 1st Ed., 2004, Springer
Co-Verification of Hardware and Software for ARM System on Chip Design (Embedded
2.
Technology) – Jason Andrews – Newnes, BK and CDROM.
System on Chip Verification – Methodologies and Techniques, Paterson and Leena Singh L, 2001,
3.
Kluwer Academic Publishers
WEB RESOURCES

1. www.vssut.ac.in

2. Searchsecurity.techtarget.com

3. www.geeksforgeeks.com

4. www.123seminarsonly.com

5. www.slideshare.net
 OPTIMIZATION TECHNIQUES IN VLSI DESIGN
I M. Tech II Semester
Course Category Professional Core Course Code 19042D11
Course Type Theory (Elective-IV) L-T-P-C 3-0-0-3
Prerequisites Internal Assessment 40
Semester End Examination 60
Total Marks 100

COURSE OUTCOMES
Cognitive
Upon successful completion of the course, the student will be able to:
Level
Compare various statistical modelling methods such as Monte carlo techniques,
CO1 Pelgroms methods, principle component based and quad tree based modelling K3
methods.

CO2 Analyze the systems by using concepts of high level and gate level statistical K2
methods

CO3 Analyze complete knowledge regarding the various algorithms used for K3
optimization of power and area.

CO4 Develop the real time applications using optimization techniques such as Genetic K3
Algorithms.

CO5 Apply CMOS technology -specific layout rules in the placement and routing of K3
transistor sand to verify the functionality, timing and power
K1: Remember, K2: Understand, K3: Apply, K4: Analyze, K5: Evaluate, K6: Create.
Contribution of Course Outcomes towards achievement of Program
Outcomes (1 – Low, 2 - Medium, 3 – High)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
- 1 - 2 2 - - - - - - -
CO1
- 3 2 3 - - - - - - - -
CO2
- 1 - 4 2 - - - - - - -
CO3
- - - 3 - 2 - - - - - -
CO4
1 2 - 3 3 - - - - - -
CO5

COURSE CONTENT
Statistical Modeling Modeling sources of variations, Monte Carlo techniques, Process
variation modeling- Pelgrom‟s model, Principle component based modeling, Quad tree based
UNIT I
modeling, Performance modeling- Response surface methodology, delay modeling,
interconnect delay models
Statistical Performance, Power and Yield Analysis Statistical timing analysis, parameter
space techniques, Bayesian networks Leakage models, Highlevel statistical analysis, Gate
UNIT II
level statistical analysis, dynamic power, leakage power, temperature and power supply
variations, High level yield estimation and gate level yield estimation
 Convex Optimization Convex sets, convex functions, geometric programming, trade-off and
sensitivity analysis, Generalized geometric programming, geometric programming applied to
UNIT III
digital circuit gate sizing, Floor planning, wire sizing, Approximation and fitting- Monomial
fitting, Maxmonomial fitting, Polynomial fitting
Genetic Algorithm Introduction, GA Technology-Steady State Algorithm-
Fitness Scaling-Inversion GA for VLSI Design, Layout and Test automation- partitioning-
automatic placement, routing technology, Mapping for FPGA- Automatic test generation-
UNIT IV
Partitioning algorithm Taxonomy-Multi-way Partitioning Hybrid genetic-encoding-local
improvement-WDFR Comparison of CAS-Standard cell placement GASP algorithm- unified
algorithm
FPGA Routing Procedures and Power Estimation Global routing-FPGA technology mapping-
circuit generation-test generation in a FPGA frame work-test generation
UNIT V
procedures, Power estimation-application of GA Standard cell placement-GA for ATG-
problem encoding- fitness function-GA Vs Conventional algorithm

TEXT BOOKS
Statistical Analysis and Optimization for VLSI: Timing and Power -Ashish Srivastava, Dennis
1.
Sylvester, David Blaauw, Springer, 2005
Genetic Algorithm for VLSI Design, Layout and Test Automation -Pinaki Mazumder,
2.
E.Mrudnick, Prentice Hall,1998
REFERENCE BOOKS
Convex Optimization Stephen Boyd, Lieven Vandenberghe, Cambridge University
1.
Press,2004
WEB RESOURCES

1.
2.
3.

4.

5.
 SEMICONDUCTOR MEMORY DESIGN AND TESTING
I M. Tech II Semester
Course Category Professional Core Course Code 19042D12
Course Type Theory (Elective-IV) L-T-P-C 3-0-0-3
Prerequisites Internal Assessment 40
Semester End Examination 60
Total Marks 100

COURSE OUTCOMES
Cognitive
Upon successful completion of the course, the student will be able to:
Level
CO1 Understand different types of RAM, ROM designs. K3

CO2 Analyze different RAM and ROM architectures and interconnects. K2

CO3 Implement fault models for memory testing. K3

CO4 Analyze different memory testing and design for testability. K3

Design reliable memories with efficient architecture to improve processes
CO5 K3
times and power.
K1: Remember, K2: Understand, K3: Apply, K4: Analyze, K5: Evaluate, K6: Create.
Contribution of Course Outcomes towards achievement of Program
Outcomes (1 – Low, 2 - Medium, 3 – High)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 1 3 3 0 0 0 0 0 0 0 0 2
CO2 1 3 2 0 0 0 0 0 0 0 0 1
CO3 2 3 1 0 0 0 0 0 0 0 0 1
CO4 0 3 3 0 0 0 0 0 0 0 0 2
CO5 1 3 2 0 0 0 0 0 0 0 0 1

COURSE CONTENT
Random Access Memory Technologies SRAM – SRAM Cell structures, MOS SRAM
Architecture, MOS SRAM cell and peripheral circuit operation, Bipolar SRAM technologies,
SOI technology, Advanced SRAM architectures and technologies, Application specific
UNIT I
SRAMs, DRAM – DRAM technology development, CMOS DRAM, DRAM cell theory and
advanced cell structures, BICMOS DRAM, soft error failure in DRAM, Advanced DRAM
design and architecture, Application specific DRAM
Non-volatile Memories Masked ROMs, High density ROM, PROM, Bipolar ROM, CMOS
PROMS, EPROM, Floating gate EPROM cell, One time programmable EPROM, EEPROM,
UNIT II
EEPROM technology and architecture, Non-volatile SRAM, Flash Memories (EPROM or
EEPROM), advanced Flash memory architecture
Memory Fault Modeling Testing and Memory Design for Testability and Fault Tolerance
RAM fault modeling, Electrical testing, Pseudo Random testing, Megabit DRAM Testing,
UNIT III
non-volatile memory modeling and testing, IDDQ fault modeling and testing, Application
specific memory testing, RAM fault modeling, BIST techniques for memory
UNIT IV Semiconductor Memory Reliability and Radiation Effects General reliability issues RAM
 failure modes and mechanism, Non-volatile memory reliability, reliability modeling and
failure rate prediction, Design for Reliability, Reliability Test Structures, Reliability
Screening and qualification, Radiation effects, Single Event Phenomenon (SEP), Radiation
Hardening techniques, Radiation Hardening Process and Design Issues, Radiation Hardened
Memory characteristics, Radiation Hardness Assurance and Testing, Radiation Dosimetry,
Water Level Radiation Testing and Test structures
Advanced Memory Technologies and High-density Memory Packing
TechnologiesFerroelectric RAMs (FRAMs), GaAs FRAMs, Analog memories, magneto
UNIT V resistive RAMs (MRAMs), Experimental memory devices, Memory Hybrids and MCMs
(2D), Memory Stacks and MCMs (3D), Memory MCM testing and reliability issues, Memory
cards, High Density Memory Packaging Future Directions

TEXT BOOKS

1. Semiconductor Memories Technology – Ashok K. Sharma, 2002, Wiley

Advanced Semiconductor Memories – Architecture, Design and Applications - Ashok K. Sharma-
2.
2002
REFERENCE BOOKS
1. Modern Semiconductor Devices for Integrated Circuits – Chenming CHu, 1st Ed., Prentice Hall
2.

WEB RESOURCES

1. https://www.electronics-notes.com/articles/electronic_components/semiconductor

2. https://www.electronicproducts.com/Digital_ICs/Memory/Fundamentals_of_nonvolatile_memory

3. https://link.springer.com/content/pdf/bbm%3A978-0-306-47972-4%2F1.pdf

4. https://www.researchgate.net/publication/220649285_Memory_Fault_Modeling

5. https://catalogimages.wiley.com/images/db/pdf/0471208132.excerpt.pdf
 VLSI Design Laboratory -II
I M. Tech II Semester
Course Category Professional Core Course Code 19042L02
Course Type Laboratory L-T-P-C 4-0-0-2
Prerequisites Internal Assessment 40
Semester End Examination 60
Total Marks 100

The students are required to design and implement the Layout of the following Experiments
of any SIX using CMOS 130nm Technology with Mentor Graphics Tool.
List of Experiments:
1. Inverter Characteristics.
2. Full Adder.
3. RS-Latch, D-Latch and Clock Divider.
4. Synchronous Counter and Asynchronous Counter.
5. Static RAM Cell.
6. Dynamic RAM Cell.
7. ROM
8. Digital-to-Analog-Converter.
9. Analog-to-Digital Converter.
PART-B: Mixed Signal Simulation
The students are required to perform the following experimental concepts with suitable
complexity mixed-signal application based circuits of any FOUR (circuits consisting of both
analog and digital parts) using necessary software tools.
1. List of experimental Concepts:
2. Analog circuit simulation.
3. Digital circuit simulation.
4. Mixed signal simulation.
5. Layout Extraction.
6. Parasitic values estimation from layout.
7. Layout Vs Schematic.
8. Net List Extraction.
9. Design Rule Checks.
Lab Requirements:
Software:
Xilinx ISE Suite 13.2 Version, Mentor Graphics-Questa Simulator, Mentor
Graphics-Precision RTL, Mentor Graphics Back End/Tanner Software tool,
Mixed Signal simulator
Hardware:
Personal Computer with necessary peripherals, configuration and operating
System and relevant VLSI (CPLD/FPGA) hardwareKits
 EMBEDDED SYSTEM DESIGN
I M. Tech III Semester
Course Category Professional Core Course Code 19043T07
Course Type Theory L-T-P-C 3-0-0-3
Prerequisites Internal Assessment 40
Semester End Examination 60
Total Marks 100

COURSE OUTCOMES
Cognitive
Upon successful completion of the course, the student will be able to:
Level
List technologies, their integration, design flow and software development
CO1 K3
for Embedded systems
Classify embedded processors, memory and its management, embedded input
CO2 K2
and output components, Bus integration and performance
Summarize device drivers, Multitasking, process, i/o and file management;
CO3 K3
middleware and application software
Explain Embedded system design and development, downloading and
CO4 K3
debugging
Demonstrate Case studies like Power PC, Micro blaze, NIOS-II; design on
CO5 K3
Altera platform
K1: Remember, K2: Understand, K3: Apply, K4: Analyze, K5: Evaluate, K6: Create.
Contribution of Course Outcomes towards achievement of Program
Outcomes (1 – Low, 2 - Medium, 3 – High)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 2 2
CO2 3 2 2
CO3 3 2 2
CO4 3 2 2 2 2
CO5 3 2 1 2 2

COURSE CONTENT
Introduction An Embedded System-Definition, Examples, Current Technologies, Integration
in system Design, Embedded system design flow, hardware design concepts, software
UNIT I
development, processor in an embedded system and other hardware units, introduction to
processor based embedded system design concepts
Embedded Hardware Embedded hardware building blocks, Embedded Processors – ISA
architecture models, Internal processor design, processor performance, Board Memory –
ROM, RAM, Auxiliary Memory, Memory Management of External Memory, Board Memory
UNIT II and performance.
Embedded board Input / output – Serial versus Parallel I/O, interfacing the I/O components,
I/O components and performance, Board buses – Bus arbitration and timing, Integrating the
Bus with other board components, Bus performance
Embedded Software Device drivers, Device Drivers for interrupt-Handling, Memory device
drivers, On-board bus device drivers, Board I/O drivers, Explanation about above drivers with
suitable examples.
UNIT III
Embedded operating systems – Multitasking and process Management, Memory
Management, I/O and file system management, OS standards example – POSIX, OS
performance guidelines, Board support packages, Middleware and Application Software –
 Middle ware, Middleware examples, Application layer software examples

Embedded System Design, Development, Implementation and Testing Embedded system

design and development lifecycle model, creating an embedded system architecture,
introduction to embedded software development process and tools- Host and Target machines,
UNIT IV linking and locating software, Getting embedded software into the target system, issues in
Hardware-Software design and co-design. Implementing the design-The main software utility
tool, CAD and the hardware, Translation tools, Debugging tools, testing on host machine,
simulators, Laboratory tools, System Boot-Up.
Embedded System Design Case Studies Case studies Processor design approach of an
embedded system– Power PC Processor based and Micro Blaze Processor based Embedded
UNIT V system design on Xilinx platform-NiosII Processor based Embedded system design on
Altera platform Respective Processor architectures should be taken into consideration while
designing an Embedded System

TEXT BOOKS
Tammy Noergaard “Embedded Systems Architecture: A Comprehensive Guide for Engineers and
1.
Programmers”, Elsevier(Singapore) Pvt.Ltd.Publications,2005
Frank Vahid, Tony D. Givargis, “Embedded system Design: A
2.
Unified Hardware/Software Introduction”, John Wily & SonsInc.2002.
REFERENCE BOOKS
1. Peter Marwedel, “Embedded System Design”, Science Publishers,2007.
2. Arnold S Burger, “Embedded System Design”, CMP,2001

Rajkamal, “Embedded Systems: Architecture, Programming and Design”, TMH Publications,

3.
Second Edition,2008
WEB RESOURCES

1. https://www.digimat.in/nptel/courses/video/106105159/L01.html

2. https://www.coursera.org/learn/introduction-embedded-systems
 TESTING AND TESTABILITY
I M. Tech III Semester
Course Category Professional Core Course Code 19043T08
Course Type Theory L-T-P-C 3-0-0-3
Prerequisites Basic knowledge of Internal Assessment 40
testing and state Semester End Examination 60
machines Total Marks 100

COURSE OUTCOMES
Cognitive
Upon successful completion of the course, the student will be able to:
Level
Remember the basic concepts of Analog and Digital testing devices used
CO1 K3
in chip designing
Understand the concepts of simulation and design verification used in chip
CO2 K2
modeling
CO3 Apply the concept of testing digital circuits used in industrial applications K3

CO4 Analyze the build in self test testing procedures used in chip manufacturing K3

CO5 Design TAP controllers used in testing process using BDSL K3

K1: Remember, K2: Understand, K3: Apply, K4: Analyze, K5: Evaluate, K6: Create.
Contribution of Course Outcomes towards achievement of Program
Outcomes (1 – Low, 2 - Medium, 3 – High)
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 2 2 3 1 2 3 2 1
CO2 2 1 3 1 2 1 2 2
CO3 2 2 3 2 1 2 2 3
CO4 2 2 3 1 2 1 2 2
CO5 2 2 3 1 1 3 2 2

COURSE CONTENT
Introduction to Testing: Testing Philosophy, Role of Testing, Digital and Analog VLSI
Testing, VLSI Technology Trends affecting Testing, Types of Testing, Fault Modeling:
UNIT I
Defects, Errors and Faults, Functional Versus Structural Testing, Levels of Fault Models,
Single Stuck-at Fault

Logic and Fault Simulation : Simulation for Design Verification and Test Evaluation,
UNIT II Modeling Circuits for Simulation, Algorithms for True-value Simulation, Algorithms for
Fault Simulation

Testability Measures: SCOAP Controllability and Observability, High Level Testability

UNIT III Measures, Digital DFT and Scan Design: Ad-Hoc DFT Methods, Scan Design, Partial-Scan
Design, Variations of Scan
Built-In Self-Test: The Economic Case for BIST, Random Logic BIST: Definitions, BIST
Process, Pattern Generation, Response Compaction, Built-In Logic Block Observers, Test-Per-
UNIT IV
Clock, Test-Per- Scan BIST Systems, Circular Self Test Path System, Memory BIST, Delay
Fault BIST
 Boundary Scan Standard : Motivation, System Configuration with Boundary Scan: TAP
UNIT V Controller and Port, Boundary Scan Test Instructions, Pin Constraints of the Standard,
Boundary Scan Description Language: BDSL Description Components, Pin Descriptions

TEXT BOOKS
Essentials of Electronic Testing for Digital, Memory and Mixed Signal VLSI Circuits -
1.
M.L. Bushnell, V. D. Agrawal, Kluwer Academic Pulishers
2.

REFERENCE BOOKS
Digital Systems and Testable Design - M. Abramovici, M.A.Breuer and A.D Friedman, Jaico
1.
PublishingHouse
2. Digital Circuits Testing and Testability - P.K. Lala, AcademicPress

WEB RESOURCES

1.
2.
3.

4.

5.