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Array or Binary Multiplier

The document discusses the hardware implementation of an array or binary multiplier. It begins by explaining that an array multiplier allows for fast multiplication using a combinational circuit that forms all product bits simultaneously, as opposed to sequential addition of partial products. It then provides an example of a 2-bit multiplier implementation using AND gates to form partial products and half adders to sum them. Finally, it illustrates a 4-bit by 3-bit array multiplier using 12 AND gates and two 4-bit adders to produce a 7-bit product.

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Moses Dian
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456 views2 pages

Array or Binary Multiplier

The document discusses the hardware implementation of an array or binary multiplier. It begins by explaining that an array multiplier allows for fast multiplication using a combinational circuit that forms all product bits simultaneously, as opposed to sequential addition of partial products. It then provides an example of a 2-bit multiplier implementation using AND gates to form partial products and half adders to sum them. Finally, it illustrates a 4-bit by 3-bit array multiplier using 12 AND gates and two 4-bit adders to produce a 7-bit product.

Uploaded by

Moses Dian
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Array or Binary Multiplier

Need of a fast multiplier


• Checking the bits of the multiplier one at a time and forming partial products is a
sequential operation that requires a sequence of add and shift microoperations.
• The multiplication of two binary numbers can be done with one microoperation by
means of a combinational circuit that forms the product bits all at once.
• This is a fast way of multiplying two numbers since all it takes is the time for the
signals to propagate through the gates that form the multiplication array.
• However, an array multiplier requires a large number of gates, and for this reason it
was not economical until the development of integrated circuits.
Hardware Implementation of Array Multiplier (2 bit Multiplicand and 2 bit Multiplier):

• Consider the multiplication of two 2-bit numbers.


• The multiplicand bits are B1 and B0, the multiplier bits are A1 and A0, and the
product is C3C2C1C0.
• The first partial product is formed by multiplying B1B0 by A0.
• The multiplication of two bits such as A0 and B0 produces a 1 if both bits are 1;
otherwise, it produces a 0.
• This is identical to an AND operation and partial product can be implemented with
AND gates.
• The second partial product is formed by multiplying B1B0 by A1 and shifting one
position to the left.
• The two partial products are added with two half-adder (HA) circuits.
• If there are more bits in the partial products, then use full adders to produce the
sum of the partial products.
• Note: the least significant bit of the product does not have to go through an adder,
since it is formed by the output of the first AND gate.
• A combinational circuit binary multiplier with more bits can be constructed in a
similar fashion.
• A bit of the multiplier is ANDed with each bit of the multiplicand in as many levels as
there are bits in the multiplier.
• The binary output in each level of AND gates is added with the partial product of the
previous level to form a new partial product.
• The last level produces the product.
• In general, for J multiplier bits and K multiplicand bits, we need (J x K) AND gates
and (J – 1) K -bit adders to produce a product of (J + K) bits.

Hardware Implementation of Array Multiplier (4 bit by 3 bit binary multiplier):


• Example: consider a multiplier circuit that multiplies a binary number represented by
four bits by a number represented by three bits.
• Let the multiplicand be represented by B3B2B1B0 and the multiplier by A2A1A0.
• Since K = 4 and J = 3, we need 12 AND gates and two 4-bit adders to produce a
product of seven bits.
• The logic diagram of the multiplier is shown below.

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