模拟集成电路课程设计（版图）

Layout in Analog Integrated Circuits

Assist. Prof. Jian Zhao
Prof. Guoxing Wang

Shanghai Jiao Tong University

School of Microelectronics
zhaojianycc@sjtu.edu.cn

LayoutinAnalogIntegratedCircuits
 Instructors
• Time
– Lecture: Tuesday 14:00 to 15:00
– Lab: Tuesday 15:00~17:30, Friday 14:00~17:30
• Lecturer
– Assist. Prof. Jian Zhao (赵健) & Prof. Guoxing Wang
– School of Microelectronics, Room 427
– zhaojianycc@sjtu.edu.cn
• TA: Eng. Luo Jing
– School of Microelectronics, Room 404.
– luojing@sjtu.edu.cn

LayoutinAnalogIntegratedCircuits Slide 1
 WeChat group

LayoutinAnalogIntegratedCircuits Slide 2
 Syllabus
L1: Introduction
L2: Process, Active & Passive Components
L3: Process variation & Matching Issues
L4: Parasitic Effects
L5: Noise & Shield
L6: Failure Mechanism & DFM
L7: Floor planning & Package
L8: Layout of Amplifiers & Data Converters

LayoutinAnalogIntegratedCircuits Slide 3
 Grade

- Home work assignments : 40% (10+15+15)

- Class performance: 20% (10% for attendance)
- One project : 40%

No copy from others!

Students are encouraged to provide

feedbacks after each course~

Website of this module is in progress…

LayoutinAnalogIntegratedCircuits Slide 4
 Textbook & Materials

IC Mask Design Essential Layout Techniques, The Art of Analog Layout,

Christopher Saint, et al., Alan Hastings,
McGraw Hill, 2002 Pearson Education, 2006

[1] Layout of Analog CMOS Integrated Circuits, Franco Malberti.

www.ims.unipv.it/Courses/download/AIC/
[2] CMOS Transistor Layout KungFu , Lee Eng Han, 2005. www.eda-utilities.com

LayoutinAnalogIntegratedCircuits Slide 5
 Outline of lecture 1 & 2
• Introduction of Analog Layout
• CMOS process brief
• Design rules
• Basic cells layout
• Design flow of Analog layout (DRC, LVS, PEX)

LayoutinAnalogIntegratedCircuits Slide 6
 IC-connecting billions of transistors
• Millions of transistors are
made
• They are connected
through layers of metals

LayoutinAnalogIntegratedCircuits Slide 7
 What is the role of layout
• Designer have to provide layout info. to foundry
instead of schematic.
Schematic design

Layout design

LayoutinAnalogIntegratedCircuits Slide 8
 What is the role of layout
• Important role between circuit design & fabrication
1. Fabrication (制造) 2. Dicing (划片)

4. Packaging (封装) 3. Bonding (键合)

LayoutinAnalogIntegratedCircuits Slide 9
 What is layout?
• Layout = Manufactural design language

LayoutinAnalogIntegratedCircuits Slide 10
 What is layout?
• Layout = Manufactural design language

LayoutinAnalogIntegratedCircuits Slide 11
 What is layout?
• A 3-D view of CMOS transistors with metals

↓ ↓ ↓ Extremely clear 3-d illustration of CMOS process

http://www.vlsi-expert.com/2014/09/fabrication-steps-cmos-
processing-part-1.html

LayoutinAnalogIntegratedCircuits Slide 12
 What is layout?
• Layout = Manufactural design language

LayoutinAnalogIntegratedCircuits Slide 13
 Mask to layout
• Layout design = Mask design
• Foundry requires geometry info.

Top View
Cross-section view
Masks

LayoutinAnalogIntegratedCircuits Slide 14
 Why layout is so important?
• Direct related to COST!
– Area (cost)
– Yield (robustness) 鲁棒性
• Imperfections (precision)
– Process variations (matching, design rules)
– Parasitic effects (shield, floor plan)
– Temperature gradient (matching, floor plan)

Layout determines almost everything!

Cost, Precision, Robustness…

LayoutinAnalogIntegratedCircuits Slide 15
 Why layout is so important?
• Layout is key step towards real chip
• Layout is fundamental knowledge for EDA

EDA for ADC EDA for DAC

(模数转换器) (数模转换器)

LayoutinAnalogIntegratedCircuits Slide 16
 Outline of lecture 1 & 2
• Introduction of Analog Layout
• CMOS process brief
• Design rules
• Basic cells layout
• Design flow of Analog layout (DRC, LVS, PEX)

LayoutinAnalogIntegratedCircuits Slide 17
 IC Fabrication Process –Example

Starting from Layout

of a single NMOS

Cross-section of the
finished NMOS

LayoutinAnalogIntegratedCircuits Slide 18
 IC Fabrication Process –a Glance (0)
• Photoresist is a light-sensitive organic polymer
• Softens where exposed to UV light

LayoutinAnalogIntegratedCircuits Slide 19
 IC Fabrication Process –a Glance (1)
(掩模版) (图形化)
Deposition -> lithography -> etching Mask & Patterning
(沉积) (光刻) (刻蚀)

Light can be precisely controlled! Photoresist

(光刻胶)
Liquid is more destructive but uncontrollable!
LayoutinAnalogIntegratedCircuits Slide 20
 Lithography (光刻)

LayoutinAnalogIntegratedCircuits Slide 21
 IC Fabrication Process –a Glance (2)
Deposition -> lithography -> etching (poly)

https://www.ece.ucdavis.edu/~bower/mosfetdetail.htm

LayoutinAnalogIntegratedCircuits Slide 22
 IC Fabrication Process –a Glance (3)
Deposition -> lithography -> etching (diffusion & oxide)

LayoutinAnalogIntegratedCircuits Slide 23
 IC Fabrication Process –a Glance (4)
Deposition -> lithography -> etching (metal)

LayoutinAnalogIntegratedCircuits Slide 24
 IC Fabrication Process –a Glance (5)
• Contact, Via and Metal are formed in the same way
(触点) (过孔)

LayoutinAnalogIntegratedCircuits Slide 25
 Outline of lecture 1 & 2
• Introduction of Analog Layout
• CMOS process brief
• Design rules
• Basic cells layout
• Design flow of Analog layout (DRC, LVS, PEX)

LayoutinAnalogIntegratedCircuits Slide 26
 Design Rules
• Design rules are a set of contracts between the circuit
designers and process engineers
• Four categories of Design Rules:
– C1: Unit dimension: Minimum line width
• Scalable design rules: lambda parameter
• Absolute dimensions (micron rules)
– C2: Intra-Layer rules
• Width and spacing
– C3: Inter-Layer rules
• Enclosures and overlaps
– C4: Special rules
• Antenna rules, area, density rules

LayoutinAnalogIntegratedCircuits Slide 27
 Why we need design rules?
• Defects, Impurities/dust particles
• Imperfections in photoresist / mask

Ideal case Practical case

LayoutinAnalogIntegratedCircuits Slide 28
 Why we need design rules?
• Prevent mask from interference
The outline of mask will be larger than the original shape!

LayoutinAnalogIntegratedCircuits Slide 29
 Intra-layer rules
• Minimum width
– Defines the resolution of technology
– Potential open circuits or fusing
• Minimum spacing rule
Process variations
– Avoid unwanted short circuit

LayoutinAnalogIntegratedCircuits Slide 30
 Intra-layer rules
• Minimum width
– Defines the resolution of technology
– Potential open circuits or fusing
• Minimum spacing rule
– Avoid unwanted short circuit

Process variations

LayoutinAnalogIntegratedCircuits Slide 31
 Inter-layer rules (anti-misalignment)
• Extension Rule (延伸规则)
– Some geometries must extend beyond the edge of others
by a minimum value
• Overlap rule (重叠规则)
• Enclosure rule (包围规则)

Extension ensure proper

action at the edge

LayoutinAnalogIntegratedCircuits Slide 32
 Inter-layer rules
• Minimum Extension Rule
• Overlap rule
• Enclosure rule
– guarantee the contact/via area

LayoutinAnalogIntegratedCircuits Slide 33
 Design rules in a practical process

Poly0 width >= 2.5 m

…
Poly1 enclosure of Contact >= 1.25 m

LayoutinAnalogIntegratedCircuits Slide 34
Design rules in a practical process

Front-end of line
FEOL 前端工艺

BEOL Back-end of line

后端工艺

LayoutinAnalogIntegratedCircuits Slide 35
 Complexity of the design rules
• More design rules refer to the process document.

LayoutinAnalogIntegratedCircuits Slide 36
 Outline of lecture 1 & 2
• Introduction of Analog Layout
• CMOS process brief
• Design rules
• Basic cells layout
• Design flow of Analog layout (DRC, LVS, PEX)

LayoutinAnalogIntegratedCircuits Slide 37
 Layout of Basic Cells
• Layout of Transistors
• Layout of Resistors
– Categories of resistors
– Layout of resistors
• Layout of Capacitors
– Categories of resistors
– Layout of resistors

LayoutinAnalogIntegratedCircuits Slide 38
 Layout of transistors
• Parasitic parameters in transistors w./ large W/L

• Large area leads to large parasitic

Process dependent! Gain, GBW…

LayoutinAnalogIntegratedCircuits Slide 39
 Layout of transistors
• Multi-finger approaches to reduce parasitic para.

How to reduce parasitic cap under same process?

LayoutinAnalogIntegratedCircuits Slide 40
 Concept of CMOS Resistors
• Which shape has larger resistance?
• Unit of CMOS resistor: Ohm/square or Ohm/

R1 R2

1 2 3 4 5

R=L/W*Rsquare=Nsquare*Rsquare

LayoutinAnalogIntegratedCircuits Slide 41
 Categories of Resistors
• Diffused Resistances
– diffused area, p , p , n , n

• Polysilicon Resistances

• Well Resistances

LayoutinAnalogIntegratedCircuits Slide 42
 Layout of resistors
• Accuracy of Resistors
– Suffer from process, temperature & voltage variation

LayoutinAnalogIntegratedCircuits Slide 43
 Intrinsic errors of CMOS resistors
• Contact resistance
• Parasitic capacitors in CMOS resistor

Metal Insulator Metal

W
L

LayoutinAnalogIntegratedCircuits Slide 44
 Intrinsic errors of CMOS resistors
• Contact resistance
• Parasitic capacitors in CMOS resistor

LayoutinAnalogIntegratedCircuits Slide 45
 What is Capacitors
Model for capacitors.

r: relative permittivity

WL: area of overlapping region
tox: thickness of overlapping region
LayoutinAnalogIntegratedCircuits Slide 46
 Non-CMOS (discrete) capacitors
• Multi-layer ceramic cap (陶瓷电容)
• Electrolytic capacitor (电解电容)

Relative permittivity 10~100

Typical value: 1pF (10-12) ~ 100 F (10-4)!!!
LayoutinAnalogIntegratedCircuits Slide 47
 CMOS capacitors
• Drawbacks
– Low permittivity X-Fab Process:
– Limited stack layers (<3) tox,M4-M5=850 nm
– Extra-tech to reduce tox

LayoutinAnalogIntegratedCircuits Slide 48
 Different categories of Cap.
• How to form a parallel plate metals in CMOS?

Poly cap. MIM cap. MOM cap.

Metal-Insulator-Metal Metal-Oxide-Metal

X-Fab Process: poly cap MIM cap MOM cap

Cap density (fF/m2) 0.85 1.25 0.31
Thickness (nm) 41 52 260

Typical value: 10 fF (10-14) ~ 100 pF (10-10)

LayoutinAnalogIntegratedCircuits Slide 49
 Different categories of Cap.
• How to form a parallel plate metals in CMOS?

Poly cap. MIM cap. MOM cap.

Metal-Insulator-Metal Metal-Oxide-Metal

Trade-off poly cap MIM cap MOM cap

Extra layer? (Cost) Yes Yes No
Density (Area) High High Low
Typical value: 10 fF (10-14) ~ 100 pF (10-10)

LayoutinAnalogIntegratedCircuits Slide 50
 Multi-layer capacitors in CMOS
• Multi-layer tech in MIM and MOM caps.

Multi-layer MIM Multi-layer MOM

LayoutinAnalogIntegratedCircuits Slide 51
 Intrinsic errors in CMOS cap.
• Plate-substrate parasitic effect (寄生效应)
• Fringed effect (边缘效应)

Model including
parasitic cap.

LayoutinAnalogIntegratedCircuits Slide 52
 Intrinsic errors in CMOS cap.
• Plate-substrate parasitic effect (寄生效应)
• Fringed effect (边缘效应)

Ideal case

Practical case

10~20% variation!
+Cfringe

LayoutinAnalogIntegratedCircuits Slide 53
 Outline of lecture 1 & 2
• Introduction of Analog Layout
• CMOS process brief
• Design rules
• Basic cells layout
• Design flow of Analog layout (DRC, LVS, PEX)

LayoutinAnalogIntegratedCircuits Slide 54
 Layout design flow
• DRC
– Design rule check
• LVS
– Layout vs. Schematic
• PEX Layout
– Parasitic extraction design
flow

LayoutinAnalogIntegratedCircuits Slide 55
 Summary
• Introduction of layout
– What is layout? Why we need layout?
• CMOS process brief
• Introduction of design rules
– Intra layer rules; Inter layer rules
• Layout of basic cells
– Active (Transistor), Passive (Resistor, Capacitor)
• Layout design flow
– Layout, DRC, LVS, PEX

LayoutinAnalogIntegratedCircuits Slide 56