EE-321 Computer Architecture & Organization

Lecture # 05
Spring 2021

Muhammad Imran Abeel <imran.abeel@seecs.edu.pk>[1]

Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
Memory Technologies Tradeoffs

[2]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Memory Hierarchy

Memory Hierarchy is the classification of memory

used by a processor from

• Lowest Capacity to highest capacity

• Fastest to Slowest

• Most expensive to cheapest

• Closest from CPU to farthest from CPU

[3]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Memory Hierarchy

Want inexpensive, fast memory

▪Main memory Processor

▫Large, inexpensive, slow memory stores

entire program and data Registers

▪Cache Cache
▫Small, expensive, fast memory stores
copy of likely accessed parts of larger
memory Main memory
▫Can be multiple levels of cache
Disk

Tape

[4]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Memory Access & Cost

Memory Typical $ per GB in

Technology Access 2004
Time (ns)
SRAM 0.5 - 5 4000 – 10,000

DRAM 50 – 70 100 - 200

Magnetic 5,000,000 – 0.5 – 2

Disk 20,000,000

[5]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Memory Access & Cost
Memory Typical Access $ per GB in 2004
Technology Time (ns)

SRAM 0.5 - 5 4000 – 10,000

DRAM 50 – 70 100 - 200

Magnetic Disk 5,000,000 – 0.5 – 2

20,000,000

[6]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Memory Access & Cost
Memory Typical $ per GB in
Technology Access 2004
Time (ns)
SRAM 0.5 - 5 4000 – 10,000

DRAM 50 – 70 100 - 200

Magnetic 5,000,000 – 0.5 – 2

Disk 20,000,000

[7]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Memory Access & Cost
Memory Typical $ per GB in
Technology Access 2004
Time (ns)
SRAM 0.5 - 5 4000 – 10,000

DRAM 50 – 70 100 - 200

Magnetic 5,000,000 – 0.5 – 2

Disk 20,000,000

[8]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 CPU Memory Bottleneck

Main
memory
Processor

Performance of high speed computers is

limited by memory bandwidth and latency
▪Latency is the time for a single access
▪Bandwidth is the number of accesses per
unit time

[9]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
Processor, DRAM Latency Gap

[10]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Physical Size : Latency

Processor
Processor

Small memory

Large memory

Big memory: Latency is

greater, signal has
further to travel.
[11]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Memory Hierarchy

Small fast Large, slow

memory memory
Processor

▪ Capacity : Register << SRAM << DRAM

▪ Latency : Register << SRAM << DRAM
▪ Bandwidth : On chip >> off chip
▪ On a data access
▫ If data is in fast memory - > Low latency access to SRAM
▫ If data is not in fast memory - > Long latency access to DRAM
[12]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
Common and Predictable Memory Reference Patterns

[13]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Real Memory Reference Pattern

[14]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Real Memory Reference Pattern

Small fast Large, slow

memory memory
Processor

▪ Exploit temporal Locality by remembering

the contents of recently accessed location.

▪ Exploit Spatial Locality by fetching blocks of

data around recently accessed locations
[15]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 5.1: Stallings
Memory Type Overview

[16]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Memory Type Overview
▪ Traditional ROM/RAM distinctions
▫ ROM
• read only, bits stored without power
▫ RAM
• read and write, lose stored bits without power
▪ Traditional distinctions blurred
▫ Advanced ROMs can be written to
• e.g., EEPROM
▫ Advanced RAMs can hold bits without power
• e.g., NVRAM, DDRAM
▪ Write ability
▫ Speed, a memory can be written
▪ Storage permanence
▫ ability of memory to hold stored bits after they are written
[17]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Write Ability
▪Ranges of write ability
▫High end
processor writes to memory simply and quickly
e.g., RAM
▫Middle range
processor writes to memory, but slower
e.g., FLASH, EEPROM
▫Lower range
special equipment, “programmer”, must be used to
write to memory
e.g., EPROM, OTP ROM
▫Low end
bits stored only during fabrication
e.g., Mask-programmed ROM [18]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Storage performance
• Range of storage permanence
– High end
• essentially never loses bits
• e.g., mask-programmed ROM
– Middle range
• holds bits days, months, or years after memory’s power
source turned off
• e.g., NVRAM
– Lower range
• holds bits as long as power supplied to memory
• e.g., SRAM
– Low end
• begins to lose bits almost immediately after written
• e.g., DRAM [19]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
Write Ability / Storage Performance

[20]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Semi-conductor Memory
Cores: An array of doughnut-shaped ferromagnetic
loops referred to as cores

[21]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Basic types of RAM
▪SRAM: Static RAM
▫Memory cell uses flip-flop to store bit memory cell
internals
▫Requires 6 transistors
SRAM
▫Holds data as long as power supplied

▪DRAM: Dynamic RAM Data' Data

▫Memory cell uses MOS transistor and

W
capacitor to store bit
▫More compact than SRAM
▫“Refresh” required due to capacitor leak DRAM

word’s cells refreshed when read Data

▫Typical refresh rate 15.625 microsec. W

▫Slower to access than SRAM

[22]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 DRAM vs SRAM
• Cell that store data as charge on capacitor.
• Needs constant refreshing.

[23]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 DRAM vs SRAM
▪SRAM: Static RAM
▫Memory cell uses flip-flop to store bit
▫Requires 6 transistors
▫Holds data as long as power supplied
gates(T1 T2 fig a) close when we dont wat to write data
not gates: T3&T1, T4&T2

[24]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 DRAM vs SRAM
When word line is 1, data can be written

Write cycle

bit and bit' are used to reduce error.

[25]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 DRAM vs SRAM

Write cycle

[26]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 DRAM vs SRAM

Read cycle

[27]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 DRAM vs SRAM

• For logic 1: Read

T3 'on' allows 1 to be read
from the bit line

0
1

T2 "on" alows ground to be read from

bit'' line

=1 =0

[28]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 DRAM vs SRAM

• For logic 0: Read

=1 =0

=1 =0

=0
=1

=0 =1

[29]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 DRAM vs SRAM

• For logic 1: Write

[30]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Basic of Memory Architecture
▪Stores large number of bits
m × n memory
▫m x n: m rows of n bits each
…
▫k = Log2(m) address input signals

m rows
▫or m = 2k rows ...
…

▫e.g., 4k x 8 memory:
12 address inputs n bits per row
8 data lines
memory external view

▪Memory access r/w

enable
2k × n read and
▫r/w: selects read or write A0 write memory
▫enable: read or write only when Ak-1
…

asserted …
Qn-1 Q0

[31]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Basic of Memory Architecture
m × n memory
▪Stores large number of bits
▫m x n: m rows of n bits each …
▫k = Log2(m) address input signals

m rows
▫or m = 2k rows ...
▫e.g., 4k x 8 memory:
…
12 address inputs
8 data lines
n bits per row
▪Memory access memory external view
r/w
▫r/w: selects read or write
enable
2k × n read and
▫enable: read or write only when A0 write memory
asserted …
Ak-1
…
Qn-1 Q0 [32]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Basic of Memory Architecture
m × n memory
▪Stores large number of bits …

▫m x n: m rows of n bits each

m rows
...
▫k = Log2(m) address input signals …

▫or m = 2k rows n bits per row

▫e.g., 4k x 8 memory:
12 address inputs memory external view
8 data lines r/w
enable
▪Memory access 2k × n read and
A0 write memory
▫r/w: selects read or write
…
▫enable: read or write only when Ak-1
asserted …
Qn-1 Q0
[33]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
Composing memory
(Revision)

[34]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Composing memory
▪Memory size needed often differs from
size of readily available memories

▫Required size 4K x 16 is but available is 2K x 8

▪When available memory is larger

▫simply ignore unneeded high-order address bits and higher data
lines

▪When available memory is smaller

▫compose several smaller memories into one larger memory [35]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Composing memory

▪Connect side-by-side to increase

width of words

[36]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Composing memory

▪Connect side-by-side to increase

width of words

[37]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Composing memory

▪Connect side-by-side to increase

width of words

[38]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Composing memory
▪ Connect top to bottom to increase number of words
Added high-order address line selects smaller memory containing desired word
using a decoder

𝐴0

…
𝐴𝑚−1 2𝑚 × 𝑛 𝑅𝑂𝑀

1×2 …
0
𝑑𝑒𝑐𝑜𝑑𝑒𝑟
𝐸𝑛𝑎𝑏𝑙𝑒 2𝑚 × 𝑛 𝑅𝑂𝑀

…
𝟐𝒎+𝟏 × 𝒏 𝑹𝑶𝑴

𝑄𝑛−1 𝑄0 [39]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Composing memory: Decoder
▪ Connect top to bottom to increase number of words
Added high-order address line selects smaller memory containing desired word
using a decoder

Upper memory block

0
1
Lower memory block

[40]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Composing memory
▪ Connect top to bottom to increase number of words
Added high-order address line selects smaller memory containing desired word
using a decoder

𝐴0

…
𝐴𝑚−1 2𝑚 × 𝑛 𝑅𝑂𝑀

1×2 …
0 𝑑𝑒𝑐𝑜𝑑𝑒𝑟
𝐸𝑛𝑎𝑏𝑙𝑒 2𝑚 × 𝑛 𝑅𝑂𝑀

…
𝟐𝒎+𝟏 × 𝒏 𝑹𝑶𝑴

𝑄𝑛−1 𝑄0 [41]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Composing memory
▪ Connect top to bottom to increase number of words
Added high-order address line selects smaller memory containing desired word
using a decoder

𝐴0

…
𝐴𝑚−1 2𝑚 × 𝑛 𝑅𝑂𝑀

1×2 …
1 𝑑𝑒𝑐𝑜𝑑𝑒𝑟
𝐸𝑛𝑎𝑏𝑙𝑒 2𝑚 × 𝑛 𝑅𝑂𝑀

…
𝟐𝒎+𝟏 × 𝒏 𝑹𝑶𝑴

𝑄𝑛−1 𝑄0 [42]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Composing memory
▪Combine techniques to increase number and
width of words

[43]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Activity

▫Compose 1K x 8 ROM
into a 2K x 16 ROM

[44]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Activity
▫ Compose 1K x 8 ROM into a 2K x 16 ROM

[45]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Interfacing Signals
▪Interfacing memory with CPU
▫Address lines
▫Data lines
▫Control lines
Enable, read, write, ready, size etc.

Address

CPU Data Memory

Control
[46]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
8088 Minimum Memory Interface
ALE

𝐴8 − 𝐴19

𝐴𝐷0 − 𝐴𝐷7

𝑅𝐷
8088 Memory
𝑊𝑅
ഥ
𝐼𝑂/𝑀
𝐷𝑇/𝑅ത
𝐷𝐸𝑁
+5𝑉 𝑀𝑁/ 𝑀𝑋 𝑆𝑆𝑂

Minimum-mode 8088 memory interface [47]

Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Memory Control Signals
𝐴𝐿𝐸 Address Latch Enable : used to latch the address in external memory

Input-output/Memory : signal external circuity whether memory

ഥ
𝐼𝑂/𝑀 or I/O bus cycle in progress

Data Transmit/Receive : signal external circuity whether 8088 is

𝐷𝑇/𝑅ത transmitting or receiving data over the bus.

𝑊𝑅 Write : identifies a write cycle in progress

𝑅𝐷 Read : identifies a read cycle in progress

𝐷𝐸𝑁 Data Enable : used to enable data bus.

𝑆𝑆𝑂 Status Line : identifies whether a code or data access is in progress

[48]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 8088 : Maximum Memory Interface

𝑀𝑅𝐷𝐶

𝑀𝑊𝑇𝐶

Bus 𝐴𝑀𝑊𝐶
controlle
𝑆0ҧ − 𝑆2 r 8288 ALE

𝐷𝑇/𝑅ത
8086 Memory
𝐷𝐸𝑁

𝐴8 − 𝐴19

0𝑉 𝑀𝑁/ 𝑀𝑋 𝐴𝐷0 − 𝐴𝐷7

Maximum-mode 8088 memory interface [49]

Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Memory control signals

• Maximum Mode Memory

Control Signals

[50]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
8088 Memory Read Cycle (min. mode)

[51]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
8088 Memory Write Cycle (min. mode)

[52]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Reading Assignment

• Maximum Mode Read and

Write Memory Bus cycles.

[53]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Hardware Organization

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Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Hardware Organization

[55]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
Memory Address Decoding : NAND

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Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
Memory Address Decoding : 3 to 8

[57]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Memory Address Decoding : 3 to 8
A 0
B 1
C
2
3 to 8 3
decoder 4
G2A 5
G2B
G1 6
7

[58]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
Memory Address Decoding : 3 to 8

[59]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
Memory Address Decoding : 3 to 8

[60]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Memory Interfacing

[61]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Memory Address

Method 3
Programmable Logic Devices (PLDs)
These devices implement a Boolean
function against each memory chip
connection
• E-g. Programmable Logic Array (PLA)

[62]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 HM6264 & 27C256 RAM/ROM devices

•Low-cost low-capacity memory devices

•First two numeric digits indicate device type

-RAM: 62
-ROM: 27
•Subsequent digits
• HM6264 → 8KB (13 address lines, 8 data lines)
• 27C256 → 32KB (15 address lines, 8 data lines)

[63]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 Questions?

[64]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)
 THANK YOU!

[65]
Course instructor : Muhammad Imran Abeel EE-321: Computer Architecture & Organization (Spring 2021)