CR-1 : @TRINITY_LIB.

TRINITY(SCH_1):PAGE1

8 7 6 5 4 3 2 1

D
PAGE
[1] COVER PAGE
CONTENTS PAGE
[35]
CONTENTS
INFRARED+SWITCHES+ACCELEROMETER+AUDIBLE F/B
TRINITY D
[2]
[3]
GCPU, SETUP
GCPU, DEBUG BUS
[36]
[37]
CONN, FAN
CONN, AVIP REV 1.01
[4] GCPU, VIDEO + PCIEX [38] CONN, RJ45 USB AUX COMBO + BORON + PWR
[5]
[6]
GCPU, EEPROM + JTAG
GCPU, PLL PWR + FSB PWR
[39]
[40]
CONN, USB + MEM PORTS + TOSLINK + WAVEPORT
CONN, HDMI
FAB G RETAIL
[7] GCPU, PWR [41] CONN, ODD + HDD
[8] GCPU, PWR [42] VREGS, BLEEDERS
[9] GCPU, DECOUPLING [43] VREGS, INPUT + OUTPUT FILTERS
[10] GCPU, DECOUPLING [44] VREGS, CPU CONTROLLER
[11] GCPU, DECOUPLING [45] VREGS, CPU OUTPUT PHASE 1 & 2
[12] GCPU, MEMORY CONTROLLER A + B [46] VREGS, V5P0DUAL
[13] GCPU, MEMORY CONTROLLER C + D [47] VREGS, V5P0
C C
[14] MEMORY PARTITION A, TOP [48] VREGS, V3P3
[15] MEMORY PARTITION A, BOTTOM [49] VREGS, VEDRAM
[16] MEMORY PARTITION B, TOP [50] VREGS, VMEM
[17] MEMORY PARTITION B, BOTTOM [51] VREGS, VCS
[18] MEMORY PARTITION C, TOP [52] VREGS, 1P8+GPUPCIE+SBPCIE+CPUPLL+EFUSE
[19] MEMORY PARTITION C, BOTTOM [53] VREGS, STANDBY SWITCHERS
[20] MEMORY PARTITION D, TOP [54] BOARD, DECOUPLING
[21] MEMORY PARTITION D, BOTTOM [55] MARGIN, VMEM + VEDRAM
[22] HANA, CLOCKS + STRAPING + JTAG [56] MARGIN, V3P3 + V5P0
[23] HANA, VIDEO + FAN + AUDIO [57] MARGIN, VREFS + VCS
[24] HANA, POWER + DECOUPLING [58] MARGIN, VGPUPCIE+VSBPCIE+VCPUPLL+V12P0+TEMP
B [25] HANA, POWER + DECOUPLING [59] XDK, DEBUG CONN B
[26] PSB, PCIEX + SMM GPIO + JTAG [60] XDK, DEBUG TITAN
[27] PSB, SMC [61] DEBUG BOARD, SPYDER CONN
[28] PSB, FLASH + USB + SPI [62] LABELS & MOUNTING
[29] PSB, ETHERNET + AUDIO + SATA [63] POWER DIAGRAM
[30] PSB, STANDBY POWER + DECOUPLING [64] CLOCK DIAGRAM
[31] PSB, MAIN POWER + DECOUPLING [65] RESET DIAGRAM
[32] SB OUT, ETHERNET [66] REFERENCE TABLES
[33] SB OUT, AUDIO [67] DOC TRACKING
[34] SB OUT, FLASH
RULES: (APPLIED WHEN POSSIBLE)
1.) MSB TO LSB IS TOP TO BOTTOM
2.) WHEN POSSIBLE: INPUTS ON LEFT, OUTPUTS ON RIGHT
3.) ORDER OF PAGES=CHIP INTERFACES, TERMINATION, POWER, DECOUPLING
4.) AVOID USING OFF PAGE CONNECTORS FOR ON PAGE CONNECTIONS
5.) LANED SIGNALS ARE GROUPED ON SYMBOLS
6.) TRANSIMITTER NAME USED AS PREFIX WITH RX AND TX CONNECTIONS
7.) SUFFIX V_ IS USED FOR VOLTAGE RAIL SIGNAL NAMES A
A 8.) SUFFIX _DP AND _DN ARE USED FOR DIFFERIENTAL PAIRS
9.) UNNAMED NETS ARE NAMED WITH /2 TEXT SIZE
10.) SUFFIX _N FOR ACTIVE LOW OR N JUNCTION
12.) SUFFIX _P FOR P JUNCTION
13.) SUFFIX _EN FOR ENABLE
14.) 'CLK' FOR CLOCKS, 'RST' FOR RESETS
15.) PWRGD FOR POWER GOOD
16.) REV AND FAB ARE SET USING CUSTOM VARIABLES. TOOLS>OPTIONS>VARIABLES

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=COVER PAGE] DRAWING
Wed Feb 10 16:23:24 2010 CONFIDENTIAL
TRINITY_XDK 1/81 G 1.01

8 7 6 5 4 3 2 1
 CR-2 : @TRINITY_LIB.TRINITY(SCH_1):PAGE2

8 7 6 5 4 3 2 1
GCPU SETUP R4D4
27 IN CPU_RST_N 2 1 CPU_RST_V1P1_N OUT 60
1.27 KOHM 1%
1 1 C5R11 402 CH 1 R4D5
FT4R2 FTP 2 KOHM
360 PF 1%
D 5%
50 V 2 CH D
2 EMPTY 402
FT5R18 FTP
1 603

27 IN CPU_PWRGD
1 C4T1
360 PF
5% U5E1 14 OF 17 IC
2 50 V
EMPTY GCPU VERSION 1
603 D5 HARD_RESET_B
CHECKSTOP_B E5 CPU_CHECKSTOP_N OUT 60
R4D1 T5 POWER_GOOD
22 IN CPU_CLK_DP 2 1
0 OHM 5%
402 CH

IN CPU_CLK_DP_R2 P2 CPU_CLK_DP

R4D2 VID6 C24 CPU_VREG_APS6 OUT 43

22 IN CPU_CLK_DN 2 1 VID5 B24 CPU_VREG_APS5 OUT 43
0 OHM 5% VID4 A24 CPU_VREG_APS4 OUT 43
C 402 CH VID3 C23
B23
CPU_VREG_APS3
CPU_VREG_APS2 OUT 43
C
VID2 OUT 43
IN CPU_CLK_DN_R2 P1 CPU_CLK_DN VID1 A23 CPU_VREG_APS1 OUT 43

1 FTP FT7P8
1 FTP FT7P7
CPU_DBG_RST_EN INTERNAL PULLDN 1 FTP FT7P6
1 FTP FT7P5
GPU_DBG_RST_EN INTERNAL PULLDN 1 FTP FT7P4
1 FTP FT7P3

OUT CPU_DBG_RST_EN P5 CPU_DBG_RST_EN<DN>

OUT GPU_DBG_RST_EN R5 GPU_DBG_RST_EN<DN>

OUT EDRAM_PSRO_DOUT N6 PSRO_DOUT

OUT CPU_PSRO0_OUT G7 PSRO0_OUT
V_CPUPLL
WHEN V_CPUPLL=1.83V N: IF V_CPUPLL CHANGES
SET VGATE=1.20V 1 R4T5 VGATE RESISTORS SHOULD BE ADJUSTED
ACTUAL=1.202V 562 OHM
1% J6 CPU_LIMIT_BYPASS
B 2 CH
402
<DN>PULSE_LIMIT_BYPASS OUT
B
CPU_VGATE V6 V_GATE <DN>PLL_BYPASS F8 CPU_PLL_BYPASS OUT
1
FT4T2 FTP
1 R4T6
1.07 KOHM
1%
2 CH RESISTOR0_DP L7 RESISTOR0_DP
402 OUT RESISTOR0_DN M7 A3 CPU_SRVID
OUT RESISTOR0_DN SRVID OUT 51
EFU_POWERON C1 VREG_EFUSE_EN OUT 52

OUT CPU_EXT_CLK_EN F7 EXT_CLK_EN<DN>

CPU_TINIT J7 TI_39_TINIT
E7 TE CORE_HF_BGR_PLL M6 CORE_HF_BGR_PLL OUT
1 R5R1
200 OHM X818336-001 BGA_2
5%
2 CH
402
6 LAYER ONLY SIGNALS

CORE_HF_BGR_PLL 6 LAYER ONLY; TP ONLY

CPU_LIMIT_BYPASS 6 LAYER ONLY; TP ONLY, INTERNAL PULLDN
CPU_PLL_BYPASS 6 LAYER ONLY; TP ONLY, INTERNAL PULLDN
CPU_CORE_HF_CLKOUT_DN 6 LAYER ONLY; TP ONLY
A CPU_CORE_HF_CLKOUT_DP 6 LAYER ONLY; TP ONLY
A
CPU_EXT_CLK_EN 6 LAYER ONLY; TP ONLY, INTERNAL PULLDN
CPU_DLL_SNIF_OUT 6 LAYER ONLY; TP ONLY
CPU_VDDS0_DP 6 LAYER ONLY
CPU_VDDS0_DN 6 LAYER ONLY
CPU_VDDS1_DP 6 LAYER ONLY
CPU_VDDS1_DN 6 LAYER ONLY
RESISTOR0_DP 6 LAYER ONLY
RESISTOR0_DN 6 LAYER ONLY
MICROSOFT PROJECT NAME PAGE FAB REV
[PAGE_TITLE=GCPU SETUP] EDRAM_PSRO_DOUT 6 LAYER ONLY DRAWING
Wed Feb 10 16:23:24 2010 CONFIDENTIAL
TRINITY_XDK 2/81 G 1.01

8 7 6 5 4 3 2 1
 CR-3 : @TRINITY_LIB.TRINITY(SCH_1):PAGE3

8 7 6 5 4 3 2 1
GCPU, DEBUG BUS

D D

U5E1 15 of 17 IC
1CPU_DLL_SNIF_OUT_TP
FT5T2 FTP GCPU VERSION 1
B9
CPU_DBG<0..10> OUT 3
CPU_DLL_SNIF_OUT W6 TB15_GPUCLK1
OUT DLL_SNIF_OUT D7
TB14_GPUCLK0
TB13_CPUCLK1 E8
OUT CPU_DBG_TBCLK1 B5 TBCLK1 D6
CPU_DBG_TBCLK0 A4 TB12_CPUCLK0
OUT TBCLK0 D9
TB11_GPU_HB
1 TB10_RESET2 C8 10
FT5P1 FTP
1 TB9_RESET1 A8 9
FT5P2 FTP
TB8_RESET0 D8 8
TB7_POST_OUT7 C5 7
B27 SPARE7
TB6_POST_OUT6 A5 6
H6 SPARE6
TB5_POST_OUT5 B6 5
J4 SPARE5
TB4_POST_OUT4 C6 4
K7 SPARE4
TB3_POST_OUT3 A6 3
L4 SPARE3
TB2_POST_OUT2 C7 2
AJ30 SPARE2 ALL POST IN'S HAVE INTERNAL PULLUPS
TB1_POST_OUT1 A7 1
AP26 SPARE1 B8 0
C AP7 SPARE0
TB0_POST_OUT0
POST_IN<0..4>
4 3 2 1 0 C
<UP>POST_IN4 F6 4
<UP>POST_IN3 G6 3
<UP>POST_IN2 G5 2
<UP>POST_IN1 F5 1
<UP>POST_IN0 H5 0
R4R5 1 R4R3 1 R4R8 1 R4R6 1 R4R13 1
X818336-001 BGA_2 200 OHM 200 OHM 200 OHM 200 OHM 200 OHM
5% 5% 5% 5% 5%
EMPTY 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY 2
402 402 402 402 402
1 4
FT4R6 FTP
1 3
FT4R4 FTP
1 2
FT4R8 FTP
1 1
FT4R7 FTP
1 0
FT4R9 FTP

B B

CPU_DBG<0..10>
3 IN CPU_DBG15_GPUCLK1_TP 1
FTP FT5R9
CPU_DBG14_GPUCLK0_TP 1
FTP FT5R12
CPU_DBG13_CPUCLK1_TP 1
FTP FT5R13
CPU_DBG12_CPUCLK0_TP 1
FTP FT5R11
CPU_DBG11_GPU_HB_TP 1
FTP FT5R16
10 CPU_DBG10_RST2 1
FTP FT5R15
9 CPU_DBG9_RST1 1
FTP FT5R10
8 CPU_DBG8_RST0 1
FTP FT5R14
7 CPU_DBG7_POST7 1
FTP FT5R1
6 CPU_DBG6_POST6 1
FTP FT5R2
5 CPU_DBG5_POST5 1
FTP FT5R3
4 CPU_DBG4_POST4 1
FTP FT5R4
3 CPU_DBG3_POST3 1
FTP FT5R5
2 CPU_DBG2_POST2 1
FTP FT5R6
1 CPU_DBG1_POST1 1
FTP FT5R7
0 CPU_DBG0_POST0 1
FTP FT5R8
A A

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=GCPU, DEBUG BUS] DRAWING
Wed Feb 10 16:23:24 2010 CONFIDENTIAL
TRINITY_XDK 3/81 G 1.01

8 7 6 5 4 3 2 1
 CR-4 : @TRINITY_LIB.TRINITY(SCH_1):PAGE4

8 7 6 5 4 3 2 1

GCPU, VIDEO + PCIEX

D GPU_CLK_DP 1
R4E1
2 C4E1
D
22 IN 0.1 UF 10%
0 OHM 5% 6.3 V U5E1 5 OF 17 IC 1
402 CH X5R FTP FT3R16
402 GCPU VERSION 1
GPU_CLK_DP_C 1 2 GPU_CLK_DP_R2 R2 NB_CLK_DP RST_DONE U6 GPU_RST_DONE 27
OUT OUT
R4E2 C5E2
PEX_TX1_DP U2 PEX_GPU_SB_L1_DP_C 1 2 PEX_GPU_SB_L1_DP 26
22 GPU_CLK_DN 1 2 1 2 GPU_CLK_DN_R2 R1 NB_CLK_DN OUT
IN
0 OHM 5% 0.1 UF 10%
402 CH C4E2 6.3 V
0.1 UF 10% X5R C5E1 PEX_GPU_SB_L1_DN
GPU_CLK_DN_C 6.3 V PEX_TX1_DN U1 PEX_GPU_SB_L1_DN_C 402 1 2 26
OUT X5R OUT
402 0.1 UF 10%
FT3R17 FTP
1 6.3 V
C5E4 X5R
27 GPU_RST_N D2 RST_IN_N* PEX_TX0_DP W2 PEX_GPU_SB_L0_DP_C 1 2 402 PEX_GPU_SB_L0_DP 26
IN OUT
PEX_SB_GPU_L1_DP T2 0.1 UF 10%
26 IN PEX_RX1_DP 6.3 V
26 IN PEX_SB_GPU_L1_DN T1 PEX_RX1_DN X5R C5E3
26 PEX_SB_GPU_L0_DP V2 PEX_RX0_DP PEX_TX0_DN W1 PEX_GPU_SB_L0_DN_C 402 1 2 PEX_GPU_SB_L0_DN 26
IN PEX_SB_GPU_L0_DN V1
OUT
26 IN PEX_RX0_DN
0.1 UF 10%
6.3 V
X5R
C 22 IN HANA_PIX_CLK_2X_DP N1 PIX_CLK_IN_DP J2
402 GPU_PIX_CLK_1X C
HANA_PIX_CLK_2X_DN N2 PIX_CLK_OUT OUT 23
22 IN PIX_CLK_IN_DN
PEX_RCAL V3 PEX_RCAL
2 R5T1 F2 14
PIX_DATA<14..0> OUT 23
PIX_DATA14
4.99 KOHM PIX_DATA13 F1 13
1% F3 12
PIX_DATA12
1 CH PIX_DATA11 G2 11
402
PIX_DATA10 G1 10
23 IN GPU_TEMP_P P4 NB_THERMD_P PIX_DATA9 H3 9
PIX_DATA8 H2 8
1 C4C2 PIX_DATA7 H1 7
100 PF PIX_DATA6 J1 6
5% PIX_DATA5 K3 5
2 50 V
EMPTY PIX_DATA4 K2 4
23 61 OUT GPU_TEMP_N 402 P3 NB_THERMD_N PIX_DATA3 K1 3
PIX_DATA2 L2 2
23 IN EDRAM_TEMP_P V4 ED_THERMD_P PIX_DATA1 L1 1
PIX_DATA0 M3 0
1 C4C6
100 PF VSYNC_OUT M1 GPU_VSYNC_OUT OUT 23
5% HSYNC_OUT M2 GPU_HSYNC_OUT OUT 23
B EDRAM_TEMP_N
2 50 V
EMPTY
402 V5 B
23 61 OUT ED_THERMD_N

23 IN CPU_TEMP_P M5 CPU_THERMD_P
1 C4C7
100 PF
5%
2 50 V
EMPTY
23 61 OUT CPU_TEMP_N 402 L5 CPU_THERMD_N

MEM_RST AD27 MEM_RST OUT 14 15 16 17 18 19 20 21

MEM_SCAN_EN AB33 MEM_SCAN_EN OUT 14 15 16 17 18 19 20 21
MEM_CALA W27 MEM_CALA MEM_SCAN_OEN_A AF7 MEM_SCAN_TOP_EN OUT 14 16 18 20
MEM_CALB AG18 MEM_CALB MEM_SCAN_OEN_B AE7

2 R6T6 1 R7T7 1 R7R6 2 R6F6 2 R7E2

2 R6T3 X818336-001 BGA_2 1 KOHM 1 KOHM 1 KOHM 1 KOHM
240 OHM 5% 5% 5% 5%
240 OHM 1%
1%
1 CH 2 CH 2 CH 1 CH 1 CH
1 CH 402 402 402 402
402
402

VIDEO DECOUPLING V_MEM

V_MEM
U5U2 IC

A 5 VCC
74LVC1G06
A
C5T36 MEM_SCAN_BOT_EN_N 2 A Y 4 MEM_SCAN_BOT_EN 15 17 19 21
0.1 UF 1 DNU OUT
10%
6.3 V R5U6 1
X5R 1 KOHM 3 GND
402 5%
CH 2
402 X801851-001

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=GCPU, VIDEO + PCIEX] DRAWING
Wed Feb 10 16:23:24 2010 CONFIDENTIAL
TRINITY_XDK 4/81 G 1.01

8 7 6 5 4 3 2 1
 CR-5 : @TRINITY_LIB.TRINITY(SCH_1):PAGE5

8 7 6 5 4 3 2 1
GCPU, EEPROM + JTAG

D D

V_MEM
1
FT4P8 FTP
1 V_MEM
FT4P6 FTP
1
2 R4R2
FT4P5 FTP 100 OHM
1 5%
FT4P4 FTP U5E1 17 of 17 IC
1 1 EMPTY V_MEM
FT4P7 FTP DB4R1
GCPU VERSION 1 402
TP 2 R4R12
60 OUT CPU_TCLK C2 CPU_TCLK<UP> <DN>SROM_EN E3 GPU_SROM_EN 1 10 KOHM V_MEM
CPU_TDO B1 5%
60 OUT CPU_TDO<UP>
C CPU_TDI B2 1 CH
60
60
OUT
OUT CPU_TMS B4
CPU_TDI<UP>
CPU_TMS<UP>
402
EMPTY
C
CPU_TRST_N A2 U4R2
60 OUT CPU_TRST_B<UP> R4R9 AT25020A
<DN>SROM_SCLK D3 GPU_SROM_SCLK 1 2 6 SCK
R4P9 1 KOHM 5%
60 OUT CPU_TRST_N_R 1 2
402 CH
5% 0 OHM 1 R4C3 R4R11 VCC 8
CH 402 200 OHM <DN>SROM_SI E1 GPU_SROM_SO 1 2 5 SDI
5% 1 KOHM 5% 2
CH SDO 1 C4R4
2 EMPTY 402
R4R7 7 HOLD_N*
V_MEM V_MEM 402
D1 1 2 1 0.1 UF
<UP>SROM_CS GPU_SROM_CS CS_N* 10%
3 4
1 KOHM 5%
402 CH
WP_N* GND
2 6.3
X5R
V
1 R4C8 1 R4C5 402
1 100 OHM 100 OHM X800552-001
FT4P2 FTP 5% 5%
2 EMPTY 2 EMPTY <DN>SROM_SO E2
60 OUT GPU_TRST_N 402 402 R6 GPU_TRST_B<DN>
60 OUT GPU_TRST_ED_N U5 GPU_TRST_ED_B<DN> 1 R4R10
10 KOHM
FT4P1 FTP
1
1 C4C8 5% GPU_SROM_CLK_R IN 60
X818336-001 BGA_2 2 EMPTY GPU_SROM_SO_R IN 60
0.01 UF 402 GPU_SROM_CS_N_R 60
10%
GPU_SROM_WP_N IN
16 V IN 60
B 2 EMPTY GPU_SROM_SI
402 OUT 60
B

A A

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=GCPU, EEPROM + JTAG] DRAWING
Wed Feb 10 16:23:24 2010 CONFIDENTIAL
TRINITY_XDK 5/81 G 1.01

8 7 6 5 4 3 2 1
 CR-6 : @TRINITY_LIB.TRINITY(SCH_1):PAGE6

8 7 6 5 4 3 2 1
GCPU, PLL POWER + FSB POWER
V_GPUPCIE V_CPUEDRAM V_CPUPLL V_EFUSE U5E1 16 of 17 IC
GCPU VERSION 1
E4 VDDE CORE_HF_CLKOUT_DP L6 CPU_CORE_HF_CLKOUT_DP OUT
D CPU_VDDS1_DP H25
CORE_HF_CLKOUT_DN K6 CPU_CORE_HF_CLKOUT_DN OUT D
OUT VDDS1_DP
OUT CPU_VDDS1_DN J26 VDDS1_DN

OUT CPU_VDDS0_DP P7 VDDS0_DP

OUT CPU_VDDS0_DN N7 VDDS0_DN
FB5R1
1 2 V_CPU_PVDDA_MEM D4 PVDDA_MEM
FB 1 C5R14
0.2A 603 10 UF
0.5 DCR 20%
6.3 V
ST5R1 X5R
1 2 2 805 V_CPU_PVSSA_MEM C4 PVSSA_MEM
SHORT
FB5T2
1 2 V_CPU_PVDDA_PEX U3 PVDDA_PEX
FB 1 C5T9
0.2A 603 10 UF
0.5 DCR 20%
6.3 V
ST5T1 X5R
1 22 805 V_CPU_PVSSA_PEX U4 PVSSA_PEX
C SHORT C
FB5R2
1 2 V_CPU_PVDDA_HS C3 PVDDA_HS
FB 1 C5R17
0.2A 603 10 UF
0.5 DCR 20%
6.3 V
ST5R2 X5R
1 2 2 805 V_CPU_PVSSA_HS B3 PVSSA_HS
SHORT
FB5T3
1 2 V_CPU_PVDDA_ED W5 PVDDA_ED
FB 1 C5T13
0.2A 603
0.5 DCR 4.7 UF
10%
6.3 V
ST5T2 2 X5R
1 2 805 V_CPU_PVSSA_ED W4 PVSSA_ED
SHORT 1
DB5R5
FB5R5
B 1 2 V_CPU_VDDA_RNG N4 VDDA_RNG
B
0.2A
FB
603
1 C5R54
10 UF
0.5 DCR 20%
6.3 V
ST5R5 X5R
1 2 2 805 V_CPU_GNDA_RNG N3 GNDA_RNG
SHORT
FB5R4
1 2 V_CPU_CORE_HF_VDDA_PLL J5 CORE_HF_VDDA_PLL
FB 1 C5R42
0.2A 603 10 UF
0.5 DCR 20%
6.3 V
ST5R4 X5R
1 2 2 805 V_CPU_CORE_HF_GNDA_PLL K5 CORE_HF_GNDA_PLL
SHORT
FB5R3
1 2 V_GPU_VDDA_PLL G4 GPU_VDDA_PLL
FB
0.2A 603 1 C5R31
0.5 DCR
10 UF
20%
6.3 V
ST5R3 2 X5R
1 2 805 V_GPU_GNDA_PLL H4 GPU_GNDA_PLL
SHORT
A R3
A
VDD_VTT

FB5T1
1 2 V_CPU_VDD_VTTA R4 VDD_VTTA
FB
0.2A 603 1 C5T4 1 C5T6
0.5 DCR X818336-001 BGA_2
4.7 UF 0.1 UF
10% 10%
2 6.3 V
2 6.3 V
MICROSOFT PROJECT NAME PAGE FAB REV
X5R X5R DRAWING
[PAGE_TITLE=GCPU, PLL POWER + FSB POWER] 805 402
Wed Feb 10 16:23:24 2010 CONFIDENTIAL
TRINITY_XDK 6/81 G 1.01

8 7 6 5 4 3 2 1
 CR-7 : @TRINITY_LIB.TRINITY(SCH_1):PAGE7

8 7 6 5 4 3 2 1
GCPU, POWER

D D

V_CPUVCS V_CPUVCS V_MEM V_MEM V_CPUCORE V_CPUCORE V_CPUCORE V_CPUCORE

U5E1 8 OF 17 IC U5E1 10 OF 17 IC
U5E1 9 OF 17 IC
U5E1 6 OF 17 IC
GCPU VERSION 1 GCPU VERSION 1
GCPU VERSION 1 A21 H16
GCPU VERSION 1 R23 Y12 VDD_CORE189 VDD_CORE143
A11 V_CS20 F10 A33 AG23 VDD_CORE91 VDD_CORE45 A19 H14
V_CS28 V_MEM111 V_MEM56 R21 AA25 VDD_CORE188 VDD_CORE142
A9 V_CS19 G11 B34 AG20 VDD_CORE90 VDD_CORE44 A17 H12
V_CS27 V_MEM110 V_MEM55 R19 AA23 VDD_CORE187 VDD_CORE141
B10 V_CS18 G9 C31 AG17 VDD_CORE89 VDD_CORE43 A15 J25
V_CS26 V_MEM109 V_MEM54 R17 AA21 VDD_CORE186 VDD_CORE140
C11 V_CS17 H10 C29 AG15 VDD_CORE88 VDD_CORE42 A13 J23
V_CS25 V_MEM108 V_MEM53 R15 AA19 VDD_CORE185 VDD_CORE139
C9 V_CS16 H8 C27 AG13 VDD_CORE87 VDD_CORE41 B22 J21
V_CS24 V_MEM107 V_MEM52 R13 AA17 VDD_CORE184 VDD_CORE138
C D10
E11
V_CS23 V_CS15 J9
K10
D32
D30
V_MEM106 V_MEM51 AG10
AG7 R11
VDD_CORE86
VDD_CORE85
VDD_CORE40
VDD_CORE39 AA15
B20
B18
VDD_CORE183 VDD_CORE137 J19
J17 C
V_CS22 V_CS14 V_MEM105 V_MEM50 T26 AA13 VDD_CORE182 VDD_CORE136
E9 V_CS13 K8 D28 AG4 VDD_CORE84 VDD_CORE38 B16 J15
V_CS21 V_MEM104 V_MEM49 T24 AB26 VDD_CORE181 VDD_CORE135
V_CS12 L9 D25 AH32 VDD_CORE83 VDD_CORE37 B14 J13
V_MEM103 V_MEM48 T22 AB24 VDD_CORE180 VDD_CORE134
V_CS11 M10 E31 AH29 VDD_CORE82 VDD_CORE36 B12 J11
V_MEM102 V_MEM47 T20 AB22 VDD_CORE179 VDD_CORE133
V_CS10 M8 E26 AH27 VDD_CORE81 VDD_CORE35 C21 K26
V_MEM101 V_MEM46 T18 AB20 VDD_CORE178 VDD_CORE132
V_CS9 N9 F32 AH24 VDD_CORE80 VDD_CORE34 C19 K24
V_MEM100 V_MEM45 T16 AB18 VDD_CORE177 VDD_CORE131
V_CS8 P10 F28 AH19 VDD_CORE79 VDD_CORE33 C17 K22
V_MEM99 V_MEM44 T14 AB16 VDD_CORE176 VDD_CORE130
V_CS7 P8 G31 AH14 VDD_CORE78 VDD_CORE32 C15 K20
V_MEM98 V_MEM43 T12 AB14 VDD_CORE175 VDD_CORE129
V_CS6 R9 G29 AH9 VDD_CORE77 VDD_CORE31 C13 K18
V_MEM97 V_MEM42 U25 AB12 VDD_CORE174 VDD_CORE128
V_CS5 T10 G27 AH8 VDD_CORE76 VDD_CORE30 D24 K16
V_MEM96 V_MEM41 U23 AC25 VDD_CORE173 VDD_CORE127
V_CS4 T8 G25 AH6 VDD_CORE75 VDD_CORE29 D22 K14
V_MEM95 V_MEM40 U21 AC23 VDD_CORE172 VDD_CORE126
V_CS3 U9 H32 AH3 VDD_CORE74 VDD_CORE28 D20 K12
V_MEM94 V_MEM39 U19 AC21 VDD_CORE171 VDD_CORE125
V_CS2 V10 H28 AJ31 VDD_CORE73 VDD_CORE27 D18 L25
V_MEM93 V_MEM38 U17 AC19 VDD_CORE170 VDD_CORE124
V_CS1 V8 H26 AJ28 VDD_CORE72 VDD_CORE26 D16 L23
V_MEM92 V_MEM37 U15 AC17 VDD_CORE169 VDD_CORE123
V_CS0 W9 J32 AJ26 VDD_CORE71 VDD_CORE25 D14 L21
V_MEM91 V_MEM36 U13 AC15 VDD_CORE168 VDD_CORE122
J29 AJ22 VDD_CORE70 VDD_CORE24 D12 L19
V_MEM90 V_MEM35 U11 AC13 VDD_CORE167 VDD_CORE121
K27 AJ21 VDD_CORE69 VDD_CORE23 E23 L17
X818336-001 BGA_2 V_MEM89 V_MEM34 V26 AD26 VDD_CORE166 VDD_CORE120
L31 AJ16 VDD_CORE68 VDD_CORE22 E21 L15
V_MEM88 V_MEM33 V24 AD24 VDD_CORE165 VDD_CORE119
L28 AJ12 VDD_CORE67 VDD_CORE21 E19 L13
V_MEM87 V_MEM32 V22 AD22 VDD_CORE164 VDD_CORE118
M30 AJ11 VDD_CORE66 VDD_CORE20 E17 L11
V_MEM86 V_MEM31 V20 AD20 VDD_CORE163 VDD_CORE117
M27 AJ7 VDD_CORE65 VDD_CORE19 E15 M26
V_MEM85 V_MEM30 V18 AD18 VDD_CORE162 VDD_CORE116
N29 AJ4 VDD_CORE64 VDD_CORE18 E13 M24
B V_CPUEDRAM V_CPUEDRAM P31
V_MEM84
V_MEM83
V_MEM29
V_MEM28 AK32 V16
V14
VDD_CORE63 VDD_CORE17 AD16
AD14
F24
VDD_CORE161
VDD_CORE160
VDD_CORE115
VDD_CORE114 M22 B
P29 AK23 VDD_CORE62 VDD_CORE16 F22 M20
V_MEM82 V_MEM27 V12 AD12 VDD_CORE159 VDD_CORE113
U5E1 7 OF 17 IC R27 AK13 VDD_CORE61 VDD_CORE15 F20 M18
V_MEM81 V_MEM26 W25 AE25 VDD_CORE158 VDD_CORE112
T32 AK3 VDD_CORE60 VDD_CORE14 F18 M16
GCPU VERSION 1 V_MEM80 V_MEM25 W23 AE23 VDD_CORE157 VDD_CORE111
R7 AB6 T28 AL31 VDD_CORE59 VDD_CORE13 F16 M14
V_EDRAM47 V_EDRAM23 V_MEM79 V_MEM24 W21 AE21 VDD_CORE156 VDD_CORE110
T6 AB4 V31 AL29 VDD_CORE58 VDD_CORE12 F14 M12
V_EDRAM46 V_EDRAM22 V_MEM78 V_MEM23 W19 AE19 VDD_CORE155 VDD_CORE109
U7 AB2 V27 AL27 VDD_CORE57 VDD_CORE11 F12 N25
V_EDRAM45 V_EDRAM21 V_MEM77 V_MEM22 W17 AE17 VDD_CORE154 VDD_CORE108
W7 AC11 W32 AL24 VDD_CORE56 VDD_CORE10 G23 N23
V_EDRAM44 V_EDRAM20 V_MEM76 V_MEM21 W15 AE15 VDD_CORE153 VDD_CORE107
Y11 AC10 W29 AL21 VDD_CORE55 VDD_CORE9 G21 N21
V_EDRAM43 V_EDRAM19 V_MEM75 V_MEM20 W13 AE13 VDD_CORE152 VDD_CORE106
Y10 AC9 Y27 AL17 VDD_CORE54 VDD_CORE8 G19 N19
V_EDRAM42 V_EDRAM18 V_MEM74 V_MEM19 W11 AF26 VDD_CORE151 VDD_CORE105
Y8 AC8 AA31 AL14 VDD_CORE53 VDD_CORE7 G17 N17
V_EDRAM41 V_EDRAM17 V_MEM73 V_MEM18 Y26 AF24 VDD_CORE150 VDD_CORE104
Y6 AC7 AA28 AL11 VDD_CORE52 VDD_CORE6 G15 N15
V_EDRAM40 V_EDRAM16 V_MEM72 V_MEM17 Y24 AF22 VDD_CORE149 VDD_CORE103
Y4 AC6 AB30 AL8 VDD_CORE51 VDD_CORE5 G13 N13
V_EDRAM39 V_EDRAM15 V_MEM71 V_MEM16 Y22 AF20 VDD_CORE148 VDD_CORE102
Y2 AC5 AB27 AL6 VDD_CORE50 VDD_CORE4 H24 N11
V_EDRAM38 V_EDRAM14 V_MEM70 V_MEM15 Y20 AF18 VDD_CORE147 VDD_CORE101
Y1 AC4 AC29 AL4 VDD_CORE49 VDD_CORE3 H22 P26
V_EDRAM37 V_EDRAM13 V_MEM69 V_MEM14 Y18 AF16 VDD_CORE146 VDD_CORE100
AA11 AC3 AD31 AM34 VDD_CORE48 VDD_CORE2 H20 P24
V_EDRAM36 V_EDRAM12 V_MEM68 V_MEM13 Y16 AF14 VDD_CORE145 VDD_CORE99
AA10 AC2 AD29 AM30 VDD_CORE47 VDD_CORE1 H18 P22
V_EDRAM35 V_EDRAM11 V_MEM67 V_MEM12 Y14 AF12 VDD_CORE144 VDD_CORE98
AA9 AC1 AE8 AM28 VDD_CORE46 VDD_CORE0 P20
V_EDRAM34 V_EDRAM10 V_MEM66 V_MEM11 VDD_CORE97
AA8 V_EDRAM33 V_EDRAM9 AD11 AE4 V_MEM65 V_MEM10 AM26 VDD_CORE96 P18
AA7 AD10 AF32 AM19 X818336-001 BGA_2 P16
V_EDRAM32 V_EDRAM8 V_MEM64 V_MEM9 VDD_CORE95
AA6 V_EDRAM31 V_EDRAM7 AD8 AF28 V_MEM63 V_MEM8 AM16 VDD_CORE94 P14
AA5 V_EDRAM30 V_EDRAM6 AD6 AF27 V_MEM62 V_MEM7 AM9 VDD_CORE93 P12
AA4 V_EDRAM29 V_EDRAM5 AD4 AF6 V_MEM61 V_MEM6 AM7 VDD_CORE92 R25
AA3 V_EDRAM28 V_EDRAM4 AD2 AF3 V_MEM60 V_MEM5 AM5
AA2 V_EDRAM27 V_EDRAM3 AD1 AG31 V_MEM59 V_MEM4 AM3 X818336-001 BGA_2
AA1 V_EDRAM26 V_EDRAM2 AE11 AG28 V_MEM58 V_MEM3 AN33
AB10 V_EDRAM25 V_EDRAM1 AE9 AG25 V_MEM57 V_MEM2 AN1
AB8 V_EDRAM24 V_EDRAM0 AF10 V_MEM1 AP34
A V_MEM0 AP2 A
X818336-001 BGA_2
X818336-001 BGA_2

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=GCPU, POWER] DRAWING
Wed Feb 10 16:23:25 2010 CONFIDENTIAL
TRINITY_XDK 7/81 G 1.01

8 7 6 5 4 3 2 1
 CR-8 : @TRINITY_LIB.TRINITY(SCH_1):PAGE8

8 7 6 5 4 3 2 1
GCPU, POWER

D D
U5E1 11 OF 17 IC
U5E1 12 OF 17 IC
GCPU VERSION 1
AF15 GCPU VERSION 1
VSS65 K29 R16
Y3 AF13 VSS260 VSS195
VSS130 VSS64 K25 R14
AA32 AF11 VSS259 VSS194 U5E1 13 OF 17 IC
VSS129 VSS63 K23 R12
AA27 AF9 VSS258 VSS193
VSS128 VSS62 K21 R10 GCPU VERSION 1
AA26 AF8 VSS257 VSS192 A34 E24
VSS127 VSS61 K19 R8 VSS354 VSS318
AA24 AF4 VSS256 VSS191 A22 E22
VSS126 VSS60 K17 T31 VSS353 VSS317
AA22 AG32 VSS255 VSS190 A20 E20
VSS125 VSS59 K15 T27 VSS352 VSS316
AA20 AG29 VSS254 VSS189 A18 E18
VSS124 VSS58 K13 T25 VSS351 VSS315
AA18 AG27 VSS253 VSS188 A16 E16
VSS123 VSS57 K11 T23 VSS350 VSS314
AA16 AG26 VSS252 VSS187 A14 E14
VSS122 VSS56 K9 T21 VSS349 VSS313
AA14 AG24 VSS251 VSS186 A12 E12
VSS121 VSS55 K4 T19 VSS348 VSS312
AA12 AG22 VSS250 VSS185 A10 E10
VSS120 VSS54 L32 T17 VSS347 VSS311
AB25 AG21 VSS249 VSS184 B33 E6
VSS119 VSS53 L27 T15 VSS346 VSS310
AB23 AG19 VSS248 VSS183 B21 F31
VSS118 VSS52 L26 T13 VSS345 VSS309
AB21 AG16 VSS247 VSS182 B19 F29
VSS117 VSS51 L24 T11 VSS344 VSS308
AB19 AG14 VSS246 VSS181 B17 F27
VSS116 VSS50 L22 T9 VSS343 VSS307
AB17 AG12 VSS245 VSS180 B15 F23
VSS115 VSS49 L20 T7 VSS342 VSS306
AB15 AG11 VSS244 VSS179 B13 F21
VSS114 VSS48 L18 T4 VSS341 VSS305
AB13 AG9 VSS243 VSS178 B11 F19
VSS113 VSS47 L16 T3 VSS340 VSS304
AB11 AG8 VSS242 VSS177 B7 F17
VSS112 VSS46 L14 U30 VSS339 VSS303
C AB9
AB7
VSS111 VSS45 AG6
AG3 L12
VSS241
VSS240
VSS176
VSS175 U27
C28
C25
VSS338 VSS302 F15
F13 C
VSS110 VSS44 L10 U26 VSS337 VSS301
AB5 AH31 VSS239 VSS174 C22 F11
VSS109 VSS43 L8 U24 VSS336 VSS300
AB3 AH28 VSS238 VSS173 C20 F9
VSS108 VSS42 L3 U22 VSS335 VSS299
AB1 AH7 VSS237 VSS172 C18 F4
VSS107 VSS41 M25 U20 VSS334 VSS298
AC31 AH4 VSS236 VSS171 C16 G32
VSS106 VSS40 M23 U18 VSS333 VSS297
AC27 AJ32 VSS235 VSS170 C14 G28
VSS105 VSS39 M21 U16 VSS332 VSS296
AC26 AJ29 VSS234 VSS169 C12 G24
VSS104 VSS38 M19 U14 VSS331 VSS295
AC24 AJ27 VSS233 VSS168 C10 G22
VSS103 VSS37 M17 U12 VSS330 VSS294
AC22 AJ25 VSS232 VSS167 D31 G20
VSS102 VSS36 M15 U10 VSS329 VSS293
AC20 AJ20 VSS231 VSS166 D29 G18
VSS101 VSS35 M13 U8 VSS328 VSS292
AC18 AJ17 VSS230 VSS165 D27 G16
VSS100 VSS34 M11 V29 VSS327 VSS291
AC16 AJ15 VSS229 VSS164 D23 G14
VSS99 VSS33 M9 V25 VSS326 VSS290
AC14 AJ10 VSS228 VSS163 D21 G12
VSS98 VSS32 M4 V23 VSS325 VSS289
AC12 AJ8 VSS227 VSS162 D19 G10
VSS97 VSS31 N31 V21 VSS324 VSS288
AD32 AJ6 VSS226 VSS161 D17 G8
VSS96 VSS30 N27 V19 VSS323 VSS287
AD25 AJ3 VSS225 VSS160 D15 G3
VSS95 VSS29 N26 V17 VSS322 VSS286
AD23 AK31 VSS224 VSS159 D13 H31
VSS94 VSS28 N24 V15 VSS321 VSS285
AD21 AK18 VSS223 VSS158 D11 H29
VSS93 VSS27 N22 V13 VSS320 VSS284
AD19 AK4 VSS222 VSS157 E32 H27
VSS92 VSS26 N20 V11 VSS319 VSS283
AD17 AL32 VSS221 VSS156 H23
VSS91 VSS25 N18 V9 VSS282
AD15 AL30 VSS220 VSS155 H21
VSS90 VSS24 N16 V7 VSS281
AD13 AL28 VSS219 VSS154 H19
B AD9
VSS89
VSS88
VSS23
VSS22 AL26 N14
N12
VSS218 VSS153 W31
W26
VSS280
VSS279 H17 B
AD7 AL22 VSS217 VSS152 H15
VSS87 VSS21 N10 W24 VSS278
AD5 AL19 VSS216 VSS151 H13
VSS86 VSS20 N8 W22 VSS277
AD3 AL16 VSS215 VSS150 H11
VSS85 VSS19 N5 W20 VSS276
AE29 AL12 VSS214 VSS149 H9
VSS84 VSS18 P32 W18 VSS275
AE27 AL9 VSS213 VSS148 H7
VSS83 VSS17 P27 W16 VSS274
AE26 AL7 VSS212 VSS147 J31
VSS82 VSS16 P25 W14 VSS273
AE24 AL5 VSS211 VSS146 J27
VSS81 VSS15 P23 W12 VSS272
AE22 AL3 VSS210 VSS145 J24
VSS80 VSS14 P21 W10 VSS271
AE20 AM33 VSS209 VSS144 J22
VSS79 VSS13 P19 W8 VSS270
AE18 AM31 VSS208 VSS143 J20
VSS78 VSS12 P17 W3 VSS269
AE16 AM29 VSS207 VSS142 J18
VSS77 VSS11 P15 Y29 VSS268
AE14 AM27 VSS206 VSS141 J16
VSS76 VSS10 P13 Y25 VSS267
AE12 AM24 VSS205 VSS140 J14
VSS75 VSS9 P11 Y23 VSS266
AE10 AM21 VSS204 VSS139 J12
VSS74 VSS8 P9 Y21 VSS265
AE6 AM14 VSS203 VSS138 J10
VSS73 VSS7 P6 Y19 VSS264
AE3 AM11 VSS202 VSS137 J8
VSS72 VSS6 R29 Y17 VSS263
AF31 AM8 VSS201 VSS136 J3
VSS71 VSS5 R26 Y15 VSS261
AF25 AM6 VSS200 VSS135
VSS70 VSS4 R24 Y13
AF23 AM4 VSS199 VSS134
VSS69 VSS3 R22 Y9
AF21 AN34 VSS198 VSS133 X818336-001 BGA_2
VSS68 VSS2 R20 Y7
AF19 AP33 VSS197 VSS132
VSS67 VSS1 R18 Y5
AF17 AP1 VSS196 VSS131
VSS66 VSS0
X818336-001 BGA_2
X818336-001 BGA_2

A A

MICROSOFT PROJECT NAME PAGE FAB REV

DRAWING
[PAGE_TITLE=GCPU, POWER] Wed Feb 10 16:23:25 2010 CONFIDENTIAL
TRINITY_XDK 8/81 G 1.01

8 7 6 5 4 3 2 1
 CR-9 : @TRINITY_LIB.TRINITY(SCH_1):PAGE9

8 7 6 5 4 3 2 1
GCPU, DECOUPLING
V_CPUCORE V_CPUEDRAM V_CPUVCS
D D

C6R4 C5D13 C5R8 C5R9 C5T26 C5E6 C5R35 C5D1

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

4.7 UF 10% 4.7 UF 10% 4.7 UF 10% 4.7 UF 10% 0.1 UF 10% 4.7 UF 10% 0.1 UF 10% 4.7 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R X5R X5R X5R
805 805 805 805 402 805 402 805

C5R15 C5D14 C6D3 C5D7 C5T32 C5E5 C5R58 C5R4

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

4.7 UF 10% 4.7 UF 10% 4.7 UF 10% 4.7 UF 10% 0.1 UF 10% 4.7 UF 10% 0.1 UF 10% 4.7 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R X5R X5R X5R
805 805 805 805 402 805 402 805

C5R7
C6R3 C5D3 1 2 C5D6 C5T24 C5T35 C5R43 C5D4
1 2 1 2 1 2 1 2 1 2 1 2 1 2
4.7 UF 10%
4.7 UF 10% 4.7 UF 10% 6.3 V 4.7 UF 10% 0.1 UF 10% 4.7 UF 10% 0.1 UF 10% 4.7 UF 10%
6.3 V 6.3 V X5R 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R X5R X5R
C 805 805
805
805 402 805 402 805 C
C5D5
C5R10 C5D8 C6R6 1 2 C5T31 C5E7 C5T7 C5R1
1 2 1 2 1 2 1 2 1 2 1 2 1 2
4.7 UF 10%
4.7 UF 10% 4.7 UF 10% 4.7 UF 10% 6.3 V 0.1 UF 10% 4.7 UF 10% 0.1 UF 10% 4.7 UF 10%
6.3 V 6.3 V 6.3 V X5R 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R 805 X5R X5R X5R X5R
805 805 805 402 805 402 805

C6D4
C5R6 1 2 C5D9 C5T27 C5T34 C5R50
C5D12 1 2 1 2 1 2 1 2 1 2
1 2
4.7 UF 10%
4.7 UF 10% 6.3 V 4.7 UF 10% 0.1 UF 10% 4.7 UF 10% 0.1 UF 10%
4.7 UF 10% 6.3 V X5R 6.3 V 6.3 V 6.3 V 6.3 V
6.3 V X5R 805 X5R X5R X5R X5R
X5R 805 805 402 805 402
805

C6R2 C5R5 C6R1 C5R18 C5T22 C5T43 C5T1

1 2 1 2 1 2 1 2 1 2 1 2 1 2

4.7 UF 10% 4.7 UF 10% 4.7 UF 10% 4.7 UF 10% 0.1 UF 10% 4.7 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R X5R X5R
B 805 805 805 805 402 805 402 B
C5R12 C5D2 C5R3 C5D10 C5T23 C5E8
1 2 1 2 1 2 1 2 1 2 1 2

4.7 UF 10% 4.7 UF 10% 4.7 UF 10% 4.7 UF 10% 0.1 UF 10% 4.7 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R X5R
805 805 805 805 402 805

C6D5 C5R16 C6R7 C5D11 C5T20 C5E9

1 2 1 2 1 2 1 2 1 2 1 2

4.7 UF 10% 4.7 UF 10% 4.7 UF 10% 4.7 UF 10% 0.1 UF 10% 4.7 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R X5R
805 805 805 805 402 805

C6D1 C6D2 C6D6 C5T33 C5T25 C4T3

1 2 1 2 1 2 1 2 1 2 1 2

4.7 UF 10% 4.7 UF 10% 4.7 UF 10% 4.7 UF 10% 0.1 UF 10% 4.7 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R X5R
805 805 805 805 402 805

C5R2
C6R5 C5R13 1 2 C6T22 C5T21 C4T4
1 2 1 2 1 2 1 2 1 2
4.7 UF 10%
A
4.7 UF 10%
6.3 V
X5R
4.7 UF 10%
6.3 V
X5R
6.3 V
X5R
4.7 UF 10%
6.3 V
X5R
0.1 UF 10%
6.3 V
X5R
4.7 UF 10%
6.3 V
X5R
A
805
805 805 805 402 805

C6T23
1 2

4.7 UF 10%
6.3 V
X5R
805

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=GCPU, DECOUPLING] DRAWING
Wed Feb 10 16:23:25 2010 CONFIDENTIAL
TRINITY_XDK 9/81 G 1.01

8 7 6 5 4 3 2 1
 CR-10 : @TRINITY_LIB.TRINITY(SCH_1):PAGE10

8 7 6 5 4 3 2 1
GCPU, DECOUPLING
V_CPUCORE

D D
C5T12 C5R26 C5T17 C5T10 C6R36
1 2 1 2 1 2 1 2 1 2

0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R
402 402 402 402 402

C5R33 C6R25 C6T11 C5T8 C5R63

1 2 1 2 1 2 1 2 1 2

0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R
402 402 402 402 402

C5R39 C5R60 C6R42 C6R45 C5R28

1 2 1 2 1 2 1 2 1 2

0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R
C 402 402 402 402 402
C
C5R40 C5R61 C5R37 C5R49 C5R59
1 2 1 2 1 2 1 2 1 2

0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R
402 402 402 402 402

C6T7 C6T20 C6R37 C6R33 C5R27

1 2 1 2 1 2 1 2 1 2

0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R
402 402 402 402 402

C5R38 C5R32 C5R57 C6T8 C5R62

1 2 1 2 1 2 1 2 1 2

0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R
B 402 402 402 402 402
B
C6T12 C6T6 C5R64 C6R15 C5R55
1 2 1 2 1 2 1 2 1 2

0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R
402 402 402 402 402

C6R31 C6R28 C5R46 C6R21 C5R51

1 2 1 2 1 2 1 2 1 2

0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R
402 402 402 402 402

C6R38 C5R36 C5R45 C6R20 C6R18

1 2 1 2 1 2 1 2 1 2

0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R
402 402 402 402 402

C6R43 C5T11 C6T14 C6R44 C6R17

1 2 1 2 1 2 1 2 1 2

0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
A 6.3 V
X5R
6.3 V
X5R
6.3 V
X5R
6.3 V
X5R
6.3 V
X5R A
402 402 402 402 402

MICROSOFT PROJECT NAME PAGE FAB REV

DRAWING
[PAGE_TITLE=GCPU, DECOUPLING] Wed Feb 10 16:23:25 2010 CONFIDENTIAL
TRINITY_XDK 10/81 G 1.01

8 7 6 5 4 3 2 1
 CR-11 : @TRINITY_LIB.TRINITY(SCH_1):PAGE11

8 7 6 5 4 3 2 1
GCPU, DECOUPLING
V_CPUCORE
D D

C5R25 C6R8 C6R39 C5R30 C6T5 C5T14

1 2 1 2 1 2 1 2 1 2 1 2

0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R X5R
402 402 402 402 402 402

C6T15 C6R34 C6T3 C5R52 C5R21 C6T9

1 2 1 2 1 2 1 2 1 2 1 2

0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R X5R
402 402 402 402 402 402

C5T19 C6R19 C6R35 C5T15 C5T16 C5T3

1 2 1 2 1 2 1 2 1 2 1 2

0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
C 6.3 V
X5R
6.3 V
X5R
6.3 V
X5R
6.3 V
X5R
6.3 V
X5R
6.3 V
X5R C
402 402 402 402 402 402

C6T18 C5R53 C6R22 C5T28 C6T19 C6R13

1 2 1 2 1 2 1 2 1 2 1 2

0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R X5R
402 402 402 402 402 402

C6R9 C5T30 C5R44 C5R41 C6T25 C5R34

1 2 1 2 1 2 1 2 1 2 1 2

0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R X5R
402 402 402 402 402 402

C6R10 C5T29 C5R47 C6R24 C6R12 C6R14

1 2 1 2 1 2 1 2 1 2 1 2

0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
B 6.3 V
X5R
6.3 V
X5R
6.3 V
X5R
6.3 V
X5R
6.3 V
X5R
6.3 V
X5R B
402 402 402 402 402 402

C5R20 C5R24 C5R48 C6T2 C5T2 C5T5

1 2 1 2 1 2 1 2 1 2 1 2

0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R X5R
402 402 402 402 402 402

C5R19 C5R56 C6R26 C6T16 C6T17 C6T13

1 2 1 2 1 2 1 2 1 2 1 2

0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R X5R
402 402 402 402 402 402

C5R22 C6T4 C6R32 C5T18 C6R40 C6T24

1 2 1 2 1 2 1 2 1 2 1 2

0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R X5R
402 402 402 402 402 402

C5R23 C5R29 C6R29 C6R30 C6R41

1 2 1 2 1 2 1 2 1 2

A 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10% 0.1 UF 10%
A
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R
402 402 402 402 402

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=GCPU, DECOUPLING] DRAWING
Wed Feb 10 16:23:25 2010 CONFIDENTIAL
TRINITY_XDK 11/81 G 1.01

8 7 6 5 4 3 2 1
 CR-12 : @TRINITY_LIB.TRINITY(SCH_1):PAGE12

8 7 6 5 4 3 2 1
GPU, MEMORY CONTROLLER 0 PARTITION A & B
U5E1 4 OF 17 IC U5E1 3 OF 17 IC
GCPU VERSION 1 GCPU VERSION 1
D 15 14 BI MA_DQ31
MA_DQ30
T34
T33
MA_DQ31 17 16 BI MB_DQ31
MB_DQ30
H33
G34
MB_DQ31 D
15 14 BI MA_DQ30 17 16 BI MB_DQ30
15 14 BI MA_DQ29 U31 MA_DQ29 17 16 BI MB_DQ29 H34 MB_DQ29
15 14 BI MA_DQ28 R33 MA_DQ28 17 16 BI MB_DQ28 F34 MB_DQ28
15 14 BI MA_DQ27 U33 MA_DQ27 17 16 BI MB_DQ27 K31 MB_DQ27
15 14 BI MA_DQ26 R32 MA_DQ26 17 16 BI MB_DQ26 D34 MB_DQ26
15 14 BI MA_DQ25 V33 MA_DQ25 17 16 BI MB_DQ25 K32 MB_DQ25
15 14 BI MA_DQ24 R31 MA_DQ24 17 16 BI MB_DQ24 C34 MB_DQ24
15 14 OUT MA_WDQS3 R34 MA_WDQS3 17 16 OUT MB_WDQS3 E34 MB_WDQS3
15 14 IN MA_RDQS3 U32 MA_RDQS3 17 16 IN MB_RDQS3 J33 MB_RDQS3
15 14 OUT MA_DM3 U34 MA_DM3 17 16 OUT MB_DM3 J34 MB_DM3

15 14 BI MA_DQ23 Y34 MA_DQ23 MA_CLK1_DP AE28 MA_CLK1_DP OUT 15 17 16 BI MB_DQ23 M32 MB_DQ23 MB_CLK1_DP B32 MB_CLK1_DP OUT 17
15 14 BI MA_DQ22 Y33 MA_DQ22 MA_CLK1_DN AE30 MA_CLK1_DN OUT 15 17 16 BI MB_DQ22 M34 MB_DQ22 MB_CLK1_DN A32 MB_CLK1_DN OUT 17
15 14 BI MA_DQ21 Y32 MA_DQ21 MA_CLK0_DP AC33 MA_CLK0_DP OUT 14 17 16 BI MB_DQ21 M31 MB_DQ21 MB_CLK0_DP B31 MB_CLK0_DP OUT 16
15 14 BI MA_DQ20 AA33 MA_DQ20 MA_CLK0_DN AC34 MA_CLK0_DN OUT 14 17 16 BI MB_DQ20 M33 MB_DQ20 MB_CLK0_DN A31 MB_CLK0_DN OUT 16
15 14 BI MA_DQ19 W33 MA_DQ19 17 16 BI MB_DQ19 K33 MB_DQ19
15 14 BI MA_DQ18 AB31 MA_DQ18 MA_A12 AL33 MA_A<11..0> 17 16 BI MB_DQ18 N34 MB_DQ18 MB_A12 C30
MB_A<11..0>
MA_DQ17 V34 AH34 11 OUT 14 15 MB_DQ17 K34 F25 11 OUT 16 17
15 14 BI MA_DQ17 MA_A11 17 16 BI MB_DQ17 MB_A11
15 14 BI MA_DQ16 AB32 MA_DQ16 MA_A10 AL34 10 17 16 BI MB_DQ16 P33 MB_DQ16 MB_A10 A25 10
15 14 OUT MA_WDQS2 AA34 MA_WDQS2 MA_A9 AG34 9 17 16 OUT MB_WDQS2 N33 MB_WDQS2 MB_A9 E29 9
15 14 IN MA_RDQS2 Y31 MA_RDQS2 MA_A8 AD33 8 17 16 IN MB_RDQS2 L34 MB_RDQS2 MB_A8 B30 8
15 14 OUT MA_DM2 W34 MA_DM2 MA_A7 AF34 7 17 16 OUT MB_DM2 L33 MB_DM2 MB_A7 B29 7
AE33 6 A30 6
C 15 14 BI MA_DQ15 W28 MA_DQ15
MA_A6
MA_A5 AD34 5 17 16 BI MB_DQ15 J28 MB_DQ15
MB_A6
MB_A5 C32 5 C
15 14 BI MA_DQ14 R30 MA_DQ14 MA_A4 AF33 4 17 16 BI MB_DQ14 C33 MB_DQ14 MB_A4 A29 4
15 14 BI MA_DQ13 W30 MA_DQ13 MA_A3 AG33 3 17 16 BI MB_DQ13 J30 MB_DQ13 MB_A3 E25 3
15 14 12 BI MA_DQ12 R28 MA_DQ12 MA_A2 AH33 2 17 16 12 BI MB_DQ12 D33 MB_DQ12 MB_A2 G26 2
15 14 BI MA_DQ11 V28 MA_DQ11 MA_A1 AK33 1 17 16 BI MB_DQ11 F33 MB_DQ11 MB_A1 B25 1
15 14 BI MA_DQ10 T29 MA_DQ10 MA_A0 AJ34 0 17 16 BI MB_DQ10 E33 MB_DQ10 MB_A0 F26 0
15 14 BI MA_DQ9 U29 MA_DQ9 MA_BA<2..0> 17 16 BI MB_DQ9 G30 MB_DQ9 MB_BA<2..0>
MA_DQ8 U28 AE34 2 OUT 14 15 MB_DQ8 F30 E28 2 OUT 16 17
15 14 BI MA_DQ8 MA_BA2 17 16 BI MB_DQ8 MB_BA2
15 14 12 OUT MA_WDQS1 T30 MA_WDQS1 MA_BA1 AE32 1 17 16 12 OUT MB_WDQS1 E30 MB_WDQS1 MB_BA1 B28 1
15 14 IN MA_RDQS1 V30 MA_RDQS1 MA_BA0 AK34 0 17 16 IN MB_RDQS1 G33 MB_RDQS1 MB_BA0 E27 0
15 14 OUT MA_DM1 V32 MA_DM1 17 16 OUT MB_DM1 H30 MB_DM1
MA_CKE AJ33 MA_CKE OUT 14 15 MB_CKE A27 MB_CKE OUT 16 17
15 14 BI MA_DQ7 Y30 MA_DQ7 MA_WE_N* AF29 MA_WE_N OUT 14 15 17 16 BI MB_DQ7 K30 MB_DQ7 MB_WE_N* B26 MB_WE_N OUT 16 17
15 14 BI MA_DQ6 AD28 MA_DQ6 MA_CAS_N* AG30 MA_CAS_N OUT 14 15 17 16 BI MB_DQ6 P28 MB_DQ6 MB_CAS_N* C26 MB_CAS_N OUT 16 17
15 14 BI MA_DQ5 Y28 MA_DQ5 MA_RAS_N* AH30 MA_RAS_N OUT 14 15 17 16 BI MB_DQ5 K28 MB_DQ5 MB_RAS_N* D26 MB_RAS_N OUT 16 17
15 14 12 BI MA_DQ4 AD30 MA_DQ4 MA_CS1_N* AF30 MA_CS1_N OUT 14 15 17 16 12 BI MB_DQ4 P30 MB_DQ4 MB_CS1_N* A28 MB_CS1_N OUT 16 17
15 14 BI MA_DQ3 AB28 MA_DQ3 MA_CS0_N* AE31 MA_CS0_N OUT 14 17 16 BI MB_DQ3 M28 MB_DQ3 MB_CS0_N* A26 MB_CS0_N OUT 16
15 14 BI MA_DQ2 AC30 MA_DQ2 17 16 BI MB_DQ2 N30 MB_DQ2
15 14 BI MA_DQ1 AB29 MA_DQ1 17 16 BI MB_DQ1 M29 MB_DQ1
15 14 BI MA_DQ0 AC28 MA_DQ0 17 16 BI MB_DQ0 N28 MB_DQ0
15 14 12 OUT MA_WDQS0 AC32 MA_WDQS0 17 16 12 OUT MB_WDQS0 N32 MB_WDQS0
15 14 IN MA_RDQS0 AA29 MA_RDQS0 17 16 IN MB_RDQS0 L29 MB_RDQS0
B 15 14 OUT MA_DM0 AA30 MA_DM0 17 16 OUT MB_DM0 L30 MB_DM0
B
R6T8
AB34 MA_VREF0 15 14 12 OUT MA_WDQS1 1 2 P34 MB_VREF0
4.75 KOHM 1% R6R2
X818336-001 BGA_2 402 CH X818336-001 BGA_2 MB_WDQS1 1 2
MA_DQ12 17 16 12 OUT
15 14 12 BI 4.75 KOHM 1%
402 CH
17 16 12 BI MB_DQ12
R6T7
15 14 12 BI MA_DQ4 1 2 R6R1
V_MEM 4.75 KOHM 1% 17 16 12 BI MB_DQ4 1 2
402 CH V_MEM 4.75 KOHM 1%
15 14 12 OUT MA_WDQS0 402 CH
17 16 12 OUT MB_WDQS0
1 R6T5 1 R6T2
549 OHM
1% V_MEM 549 OHM V_MEM
1%
2 EMPTY MEMORY CONTROLLER A, DECOUPLING 2 EMPTY MEMORY CONTROLLER B, DECOUPLING
402
MB_VREF0 402
MA_VREF0

1 R6T4 1 R6T1
NEED NEW VREF RESISTORS 1.27 KOHM C6T27 C6T10 C6T32 C6T29 1.27 KOHM C6R27 C6R11 C6R16 C6T30 C6R23 C6R46
1% 0.1 UF 0.1 UF 0.1 UF 1% 0.1 UF 0.1 UF 0.1 UF 4.7 UF 0.1 UF 0.1 UF
0.1 UF 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 EMPTY 10% 6.3 V 6.3 V 6.3 V 2 EMPTY 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
402 6.3 V X5R X5R X5R 402 X5R X5R X5R X5R X5R X5R
X5R 402 402 402 402 402 402 805 402 402
402

A A

TO CHANGE GPU VREF, CHANGE THESE RESISTORS TO MATCH THE TABLE

R6T4, R6T1, R5T3, R5T4

MEM VREF RESISTOR VALUE N: GPU VREF SET INTERNALLY BY DEFAULT. EXTERNAL RESISTOR DIVIDER USED TO MANUALLY SET GPU VREF VOLTAGE.
THESE ARE THE GPU VREFS NEEDED
70% 1.27KOHM
FOR VARIOUS MEMORIES. CONSULT
72% 1.40KOHM
WITH MEM TEAM FOR USAGE.
73% 1.47KOHM
74% 1.54KOHM
MICROSOFT PROJECT NAME PAGE FAB REV
[PAGE_TITLE=GPU, MEMORY CONTROLLER A + B] DRAWING
Wed Feb 10 16:23:26 2010 CONFIDENTIAL
TRINITY_XDK 12/81 G 1.01

8 7 6 5 4 3 2 1
 CR-13 : @TRINITY_LIB.TRINITY(SCH_1):PAGE13

8 7 6 5 4 3 2 1
GPU, MEMORY CONTROLLER 1 PARTITION C & D
U5E1 2 OF 17 IC U5E1 1 OF 17 IC
GCPU VERSION 1 GCPU VERSION 1
19 18 BI MC_DQ31 AP15 MC_DQ31 21 20 BI MD_DQ31 AM23 MD_DQ31
D 19 18 BI MC_DQ30
MC_DQ29
AM15
AN15
MC_DQ30 21 20 BI MD_DQ30
MD_DQ29
AL23
AP23
MD_DQ30 D
19 18 BI MC_DQ29 21 20 BI MD_DQ29
19 18 BI MC_DQ28 AL15 MC_DQ28 21 20 BI MD_DQ28 AP24 MD_DQ28
19 18 BI MC_DQ27 AL13 MC_DQ27 21 20 BI MD_DQ27 AP22 MD_DQ27
19 18 BI MC_DQ26 AN16 MC_DQ26 21 20 BI MD_DQ26 AN25 MD_DQ26
19 18 BI MC_DQ25 AM13 MC_DQ25 21 20 BI MD_DQ25 AN21 MD_DQ25
19 18 BI MC_DQ24 AP17 MC_DQ24 21 20 BI MD_DQ24 AP25 MD_DQ24
19 18 OUT MC_WDQS3 AP16 MC_WDQS3 21 20 OUT MD_WDQS3 AN24 MD_WDQS3
19 18 IN MC_RDQS3 AN14 MC_RDQS3 21 20 IN MD_RDQS3 AN23 MD_RDQS3
19 18 OUT MC_DM3 AP14 MC_DM3 21 20 OUT MD_DM3 AN22 MD_DM3

19 18 BI MC_DQ23 AP11 MC_DQ23 MC_CLK1_DP AP9 MC_CLK1_DP OUT 19 21 20 BI MD_DQ23 AN19 MD_DQ23 MD_CLK1_DP AJ24 MD_CLK1_DP OUT 21
19 18 BI MC_DQ22 AL10 MC_DQ22 MC_CLK1_DN AP8 MC_CLK1_DN OUT 19 21 20 BI MD_DQ22 AP19 MD_DQ22 MD_CLK1_DN AK24 MD_CLK1_DN OUT 21
19 18 BI MC_DQ21 AN11 MC_DQ21 MC_CLK0_DP AP6 MC_CLK0_DP OUT 18 21 20 BI MD_DQ21 AN20 MD_DQ21 MD_CLK0_DP AL25 MD_CLK0_DP OUT 20
19 18 BI MC_DQ20 AM10 MC_DQ20 MC_CLK0_DN AP5 MC_CLK0_DN OUT 18 21 20 BI MD_DQ20 AL18 MD_DQ20 MD_CLK0_DN AM25 MD_CLK0_DN OUT 20
19 18 BI MC_DQ19 AN13 MC_DQ19 21 20 BI MD_DQ19 AL20 MD_DQ19
19 18 BI MC_DQ18 AN10 MC_DQ18 MC_A12 AE1 MC_A<11..0> 21 20 BI MD_DQ18 AP18 MD_DQ18 MD_A12 AK30
MD_A<11..0>
MC_DQ17 AP13 AH1 11 OUT 18 19 MD_DQ17 AP21 AN31 11 OUT 20 21
19 18 BI MC_DQ17 MC_A11 21 20 BI MD_DQ17 MD_A11
19 18 BI MC_DQ16 AN9 MC_DQ16 MC_A10 AE2 10 21 20 BI MD_DQ16 AN18 MD_DQ16 MD_A10 AN32 10
19 18 OUT MC_WDQS2 AP10 MC_WDQS2 MC_A9 AJ2 9 21 20 OUT MD_WDQS2 AM18 MD_WDQS2 MD_A9 AK26 9
19 18 IN MC_RDQS2 AP12 MC_RDQS2 MC_A8 AP4 8 21 20 IN MD_RDQS2 AP20 MD_RDQS2 MD_A8 AK25 8
19 18 OUT MC_DM2 AN12 MC_DM2 MC_A7 AK1 7 21 20 OUT MD_DM2 AM20 MD_DM2 MD_A7 AN26 7
MC_A6 AL1 6 MD_A6 AH26 6
MC_DQ15 AJ9 AP3 5 MD_DQ15 AJ19 AH25 5
C 19
19
18
18
BI
BI MC_DQ14 AJ13
MC_DQ15
MC_DQ14
MC_A5
MC_A4 AK2 4
21 20
21 20
BI
BI MD_DQ14 AH23
MD_DQ15
MD_DQ14
MD_A5
MD_A4 AN27 4 C
19 18 BI MC_DQ13 AK9 MC_DQ13 MC_A3 AJ1 3 21 20 BI MD_DQ13 AK19 MD_DQ13 MD_A3 AP32 3
19 18 13 BI MC_DQ12 AH13 MC_DQ12 MC_A2 AH2 2 21 20 13 BI MD_DQ12 AJ23 MD_DQ12 MD_A2 AN29 2
19 18 BI MC_DQ11 AK11 MC_DQ11 MC_A1 AF1 1 21 20 BI MD_DQ11 AK21 MD_DQ11 MD_A1 AM32 1
19 18 BI MC_DQ10 AK12 MC_DQ10 MC_A0 AG2 0 21 20 BI MD_DQ10 AK22 MD_DQ10 MD_A0 AN30 0
19 18 BI MC_DQ9 AH11 MC_DQ9 MC_BA<2..0> 21 20 BI MD_DQ9 AH21 MD_DQ9 MD_BA<2..0>
MC_DQ8 AM12 AL2 2 OUT 18 19 MD_DQ8 AM22 AK27 2 OUT 20 21
19 18 BI MC_DQ8 MC_BA2 21 20 BI MD_DQ8 MD_BA2
19 18 13 OUT MC_WDQS1 AH12 MC_WDQS1 MC_BA1 AM1 1 21 20 13 OUT MD_WDQS1 AH22 MD_WDQS1 MD_BA1 AN28 1
19 18 IN MC_RDQS1 AK10 MC_RDQS1 MC_BA0 AF2 0 21 20 IN MD_RDQS1 AK20 MD_RDQS1 MD_BA0 AK29 0
19 18 OUT MC_DM1 AH10 MC_DM1 21 20 OUT MD_DM1 AH20 MD_DM1
MC_CKE AG1 MC_CKE OUT 18 19 MD_CKE AP30 MD_CKE OUT 20 21
19 18 BI MC_DQ7 AN8 MC_DQ7 MC_WE_N* AH5 MC_WE_N OUT 18 19 21 20 BI MD_DQ7 AH18 MD_DQ7 MD_WE_N* AP28 MD_WE_N OUT 20 21
19 18 BI MC_DQ6 AN2 MC_DQ6 MC_CAS_N* AG5 MC_CAS_N OUT 18 19 21 20 BI MD_DQ6 AJ14 MD_DQ6 MD_CAS_N* AP29 MD_CAS_N OUT 20 21
19 18 BI MC_DQ5 AK8 MC_DQ5 MC_RAS_N* AF5 MC_RAS_N OUT 18 19 21 20 BI MD_DQ5 AJ18 MD_DQ5 MD_RAS_N* AP31 MD_RAS_N OUT 20 21
19 18 13 BI MC_DQ4 AN3 MC_DQ4 MC_CS1_N* AJ5 MC_CS1_N OUT 18 19 21 20 BI MD_DQ4 AK14 MD_DQ4 MD_CS1_N* AK28 MD_CS1_N OUT 20 21
19 18 BI MC_DQ3 AN6 MC_DQ3 MC_CS0_N* AM2 MC_CS0_N OUT 18 21 20 BI MD_DQ3 AM17 MD_DQ3 MD_CS0_N* AP27 MD_CS0_N OUT 20
19 18 BI MC_DQ2 AK5 MC_DQ2 21 20 BI MD_DQ2 AK15 MD_DQ2
19 18 BI MC_DQ1 AK6 MC_DQ1 21 20 BI MD_DQ1 AK16 MD_DQ1
19 18 BI MC_DQ0 AN5 MC_DQ0 21 20 BI MD_DQ0 AH16 MD_DQ0
19 18 13 OUT MC_WDQS0 AN4 MC_WDQS0 21 20 OUT MD_WDQS0 AH15 MD_WDQS0
19 18 IN MC_RDQS0 AK7 MC_RDQS0 21 20 IN MD_RDQS0 AK17 MD_RDQS0
19 18 OUT MC_DM0 AN7 MC_DM0 21 20 OUT MD_DM0 AH17 MD_DM0
B MC_WDQS1
R5T7
1 2 B
19 18 13 OUT R6T9
AE5 MC_VREF0 4.75 KOHM 1% AN17 MD_VREF0 21 20 13 OUT MD_WDQS1 1 2
402 CH 4.75 KOHM 1%
X818336-001 BGA_2 19 18 13 BI MC_DQ12 X818336-001 BGA_2 402 CH
21 20 13 BI MD_DQ12

R5T6 V_MEM
19 18 13 BI MC_DQ4 1 2
4.75 KOHM 1% MEMORY CONTROLLER D, DECOUPLING
402 CH
V_MEM 19 18 13 OUT MC_WDQS0 V_MEM
1 C5T48 1 C5T39 1 C6T31 1 C5T38
2 R5T2 V_MEM 1 R5T5 0.1 UF
10%
0.1 UF
10%
0.1 UF
10%
0.1 UF
10%
549 OHM 549 OHM 6.3 V 6.3 V 6.3 V
1%
MEMORY CONTROLLER C, DECOUPLING 1% 2 X5R 2 X5R 2 X5R 2 6.3
X5R
V
1 EMPTY 2 EMPTY 402 402 402 402
402 402
MC_VREF0
MD_VREF0
1 R5T3 1 C5U2 1 C5T37 1 C5T41 1 C6T28 1 C5T49
1.27 KOHM 0.1 UF 0.1 UF 0.1 UF
1% 4.7 UF 0.1 UF 10% 10% 10% 1 R5T4
NEED TO VREF RESISTOR VALUES 10% 10% 6.3 V 6.3 V
2 EMPTY 2 6.3 V
2 6.3 V 2 X5R 2 X5R 2 6.3
X5R
V 1.27 KOHM
1%
402 X5R X5R 402 402 402 1 C6T26 1 C5T42 1 C5T45 1 C5T44
805 402 2 EMPTY
402 0.1 UF 0.1 UF 0.1 UF 0.1 UF
10% 10% 10% 10%
6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 6.3
X5R
V

A 402 402 402 402 A

1 C5T50 1 C5T46 1 C6T33 1 C5T47
TO CHANGE GPU VREF, CHANGE THESE RESISTORS TO MATCH THE TABLE 0.1 UF 0.1 UF 0.1 UF 0.1 UF
10% 10% 10% 10%
R6T4, R6T1, R5T3, R5T4 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R N: GPU VREF SET INTERNALLY BY DEFAULT. EXTERNAL RESISTOR DIVIDER USED TO MANUALLY SET GPU VREF VOLTAGE.
402 402 402 402
GPU MEM VREF RESISTOR VALUE
THESE ARE THE GPU VREFS NEEDED
70% 1.27KOHM
FOR VARIOUS MEMORIES. CONSULT
72% 1.40KOHM
WITH MEM TEAM FOR USAGE.
73% 1.47KOHM
74% 1.54KOHM
MICROSOFT PROJECT NAME PAGE FAB REV
DRAWING
[PAGE_TITLE=[GPU, MEMORY CONTROLLER C + D] Wed Feb 10 16:23:26 2010 CONFIDENTIAL
TRINITY_XDK 13/81 G 1.01

8 7 6 5 4 3 2 1
 CR-14 : @TRINITY_LIB.TRINITY(SCH_1):PAGE14

8 7 6 5 4 3 2 1
MEMORY PARTITION A, TOP
CHIP SELECT = 0, MIRROR FUNCTION = 0
V_MEM

D D
1 R7E5 1 R7E4
60.4 OHM 60.4 OHM
1% 1% V_MEM
2 CH
402 2 CH
402
U7E1 IC
U7E1 IC
GDDR136 (1Gbit)
GDDR136 (1Gbit) V1
MA_CLK0_DP J11 T3 MA_DQ31 VDDQ<21> MF=0
12 IN CLK_DP MF=0 DQ31 BI 12 15 R12 VDDQ<20>
12 IN MA_CLK0_DN J10 CLK_DN DQ30 T2 MA_DQ30 BI 12 15 R9 T12
MEM_RST V9 R3 MA_DQ29 VDDQ<19> VSSQ<19>
4 IN RESET DQ29 BI 12 15 R4 T9
R2 MA_DQ28 VDDQ<18> VSSQ<18>
DQ28 BI 12 15 R1 VDDQ<17> VSSQ<17> T4
DQ27 M3 MA_DQ27 BI 12 15 N12 T1
N2 MA_DQ26 VDDQ<16> VSSQ<16>
DQ26 BI 12 15 N9 VDDQ<15> VSSQ<15> P12
DQ25 L3 MA_DQ25 BI 12 15 V12 P9
M2 MA_DQ24 VDDQ<14> VSSQ<14>
DQ24 BI 12 15 N4 VDDQ<13> VSSQ<13> P4
WDQS3 P2 MA_WDQS3 IN 12 N1 P1
P3 MA_RDQS3 VDDQ<12> VSSQ<12>
RDQS3 OUT 15 12 J9 VSSQ<11> L11
N3 MA_DM3 VDDQ<11>
DM3 IN 12 J4 VDDQ<10> VSSQ<10> L2
E12 VDDQ<9> VSSQ<9> G11
MA_A<11..0> J2 A12 (1Gbit only, dual-load) DQ23 T10 MA_DQ23 BI 12 15 E9 G2
12 IN 11 L4 T11 MA_DQ22 VDDQ<8> VSSQ<8>
A11/A7 DQ22 BI 12 15 E4 VDDQ<7> D12
10 K2 R10 MA_DQ21 VSSQ<7>
C 9 M9
A10/A8
A9/A3
DQ21
DQ20 R11 MA_DQ20 BI
BI
12 15
12 15
E1
C12
VDDQ<6> VSSQ<6> D9
D4 C
8 K11 M10 MA_DQ19 VDDQ<5> VSSQ<5>
A8/A10 DQ19 BI 12 15 C9 VDDQ<4> D1
7 L9 N11 MA_DQ18 VSSQ<4>
A7/A11 DQ18 BI 12 15 C4 VDDQ<3> B12
6 K10 L10 MA_DQ17 VSSQ<3>
A6/A2 DQ17 BI 12 15 C1 VDDQ<2> B9
5 H11 M11 MA_DQ16 VSSQ<2>
A5/A1 DQ16 BI 12 15 A12 VDDQ<1> B4
4 K9 P11 MA_WDQS2 VSSQ<1>
A4/A0 WDQS2 IN 12 A1 VDDQ<0> B1
3 M4 P10 MA_RDQS2 VSSQ<0>
A3/A9 RDQS2 OUT 15 12
2 K3 A2/A6 DM2 N10 MA_DM2 IN 12 V2 V3
1 H2 VDD<7> VSS<7>
A1/A5 M12 VDD<6> L12
0 K4 G10 MA_DQ15 VSS<6>
A0/A4 DQ15 BI 12 15 M1 VDD<5> L1
F11 MA_DQ14 VSS<5>
12 MA_BA<2..0> DQ14 BI 12 15 V11 VDD<4> VSS<4> G12
IN 2 H10 BA2/RAS_N DQ13 F10 MA_DQ13 BI 12 15 F12 G1
1 G9 E11 MA_DQ12 VDD<3> VSS<3>
BA1/BA0 DQ12 BI 12 15 F1 VDD<2> A10
0 G4 C10 MA_DQ11 VSS<2>
BA0/BA1 DQ11 BI 12 15 A11 VDD<1> V10
C11 MA_DQ10 VSS<1>
DQ10 BI 12 15 A2 VDD<0> VSS<0> A3
12 IN MA_CKE H4 CKE/WE_N DQ9 B10 MA_DQ9 BI 12 15
12 IN MA_WE_N H9 WE_N/CKE DQ8 B11 MA_DQ8 BI 12 15 K12
MA_CAS_N F4 D11 MA_WDQS1 VDDA<1>
12 IN CAS_N/CS_N WDQS1 IN 12 K1 VDDA<0>
12 IN MA_RAS_N H3 RAS_N/BA2 RDQS1 D10 MA_RDQS1 OUT 15 12
12 IN MA_CS0_N F9 CS_N/CAS_N DM1 E10 MA_DM1 IN 12 J12
MA_CS1_N J3 VSSA<1>
12 IN CS1_N (1Gbit only, single-load) J1 VSSA<0>
4 IN MEM_SCAN_TOP_EN A9 MF DQ7 G3 MA_DQ7 BI 12 15
B MEM_SCAN_EN V4
DQ6 F2
F3
MA_DQ6
MA_DQ5 BI 12 15
B
4 IN SCAN_EN DQ5 BI 12 15
E2 MA_DQ4 X802980-019
DQ4 BI 12 15
14 IN MEM_A_VREF1 H1 VREF1 DQ3 C3 MA_DQ3 BI 12 15
15 IN MEM_A_VREF0 H12 VREF0 DQ2 C2 MA_DQ2 BI 12 15
DQ1 B3 MA_DQ1 BI 12 15
DQ0 B2 MA_DQ0 BI 12 15
WDQS0 D2 MA_WDQS0 IN 12
D3 MA_RDQS0 MX_CS1_N CONNECTED
RDQS0 OUT 15 12
TO J3 TO SUPPORT 1G
DM0 E3 MA_DM0 IN 12
RAM CONFIGS.
ZQ A4 MA_ZQ_TOP

V_MEM 1 R7E8
243 OHM
X802980-019 1%
2 CH
402
1 R7T5
549 OHM PARTITION A DECOUPLING
1% V_MEM V_MEM
2 EMPTY MEMORY A, TOP, DECOUPLING
402
MEM_A_VREF1 OUT 14 15
1 C7E8
4.7 UF C7E14 C7E11 C7E6 C7E5 C7E13 C7E10 C7E4 C7E7
10% 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
1 R7T4 6.3 V 10% 10% 10% 10% 10% 10% 10% 10%
1.27 KOHM 2 X5R 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
1% C7T7 805 X5R X5R X5R X5R X5R X5R X5R X5R
2 EMPTY 0.1 UF 402 402 402 402 402 402 402 402
10%
A 402 6.3 V
X5R
TO CHANGE MEM VREF, CHANGE THESE RESISTORS TO MATCH THE TABLE A
402 R7T4, R7E7, R7R4, R7D5, R5U4, R5F2, R6U4, R6F2

MEM VREF RESISTOR VALUE

69% 1.21KOHM
70% 1.27KOHM
72% 1.40KOHM
THESE ARE THE MEM VREFS NEEDED
FOR VARIOUS MEMORIES. CONSULT
WITH MEM TEAM FOR USAGE.

MICROSOFT PROJECT NAME PAGE FAB REV

DRAWING
[PAGE_TITLE=MEMORY PARTITION A, TOP] Wed Feb 10 16:23:26 2010 CONFIDENTIAL
TRINITY_XDK 14/81 G 1.01

8 7 6 5 4 3 2 1
 CR-15 : @TRINITY_LIB.TRINITY(SCH_1):PAGE15

8 7 6 5 4 3 2 1

V_MEM
MEMORY PARTITION A, BOTTOM CHIP SELECT = 1, MIRROR FUNCTION = 1

D D
1 R7T3 1 R7T2
60.4 OHM 60.4 OHM
1% 1%
2 CH 2 CH U7T1 EMPTY
402 402 V_MEM
GDDR136 (1Gbit)
12 IN MA_CLK1_DP J11 CLK_DP MF=1 DQ31 T3 MA_DQ23 BI 12 14 U7T1 EMPTY
12 IN MA_CLK1_DN J10 CLK_DN DQ30 T2 MA_DQ22 BI 12 14
MEM_RST V9 R3 MA_DQ21 GDDR136 (1Gbit)
4 IN RESET DQ29 BI 12 14 V1
R2 MA_DQ20 VDDQ<21> MF=1
DQ28 BI 12 14 R12 VDDQ<20>
DQ27 M3 MA_DQ19 BI 12 14 R9 T12
N2 MA_DQ18 VDDQ<19> VSSQ<19>
DQ26 BI 12 14 R4 VDDQ<18> VSSQ<18> T9
DQ25 L3 MA_DQ17 BI 12 14 R1 T4
M2 MA_DQ16 VDDQ<17> VSSQ<17>
DQ24 BI 12 14 N12 VDDQ<16> VSSQ<16> T1
WDQS3 P2 MA_WDQS2 IN 12 N9 P12
P3 MA_RDQS2 VDDQ<15> VSSQ<15>
RDQS3 OUT 14 12 V12 VDDQ<14> VSSQ<14> P9
DM3 N3 MA_DM2 IN 12 N4 P4
VDDQ<13> VSSQ<13>
N1 VDDQ<12> VSSQ<12> P1
MA_A<11..0> J2 A12 (1Gbit only, dual-load) DQ23 T10 MA_DQ31 BI 12 14 J9 L11
12 IN 11 L9 T11 MA_DQ30 VDDQ<11> VSSQ<11>
A7/A11 DQ22 BI 12 14 J4 L2
10 K11 R10 MA_DQ29 VDDQ<10> VSSQ<10>
A8/A10 DQ21 BI 12 14 E12 G11
C 9
8
M4
K2
A3/A9 DQ20 R11
M10
MA_DQ28
MA_DQ27 BI 12 14 E9
VDDQ<9>
VDDQ<8>
VSSQ<9>
VSSQ<8> G2 C
A10/A8 DQ19 BI 12 14 E4 D12
7 L4 N11 MA_DQ26 VDDQ<7> VSSQ<7>
A11/A7 DQ18 BI 12 14 E1 D9
6 K3 L10 MA_DQ25 VDDQ<6> VSSQ<6>
A2/A6 DQ17 BI 12 14 C12 VDDQ<5> D4
5 H2 M11 MA_DQ24 VSSQ<5>
A1/A5 DQ16 BI 12 14 C9 VDDQ<4> D1
4 K4 P11 MA_WDQS3 VSSQ<4>
A0/A4 WDQS2 IN 12 C4 VDDQ<3> B12
3 M9 P10 MA_RDQS3 VSSQ<3>
A9/A3 RDQS2 OUT 14 12 C1 VDDQ<2> B9
2 K10 N10 MA_DM3 VSSQ<2>
A6/A2 DM2 IN 12 A12 VDDQ<1> B4
1 H11 VSSQ<1>
A5/A1 A1 B1
0 K9 G10 MA_DQ7 VDDQ<0> VSSQ<0>
A4/A0 DQ15 BI 12 14
MA_BA<2..0> DQ14 F11 MA_DQ6 BI 12 14 V2 V3
12 IN 2 H3 F10 MA_DQ5 VDD<7> VSS<7>
RAS_N/BA2 DQ13 BI 12 14 M12 L12
1 G4 E11 MA_DQ4 VDD<6> VSS<6>
BA0/BA1 DQ12 BI 12 14 M1 L1
0 G9 C10 MA_DQ3 VDD<5> VSS<5>
BA1/BA0 DQ11 BI 12 14 V11 G12
C11 MA_DQ2 VDD<4> VSS<4>
DQ10 BI 12 14 F12 VDD<3> VSS<3> G1
12 IN MA_CKE H9 WE_N/CKE DQ9 B10 MA_DQ1 BI 12 14 F1 A10
MA_WE_N H4 B11 MA_DQ0 VDD<2> VSS<2>
12 IN CKE/WE_N DQ8 BI 12 14 A11 VDD<1> V10
MA_CAS_N F9 D11 MA_WDQS0 VSS<1>
12 IN CS_N/CAS_N WDQS1 IN 12 A2 VDD<0> A3
MA_RAS_N H10 D10 MA_RDQS0 VSS<0>
12 IN BA2/RAS_N RDQS1 OUT 14 12
12 IN MA_CS1_N F4 CAS_N/CS_N DM1 E10 MA_DM0 IN 12 K12
J3 VDDA<1>
CS1_N (1Gbit only, single-load) K1 VDDA<0>
4 IN MEM_SCAN_BOT_EN A9 MF DQ7 G3 MA_DQ15 BI 12 14
F2 MA_DQ14
B 4 IN MEM_SCAN_EN V4 SCAN_EN
DQ6
DQ5 F3 MA_DQ13 BI
BI
12 14
12 14
J12
J1
VSSA<1>
B
E2 MA_DQ12 VSSA<0>
DQ4 BI 12 14
15 IN MEM_A_VREF0 H1 VREF1 DQ3 C3 MA_DQ11 BI 12 14
14 IN MEM_A_VREF1 H12 VREF0 DQ2 C2 MA_DQ10 BI 12 14
B3 MA_DQ9 X802980-019
DQ1 BI 12 14
DQ0 B2 MA_DQ8 BI 12 14
WDQS0 D2 MA_WDQS1 IN 12
RDQS0 D3 MA_RDQS1 OUT 14 12
DM0 E3 MA_DM1 IN 12

ZQ A4 MA_ZQ_BOT

1 R7T6
243 OHM
X802980-019 1%
V_MEM 2 CH
402

1 R7E6 V_MEM
549 OHM
1%
2 EMPTY MEMORY A, BOTTOM, DECOUPLING
402
MEM_A_VREF0 OUT 14 15

1 R7E7 C7T12 C7T9 C7T5 C7T4 C7T11 C7T8 C7T3 C7T6

1.27 KOHM 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
1% C7E9 10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
2 EMPTY 0.1 UF
A 402
10%
6.3 V
X5R
402
X5R
402
X5R
402
X5R
402
X5R
402
X5R
402
X5R
402
X5R
402 A
X5R
402

MICROSOFT PROJECT NAME PAGE FAB REV

DRAWING
[PAGE_TITLE=MEMORY PARTITION A, BOTTOM] Wed Feb 10 16:23:26 2010 CONFIDENTIAL
TRINITY_XDK 15/81 G 1.01

8 7 6 5 4 3 2 1
 CR-16 : @TRINITY_LIB.TRINITY(SCH_1):PAGE16

8 7 6 5 4 3 2 1
MEMORY PARTITION B, TOP CHIP SELECT = 0, MIRROR FUNCTION = 0

V_MEM
D D

1 R7D3 1 R7D2 V_MEM

60.4 OHM 60.4 OHM
1% 1%
U7D1 IC
2 CH 2 CH
402 402 GDDR136 (1Gbit)
U7D1 IC V1 VDDQ<21> MF=0
R12 VDDQ<20>
GDDR136 (1Gbit) R9 VDDQ<19> T12
MB_CLK0_DP J11 T3 MB_DQ31 VSSQ<19>
12 IN CLK_DP MF=0 DQ31 BI 12 17 R4 T9
MB_CLK0_DN J10 T2 MB_DQ30 VDDQ<18> VSSQ<18>
12 IN CLK_DN DQ30 BI 12 17 R1 VDDQ<17> T4
MEM_RST V9 R3 MB_DQ29 VSSQ<17>
4 IN RESET DQ29 BI 12 17 N12 T1
R2 MB_DQ28 VDDQ<16> VSSQ<16>
DQ28 BI 12 17 N9 VDDQ<15> VSSQ<15> P12
DQ27 M3 MB_DQ27 BI 12 17 V12 P9
N2 MB_DQ26 VDDQ<14> VSSQ<14>
DQ26 BI 12 17 N4 VDDQ<13> VSSQ<13> P4
DQ25 L3 MB_DQ25 BI 12 17 N1 P1
M2 MB_DQ24 VDDQ<12> VSSQ<12>
DQ24 BI 12 17 J9 VSSQ<11> L11
P2 MB_WDQS3 VDDQ<11>
WDQS3 IN 12 J4 VDDQ<10> VSSQ<10> L2
RDQS3 P3 MB_RDQS3 OUT 17 12 E12 G11
N3 MB_DM3 VDDQ<9> VSSQ<9>
DM3 IN 12 E9 VDDQ<8> VSSQ<8> G2
E4 VDDQ<7> VSSQ<7> D12
J2 T10 MB_DQ23
C 12 IN MB_A<11..0> 11 L4
A12 (1Gbit only, dual-load)
A11/A7
DQ23
DQ22 T11 MB_DQ22 BI
BI
12 17
12 17
E1
C12
VDDQ<6> VSSQ<6> D9
D4 C
10 K2 R10 MB_DQ21 VDDQ<5> VSSQ<5>
A10/A8 DQ21 BI 12 17 C9 VDDQ<4> D1
9 M9 R11 MB_DQ20 VSSQ<4>
A9/A3 DQ20 BI 12 17 C4 VDDQ<3> B12
8 K11 M10 MB_DQ19 VSSQ<3>
A8/A10 DQ19 BI 12 17 C1 VDDQ<2> B9
7 L9 N11 MB_DQ18 VSSQ<2>
A7/A11 DQ18 BI 12 17 A12 VDDQ<1> B4
6 K10 L10 MB_DQ17 VSSQ<1>
A6/A2 DQ17 BI 12 17 A1 VDDQ<0> B1
5 H11 M11 MB_DQ16 VSSQ<0>
A5/A1 DQ16 BI 12 17
4 K9 A4/A0 WDQS2 P11 MB_WDQS2 IN 12 V2 V3
3 M4 P10 MB_RDQS2 VDD<7> VSS<7>
A3/A9 RDQS2 OUT 17 12 M12 VDD<6> L12
2 K3 N10 MB_DM2 VSS<6>
A2/A6 DM2 IN 12 M1 VDD<5> L1
1 H2 VSS<5>
A1/A5 V11 VDD<4> G12
0 K4 G10 MB_DQ15 VSS<4>
A0/A4 DQ15 BI 12 17 F12 VDD<3> G1
F11 MB_DQ14 VSS<3>
12 MB_BA<2..0> DQ14 BI 12 17 F1 VDD<2> VSS<2> A10
IN 2 H10 BA2/RAS_N DQ13 F10 MB_DQ13 BI 12 17 A11 V10
1 G9 E11 MB_DQ12 VDD<1> VSS<1>
BA1/BA0 DQ12 BI 12 17 A2 VDD<0> A3
0 G4 C10 MB_DQ11 VSS<0>
BA0/BA1 DQ11 BI 12 17
DQ10 C11 MB_DQ10 BI 12 17 K12
MB_CKE H4 B10 MB_DQ9 VDDA<1>
12 IN CKE/WE_N DQ9 BI 12 17 K1 VDDA<0>
12 IN MB_WE_N H9 WE_N/CKE DQ8 B11 MB_DQ8 BI 12 17
12 IN MB_CAS_N F4 CAS_N/CS_N WDQS1 D11 MB_WDQS1 IN 12 J12
MB_RAS_N H3 D10 MB_RDQS1 VSSA<1>
12 IN RAS_N/BA2 RDQS1 OUT 17 12 J1 VSSA<0>
12 IN MB_CS0_N F9 CS_N/CAS_N DM1 E10 MB_DM1 IN 12
B 12 IN MB_CS1_N
MEM_SCAN_TOP_EN
J3
A9
CS1_N (1Gbit only, single-load)
G3 MB_DQ7 B
4 IN MF DQ7 BI 12 17
F2 MB_DQ6 X802980-019
DQ6 BI 12 17
4 IN MEM_SCAN_EN V4 SCAN_EN DQ5 F3 MB_DQ5 BI 12 17
DQ4 E2 MB_DQ4 BI 12 17
16 IN MEM_B_VREF1 H1 VREF1 DQ3 C3 MB_DQ3 BI 12 17
17 IN MEM_B_VREF0 H12 VREF0 DQ2 C2 MB_DQ2 BI 12 17
DQ1 B3 MB_DQ1 BI 12 17
DQ0 B2 MB_DQ0 BI 12 17
WDQS0 D2 MB_WDQS0 IN 12
RDQS0 D3 MB_RDQS0 OUT 17 12
DM0 E3 MB_DM0 IN 12

ZQ A4 MB_ZQ_TOP

V_MEM 1 R7E1
243 OHM
X802980-019 1%
2 CH
402
1 R7R2
549 OHM PARTITION B DECOUPLING
1%
2 EMPTY
402
MEM_B_VREF1 OUT 16 17
V_MEM V_MEM
MEMORY B, TOP, DECOUPLING
1 R7R4
1.27 KOHM C7R6
1%
A 2 EMPTY
0.1 UF
10%
1 C7D11 A
402 6.3 V 4.7 UF C7D13 C7D9 C7E3 C7E2 C7D14 C7D10 C7D7 C7D8
X5R 10% 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
402 6.3 V 10% 10% 10% 10% 10% 10% 10% 10%
2 X5R 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
805 X5R X5R X5R X5R X5R X5R X5R X5R
402 402 402 402 402 402 402 402

MICROSOFT PROJECT NAME PAGE FAB REV

DRAWING
[PAGE_TITLE=MEMORY PARITION B, TOP] Wed Feb 10 16:23:27 2010 CONFIDENTIAL
TRINITY_XDK 16/81 G 1.01

8 7 6 5 4 3 2 1
 CR-17 : @TRINITY_LIB.TRINITY(SCH_1):PAGE17

8 7 6 5 4 3 2 1
MEMORY PARTITION B, BOTTOM
CHIP SELECT = 1, MIRROR FUNCTION = 1

D D
V_MEM

1 R7R1 1 R7R3
60.4 OHM 60.4 OHM
1% 1%
U7R1 EMPTY
2 CH 2 CH V_MEM
402 402 GDDR136 (1Gbit)
12 IN MB_CLK1_DP J11 CLK_DP MF=1 DQ31 T3 MB_DQ23 BI 12 16 U7R1 EMPTY
12 IN MB_CLK1_DN J10 CLK_DN DQ30 T2 MB_DQ22 BI 12 16
MEM_RST V9 R3 MB_DQ21 GDDR136 (1Gbit)
4 IN RESET DQ29 BI 12 16 V1
R2 MB_DQ20 VDDQ<21> MF=1
DQ28 BI 12 16 R12 VDDQ<20>
DQ27 M3 MB_DQ19 BI 12 16 R9 T12
N2 MB_DQ18 VDDQ<19> VSSQ<19>
DQ26 BI 12 16 R4 VDDQ<18> VSSQ<18> T9
DQ25 L3 MB_DQ17 BI 12 16 R1 T4
M2 MB_DQ16 VDDQ<17> VSSQ<17>
DQ24 BI 12 16 N12 VDDQ<16> VSSQ<16> T1
WDQS3 P2 MB_WDQS2 IN 12 N9 P12
P3 MB_RDQS2 VDDQ<15> VSSQ<15>
RDQS3 OUT 16 12 V12 VDDQ<14> VSSQ<14> P9
DM3 N3 MB_DM2 IN 12 N4 P4
VDDQ<13> VSSQ<13>
N1 P1
C 12 IN MB_A<11..0> 11
J2
L9
A12 (1Gbit only, dual-load) DQ23 T10
T11
MB_DQ31
MB_DQ30 BI 12 16 J9
VDDQ<12>
VDDQ<11>
VSSQ<12>
VSSQ<11> L11 C
A7/A11 DQ22 BI 12 16 J4 L2
10 K11 R10 MB_DQ29 VDDQ<10> VSSQ<10>
A8/A10 DQ21 BI 12 16 E12 G11
9 M4 R11 MB_DQ28 VDDQ<9> VSSQ<9>
A3/A9 DQ20 BI 12 16 E9 G2
8 K2 M10 MB_DQ27 VDDQ<8> VSSQ<8>
A10/A8 DQ19 BI 12 16 E4 D12
7 L4 N11 MB_DQ26 VDDQ<7> VSSQ<7>
A11/A7 DQ18 BI 12 16 E1 D9
6 K3 L10 MB_DQ25 VDDQ<6> VSSQ<6>
A2/A6 DQ17 BI 12 16 C12 VDDQ<5> D4
5 H2 M11 MB_DQ24 VSSQ<5>
A1/A5 DQ16 BI 12 16 C9 VDDQ<4> D1
4 K4 P11 MB_WDQS3 VSSQ<4>
A0/A4 WDQS2 IN 12 C4 VDDQ<3> B12
3 M9 P10 MB_RDQS3 VSSQ<3>
A9/A3 RDQS2 OUT 16 12 C1 VDDQ<2> B9
2 K10 N10 MB_DM3 VSSQ<2>
A6/A2 DM2 IN 12 A12 VDDQ<1> B4
1 H11 VSSQ<1>
A5/A1 A1 B1
0 K9 G10 MB_DQ7 VDDQ<0> VSSQ<0>
A4/A0 DQ15 BI 12 16
MB_BA<2..0> DQ14 F11 MB_DQ6 BI 12 16 V2 V3
12 IN 2 H3 F10 MB_DQ5 VDD<7> VSS<7>
RAS_N/BA2 DQ13 BI 12 16 M12 L12
1 G4 E11 MB_DQ4 VDD<6> VSS<6>
BA0/BA1 DQ12 BI 12 16 M1 L1
0 G9 C10 MB_DQ3 VDD<5> VSS<5>
BA1/BA0 DQ11 BI 12 16 V11 G12
C11 MB_DQ2 VDD<4> VSS<4>
DQ10 BI 12 16 F12 VDD<3> VSS<3> G1
12 IN MB_CKE H9 WE_N/CKE DQ9 B10 MB_DQ1 BI 12 16 F1 A10
MB_WE_N H4 B11 MB_DQ0 VDD<2> VSS<2>
12 IN CKE/WE_N DQ8 BI 12 16 A11 VDD<1> V10
MB_CAS_N F9 D11 MB_WDQS0 VSS<1>
12 IN CS_N/CAS_N WDQS1 IN 12 A2 VDD<0> A3
MB_RAS_N H10 D10 MB_RDQS0 VSS<0>
12 IN BA2/RAS_N RDQS1 OUT 16 12
MB_CS1_N F4 E10 MB_DM0
B 12 IN J3
CAS_N/CS_N
CS1_N (1Gbit only, single-load)
DM1 IN 12 K12
K1
VDDA<1>
B
MEM_SCAN_BOT_EN A9 G3 MB_DQ15 VDDA<0>
4 IN MF DQ7 BI 12 16
DQ6 F2 MB_DQ14 BI 12 16 J12
MEM_SCAN_EN V4 F3 MB_DQ13 VSSA<1>
4 IN SCAN_EN DQ5 BI 12 16 J1
E2 MB_DQ12 VSSA<0>
DQ4 BI 12 16
17 IN MEM_B_VREF0 H1 VREF1 DQ3 C3 MB_DQ11 BI 12 16
16 IN MEM_B_VREF1 H12 VREF0 DQ2 C2 MB_DQ10 BI 12 16
B3 MB_DQ9 X802980-019
DQ1 BI 12 16
DQ0 B2 MB_DQ8 BI 12 16
WDQS0 D2 MB_WDQS1 IN 12
RDQS0 D3 MB_RDQS1 OUT 16 12
DM0 E3 MB_DM1 IN 12

ZQ A4 MB_ZQ_BOT
V_MEM 1 R7T1
243 OHM
X802980-019 1%
2 CH
1 R7D4 402
549 OHM
1% V_MEM
2 EMPTY
402
MEM_B_VREF0 16 17
MEMORY B, BOTTOM, DECOUPLING
OUT

1 R7D5
1.27 KOHM C7R7 C7R4 C7T2 C7T1 C7R8 C7R5 C7R2 C7R3
1% C7D12 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
A 2 EMPTY 0.1 UF
10%
10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
A
402 6.3 V X5R X5R X5R X5R X5R X5R X5R X5R
X5R 402 402 402 402 402 402 402 402
402

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=MEMORY PARITION B, BOTTOM] DRAWING
Wed Feb 10 16:23:27 2010 CONFIDENTIAL
TRINITY_XDK 17/81 G 1.01

8 7 6 5 4 3 2 1
 CR-18 : @TRINITY_LIB.TRINITY(SCH_1):PAGE18

8 7 6 5 4 3 2 1
MEMORY PARTITION C, TOP
CHIP SELECT = 0, MIRROR FUNCTION = 0

V_MEM
D D
1 R5F4 1 R5F3
60.4 OHM 60.4 OHM V_MEM
1% 1%
2 CH 2 CH U5F1 IC
402 402 U5F1 IC
GDDR136 (1Gbit)
GDDR136 (1Gbit) V1 VDDQ<21> MF=0
13 IN MC_CLK0_DP J11 CLK_DP MF=0 DQ31 T3 MC_DQ31 BI 13 19 R12 VDDQ<20>
13 IN MC_CLK0_DN J10 CLK_DN DQ30 T2 MC_DQ30 BI 13 19 R9 VDDQ<19> VSSQ<19> T12
4 IN MEM_RST V9 RESET DQ29 R3 MC_DQ29 BI 13 19 R4 VDDQ<18> VSSQ<18> T9
DQ28 R2 MC_DQ28 BI 13 19 R1 VDDQ<17> VSSQ<17> T4
DQ27 M3 MC_DQ27 BI 13 19 N12 VDDQ<16> VSSQ<16> T1
DQ26 N2 MC_DQ26 BI 13 19 N9 VDDQ<15> VSSQ<15> P12
DQ25 L3 MC_DQ25 BI 13 19 V12 VDDQ<14> VSSQ<14> P9
DQ24 M2 MC_DQ24 BI 13 19 N4 VDDQ<13> VSSQ<13> P4
WDQS3 P2 MC_WDQS3 IN 13 N1 VDDQ<12> VSSQ<12> P1
RDQS3 P3 MC_RDQS3 OUT 19 13 J9 VDDQ<11> VSSQ<11> L11
DM3 N3 MC_DM3 IN 13 J4 VDDQ<10> VSSQ<10> L2
E12 VDDQ<9> VSSQ<9> G11
MC_A<11..0> J2 A12 (1Gbit only, dual-load) DQ23 T10 MC_DQ23 BI 13 19 E9 VDDQ<8> VSSQ<8> G2
13 IN 11 L4 T11 MC_DQ22 E4 D12
A11/A7 DQ22 BI 13 19 VDDQ<7> VSSQ<7>
C 10
9
K2
M9
A10/A8 DQ21 R10
R11
MC_DQ21
MC_DQ20 BI 13 19 E1
C12
VDDQ<6> VSSQ<6> D9
D4 C
A9/A3 DQ20 BI 13 19 VDDQ<5> VSSQ<5>
8 K11 A8/A10 DQ19 M10 MC_DQ19 BI 13 19 C9 VDDQ<4> VSSQ<4> D1
7 L9 A7/A11 DQ18 N11 MC_DQ18 BI 13 19 C4 VDDQ<3> VSSQ<3> B12
6 K10 A6/A2 DQ17 L10 MC_DQ17 BI 13 19 C1 VDDQ<2> VSSQ<2> B9
5 H11 A5/A1 DQ16 M11 MC_DQ16 BI 13 19 A12 VDDQ<1> VSSQ<1> B4
4 K9 A4/A0 WDQS2 P11 MC_WDQS2 IN 13 A1 VDDQ<0> VSSQ<0> B1
3 M4 A3/A9 RDQS2 P10 MC_RDQS2 OUT 19 13
2 K3 A2/A6 DM2 N10 MC_DM2 IN 13 V2 VDD<7> VSS<7> V3
1 H2 A1/A5 M12 VDD<6> VSS<6> L12
0 K4 A0/A4 DQ15 G10 MC_DQ15 BI 13 19 M1 VDD<5> VSS<5> L1
MC_BA<2..0> DQ14 F11 MC_DQ14 BI 13 19 V11 VDD<4> VSS<4> G12
13 IN 2 H10 F10 MC_DQ13 F12 G1
BA2/RAS_N DQ13 BI 13 19 VDD<3> VSS<3>
1 G9 BA1/BA0 DQ12 E11 MC_DQ12 BI 13 19 F1 VDD<2> VSS<2> A10
0 G4 BA0/BA1 DQ11 C10 MC_DQ11 BI 13 19 A11 VDD<1> VSS<1> V10
DQ10 C11 MC_DQ10 BI 13 19 A2 VDD<0> VSS<0> A3
13 IN MC_CKE H4 CKE/WE_N DQ9 B10 MC_DQ9 BI 13 19
13 IN MC_WE_N H9 WE_N/CKE DQ8 B11 MC_DQ8 BI 13 19 K12 VDDA<1>
13 IN MC_CAS_N F4 CAS_N/CS_N WDQS1 D11 MC_WDQS1 IN 13 K1 VDDA<0>
13 IN MC_RAS_N H3 RAS_N/BA2 RDQS1 D10 MC_RDQS1 OUT 19 13
13 IN MC_CS0_N F9 CS_N/CAS_N DM1 E10 MC_DM1 IN 13 J12 VSSA<1>
13 IN MC_CS1_N J3 CS1_N (1Gbit only, single-load) J1 VSSA<0>
MEM_SCAN_TOP_EN A9 G3 MC_DQ7
B 4 IN MF DQ7
DQ6 F2 MC_DQ6 BI
BI
13 19
13 19 B
4 IN MEM_SCAN_EN V4 SCAN_EN DQ5 F3 MC_DQ5 BI 13 19 X802980-019
DQ4 E2 MC_DQ4 BI 13 19
18 IN MEM_C_VREF1 H1 VREF1 DQ3 C3 MC_DQ3 BI 13 19
19 IN MEM_C_VREF0 H12 VREF0 DQ2 C2 MC_DQ2 BI 13 19
DQ1 B3 MC_DQ1 BI 13 19
DQ0 B2 MC_DQ0 BI 13 19
WDQS0 D2 MC_WDQS0 IN 13
RDQS0 D3 MC_RDQS0 OUT 19 13
DM0 E3 MC_DM0 IN 13

ZQ A4 MC_ZQ_TOP

1 R5F5
243 OHM
X802980-019 1%
V_MEM 2 CH
402

1 R5U5
549 OHM
1%
2 EMPTY MC_CLK0
402 MEM_C_VREF1 OUT 18 19
STITCHING CAP PARTITION C DECOUPLING V_MEM
1 R5U4 V_MEM V_MEM
C5U9 MEMORY C, TOP, DECOUPLING
1.27 KOHM 0.1 UF
1% 10%
A 2 EMPTY 6.3 V
X5R
A
402 402 1 C5U1
0.1 UF 1 C5F10 C6F10 C6F8 C6F4 C6F1 C6F2 C6F5 C6F7 C6F9
10% 4.7 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
6.3 V 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 X5R 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
402 2 X5R X5R X5R X5R X5R X5R X5R X5R X5R
805 402 402 402 402 402 402 402 402

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=MEMORY PARTITION C, TOP] DRAWING
Wed Feb 10 16:23:27 2010 CONFIDENTIAL
TRINITY_XDK 18/81 G 1.01

8 7 6 5 4 3 2 1
 CR-19 : @TRINITY_LIB.TRINITY(SCH_1):PAGE19

8 7 6 5 4 3 2 1
MEMORY PARTITION C, BOTTOM
CHIP SELECT = 1, MIRROR FUNCTION = 1

V_MEM
D D
1 R5U3 1 R5U2
60.4 OHM 60.4 OHM
1% 1%
2 CH 2 CH
402 402
U5U1 EMPTY
V_MEM
GDDR136 (1Gbit)
MC_CLK1_DP J11 T3 MC_DQ23 U5U1 EMPTY
13 IN CLK_DP MF=1 DQ31 BI 13 18
13 IN MC_CLK1_DN J10 CLK_DN DQ30 T2 MC_DQ22 BI 13 18 GDDR136 (1Gbit)
4 IN MEM_RST V9 RESET DQ29 R3 MC_DQ21 BI 13 18 V1 VDDQ<21> MF=1
DQ28 R2 MC_DQ20 BI 13 18 R12 VDDQ<20>
DQ27 M3 MC_DQ19 BI 13 18 R9 VDDQ<19> VSSQ<19> T12
DQ26 N2 MC_DQ18 BI 13 18 R4 VDDQ<18> VSSQ<18> T9
DQ25 L3 MC_DQ17 BI 13 18 R1 VDDQ<17> VSSQ<17> T4
DQ24 M2 MC_DQ16 BI 13 18 N12 VDDQ<16> VSSQ<16> T1
WDQS3 P2 MC_WDQS2 IN 13 N9 VDDQ<15> VSSQ<15> P12
RDQS3 P3 MC_RDQS2 OUT 18 13 V12 VDDQ<14> VSSQ<14> P9
DM3 N3 MC_DM2 IN 13 N4 VDDQ<13> VSSQ<13> P4
N1 VDDQ<12> VSSQ<12> P1
MC_A<11..0> J2 A12 (1Gbit only, dual-load) DQ23 T10 MC_DQ31 BI 13 18 J9 VDDQ<11> VSSQ<11> L11
13 IN 11 L9 T11 MC_DQ30 J4 L2
C 10 K11
A7/A11
A8/A10
DQ22
DQ21 R10 MC_DQ29 BI
BI
13 18
13 18 E12
VDDQ<10>
VDDQ<9>
VSSQ<10>
VSSQ<9> G11 C
9 M4 A3/A9 DQ20 R11 MC_DQ28 BI 13 18 E9 VDDQ<8> VSSQ<8> G2
8 K2 A10/A8 DQ19 M10 MC_DQ27 BI 13 18 E4 VDDQ<7> VSSQ<7> D12
7 L4 A11/A7 DQ18 N11 MC_DQ26 BI 13 18 E1 VDDQ<6> VSSQ<6> D9
6 K3 A2/A6 DQ17 L10 MC_DQ25 BI 13 18 C12 VDDQ<5> VSSQ<5> D4
5 H2 A1/A5 DQ16 M11 MC_DQ24 BI 13 18 C9 VDDQ<4> VSSQ<4> D1
4 K4 A0/A4 WDQS2 P11 MC_WDQS3 IN 13 C4 VDDQ<3> VSSQ<3> B12
3 M9 A9/A3 RDQS2 P10 MC_RDQS3 OUT 18 13 C1 VDDQ<2> VSSQ<2> B9
2 K10 A6/A2 DM2 N10 MC_DM3 IN 13 A12 VDDQ<1> VSSQ<1> B4
1 H11 A5/A1 A1 VDDQ<0> VSSQ<0> B1
0 K9 A4/A0 DQ15 G10 MC_DQ7 BI 13 18
MC_BA<2..0> DQ14 F11 MC_DQ6 BI 13 18 V2 VDD<7> VSS<7> V3
13 IN 2 H3 F10 MC_DQ5 M12 L12
RAS_N/BA2 DQ13 BI 13 18 VDD<6> VSS<6>
1 G4 BA0/BA1 DQ12 E11 MC_DQ4 BI 13 18 M1 VDD<5> VSS<5> L1
0 G9 BA1/BA0 DQ11 C10 MC_DQ3 BI 13 18 V11 VDD<4> VSS<4> G12
DQ10 C11 MC_DQ2 BI 13 18 F12 VDD<3> VSS<3> G1
13 IN MC_CKE H9 WE_N/CKE DQ9 B10 MC_DQ1 BI 13 18 F1 VDD<2> VSS<2> A10
13 IN MC_WE_N H4 CKE/WE_N DQ8 B11 MC_DQ0 BI 13 18 A11 VDD<1> VSS<1> V10
13 IN MC_CAS_N F9 CS_N/CAS_N WDQS1 D11 MC_WDQS0 IN 13 A2 VDD<0> VSS<0> A3
13 IN MC_RAS_N H10 BA2/RAS_N RDQS1 D10 MC_RDQS0 OUT 18 13
13 IN MC_CS1_N F4 CAS_N/CS_N DM1 E10 MC_DM0 IN 13 K12 VDDA<1>
J3 CS1_N (1Gbit only, single-load) K1 VDDA<0>
B 4 IN MEM_SCAN_BOT_EN A9 MF DQ7 G3
F2
MC_DQ15
MC_DQ14 BI 13 18
J12 B
DQ6 BI 13 18 VSSA<1>
4 IN MEM_SCAN_EN V4 SCAN_EN DQ5 F3 MC_DQ13 BI 13 18 J1 VSSA<0>
DQ4 E2 MC_DQ12 BI 13 18
19 IN MEM_C_VREF0 H1 VREF1 DQ3 C3 MC_DQ11 BI 13 18
18 IN MEM_C_VREF1 H12 VREF0 DQ2 C2 MC_DQ10 BI 13 18 X802980-019
DQ1 B3 MC_DQ9 BI 13 18
DQ0 B2 MC_DQ8 BI 13 18
WDQS0 D2 MC_WDQS1 IN 13
RDQS0 D3 MC_RDQS1 OUT 18 13
DM0 E3 MC_DM1 IN 13

ZQ A4 MC_ZQ_BOT

1 R5U1
V_MEM 243 OHM
X802980-019 1%
2 CH
402
1 R5F1 V_MEM
549 OHM MEMORY C, BOTTOM, DECOUPLING
1%
2 EMPTY
402 MEM_C_VREF0 OUT 18 19

C6U9 C6U6 C6U3 C6U1 C6U2 C6U4 C6U5 C6U8

0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
1 R5F2 10% 10% 10% 10% 10% 10% 10% 10%
1.27 KOHM 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
1% C5F1 X5R X5R X5R X5R X5R X5R X5R X5R
0.1 UF 402 402 402 402 402 402 402 402
2 EMPTY 10% A
A 402 6.3 V
X5R
402

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=MEMORY PARITION C, BOTTOM] DRAWING
Wed Feb 10 16:23:27 2010 CONFIDENTIAL
TRINITY_XDK 19/81 G 1.01

8 7 6 5 4 3 2 1
 CR-20 : @TRINITY_LIB.TRINITY(SCH_1):PAGE20

8 7 6 5 4 3 2 1
MEMORY PARTITION D, TOP
V_MEM CHIP SELECT = 0, MIRROR FUNCTION = 0

1 R6F4 1 R6F3
D 60.4 OHM
1%
60.4 OHM
1%
D
2 CH 2 CH V_MEM
402 402
U6F1 IC
U6F1 IC GDDR136 (1Gbit)
V1 VDDQ<21> MF=0
GDDR136 (1Gbit) R12 VDDQ<20>
13 IN MD_CLK0_DP J11 CLK_DP MF=0 DQ31 T3 MD_DQ31 BI 13 21 R9 T12
MD_CLK0_DN J10 T2 MD_DQ30 VDDQ<19> VSSQ<19>
13 IN CLK_DN DQ30 BI 13 21 R4 T9
MEM_RST V9 R3 MD_DQ29 VDDQ<18> VSSQ<18>
4 IN RESET DQ29 BI 13 21 R1 VDDQ<17> T4
R2 MD_DQ28 VSSQ<17>
DQ28 BI 13 21 N12 T1
M3 MD_DQ27 VDDQ<16> VSSQ<16>
DQ27 BI 13 21 N9 VDDQ<15> VSSQ<15> P12
DQ26 N2 MD_DQ26 BI 13 21 V12 P9
L3 MD_DQ25 VDDQ<14> VSSQ<14>
DQ25 BI 13 21 N4 VDDQ<13> VSSQ<13> P4
DQ24 M2 MD_DQ24 BI 13 21 N1 P1
P2 MD_WDQS3 VDDQ<12> VSSQ<12>
WDQS3 IN 13 J9 VSSQ<11> L11
P3 MD_RDQS3 VDDQ<11>
RDQS3 OUT 21 13 J4 VDDQ<10> VSSQ<10> L2
DM3 N3 MD_DM3 IN 13 E12 G11
VDDQ<9> VSSQ<9>
E9 VDDQ<8> VSSQ<8> G2
MD_A<11..0> J2 A12 (1Gbit only, dual-load) DQ23 T10 MD_DQ23 BI 13 21 E4 D12
13 IN 11 L4 T11 MD_DQ22 VDDQ<7> VSSQ<7>
A11/A7 DQ22 BI 13 21 E1 VDDQ<6> D9
10 K2 R10 MD_DQ21 VSSQ<6>
A10/A8 DQ21 BI 13 21 C12 VDDQ<5> D4
9 M9 R11 MD_DQ20 VSSQ<5>
A9/A3 DQ20 BI 13 21 C9 D1
C 8
7
K11
L9
A8/A10 DQ19 M10
N11
MD_DQ19
MD_DQ18 BI 13 21 C4
VDDQ<4>
VDDQ<3>
VSSQ<4>
VSSQ<3> B12 C
A7/A11 DQ18 BI 13 21 C1 VDDQ<2> B9
6 K10 L10 MD_DQ17 VSSQ<2>
A6/A2 DQ17 BI 13 21 A12 VDDQ<1> B4
5 H11 M11 MD_DQ16 VSSQ<1>
A5/A1 DQ16 BI 13 21 A1 VDDQ<0> B1
4 K9 P11 MD_WDQS2 VSSQ<0>
A4/A0 WDQS2 IN 13
3 M4 A3/A9 RDQS2 P10 MD_RDQS2 OUT 21 13 V2 V3
2 K3 N10 MD_DM2 VDD<7> VSS<7>
A2/A6 DM2 IN 13 M12 VDD<6> L12
1 H2 VSS<6>
A1/A5 M1 VDD<5> L1
0 K4 G10 MD_DQ15 VSS<5>
A0/A4 DQ15 BI 13 21 V11 VDD<4> G12
F11 MD_DQ14 VSS<4>
13 MD_BA<2..0> DQ14 BI 13 21 F12 VDD<3> VSS<3> G1
IN 2 H10 BA2/RAS_N DQ13 F10 MD_DQ13 BI 13 21 F1 A10
1 G9 E11 MD_DQ12 VDD<2> VSS<2>
BA1/BA0 DQ12 BI 13 21 A11 VDD<1> V10
0 G4 C10 MD_DQ11 VSS<1>
BA0/BA1 DQ11 BI 13 21 A2 VDD<0> A3
C11 MD_DQ10 VSS<0>
DQ10 BI 13 21
13 IN MD_CKE H4 CKE/WE_N DQ9 B10 MD_DQ9 BI 13 21 K12
MD_WE_N H9 B11 MD_DQ8 VDDA<1>
13 IN WE_N/CKE DQ8 BI 13 21 K1 VDDA<0>
13 IN MD_CAS_N F4 CAS_N/CS_N WDQS1 D11 MD_WDQS1 IN 13
13 IN MD_RAS_N H3 RAS_N/BA2 RDQS1 D10 MD_RDQS1 OUT 21 13 J12
MD_CS0_N F9 E10 MD_DM1 VSSA<1>
13 IN CS_N/CAS_N DM1 IN 13 J1 VSSA<0>
13 IN MD_CS1_N J3 CS1_N (1Gbit only, single-load)
4 IN MEM_SCAN_TOP_EN A9 MF DQ7 G3 MD_DQ7 BI 13 21
DQ6 F2 MD_DQ6 BI 13 21
MEM_SCAN_EN V4 F3 MD_DQ5 X802980-019
B 4 IN SCAN_EN DQ5
DQ4 E2 MD_DQ4 BI
BI
13 21
13 21 B
20 IN MEM_D_VREF1 H1 VREF1 DQ3 C3 MD_DQ3 BI 13 21
21 IN MEM_D_VREF0 H12 VREF0 DQ2 C2 MD_DQ2 BI 13 21
DQ1 B3 MD_DQ1 BI 13 21
DQ0 B2 MD_DQ0 BI 13 21
WDQS0 D2 MD_WDQS0 IN 13
RDQS0 D3 MD_RDQS0 OUT 21 13
DM0 E3 MD_DM0 IN 13

ZQ A4 MD_ZQ_TOP

1 R6F5
243 OHM
X802980-019 1%
V_MEM 2 CH
402

1 R6U5
549 OHM
1%
2 EMPTY
402
MEM_D_VREF1 OUT 20 21
PARTITION D DECOUPLING
1 R6U4 V_MEM V_MEM
1.27 KOHM C6U7
1% 0.1 UF MEMORY D, TOP, DECOUPLING
2 EMPTY 10%
402 6.3 V
A X5R
402
1 C6F11 A
4.7 UF
10%
6.3 V
C5F9 C5F7 C5F4 C5F3 C5F2 C5F5 C5F6 C5F8
2 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
X5R 10% 10% 10% 10% 10% 10% 10% 10%
805 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
X5R X5R X5R X5R X5R X5R X5R X5R
402 402 402 402 402 402 402 402

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=MEMORY PARTITION D, TOP] DRAWING
Wed Feb 10 16:23:28 2010 CONFIDENTIAL
TRINITY_XDK 20/81 G 1.01

8 7 6 5 4 3 2 1
 CR-21 : @TRINITY_LIB.TRINITY(SCH_1):PAGE21

8 7 6 5 4 3 2 1
MEMORY PARTITION D, BOTTOM
CHIP SELECT = 1, MIRROR FUNCTION = 1

V_MEM
D D

1 R6U2 1 R6U3
60.4 OHM
60.4 OHM 1%
1%
2 CH 2 CH
402 U6U1 EMPTY
402
GDDR136 (1Gbit) V_MEM
13 IN MD_CLK1_DP J11 CLK_DP MF=1 DQ31 T3 MD_DQ23 BI 13 20
MD_CLK1_DN J10 T2 MD_DQ22 U6U1 EMPTY
13 IN CLK_DN DQ30 BI 13 20
4 IN MEM_RST V9 RESET DQ29 R3 MD_DQ21 BI 13 20 GDDR136 (1Gbit)
DQ28 R2 MD_DQ20 BI 13 20 V1 VDDQ<21> MF=1
DQ27 M3 MD_DQ19 BI 13 20 R12 VDDQ<20>
DQ26 N2 MD_DQ18 BI 13 20 R9 VDDQ<19> VSSQ<19> T12
DQ25 L3 MD_DQ17 BI 13 20 R4 VDDQ<18> VSSQ<18> T9
DQ24 M2 MD_DQ16 BI 13 20 R1 VDDQ<17> VSSQ<17> T4
WDQS3 P2 MD_WDQS2 IN 13 N12 VDDQ<16> VSSQ<16> T1
RDQS3 P3 MD_RDQS2 OUT 20 13 N9 VDDQ<15> VSSQ<15> P12
DM3 N3 MD_DM2 IN 13 V12 VDDQ<14> VSSQ<14> P9
N4 VDDQ<13> VSSQ<13> P4
MD_A<11..0> J2 A12 (1Gbit only, dual-load) DQ23 T10 MD_DQ31 BI 13 20 N1 VDDQ<12> VSSQ<12> P1
13 IN 11 L9 T11 MD_DQ30 J9 L11
A7/A11 DQ22 BI 13 20 VDDQ<11> VSSQ<11>
C 10
9
K11
M4
A8/A10 DQ21 R10
R11
MD_DQ29
MD_DQ28 BI 13 20 J4
E12
VDDQ<10> VSSQ<10> L2
G11 C
A3/A9 DQ20 BI 13 20 VDDQ<9> VSSQ<9>
8 K2 A10/A8 DQ19 M10 MD_DQ27 BI 13 20 E9 VDDQ<8> VSSQ<8> G2
7 L4 A11/A7 DQ18 N11 MD_DQ26 BI 13 20 E4 VDDQ<7> VSSQ<7> D12
6 K3 A2/A6 DQ17 L10 MD_DQ25 BI 13 20 E1 VDDQ<6> VSSQ<6> D9
5 H2 A1/A5 DQ16 M11 MD_DQ24 BI 13 20 C12 VDDQ<5> VSSQ<5> D4
4 K4 A0/A4 WDQS2 P11 MD_WDQS3 IN 13 C9 VDDQ<4> VSSQ<4> D1
3 M9 A9/A3 RDQS2 P10 MD_RDQS3 OUT 20 13 C4 VDDQ<3> VSSQ<3> B12
2 K10 A6/A2 DM2 N10 MD_DM3 IN 13 C1 VDDQ<2> VSSQ<2> B9
1 H11 A5/A1 A12 VDDQ<1> VSSQ<1> B4
0 K9 A4/A0 DQ15 G10 MD_DQ7 BI 13 20 A1 VDDQ<0> VSSQ<0> B1
MD_BA<2..0> DQ14 F11 MD_DQ6 BI 13 20
13 IN 2 H3 F10 MD_DQ5 V2 V3
RAS_N/BA2 DQ13 BI 13 20 VDD<7> VSS<7>
1 G4 BA0/BA1 DQ12 E11 MD_DQ4 BI 13 20 M12 VDD<6> VSS<6> L12
0 G9 BA1/BA0 DQ11 C10 MD_DQ3 BI 13 20 M1 VDD<5> VSS<5> L1
DQ10 C11 MD_DQ2 BI 13 20 V11 VDD<4> VSS<4> G12
13 IN MD_CKE H9 WE_N/CKE DQ9 B10 MD_DQ1 BI 13 20 F12 VDD<3> VSS<3> G1
13 IN MD_WE_N H4 CKE/WE_N DQ8 B11 MD_DQ0 BI 13 20 F1 VDD<2> VSS<2> A10
13 IN MD_CAS_N F9 CS_N/CAS_N WDQS1 D11 MD_WDQS0 IN 13 A11 VDD<1> VSS<1> V10
13 IN MD_RAS_N H10 BA2/RAS_N RDQS1 D10 MD_RDQS0 OUT 20 13 A2 VDD<0> VSS<0> A3
13 IN MD_CS1_N F4 CAS_N/CS_N DM1 E10 MD_DM0 IN 13
J3 CS1_N (1Gbit only, single-load) K12 VDDA<1>
MEM_SCAN_BOT_EN A9 G3 MD_DQ15 K1
B 4 IN MF DQ7
DQ6 F2 MD_DQ14 BI
BI
13 20
13 20
VDDA<0>
B
4 IN MEM_SCAN_EN V4 SCAN_EN DQ5 F3 MD_DQ13 BI 13 20 J12 VSSA<1>
DQ4 E2 MD_DQ12 BI 13 20 J1 VSSA<0>
21 IN MEM_D_VREF0 H1 VREF1 DQ3 C3 MD_DQ11 BI 13 20
20 IN MEM_D_VREF1 H12 VREF0 DQ2 C2 MD_DQ10 BI 13 20
DQ1 B3 MD_DQ9 BI 13 20 X802980-019
DQ0 B2 MD_DQ8 BI 13 20
WDQS0 D2 MD_WDQS1 IN 13
RDQS0 D3 MD_RDQS1 OUT 20 13
DM0 E3 MD_DM1 IN 13

ZQ A4 MD_ZQ_BOT

1 R6U1
V_MEM 243 OHM
X802980-019 1%
2 CH
402
1 R6F1
549 OHM
1%
2 EMPTY
402
MEM_D_VREF0 OUT 20 21

1 R6F2 V_MEM
1.27 KOHM C6F3 V_MEM
1% 0.1 UF MEMORY D, BOTTOM, DECOUPLING
10% MEMORY D, BOTTOM, DECOUPLING
2 EMPTY 6.3 V
A 402 X5R
402 A
C5U12 C6U10 C6F6 C7E12 C7T10 C7E1 C7D15 C7R9 C5U8 C5U5 C5U4 C5U3 C5U6 C5U7 C5U11 C5U10
0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
10% 10% 10% 10% 10% 10% 10% 10% 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 10% 10% 10% 10% 10% 10% 10% 10%
X5R X5R X5R X5R X5R X5R X5R X5R 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
402 402 402 402 402 402 402 402 X5R X5R X5R X5R X5R X5R X5R X5R
402 402 402 402 402 402 402 402

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=MEMORY PARTITION D, BOTTOM] DRAWING
Wed Feb 10 16:23:28 2010 CONFIDENTIAL
TRINITY_XDK 21/81 G 1.01

8 7 6 5 4 3 2 1
 CR-22 : @TRINITY_LIB.TRINITY(SCH_1):PAGE22

8 7 6 5 4 3 2 1
V_12P0 HANA, CLOCKS + STRAPPING R3C6
1 2
33 OHM 5%
R3C10
1
69.8 OHM 1%
2
402 CH 402 CH
R4B16 R4B7 R4B6
1 2 1 2 HANA_V_12P0_DET_R 1 2 CPU_CLK_DP OUT 2
11 KOHM 1% 787 OHM 1% 787 OHM 1% 1 FTP FT3P2
CPU_CLK_DN OUT 2
R3B9 402 CH 402 CH 402 CH R3C5 R3C9
1 2 SMC_HDMI_HPD
D 1 MOHM 5% FT3R14 FTP
1 1 C4B2 ANA_V12P0_PWRGD OUT
OUT
27
27 42
1 2 1 2 D
402 CH SMC_RST_N 27 42 59 33 OHM 5% 69.8 OHM 1%
27 ANA_RST_N 470 PF OUT 402 CH 402 CH
IN 5%
50 V 1 R3R16
Y3B1 2 EMPTY 1 KOHM 1
27 MHZ R3B3 2 402 U3B2 1 OF 4 IC FTP FT3R1
1 2 10 KOHM 5% 1 R3C4 R3C8
5% HANA 2 CH FTP FT3R3 1 2 1 2
CH 402
SM 402 1 33 OHM 5% 49.9 OHM 1%
HANA_V_12P0_DET B6 V_12P0_DET V_RST_OK E11 402 CH 402 CH
XTAL
M2 D10
2 R3R15
2 C3B6 2 C3B5 CORE_RST_N*<DN> V_12P0_OK 10 KOHM GPU_CLK_DP
1 E12 M3 5% OUT 4
FT3P1 FTP
HANA_POR_BYPASS POR_BYPASS<DN> SMC_RST_N* SMC_RST_N_R
GPU_CLK_DN
22 PF 22 PF OUT 4
V_3P3STBY 5% 5% 1 CH R3C3 R3C7
50 V 50 V 402
1 NPO 1 NPO 1 2 1 2
402 402 33 OHM 5% 49.9 OHM 1%
402 CH 402 CH
2 R3N7 HANA_XTAL_IN P2 XTAL_IN CPU_CLK_DP R14 CPU_CLK_DP_R
1 KOHM HANA_XTAL_OUT R2 XTAL_OUT CPU_CLK_DN P14 CPU_CLK_DN_R
5%
1 EMPTY R3C2 R3C1
402
HANA_XTAL_VSS_CAP P3 XTAL_VSS_CAP NB_CLK_DP R13 GPU_CLK_DP_R 1 2 1 2
NB_CLK_DN P13 GPU_CLK_DN_R 33 OHM 5% 49.9 OHM 1%
M4 402 CH 402 CH
1 FTP FT3R11
HANA_XTAL_BYPASS XTAL_BYPASS<DN>
PCIEX_CLK_DP R10 PCIEX_CLK_DP_R
1 P10
PCIEX_CLK_DP OUT 26
FT3R13 FTP PCIEX_CLK_DN PCIEX_CLK_DN_R
PCIEX_CLK_DN
C R3B11 R9 R3B21 R3B20
OUT 26
C
ANA_CLK_OE 2 1 N3 SATA_CLK_DP SATA_CLK_DP_R
1 2 1 2 1
27 IN ANA_CLK_OE_R ANA_CLK_OE<DN> P9 FTP FT3R10
SATA_CLK_DN SATA_CLK_DN_R
1 KOHM 5% 33 OHM 5% 49.9 OHM 1%
R3B10 2 402 CH R3P1 R6 402 CH 402 CH
10 KOHM 2 1 K13 SATA_CLK_REF SATA_CLK_REF_R
5%
HANA_CLK_DRV_RSET2 CLK_DRV_RSET2
475 OHM 1% HANA_CLK_DRV_RSET1 R11 CLK_DRV_RSET1
EMPTY 1 PIX_CLK_OUT_DP M15 HANA_PIX_CLK_2X_DP_R
402 402 CH
PIX_CLK_OUT_DN M14 HANA_PIX_CLK_2X_DN_R R3B19 R3B18
R3N8 1 2 1 2
2 1 P6 33 OHM 5% 49.9 OHM 1% 1
ENET_CLK ENET_CLK_R
402 CH 402 CH FTP FT2R4
475 OHM 1%
402 CH R8 SATA_CLK_DP
STBY_CLK STBY_CLK_R
OUT 26
SATA_CLK_DN OUT 26
AUD_CLK R4 AUD_CLK_R R3B17 R3B16
41 27 BI SMB_DATA N1 SMB_DATA 1 2 1 2 1 FTP FT2R3
59 27 59 55 IN SMB_CLK P1 SMB_CLK 33 OHM 5% 49.9 OHM 1%
402 CH 402 CH
AV_CLK N2 HANA_AV_CLK 1 FTP FT3N1 R3B14
1 2 SATA_CLK_REF OUT 26
33 OHM 5%
60 IN HANA_TCLK G12 TCK<DN> 402 CH 1 C3B9 1 FTP FT2P2
60 OUT HANA_TDO F11 TDO R3N5 1
HANA_TDI J12 10 KOHM 10 PF
B 60
60
IN
IN HANA_TMS F12
TDI<UP>
TMS<UP>
5%
R3C12 R3C14
5%
50 V B
60 HANA_TRST H12 TRST<DN>
CH 2 1 2 1 2 2 EMPTY
OUT 402 402
33 OHM 5% 69.8 OHM 1% 1
402 CH 402 CH FTP FT3P3
1 X802478-003
FT3P7 FTP
FT3P6 FTP
1 HANA_PIX_CLK_2X_DP OUT 4
FT3P5 FTP
1 I2C ADDRESS HANA_PIX_CLK_2X_DN OUT 4
1 0011 100 R/W HEX 0111 000 R/W HEX R3C11 R3C13
FT3P8 FTP
FT3P9 FTP
1 WRITE 0011 100 0 0X38 WRITE 0111 000 0 0X70 1 2 1 2 1 FTP FT3P4
READ 0011 100 1 0X39 READ 0111 000 1 0X71 33 OHM 5% 69.8 OHM 1%
402 CH 402 CH
0011 110 R/W HEX
WRITE 0011 110 0 0X3C
READ 0011 110 1 0X3D
R3B13
1 2 ENET_CLK OUT 32
33 OHM 5%
402 CH 1 C3B8 1
FTP FT2R5
10 PF
5%
50 V
2 EMPTY
402
R3B15
1 2 STBY_CLK OUT 27
33 OHM 5% 1 C3B10
402 CH 1 FTP FT3N2
10 PF
5%
50 V
2 EMPTY
402
A 1 FTP FT2R1 A
R3B12
1 2 AUD_CLK OUT 29
33 OHM 5%
402 CH 1 C3B7
10 PF
5%
50 V
2 EMPTY
402

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=HANA, CLOCKS + STRAPING, JTAG] DRAWING
Wed Feb 10 16:23:28 2010 CONFIDENTIAL
TRINITY_XDK 22/81 G 1.01

8 7 6 5 4 3 2 1
 CR-23 : @TRINITY_LIB.TRINITY(SCH_1):PAGE23

8 7 6 5 4 3 2 1
HANA, VIDEO + FAN + AUDIO U3B2 2 OF 4 IC
HANA L3 ANA_VID_INT
VID_INT OUT 26

GPU_PIX_CLK_1X G14 DAC_D_OUT_DP A7 VID_DACD_DP OUT 37

4 IN PIX_CLK_IN B7
D 4 IN PIX_DATA<14..0> 14 C14
DAC_D_OUT_DN
DAC_C_OUT_DP A8
VID_DACD_DN
VID_DACC_DP OUT 37
D
PIX_DATA14 B8
13 C15 DAC_C_OUT_DN VID_DACC_DN
PIX_DATA13 A9 VID_DACB_DP
STBY_CLK STITCH SATA_CLK_REF STITCH 12 D14 PIX_DATA12
DAC_B_OUT_DP OUT 37
V_1P8STBY V_3P3STBY V_1P8STBY V_3P3STBY V_3P3 V_1P8 DAC_B_OUT_DN B9 VID_DACB_DN
11 D15 PIX_DATA11
10 E14 DAC_A_OUT_DP A10 VID_DACA_DP OUT 37
PIX_DATA10 B10
9 E15 DAC_A_OUT_DN VID_DACA_DN
PIX_DATA9
8 F14 PIX_DATA8
1 C3T18 1 C3T16 1 C3T8 1 C2R8 7 F15
1 R4B13 1 R4B12 1 R4B9 1 R4B8
PIX_DATA7 37.4 OHM 37.4 OHM 37.4 OHM 37.4 OHM
0.1 UF 0.1 UF 0.1 UF 0.1 UF 6 G15 PIX_DATA6 1% 1% 1% 1%
10% 10% 10% 10% 5 H14 PIX_DATA5 2 CH 2 CH 2 CH 2 CH
6.3 V 6.3 V 6.3 V 6.3 V H15 402 402 402 402
2 X5R 2 X5R 2 X5R 2 X5R 4 PIX_DATA4
402 402 402 402 3 J14 PIX_DATA3
2 J15 PIX_DATA2 BOARD TEMP SENSOR
1 K14 PIX_DATA1
0 K15 PIX_DATA0
23 IN BRD_TEMP_P Q4G1
4 IN GPU_HSYNC_OUT L14 HSYNC_IN 2 EMPTY
4 IN GPU_VSYNC_OUT L15 VSYNC_IN V_3P3STBY 1
HANA_DAC_RSET C8 DAC_RSET
3
1 R4B10 2 R3B2 BRD_TEMP_N
787 OHM 422 OHM 23 38 OUT
1% 1%
C 2 CH 1 CH C
402 402

HSYNC_OUT B5 VID_HSYNC_OUT_R OUT 37

HDMI_HPD A4 VSYNC_OUT A5 VID_VSYNC_OUT_R OUT 37
40 IN HDMI_HPD
A2
HDMI_TXC_DP OUT 40
TMDS_EXT_SWING HDMI_EXT_SWING
29 SB_SPDIF_OUT M1 SPDIF_IN 2
C3B4
1 HDMI_TXC_DP_R
R3B8
IN 2 1
29 I2S_BCLK K1 I2S_SCK TMDS_TXC_DP B1 0.1 UF 10% 301 OHM 1%
IN I2S_WS K2 6.3 V 603 CH
29 IN I2S_WS X5R
I2S_SD3 L2 I2S_SD3 402
K4 TMDS_TXC_DN B2 HDMI_TXC_DN OUT 40
I2S_SD2 I2S_SD2
I2S_SD1 K3 I2S_SD1
HDMI_TX2_DP OUT 40
2
C3B1
1
R3B5
29 IN I2S_SD L1 I2S_SD0 HDMI_TX2_DP_R 2 1
TMDS_TX2_DP H1 0.1 UF 10% 301 OHM 1%
2 R3B4 2 R3N4 2 R3N3 6.3 V 603 CH
10 KOHM 10 KOHM 10 KOHM X5R
5% 5% 5% TMDS_TX2_DN H2 402 HDMI_TX2_DN 40
OUT
1 CH 1 CH 1 CH
B 402 402 402
HDMI_TX1_DP OUT 40 B
2
C3B2
1
R3B6
HDMI_TX1_DP_R 2 1
TMDS_TX1_DP F1 0.1 UF 10% 301 OHM 1%
6.3 V 603 CH
X5R
TMDS_TX1_DN F2 402 HDMI_TX1_DN 40
OUT
HDMI_TX0_DP OUT 40
HANA_OP2_DP C11 FAN_OP2_DP C3B3 R3B7
1 R4B15 2 1 HDMI_TX0_DP_R 2 1
10 KOHM 23 HANA_OP2_DN A11 FAN_OP2_DN
5% IN TMDS_TX0_DP D1 0.1 UF 10% 301 OHM 1%
6.3 V 603 CH
2 CH X5R
402 402
R4C1 TMDS_TX0_DN D2 HDMI_TX0_DN OUT 40
27 IN SMC_PWM0 2 1 FAN_OP1_DP C12 FAN_OP1_DP
205 KOHM 1% 1 CUSTOM THERMAL
DB4N4
402 CH 1 CALIBRATION PADS
DB4N6
ST3C5 1 C4P2 LOCATION MUST
61 4 IN CPU_TEMP_N 2 1 0.22 UF B4 HANA_SPDIF_OUT 1
DB4N5 REMAIN LOCKED
10% SPDIF_OUT OUT 37 39 1
SHORT 6.3 V 36 IN FAN1_FDBK B12 FAN_OP1_DN DDC_SCK B3 HDMI_DDC_CLK BI 27 37 40 55 DB4N7
2 X5R DDC_SDA A3 HDMI_DDC_DATA 27 37 40 55
ST3C2 402 BI
61 4 IN GPU_TEMP_N 2 1 A15 R4B14
TEMP_N B11 1 2 HANA_OP2_DN 1 C4C1
FAN_OUT2 HANA_OP2_OUT
OUT 23
SHORT 0 OHM 5% 100 PF
402 CH 5%
ST3C4
EDRAM_TEMP_N 2 1 BND_GAP_CAP A6 BND_GAP_CAP FAN_OUT1 A12 FAN1_OUT OUT 36 2 50 V
EMPTY A
A 61 4 IN 402
SHORT 1 TEMP_RSET A14 TEMP_RSET
FT4N2 FTP
1 DB3P1 TEMP3_P C13 CAL_TEMP_P CAL_TEMP_N OUT 23
ST3C3
38 23 IN BRD_TEMP_N 2 1 2 C4B3 TEMP2_P B15 CPU_TEMP_P OUT 4 61
0.01 UF R4C2 1
SHORT 10% 11 KOHM TEMP1_P B13 GPU_TEMP_P 4 61
16 V 1% OUT
ST3C1 1 X7R CH 2
CAL_TEMP_N 2 1 402 402 TEMP0_P A13 EDRAM_TEMP_P OUT 4 61
23 IN 1
FT4N1 FTP
SHORT TEMPCAL_P B14 BRD_TEMP_P OUT 23 38

X802478-003 MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=HANA, VIDEO + FAN + AUDIO] DRAWING
Wed Feb 10 16:23:28 2010 CONFIDENTIAL
TRINITY_XDK 23/81 G 1.01

8 7 6 5 4 3 2 1
 CR-24 : @TRINITY_LIB.TRINITY(SCH_1):PAGE24

8 7 6 5 4 3 2 1
HANA, POWER + DECOUPLING

D D

V_3P3STBY V_1P8STBY

V_3P3STBY U3B2 3 OF 4 IC
FB3N4 HANA
1 2 V_HANA_VAA_RTS33S D12 VAA_RTS33S VAA_VID_PLL M12
FB D11 AVSS_RTS33S AVSS_VID_PLL M13
C3N37 0.2A 603 1 C3N36 C3N38
0.5 DCR VAA_GP_PLL R7
4.7 UF 4.7 UF 0.1 UF
10% 10% 10% AVSS_GP_PLL P7
6.3 V 6.3 V 6.3 V
X5R 2 X5R X5R
805 805 402 VAA_100M_PLL_A N15
AVSS_100M_PLL_A1 P15
AVSS_100M_PLL_A0 R15
V_3P3 VAA_100M_PLL_D R12
C FB3N3 AVSS_100M_PLL_D P12
C
1 2 V_HANA_VAA_DAC33M E9 VAA_DAC33M3
VDDC_STBY_PLL N7
FB D9 VAA_DAC33M2
VSSC_STBY_PLL M7
C3N13 0.5A 603 1 C3N23 C3N20 1 C3N27 C9 VAA_DAC33M1
0.1DCR D8 AVSS_DAC33M1
4.7 UF 4.7 UF 0.1 UF 0.1 UF VDDC_25M_PLL N5
10% 10% 10% 10%
6.3 V 6.3 V 6.3 V M5
X5R 2 X5R X5R 2 6.3
X5R
V C7 VAA_DAC33M0
VSSC_25M_PLL
805 805 402 402 D7 AVSS_DAC33M0
VDDC_AUD_PLL N4
VSSC_AUD_PLL P4
C6 VAA_POR33S
VDD_DAC18S E7
C10 VAA_FAN33S
VAA_POR18S D6

VDDIO18S_100M_PLL5 N14
VDDIO18S_100M_PLL4 N13
VDDIO18S_100M_PLL3 P11
V_3P3STBY M10
VDDIO18S_100M_PLL2
R3N6 VSSIO18S_100M_PLL2 N12
1 2 V_HANA_VAA_XTAL_33S R3 VAA_XTAL33S
100 OHM 5% VDDIO18S_100M_PLL1 N9
402 CH 1 C3N17 N8 N11
B 0.1 UF P8
VDDIO33S_STBY_PLL
VSSIO33S_STBY_PLL
VSSIO18S_100M_PLL1
B
10% VDDIO18S_100M_PLL0 M9
2 6.3
X5R
V M6 VDDIO33S_25M_PLL VSSIO18S_100M_PLL0 N10
402 N6 VSSIO33S_25M_PLL
VDDIO18S_PIX_PLL L13
P5 VDDIO33S_AUD_PLL VSSIO18S_PIX_PLL L12
R5 VSSIO33S_AUD_PLL

X802478-003

V_3P3STBY V_1P8STBY V_3P3STBY V_1P8STBY

A 1 C3N22 1 C3N5 1 C3C2 1 C3C1 1 C3N34 1 C3N15 1 C3N16 1 C3N21 1 C3N26 1 C3P5 1 C3N24 1 C3N32 1 C3N14 1 C3P2 1 C3N28 1 C3P6 1 C3N25 1 C3P7 1 C3P8 1 C3P9 1 C3N35 A
4.7 UF 4.7 UF 4.7 UF 4.7 UF 4.7 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
805 805 805 805 805 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402

MICROSOFT PROJECT NAME PAGE FAB REV

DRAWING
[PAGE_TITLE=HANA, POWER + DECOUPLING] Wed Feb 10 16:23:29 2010 CONFIDENTIAL
TRINITY_XDK 24/81 G 1.01

8 7 6 5 4 3 2 1
 CR-25 : @TRINITY_LIB.TRINITY(SCH_1):PAGE25

8 7 6 5 4 3 2 1
HANA, POWER + DECOUPLING

D V_3P3STBY
D
U3B2 4 of 4 IC V_1P8STBY
HANA FB3P1
E13 VDD33S3 VDD18S21 L11 V_HANA_VDD18S 1 2
J4 VDD33S2 VDD18S20 K11 FB
J3 VDD33S1 VDD18S19 G11 0.5 603
C3 J10
1 C3P1 1 C3P3 0.2DCR 1 C3P4
VDD33S0 VDD18S18
VDD18S17 H10 0.1 UF 4.7 UF 4.7 UF
V_3P3STBY 10% 10% 10%
F4 VSSIO_33S_AVSS8 VDD18S16 J9 6.3 V 6.3 V 6.3 V
E4 VSSIO_33S_AVSS7 VDD18S15 H9 2 X5R 2 X5R 2 X5R
FB3N1 F3 M8 402 805 805
VSSIO_33S_AVSS6 VDD18S14
1 2 V_HANA_VDDIO_33S_AVCC G4 VDDIO_33S_AVCC5 VDD18S13 L8
FB G3 VDDIO_33S_AVCC4 VDD18S12 K8
C3N1 0.5 603 1 C3N3 C3N6 1 C3N7 1 C3N11 1 C3N10 C2 VDDIO_33S_AVCC3 VDD18S11 G8
0.2DCR G1 VDDIO_33S_AVCC2 VDD18S10 F8
4.7 UF 4.7 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
10% 10% 10% 10% 10% 10% C1 VDDIO_33S_AVCC1 VDD18S9 L7
6.3 V 6.3 V 6.3 V 6.3 V
X5R 2 X5R X5R 2 X5R 2 6.3
X5R
V
2 6.3
X5R
V G2 VDDIO_33S_AVCC0 VDD18S8 K7
805 805 402 402 402 402 VDD18S7 G7
A1 VSSIO_33S_AVSS5 VDD18S6 F7
E1 VSSIO_33S_AVSS4 VDD18S5 J6
J1 VSSIO_33S_AVSS3 VDD18S4 H6 1 C3N33 1 C3N30 1 C3N29 1 C3N31 1 C3N19 1 C3N39 1 C3N18
C V_3P3STBY
E2
E3
VSSIO_33S_AVSS2 VDD18S3 J5
H5 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF C
VSSIO_33S_AVSS1 VDD18S2 10% 10% 10% 10% 10% 10% 10%
J2 VSSIO_33S_AVSS0 VDD18S1 E5 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
VDD18S0 D5 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
H3 402 402 402 402 402 402 402
VDDIO_33S_PVDD1
VSS35 J13
1 C3N8 C3N12 VSS34 H13
0.1 UF 0.1 UF VSS33 G13
10% 10% VSS32 F13
2 6.3
X5R
V 6.3 V
X5R VSS31 D13
402 402 VSS30 K12
VSS29 M11
VSS28 J11
VSS27 H11
VSS26 L10
VSS25 K10
VSS24 G10
VSS23 F10
VSS22 E10
VSS21 L9
VSS20 K9
V_3P3STBY VSS19 G9
F9
B 1
FB3N2
2 D3
VSS18
VSS17 J8 B
V_HANA_VDDIO_33S_PVCC0 VDDIO_33S_PVCC0 H8
VSS16
FB E8
0.2A 603 1 C3N4 VSS15
C3N2 0.5 DCR C3N9 H4 VSSIO_33S_PVSS1
VSS14 J7
4.7 UF 4.7 UF 0.1 UF VSS13 H7
10% 10% 10% D4 VSSIO_33S_PVSS0
6.3 V 6.3 V 6.3 V VSS12 L6
X5R 2 X5R X5R VSS11 K6
805 805 402 G6
VSS10
VSS9 F6
VSS8 E6
VSS7 L5
VSS6 K5
VSS5 G5
VSS4 F5
VSS3 C5
VSS2 L4
VSS1 C4
VSS0 R1

X802478-003

A A

MICROSOFT PROJECT NAME PAGE FAB REV

DRAWING
[PAGE_TITLE=HANA, POWER + DECOUPLING] Wed Feb 10 16:23:29 2010 CONFIDENTIAL
TRINITY_XDK 25/81 G 1.01

8 7 6 5 4 3 2 1
 CR-26 : @TRINITY_LIB.TRINITY(SCH_1):PAGE26

8 7 6 5 4 3 2 1

V_1P8 V_3P3
SB, PCIEX + SMM GPIO + JTAG U3D1 1 of 6 IC
PSB VERSION A0 C3E1
PEX_TX1_DP N20 PEX_SB_GPU_L1_DP_C 1 2 PEX_SB_GPU_L1_DP 4
22 IN SATA_CLK_DP K1 SATA_CLK_DP OUT
22 IN SATA_CLK_DN J1 SATA_CLK_DN 0.1 UF 10%
6.3 V
2 R3T4 2 R3R14 2 R2R19 X5R
D 1 KOHM
5%
1 KOHM
5%
1 KOHM
5%
22 IN SATA_CLK_REF H3 SATA_CLK_REF 402 D
1 EMPTY 1 EMPTY 1 EMPTY SATA_CLK_SEL H4 SATA_CLK_SEL<UP>
402 402 402 DB2R8
C3D2
PEX_TX1_DN M20 PEX_SB_GPU_L1_DN_C 1 2 PEX_SB_GPU_L1_DN 4
TP 1 ECB_CLK_BYP A6 ECB_CLK_BYP<DN> OUT
ECB_CLK_SEL B6 ECB_CLK_SEL<DN> 0.1 UF 10%
DB3T1 6.3 V
1 U20 X5R
TP HBEDB_CLK_BYP HBEDB_CLK_BYP<DN> 402
HBEDB_CLK_SEL V20 HBEDB_CLK_SEL<DN>
DB3R2
TP 1 XUSB_CLK_BYP B15 XUSB_CLK_BYP<DN> C3E3
PEX_TX0_DP R19 PEX_SB_GPU_L0_DP_C 1 2 PEX_SB_GPU_L0_DP 4
XUSB_CLK_SEL C15 XUSB_CLK_SEL<DN> OUT
0.1 UF 10%
6.3 V
2 R2R23 22 IN PCIEX_CLK_DN L22 PEX_CLK_DP X5R
22 PCIEX_CLK_DP L21 PEX_CLK_DN 402
1 KOHM IN
5%
1 CH 4 PEX_GPU_SB_L1_DP P22 PEX_RX1_DP C3E2
IN PEX_TX0_DN P19 PEX_SB_GPU_L0_DN_C 1 2 PEX_SB_GPU_L0_DN 4
402 4 IN PEX_GPU_SB_L1_DN N22 PEX_RX1_DN OUT
0.1 UF 10%
4 IN PEX_GPU_SB_L0_DP T21 PEX_RX0_DP 6.3 V
X5R
4 IN PEX_GPU_SB_L0_DN R21 PEX_RX0_DN 402
PEX_RBIAS1 K20 PEX_RBIAS1 R2C9
C 1 C3R14 1 R3R22
PEX_RBIAS0 K19 PEX_RBIAS0 UART0_TXD D14 KER_DBG_TXD_R 2 1 KER_DBG_TXD OUT 59
C
1 R3R24 1 C3R9 47 OHM 5%
0.1 UF 499 OHM 59 KER_DBG_RXD D15 UART0_RXD<UP> 402 CH
10% 124 OHM 1% IN
6.3 V 1% 0.1 UF
2 X5R 10% 2 CH
402 2 CH 2 6.3 V 402 <DN>GPIO31 D10 SB_GPIO_RESERVED31 1
402 X5R GPIO<1> = 0 ENABLE DEBUG OUTPUT DB2R13
402 <DN>GPIO30 D11 SB_GPIO_RESERVED30 1 DB3R5
1 DISABLE DEBUG OUTPUT D12 1
<DN>GPIO29 SB_GPIO_RESERVED29
DB3R4
<DN>GPIO28 D13 SB_GPIO_RESERVED28 1 DB3R3
GPIO<0,2,3> = 111 XENON C8 1
<DN>GPIO27 SB_GPIO_RESERVED27
DB2R11
110 ZEPHYR A D9 1
<DN>GPIO26 SB_GPIO_RESERVED26
DB2R14
101 ZEPHYR B C9 1
<DN>GPIO25 SB_GPIO_RESERVED25
DB2R12
V_3P3 100 ZEPHYR C B9 1
<DN>GPIO24 SB_GPIO_RESERVED24
DB2R9
011 FALCON A9 1
GPIO23 SB_GPIO_RESERVED23
DB2R6
010 JASPER C10 1
GPIO22 SB_GPIO_RESERVED22
DB2R4
001 TRINITY B10 1
GPIO21 SB_GPIO_RESERVED21
DB2R2
1 R2R21 1 R2R22 1 R2R24 1 R2R25 1 R2R20 1 R3R9 1 R3R7 1 R3R8 GPIO20 A10 SB_GPIO_RESERVED20 1 DB2R10
10 KOHM 10 KOHM 10 KOHM 10 KOHM 10 KOHM 10 KOHM 10 KOHM 10 KOHM GPIO<5> = 0 LESS THEN 1GB SYSTEM FLASH C11 1
5% 5% 5% 5% 5% 5% 5% 5% GPIO19 SB_GPIO_RESERVED19
DB2R7
1, 1GB SYSTEM FLASH B11 1
GPIO18 SB_GPIO_RESERVED18
DB2R5
2 EMPTY 2 EMPTY 2 EMPTY 2 CH 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY GPIO17 A11 SB_GPIO_RESERVED17 1
402 402 402 402 402 402 402 402 DB2R3
GPIO16 C12 SB_GPIO_RESERVED16 1 DB3R1 SB_GPIO<0..15>
0 1 2 3 5 11 14 15 B12 15 BI 26
SB_GPIO<0..15> GPIO15
BI 26 A12 14
GPIO14
B 1 R2D15 1 R2D16 1 R2D17 1 R2D18 1 R2D14 1 R3D5 1 R3D3 1 R3D4
GPIO13 C13
B13
SCART_RGB
AUD_RST_N OUT 37
B
GPIO12 OUT 33
1 KOHM 1 KOHM 1 KOHM 1 KOHM 1 KOHM 1 KOHM 1 KOHM 1 KOHM GPIO11 A13 11
5% 5% 5% 5% 5% 5% 5% 5% C14 ANA_VID_INT
GPIO10 IN 23
2 CH 2 CH 2 CH 2 EMPTY 2 CH 2 EMPTY 2 EMPTY 2 EMPTY GPIO9 B14 WSS_CNTL0 37
402 402 402 402 402 402 402 402
A14 WSS_CNTL1 OUT
GPIO8 OUT 37 SATA_CLK V_3P3 STITCH
GPIO7 E3 PCIEX_INT OUT 26 V_3P3
GPIO6 F1 SB_GPIO_RESERVED6 OUT 26
GPIO5 F2 5
FT3T5 FTP
1 GPIO4 F3 ENET_RST_N OUT 32
V_3P3STBY FT3T4 FTP
1 GPIO3 G1 3
FT3T6 FTP
1 GPIO2 G2 2 2 C2C7 2 C2B3
1 R3G19
10 KOHM FT3T7 FTP
1
1
GPIO1 G3
G4
1
0
0.1 UF
10%
0.1 UF
10%
5% FT3T8 FTP GPIO0
6.3 V
1 TP DB2R15 1 X5R 1 6.3
X5R
V
R3D7 2 CH
402 60 IN SB_TCLK W20 TCK<DN> 1 TP DB2R16 402 402
26 OUT SB_GPIO<15> 1 2 AUD_SPI_MISO IN 35 60 OUT SB_TDO V22 TDO 1 FTP FT2R2
0 OHM 5% 1 R3D8 60 IN SB_TDI V21 TDI<UP>
402 CH 10 KOHM 60 IN SB_TMS W22 TMS<UP>
5% 60 OUT SB_TRST W21 TRST<DN>
2 EMPTY
402
X817692-001

V_3P3STBY V_3P3STBY V_3P3STBY

V_3P3STBY

1 R3G18 1 R3G20 1 R2G4 1 R2G21 A

A 10 KOHM
5%
10 KOHM
5%
10 KOHM
5%
10 KOHM
5%
R2R26 2 CH R2D19 2 CH
402 R2G3 2 CH
402 R3D10 2 CH
402
26 IN SB_GPIO_RESERVED6 1 2 402 AUD_SPI_CLK OUT 35 26 IN PCIEX_INT 1 2 AUD_SPI_MOSI OUT 35 26 IN SB_GPIO<11> 1 2 AUD_RDY_BSBY OUT 35 26 IN SB_GPIO<14> 1 2 AUD_SSB OUT 35
0 OHM 5% 1 R2E9 0 OHM 5% 1 R2E8 0 OHM 5% 1 R2G5 0 OHM 5% 1 R3D9
402 CH 10 KOHM 402 CH 402 CH 10 KOHM 402 CH
5% 10 KOHM 5% 10 KOHM
5% 5%
2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY
402 402
402 402

MICROSOFT PROJECT NAME PAGE FAB REV

DRAWING
[PAGE_TITLE=SB, PCIEX + SMM GPIO + JTAG] Wed Feb 10 16:23:29 2010 CONFIDENTIAL
TRINITY_XDK 26/81 G 1.01

8 7 6 5 4 3 2 1
 CR-27 : @TRINITY_LIB.TRINITY(SCH_1):PAGE27

8 7 6 5 4 3 2 1
SB, SMC
2 of 6 IC
U3D1
SB VERSION 106
R2C1
22 IN STBY_CLK Y12 STBY_CLK SMC_UART1_TXD B16 SMC_DBG_TXD_R 1 2 SMC_DBG_TXD OUT 59
D 22 IN SMC_RST_N C17 SMC_RST_N*
47 OHM 5%
402 CH D
C3R2 SMC_P2_GPIO7 E22 PWRSW_N 38
V_3P3STBY 1 UF
10% E21 VREG_V3P3_EN IN
SMC_P2_GPIO6 OUT 48
16 V E20 ANA_V12P0_PWRGD
X5R SMC_P2_GPIO5 IN 22
FT3R15 FTP
1 603 SMC_P2_GPIO4 E19 VREG_VEDRAM_PWRGD IN 49
SMC_P2_GPIO3 F22 ANA_RST_N OUT 22
27 IN SB_RST_N G20 SB_RST_N* SMC_P2_GPIO2 F21 VREG_VEDRAM_EN OUT 49
SMC_P2_GPIO1 F20 PSU_V12P0_EN OUT 38 42
27 IN SB_MAIN_PWRGD G19 MAIN_PWR_OK SMC_P2_GPIO0 F19 ANA_CLK_OE OUT 22

D16 SMC_UART1_RXD<UP>

59 IN SMC_DBG_EN C16 SMC_DBG<DN>

R3R6
41 OUT TRAY_OPEN 2 1 TRAY_OPEN_R A18 SMC_P4_GPIO7
33 OHM 5% SMC_P1_GPIO7 Y21 VREG_CPU_EN OUT 44
41 IN TRAY_STATUS 402 CH B18 SMC_P4_GPIO6 SMC_P1_GPIO6 Y22 VREG_CPUCORE_VCS_PWRGD IN 44 51
R2C5 AA20 VREG_V5P0_EN
C 60 59 37 IN EXT_PWR_ON_N 2 1 EXT_PWR_ON_R C18 SMC_P4_GPIO5
SMC_P1_GPIO5
SMC_P1_GPIO4 AA21 VREG_V5P0_SEL OUT
OUT
47
46 C
10 KOHM 5% SMC_P1_GPIO3 AB20 VREG_VMEM_EN OUT 50
50 BI VREG_VMEM_PWRGD_CPU_TRST_N_R 402 CH D18 SMC_P4_GPIO4 SMC_P1_GPIO2 Y20 BINDSW_N IN 38
SMC_P1_GPIO1 AA19 TILTSW_N IN 35
55 40 37 23 BI HDMI_DDC_DATA A19 SMC_P4_GPIO3 SMC_P1_GPIO0 AB19 EJECTSW_N IN 38

60 BI SMC_CPU_CHKSTOP_DETECT B19 SMC_P4_GPIO2

FT3R4 FTP
1 V_3P3STBY
R3R19
SMC_P0_GPIO7 J20 GPU_RST_DONE_R 2 1 GPU_RST_DONE IN 4
1 R3R18 1 R3R17 1 KOHM 5% 1 R3R20
1.27 KOHM 402 CH
1 1% 1.27 KOHM 10 KOHM
FT3R6 FTP 1% 5%
2 CH
402 2 CH 2 CH
59 55 41 22 BI SMB_DATA 402 C19 SMC_P4_GPIO1 402

55 41 22 59 BI SMB_CLK A20 SMC_P4_GPIO0

1 SMC_P0_GPIO6 H21 CPU_RST_N OUT 2
FT3R5 FTP

B R3R3
37 IN AV_MODE2 2 1 AV_MODE2_R B20 SMC_P3_GPIO7 B
10 KOHM 5% R3M1 1
37 IN AV_MODE1 402 CH 2 1 AV_MODE1_R B21 SMC_P3_GPIO6 R3R23 FTP FT3R12
R3R4 10 KOHM 5% SMC_P0_GPIO5 H19 SB_MAIN_PWRGD_R 2 1 SB_MAIN_PWRGD OUT 27
37 IN AV_MODE0 2 1 402 CH AV_MODE0_R C20 SMC_P3_GPIO5 1 R3R21 1 KOHM 5%
10 KOHM 5% 10 KOHM 402 CH
55 40 37 23 BI HDMI_DDC_CLK 402 CH C22 SMC_P3_GPIO4 5%
2 CH
402
47 IN VREG_V5P0_PWRGD C21 SMC_P3_GPIO3
FT4R10 FTP
1
22 IN SMC_HDMI_HPD D22 SMC_P3_GPIO2

48 IN VREG_V3P3_PWRGD D21 SMC_P3_GPIO1 H20 SB_RST_N

1 SMC_P0_GPIO4 OUT 27
FT3R9 FTP V_1P8STBY
V_3P3STBY D20 SMC_P3_GPIO0

N: DBG_LED0 PULLDOWN = SMC PRODUCTION MODE

R3D1
1 2 KOHM DBG_LED0 PULLUP = SMC DEVELOPMENT MODE 1 R3T2 1 R3T3
1 1% 100 KOHM 100 KOHM
DB2G3 CH 5% 5%
2 402 2 CH 2 CH
402 402
OUT DBG_LED0 SMC_P0_GPIO3 J19 BORONFPM_DATA BI 38
1 R3D2 SMC_P0_GPIO2 J22 BORONFPM_CLK BI 38
FT2V1 FTP
1 2 KOHM A16
1% SMC_IR_IN
2 EMPTY
402
TP 1 G22 SMC_P0_GPIO1 J21 GPU_RST_N OUT 4
DB3R7 EN_TEST1_N ENTEST1_N*<UP> H22 CPU_PWRGD
A TP
DB3R6
1 EN_TEST0_N G21 ENTEST0_N*<UP>
SMC_P0_GPIO0 OUT 2
A
35 IN IR_DATA A17 SMC_PWM1
SMC_PWM1 OUT 36
SMC_PWM0 B17 SMC_PWM0 OUT 23

X817692-001

MICROSOFT PROJECT NAME PAGE FAB REV

DRAWING
[PAGE_TITLE=SB, SMC] Wed Feb 10 16:23:29 2010 CONFIDENTIAL
TRINITY_XDK 27/81 G 1.01

8 7 6 5 4 3 2 1
 CR-28 : @TRINITY_LIB.TRINITY(SCH_1):PAGE28

8 7 6 5 4 3 2 1
SB, FLASH + USB + SPI

D N: ALL PORTS ARE DIFFERENTIAL USB PAIRS ON THIS PAGE D

U3D1 3 of 6 IC
PSB VERSION A0 R2C8
59 IN SPI_CLK U3 SPI_CLK SPI_MISO AB5 SPI_MISO_R 2 1 SPI_MISO OUT 59
59 IN SPI_MOSI Y5 SPI_MOSI 33 OHM 5%
59 IN SPI_SS_N AA5 SPI_SS_N*<UP> 402 CH

34 BI FLSH_DATA<7..0> 7 Y2 W1 FLSH_CLE
FLSH_DATA7 FLSH_CLE OUT 34
6 AA2 FLSH_DATA6
5 Y3 FLSH_DATA5 FLSH_CE_N* V3 FLSH_CE_N OUT 34
4 AA3 FLSH_DATA4
3 AB3 FLSH_DATA3 FLSH_RE_N* V2 FLSH_RE_N OUT 34
2 Y4 FLSH_DATA2
1 AA4 FLSH_DATA1 FLSH_WE_N* W3 FLSH_WE_N OUT 34
0 AB4 FLSH_DATA0
FLSH_ALE W2 FLSH_ALE OUT 34

C C
34 OUT FLSH_WP_N Y1 FLSH_WP_N*<DN>
USBB_D4_DP Y10 MUPORT_DP BI 41
USBB_D4_DN W10 MUPORT_DN BI 41

USBB_D3_DP Y8 BORONFPMPORT_DP BI 38
V_3P3STBY USBB_D3_DN W8 BORONFPMPORT_DN BI 38

USBB_D2_DP AB7 WAVEPORT_DP BI 39

USBB_D2_DN AA7 WAVEPORT_DN BI 39
2 R2T1 AB9 GAMEPORT1_DP
2.2 KOHM USBB_D1_DP BI 39
5% USBB_D1_DN AA9 GAMEPORT1_DN BI 39
1 CH
402 USBB_D0_DP AB11 GAMEPORT2_DP BI 39
USBB_D0_DN AA11 GAMEPORT2_DN BI 39
34 IN FLSH_READY V1 FLSH_READY

B B
39 BI EXPPORT_PORT2_DP W18 USBA_D3_DP
39 BI EXPPORT_PORT2_DN Y18 USBA_D3_DN

39 BI EXPPORT_PORT1_DP AA17 USBA_D2_DP

39 BI EXPPORT_PORT1_DN AB17 USBA_D2_DN

38 BI EXPPORT_RJ45_DP W16 USBA_D1_DP

38 BI EXPPORT_RJ45_DN Y16 USBA_D1_DN

39 BI EXPPORT_PORT3_DP AA15 USBA_D0_DP

39 BI EXPPORT_PORT3_DN AB15 USBA_D0_DN

SB_USB_RBIAS W12 USB_RBIAS

1 C2T13
0.1 UF 1 R2T2
10% 113 OHM
1%
2 6.3 V
EMPTY 2 CH
402 402

A X817692-001
A

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=SB,
[PAGE_TITLE=SB, FLASH
FLASH ++ USB
USB ++ SPI]
SPI] DRAWING
Wed Feb 10 16:23:29 2010 CONFIDENTIAL
TRINITY_XDK 28/81 G 1.01

8 7 6 5 4 3 2 1
 CR-29 : @TRINITY_LIB.TRINITY(SCH_1):PAGE29

8 7 6 5 4 3 2 1
SB, ETHERNET + AUDIO + SATA

D D

U3D1 4 of 6 IC
PSB VERSION A0
R2D8 R2D13
32 IN MII_TX_CLK 1 2 MII_TX_CLK_R B3 MII_TX_CLK MII_MDC_CLK_OUT E2 MII_MDC_CLK_OUT_R 1 2 MII_MDC_CLK_OUT OUT 32
33 OHM 5% 33 OHM 5%
402 CH R2D7 402 CH
32 IN MII_RX_CLK 1 2 MII_RX_CLK_R C3 MII_RX_CLK
33 OHM 5%
402 CH
32 IN MII_RXD3 D1 MII_RXD3
32 IN MII_RXD2 D2 MII_RXD2 C5 MII_TXD3
MII_RXD1 D3 MII_TXD3 OUT 32
32 IN MII_RXD1 A4 MII_TXD2
MII_RXD0 C1 MII_TXD2 OUT 32
32 IN MII_RXD0 B4 MII_TXD1
MII_TXD1 OUT 32
MII_RXDV C2 MII_TXD0 C4 MII_TXD0 OUT 32
32 IN MII_RXDV
32 IN MII_RXER B2 MII_RXER A3 MII_TXEN
MII_TXEN OUT 32
32 IN MII_COL B5 MII_COL
32 IN MII_CRS A5 MII_CRS
C 32 BI MII_MDIO E1 MII_MDIO
C
22 IN AUD_CLK A8 AUD_CLK

R2D9
I2S_MCLK_OUT C7 I2S_MCLK_R 1 2 I2S_MCLK OUT 33
R2D12 47 OHM 5%
B8 1 2 402 CH I2S_BCLK
I2S_BCLK_OUT I2S_BCLK_R
OUT 23 33
47 OHM 5% R2D11
A7 402 CH 1 2 I2S_SD
I2S_SD I2S_SD_R
OUT 23 33
R2D10 47 OHM 5%
B7 1 2 402 CH I2S_WS
I2S_WS I2S_WS_R
OUT 23 33
47 OHM 5% R2D5
HDD_RX_DP N4 C6 402 CH 1 2 SB_SPDIF_OUT
B 41
41
IN
IN HDD_RX_DN P4
SATA1_RX_DP
SATA1_RX_DN
SPDIF SPDIF_R

47 OHM 5%
OUT 23
B
402 CH
41 IN ODD_RX_DP L3 SATA0_RX_DP
41 IN ODD_RX_DN M3 SATA0_RX_DN 1 R2R14 1 R2R17 1 R2R16 1 R2R18
10 KOHM 10 KOHM 10 KOHM 10 KOHM
5% 5% 5% 5%
2 CH 2 CH 2 CH 2 CH
402 402 402 402

SATA_RBIAS U2 SATA_RBIAS

R2E1
1 C2E1 1 374 OHM
0.1 UF 1%
10% 2 CH
2 6.3
X5R
V 402
SATA1_TX_DP R2 HDD_TX_DP 41
402 P2 HDD_TX_DN OUT
SATA1_TX_DN OUT 41

SATA0_TX_DP N1 ODD_TX_DP OUT 41

SATA0_TX_DN M1 ODD_TX_DN OUT 41

X817692-001

A A

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=SB, ETHERNET + AUDIO + SATA] DRAWING
Wed Feb 10 16:23:30 2010 CONFIDENTIAL
TRINITY_XDK 29/81 G 1.01

8 7 6 5 4 3 2 1
 CR-30 : @TRINITY_LIB.TRINITY(SCH_1):PAGE30

8 7 6 5 4 3 2 1

V_1P8STBY
PSB, STANDBY POWER + DECOUPLING
V_1P8STBY V_3P3STBY

U3D1 5 of 6 IC
D PSB VERSION A0
D
FB3T2
1 2 V_AVDD_USB AB13 AVDD_USB VDD18_AUX<9> J18
FB VDD18_AUX<8> H18
C3T17 0.2A 603 1 C3T14 1 C3T11 VDD18_AUX<7> G18
0.5 DCR VDD18_AUX<6> J15
4.7 UF 2.2 UF 0.1 UF
10% 10% 10% VDD18_AUX<5> H15
6.3 V 6.3 V
X5R 2 X5R 2 6.3
X5R
V
VDD18_AUX<4> R14
805 ST3T1 603 402 VDD18_AUX<3> H14
1 2 V_AVSS_USB AA13 AVSS_USB VDD18_AUX<2> R12 V_1P8STBY
VDD18_AUX<1> P12
FB3T1 SHORT VDD18_AUX<0> R9
1 2 V_CMPAVDD18_USB Y13 CMPAVDD18_USB
FB 1 C3T13 1 C3T10 1 C3T6 C2T6 C3R12 C3R13
0.2A 603 0.1 UF 0.1 UF 0.1 UF 0.1 UF
0.5 DCR 2.2 UF 0.1 UF 10% 10% 10% 10%
10% 10% 6.3 V 6.3 V 6.3 V 6.3 V
ST2T2 2 6.3 V
2 6.3 V 2 X5R X5R X5R X5R
X5R X5R 402 402 402 402
1 2 603 402 V_CMPAVSS18_USB W13 CMPAVSS18_USB
SHORT
V13 VDD18_USB<9>
V12 VDD18_USB<8>
C FB2T3
1 2
V11
V10
VDD18_USB<7>
C
V_VDD18_USB VDD18_USB<6>
FB V9 VDD18_USB<5>
1 C2T16 0.5 603 1 C2T15 1 C2T14 1 C2T10 1 C2T11 V8 VDD18_USB<4>
4.7 UF 0.2DCR V7 VDD18_USB<3> VDD33_AUX<14> V19 SB BALLS V18 AND V19 ARE IN THE
10% 10 UF 0.1 UF 0.1 UF 0.1 UF
6.3 V 20% 10% 10% 10% Y6 VDD18_USB<2> VDD33_AUX<13> D19 LOWER RIGHT HAND OF THE CHIP
2 X5R 2 6.3 V
2 6.3 V
2 6.3 V
2 6.3 V W6 VDD18_USB<1> VDD33_AUX<12> V18
805 X5R X5R X5R X5R THEY HAVE BEEN ISOLATED
805 402 402 402 V6 VDD18_USB<0> VDD33_AUX<11> F18
VDD33_AUX<10> E18 FOR BETTER POWER ROUTING
VDD33_AUX<9> E17
VDD33_AUX<8> D17
VDD33_AUX<7> E16
VDD33_AUX<6> E15
VDD33_AUX<5> W5
VDD33_AUX<4> V5
VDD33_AUX<3> U5
VDD33_AUX<2> W4
VDD33_AUX<1> V4
VDD33_AUX<0> U4

B B

VSS_USB<25> Y19
VSS_USB<24> W19
VSS_USB<23> AB18
VSS_USB<22> AA18
V_3P3STBY VSS_USB<21> Y17
VSS_USB<20> W17
FB3T3 VSS_USB<19> AB16 V_3P3STBY
1 2 V_CMPAVDD33_USB Y14 CMPAVDD33_USB VSS_USB<18> AA16
FB VSS_USB<17> Y15
0.2A 603 VSS_USB<16> W15
C3T19 0.5 DCR 1 C3T15 1 C3T12 1 C3T9 AB14
VSS_USB<15>
4.7 UF 2.2 UF 0.1 UF 0.1 UF VSS_USB<14> AA14
10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V VSS_USB<13> AB12 C3R1 C3R4
2 2 2 0.1 UF 0.1 UF
X5R X5R X5R X5R VSS_USB<12> AA12 10% 10%
805 ST3T2 603 402 402 Y11 6.3 V 6.3 V
1 2 W14 VSS_USB<11> X5R X5R
V_CMPAVSS33_USB CMPAVSS33_USB W11 402 402
VSS_USB<10>
VSS_USB<9> AB10
SHORT
VSS_USB<8> AA10
FB3R1 VSS_USB<7> Y9
1 2 VSS_USB<6> W9
V_VDD33_USB V17 VDD33_USB<3>
VSS_USB<5> AB8
FB V16 VDD33_USB<2> AA8
A C3R5 0.2A
0.5 DCR
603
1 C3T4 1 C3T7 V15
V14
VDD33_USB<1>
VSS_USB<4>
VSS_USB<3> Y7 A
4.7 UF VDD33_USB<0> W7
10% 2.2 UF 0.1 UF VSS_USB<2>
6.3 V 10% 10% VSS_USB<1> AB6
X5R 6.3 V 6.3 V AA6
805 2 X5R 2 X5R VSS_USB<0>
603 402
X817692-001

MICROSOFT PROJECT NAME PAGE FAB REV

DRAWING
[PAGE_TITLE=PSB, STANDBY POWER + DECOUPLING] Wed Feb 10 16:23:30 2010 CONFIDENTIAL
TRINITY_XDK 30/81 G 1.01

8 7 6 5 4 3 2 1
 CR-31 : @TRINITY_LIB.TRINITY(SCH_1):PAGE31

8 7 6 5 4 3 2 1
PSB, MAIN POWER + DECOUPLING
V_SBPCIE V_1P8
U3D1 6 of 6 IC
FB3R2 PSB VERSION A0
1 2 V_AVDD_PEX L19 AVDD_PEX VDD18<17> U19
L20 U18
V_1P8
FB V_AVSS_PEX AVSS_PEX VDD18<16>
D 1 C3T2 0.2A
0.5 DCR
603
1 C3R16 1 C3R15 T18
VDD18<15> R15
P15
D
4.7 UF V_VDD_PEX_FB VDD_PEX<4> VDD18<14>
10% 2.2 UF 0.01 UF R18 VDD_PEX<3> VDD18<13> M15
6.3 V 10% 10%
2 X5R 6.3 V 16 V P18 VDD_PEX<2> VDD18<12> M14 1 C3R11 1 C3R10 1 C3R7 1 C2R20 1 C3R18 1 C3R8 1 C2R14 1 C2T4 1 C3R17
805 2 X5R 2 X7R N18 VDD_PEX<1> VDD18<11> J12 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
ST3R1 603 402 M18 H12 10% 10% 10% 10% 10% 10% 10% 10% 10%
1 2 VDD_PEX<0> VDD18<10>
R11 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
VDD18<9> 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
SHORT VDD18<8> J11 402 402 402 402 402 402 402 402 402
VDD18<7> H11
R3T1 VDD18<6> M9
1 2 U22 VDD18<5> H9
VSS_PEX<15> R8
0 OHM % T22 VDD18<4>
805 CH 1 C3T5 1 C3T3 1 C3T1 VSS_PEX<14> P8
R22 VDD18<3>
VSS_PEX<13> M8
4.7 UF 0.1 UF 0.01 UF M22 VDD18<2>
10% 10% 10% VSS_PEX<12> J8
K22 VDD18<1>
2 6.3
X5R
V
2 6.3
X5R
V
2 16
X7R
V
U21
VSS_PEX<11>
VSS_PEX<10>
VDD18<0> H8 V_1P8
805 402 402 P21 VSS_PEX<9>
N21 VSS_PEX<8>
M21 VSS_PEX<7> V_3P3
K21 VSS_PEX<6>
T20 C2T9 C2R17 1 C2T12
VSS_PEX<5>
R20 VSS_PEX<4> VDD33<13> E14 1 UF 1 UF 4.7 UF
10% 10% 10%
P20 E13 16 V 16 V
C T19
VSS_PEX<3> VDD33<12>
E12 X5R X5R 2 6.3
X5R
V
N19
VSS_PEX<2>
VSS_PEX<1>
VDD33<11>
VDD33<10> E11 603 603 805 C
M19 VSS_PEX<0> VDD33<9> E10
VDD33<8> E9
VDD33<7> D8
V_1P8 VDD33<6> D7
VDD33<5> D6
FB2R3 VDD33<4> G5
1 2 VDD33<3> D5
V_AVDD1_SATA J3 AVDD1_SATA
VDD33<2> F4
FB V_AVSS1_SATA J2 AVSS1_SATA
1 C2R10 1 C2T7 0.2A 603 VDD33<1> E4
0.5 DCR 1 C2R19 1 C2R18 H1 VDD33<0> D4 V_3P3
4.7 UF 4.7 UF V_AVDD0_SATA AVDD0_SATA
10% 10% 2.2 UF 0.1 UF V_AVSS0_SATA H2 AVSS0_SATA
6.3 V 6.3 V 10% 10%
2 X5R 2 X5R 2 6.3 V
2 6.3 V
805 805 X5R X5R V_CMPAVDD_SATA U1 CMPAVDD_SATA
ST2R2 603 402 T1 1 C2R12 1 C2R11 1 C2R13 1 C3R6 1 C2R9
1 2 V_CMPAVSS_SATA CMPAVSS_SATA
0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
V_VDD_SATA T5 VDD_SATA<5> 10% 10% 10% 10% 10%
SHORT VSS<41> N15 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V
R5 VDD_SATA<4> 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
VSS<40> L15
P5 VDD_SATA<3> 402 402 402 402 402
VSS<39> K15
FB2R2 N5 VDD_SATA<2>
VSS<38> P14
1 2 M5 VDD_SATA<1> N14
B FB
L5 VDD_SATA<0>
VSS<37>
VSS<36> L14 B
0.2A 603 VSS<35> K14
0.5 DCR 1 C2R15 1 C2R16 J14
VSS<34>
2.2 UF 0.1 UF VSS<33> R13
10% 10%
6.3 V 6.3 V VSS<32> P13
2 X5R 2 X5R VSS<31> N13
ST2R1 603 402 M13
1 2 VSS<30>
VSS<29> L13 V_3P3
VSS<28> K13
SHORT
VSS<27> J13
FB2T2 VSS<26> H13
1 2 VSS<25> N12 1 C2R7
FB
VSS<24> M12 C3R3
VSS<23> L12 1 UF 4.7 UF
0.2A 603 10% 10%
0.5 DCR 1 C2T8 1 C2T5 VSS<22> K12 16 V 6.3 V
2.2 UF 0.1 UF VSS<21> P11 X5R 2 X5R
10% 10% N11 603 805
VSS<20>
6.3 V 6.3 V M11
2 X5R 2 X5R VSS<19>
ST2T1 603 402 T4 VSS_SATA<18> VSS<18> L11
1 2 R4 VSS_SATA<17> VSS<17> K11
M4 VSS_SATA<16> VSS<16> R10
SHORT L4 VSS_SATA<15> VSS<15> P10
K4 VSS_SATA<14> VSS<14> N10
J4 VSS_SATA<13> VSS<13> M10
FB2T1 T3 VSS_SATA<12> VSS<12> L10
1 2 R3 VSS_SATA<11> VSS<11> K10
FB P3 VSS_SATA<10> VSS<10> J10
0.5 603 1 C2T1 1 C2T3 1 C2T2 N3 VSS_SATA<9> VSS<9> H10
A 0.2DCR
10 UF
20%
0.1 UF
10%
0.1 UF
10%
K3
T2
VSS_SATA<8> VSS<8> P9
N9
A
VSS_SATA<7> VSS<7>
6.3 V 6.3 V 6.3 V N2 L9
2 X5R 2 X5R 2 X5R VSS_SATA<6> VSS<6>
805 402 402 M2 VSS_SATA<5> VSS<5> K9
L2 VSS_SATA<4> VSS<4> J9
K2 VSS_SATA<3> VSS<3> N8
R1 VSS_SATA<2> VSS<2> L8
P1 VSS_SATA<1> VSS<1> K8
L1 VSS_SATA<0> VSS<0> A15

X817692-001

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=PSB, MAIN POWER + DECOUPLING] DRAWING
Wed Feb 10 16:23:30 2010 CONFIDENTIAL
TRINITY_XDK 31/81 G 1.01

8 7 6 5 4 3 2 1
 CR-32 : @TRINITY_LIB.TRINITY(SCH_1):PAGE32

8 7 6 5 4 3 2 1
PSB OUT, ETHERNET

D D
MICREL AND ATHEROS ENET PHY
NOTE : THIS PAGE OF THE SCHEMATIC DISPLAYS ONLY THE MICREL PART AND ITS ASSOCIATED STUFFING OPTIONS.
THE NO STUFF PARTS WILL BE STUFFED ALONG WITH THE ATHEROS PHY AND WILL BE IMPLEMENTED AS A BOM STUFFING OPTION..

DEFAULT ETHERNET PHY ADDRESS = 00001

V_3P3 AUTO_NEGOTIATION ENABLED BY DEFAULT USING INTERNAL PULL-UP ON LED0/NWAYEN
AUTO MDIX ENABLED BY DEFAULT
FB2C1
1 2 V_ENET
0.1DCR
0.5A 603
1 C2C8 2 C2C9 1 C2D3 1 C2P4 1 C2P5 1 R2R10 1 R2D4
10 UF 0.1 UF 0.1 UF 0.1 UF U2D1 IC 1 R2R9 4.75 KOHM 4.75 KOHM
4.7 UF 20% 10% 10% 10% FB2R1 1 KOHM 1% 1%
10% 6.3 V 6.3 V 6.3 V 6.3 V 1 2 ETHERNETPHY_KSZ8041NL_AR8032 1%
2 6.3 V 1 X5R 2 X5R 2 X5R 2 X5R EMPTY 2 EMPTY 2 CH 2 CH
X5R 805 402 402 402 0 OHM R2D6 5% 402 402
805 0.5A 603 402
402 1 2 CH 0.1DCR VDD_V3P3_V2P5IP 17 VDDIO_3.3 VDD2.5 INTRP INTP 21
1 2 VDDA_V3P3_V2P5OP 3 VDDA_3.3 VDD25_REG RXDV/CRSDV/CONFIG2 RX_DV 18 MII_RXDV OUT 29
0 OHM CRS/CONFIG1 CRS 29 MII_CRS 29
1 C2R6 402 R2R2 5%
CH COL/CONFIG0 COL 28 MII_COL OUT
29
1 C2P3 1 C2D5 1 C2D2 OUT
10 UF 1 R2R15 1 R2R7 1 R2R12
C 20%
6.3 V
10 UF
20%
0.1 UF
10%
1 UF
10% 1 KOHM 1 KOHM 1 KOHM C
2 X5R 2 6.3 V
2 25 V
2 10 V 1% 1% 1%
805 X5R EMPTY EMPTY 2 EMPTY 2 EMPTY 2 EMPTY
805 603 402 402 402 402

R2R3
2 1 ENET_1.8VEXT 2 VDDPLL_1.8 VDD3
1 C2C10 0 OHM 5% 1 C2D1 1 C2P2
402 EMPTY 0.1 UF 10 UF
1 UF 10% 20%
+80%/-20% 25 V 6.3 V
50 V X7R X5R
2 EMPTY 2 603 2 805
805

DB2R1
1 ENET_REF_CLK_OUT 8 XO XO RXC RXC 19 MII_RX_CLK OUT 29
22 IN ENET_CLK 9 XI/REFCLK XI TXC TXC 22 MII_TX_CLK OUT 29

26 IN ENET_RST_N 2 1 ENET_REXT 10 REXT RST#

0 OHM R2R5 5% 1 R2R1 1 R2D1
402 EMPTY 1 C2R5
B 10 KOHM
1%
6.81 KOHM
1%
100 PF
5% B
50 V
2 EMPTY 2 CH NPO
1 R2D2 402 402 2 402
4.75 KOHM
1%
2 CH
402
29 BI MII_MDIO 11 MDIO MDIO
29 IN MII_MDC_CLK_OUT 12 MDC MDC

29 IN MII_TXEN 23 TXEN/TX_EN TXEN RXER/RX_ER/ISO RXER 20 MII_RXER OUT 29

29 IN MII_TXD3 27 TXD3 TXD3 RXD3/PHYAD0 RXD[3] 13 MII_RXD3 OUT 29
29 IN MII_TXD2 26 TXD2 TXD2 RXD2/PHYAD1 RXD[2] 14 MII_RXD2 OUT 29
29 IN MII_TXD1 25 TXD1/TXD_1 TXD1 RXD1/RXD_1/PHYAD2 RXD[1] 15 MII_RXD1 OUT 29
29 IN MII_TXD0 24 TXD0/TXD_0 TXD0 RXD0/RXD_0/DUPLEX RXD[0] 16 MII_RXD0 OUT 29
2 R2R11 1 R2R13
1 KOHM 1 KOHM
1% 1%
1 EMPTY 2 EMPTY
402 402

38 BI ENET_RX_DN 4 RX- RX TX- TX- 6 ENET_TX_DN BI 38

38 BI ENET_RX_DP 5 RX+ RX+ TX+ TX+ 7 ENET_TX_DP BI 38
R2R8
26 IN ENET_RST_N 1 2 ENET_RSTN_R 32 RST# REXT
0 OHM 5%
402 CH GND_DECOUPLE 1 GND VDD12_REG LED1/SPEED LED1 31 ENET_ACT_N
33 GNDSLUG PAD LED0/NWAYEN LED0 30 ENET_LINK_N
1 R2R6 1 R2D3 1 R2R4 1 C2R3 C2D4
A 2.37 KOHM
1%
10 KOHM
1%
0 OHM
5%
0.1 UF 1 1 UF
10% 10%
A
25 V 16 V X819763-001 QFN
2 EMPTY 2 CH 2 CH EMPTY EMPTY
402 402 402 2 603 2 603

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=PSB OUT, ETHERNET] DRAWING
Wed Feb 10 16:23:30 2010 CONFIDENTIAL
TRINITY_XDK 32/81 G 1.01

8 7 6 5 4 3 2 1
 CR-33 : @TRINITY_LIB.TRINITY(SCH_1):PAGE33

8 7 6 5 4 3 2 1
PSB OUT, AUDIO

D D

V_3P3
R3B22
1 2 V_AUD

0 OHM %
805 CH 1 C3B11 1 C3B12 1 C3A7 1 C3A6 1 C3A5
1 U3A5 IC
FT3N3 FTP 2.2 UF 0.1 UF 0.1 UF 2.2 UF 0.1 UF
10% 10% 10% AUDIODAC_CSS4354_WM1824 10% 10%
6.3 V 6.3 V 6.3 V 6.3 V
2 X5R 2 X5R 2 X5R 2 X5R 2 6.3
X5R
V
603 402 402 6 VCP LINEVDD VBIAS VMID 18 V_AUD_BIAS 603 402
17 VA AVDD
3 VL DBVDD
20 1_2VRMS NC
VFILT_P NC 8 V_AUD_FILT_P

1 C3A8 1 C3M4 1 C3M6

C 0.15 UF 1 UF 1 UF C
10% 10% 10%
10 V 16 V 16 V
2 X5R 2 X5R 2 X5R
402 603 603

FLYP_P NC 7 V_AUD_FLYP_P

1 C3N41
2.2 UF
10%
FB3A2
1 2 AUD_L_OUT
FLYP NC 5 V_AUD_FLYP_N 2 6.3
X5R
V
0.7DCR
OUT 37
603 0.2 603
1 R3A10
R3A8 2 C3A4 10 KOHM
I2S_MCLK 2 15 1 2 1%
29 IN MCLK MCLK AOUTA LINEVOUTL AUD_VOUTL AUD_VOUTL_R 1000 PF
10% 2 CH
1.33 KOHM 1% 50 V 402
29 IN I2S_BCLK 1 SCLK BCLK 402 CH 1 X7R
AOUT_REF NC 14 402
29 IN I2S_WS 23 LRCK LRCLK
R3A9 2 C3A3 1 R3A11
29 IN I2S_SD 24 SDIN DACDAT AOUTB LINEVOUTR 13 AUD_VOUTR 1 2 AUD_VOUTR_R 1000 PF 10 KOHM
1.33 KOHM 1% 10% 1%
B 402 CH 1 50 V
X7R
402
2 CH
402 B
FLYN_P CPCA 9 V_AUD_FLYN_P FB3A1
1 C3A9 1 2 AUD_R_OUT OUT 37
0.7DCR
2.2 UF 0.2 603
10%
6.3 V
FLYN CPCB 11 V_AUD_FLYN_N 2 X5R
603
26 IN AUD_RST_N 19 RESET MUTE

FT3M6 FTP
1 1 R3M6
1 KOHM
5%
2 CH VFILT CPVOUTN 12 V_AUD_FILT_N
402
1 C3A10 1 C3M2 1 C3M3
0.15 UF 10 UF 10 UF
10% 10% 10%
10 V
22 PS_N/LJ AIFMODE AGND AGND 16 2 X5R 2 10 V
X5R 2 10
X5R
V
DGND NC 4 402 805 805
21 DEM NC CPGND LINEGND 10

ME GNDPAD 25

X851154-002 QFN25

A A

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=PSB OUT, AUDIO] DRAWING
Wed Feb 10 16:23:30 2010 CONFIDENTIAL
TRINITY_XDK 33/81 G 1.01

8 7 6 5 4 3 2 1
 CR-34 : @TRINITY_LIB.TRINITY(SCH_1):PAGE34

8 7 6 5 4 3 2 1
PSB OUT, FLASH

D D

V_3P3STBY

N: STUFFED AT CONFIG LEVEL

1 R1T9 1 R1T10 1 R1T5 1 C1T2 1 C1T3 1 C2T18
10 KOHM
5% 10 KOHM 10 KOHM
5% 5% 4.7 UF 0.1 UF 0.1 UF
FT1T8 FTP
1 2 EMPTY 10% 10% 10%
1 402 2 CH 2 CH 2 6.3 V
2 6.3 V
2 6.3 V
FT1T7 FTP 402 402 X5R X5R X5R
FT1T6 FTP
1 805 402 402 U1E2 IC
1
C FT1T5
FT1T4
FTP
FTP
1 NAND FLASH
7 FLSH_READY C
1 RDY OUT 28
FT1T3 FTP R1T14
FT1T2 FTP
1 38 2 1
1 NC<27> FLSH_NC38
FT1T1 FTP 37 VCC1 NC<26> 48 0 OHM 5%
12 VCC0 NC<25> 47 402 EMPTY
1 FTP FT1T11 46
FLSH_DATA<7..0> NC<24>
28 IN 7 44 45
DATA<7> NC<23>
6 43 DATA<6> NC<22> 40
5 42 DATA<5> NC<21> 39
4 41 DATA<4> NC<20> 35
3 32 DATA<3> NC<19> 34
2 31 DATA<2> NC<18> 33
1 30 DATA<1> NC<17> 28
0 29 DATA<0> NC<16> 27
NC<15> 26
1 R1T8 1 R1T11 1 R1T12 1 R1T13 1 R1T15 1 R1T16 1 R1T17 1 R1T18 28 IN FLSH_CE_N 9 CE_N* NC<14> 25
10 KOHM 10 KOHM 10 KOHM 10 KOHM 10 KOHM 10 KOHM 10 KOHM 10 KOHM 28 FLSH_RE_N 8 RE_N* NC<13> 24
5% 5% 5% 5% 5% 5% 5% 5% IN FLSH_WE_N 18 23
28 IN WE_N* NC<12>
2 CH 2 EMPTY 2 CH 2 CH 2 CH 2 CH 2 CH 2 CH 28 FLSH_WP_N 19 WP_N* NC<11> 22
402 402 402 402 402 402 402 402 IN FLSH_ALE 17 21
28 IN ALE NC<10>
28 IN FLSH_CLE 16 CLE NC<9> 20
15
B 6 VSS/NC
NC<8>
NC<7> 14 B
36 VSS1 NC<6> 11
13 VSS0 NC<5> 10
NC<4> 5
NC<3> 4
NC<2> 3
NC<1> 2
NC<0> 1

X818098-001 TSOP

XSB SOUTHBRIDGE PSB SOUTHBRIDGE

FLSH_DATA0 N: RETAIL=16MB
N: XDK=64MB FLSH_DATA[1:0] FLASH CONFIGURATION
FLSH_DATA1

0 1 0X0 0.5KB, 16KB BLOCKS, 16MB

0 8MB 16MB 0X1 0.5KB, 16KB BLOCKS, 16MB RETAIL
0X2 2KB PAGES, 128KB BLOCKS, VARIOUS SIZES (256MB) XDK
1 32MB 64MB 0X3 4KB PAGES, 256KB BLOCKS, VARIOUS SIZES
A A

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=PSB OUT, FLASH] DRAWING
Wed Feb 10 16:23:30 2010 CONFIDENTIAL
TRINITY_XDK 34/81 G 1.01

8 7 6 5 4 3 2 1
 CR-35 : @TRINITY_LIB.TRINITY(SCH_1):PAGE35

8 7 6 5 4 3 2 1
CONN, INFARED + ACCELEROMETER + SWITCHES + AUDIBLE F/B
ACCELEROMETER TILT SWITCH, SOLICO
V_3P3STBY V_1P8STBY V_3P3STBY V_3P3STBY
D 1 R2N5 1 R2N6
D
0 OHM 0 OHM 1 R5G1
5% 5% SM 10 KOHM
1 R2N7 TILT 5%
2 EMPTY 2 EMPTY SW5G2 2 CH
402 402 10 KOHM
5% SM 402
V_BMA
2 EMPTY 4 1 R5G2
1 C2N5 1 C2N4 1 R2N4 402 3 2 TILTSW_N_R 2 1 TILTSW_N OUT 27
0 OHM
5% 10 KOHM 5%
1 R1N5 1 R1N4 0.1 UF 0.1 UF X800550-004 402 CH
2.2 KOHM 2.2 KOHM 10% 10% 2 EMPTY
6.3 V 6.3 V 402
5% 5% 2 EMPTY 2 EMPTY R2N8
Q1N3 1 2 EMPTY 2 EMPTY 402 402 U2N1 EMPTY TILTSW_N_R2 1 2
EMPTY 402 402
BMAX20 0 OHM 5%
PMBUS_CLK SOT23 3 2 2 11 1 402 EMPTY
55 IN PMBUS_CLK_FET VDD CAPZ CAPZ
DB2N1
10 VDDIO CAPY 12 CAPY 1
DB2N2 3
R2N3 5 CSB CAPX 1 CAPX 1
DB2N3 Q2N1
1 2 7 SCL INT 4 ACCELEROMETER_INT 1
0 OHM 5% Q1N2 1 9 SDA SDO 8 EMPTY
402 EMPTY EMPTY BMA_PS_R 6 PS VSS 3 2
PMBUS_DATA SOT23 3 2
61 58 57 56 55 44 BI PMBUS_DATA_FET X851300-001 LGA12
C 1
R2N2
2 C
0 OHM 5%
402 EMPTY

IR MODULE V_3P3STBY

R6G1
V_IR 1 2 1
49.9 OHM 1%
402 CH TH
C5G6 1 C5G7 2 R3R11 X850477-001 POWER BUTTON 2 TH
4.7 UF 0.1 UF 10 KOHM SWITCH
10% 10% 5% I186
6.3 V 6.3 V
X5R 2 X5R 1 CH U1F5
805 402 402
U6G1 IC
SW3G1
TH
IR THR X853774-001
4 1 PWRSW_N_R IN 38
VCC 3 3 2
B DATA 1
2
IR_DATA OUT 27
B
GND
ME2 5
ME1 4
X821027-001 1

U1G3
AUDIBLE FEEDBACK SMT
V_3P3STBY X851794-001

U3G4 IC J1F1
1 1X2HDR
ISD2130 FTP FT3V6
14 VCCO SPK_P 7 SPKR_DRIVE_P 1
10 VCCD_PWM1 SPK_N 9 SPKR_DRIVE_N 2
6 VCCD_PWM0 INTB/GPIO3 11 1
FTP FT3V7
1 C3G13 1 C3V5 1 C3V4 1 C3G14 1 C3V6 20 NC5 RDY/BSYB/GPIO4 12 TH
19 15 HDR
4.7 UF 0.01 UF 1000 PF 4.7 UF 0.1 UF NC4 GPIO5
10% 10% 10% 10% 10% 2 18 NOTE: SPEAKER HEADER
SCLK/GPI1 NC3
16 V 16 V 50 V 16 V 6.3 V 4 1
2 X5R 2 X7R 2 X7R 2 X5R 2 X5R MOSI/GPIO0 MISO/GPIO2 EJECTSW_N 38
1206 402 402 1206 402 3 SSB NC2 17 IN
8 VSSD_PWM NC1 16 AUD_RDY_BSBY IN 26
5 VSSD NC0 13
21
PWRSW_N IN 38
A
GND
AUD_SPI_MISO OUT 26
A
26 IN AUD_SPI_CLK
QFN21 X851696-001 1
FTP FT2V4
26 IN AUD_SPI_MOSI 1
FTP FT2R7
26 IN AUD_SSB
1
FT2T4 FTP
1
FT2T5 FTP
FT2R6 FTP
1

DRAWING MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=CONN,INFRARED+ACCELEROMETER+SWITCHES+AUDIBLE F/B] Wed Feb 10 16:23:31 2010
CONFIDENTIAL
TRINITY_XDK 35/81 G 1.01

8 7 6 5 4 3 2 1
 CR-36 : @TRINITY_LIB.TRINITY(SCH_1):PAGE36

8 7 6 5 4 3 2 1
CONN, FAN

D D

V_12P0

R4A7
2 1 V_3P3
5.11 KOHM 1%
402 EMPTY V_12P0
2
FAN1_Q1_C 1 Q5A2
MJD210 1 R5A3
3 EMPTY 4.75 KOHM
3 1 C6A7 1 C5A12 1%
23 FAN1_OUT 1 Q4A1 3 100 UF
IN 20% 1 UF 2 CH
EMPTY D4A1 16 V 10% 402
2 1N4148
C SOT23 2 EMPTY
RDL 2 16
X5R
V
C

FAN_PULLUP
1 EMPTY 603
J5A4

FAN1_Q1_E
2 C4P1 1X4HDR
2700 PF 1
10%
2
1 50 V
EMPTY R5A9 3
402 V_FAN1 1 2 4
2 R4A1
100 OHM 0 OHM %
5% 805 EMPTY 1 C5A15 HDR
1 EMPTY 1 UF
402 10%
16 V
2 EMPTY
1 R5M5

FAN1_FDBK_R
603
30.1 KOHM
1%
2 EMPTY
402
R5M3
2 1
5.11 KOHM1% FAN1_FDBK OUT 23
402 EMPTY
1 R5M4
B 11 KOHM
1% B
2 EMPTY
402

FAN CONTROL
R5A10
27 IN SMC_PWM1 SMC_PWM1_R

33 OHM 5%
402 CH

A A

MICROSOFT PROJECT NAME PAGE FAB REV

DRAWING
[PAGE_TITLE= CONN, FAN] Wed Feb 10 16:23:31 2010 CONFIDENTIAL
TRINITY_XDK 36/81 G 1.01

8 7 6 5 4 3 2 1
 CR-37 : @TRINITY_LIB.TRINITY(SCH_1):PAGE37

8 7 6 5 4 3 2 1
V_5P0
1
RT3A1
2
CONN, AVIP DAC STANDARD ADVANCED SDTV HDTV SCART VGA
V_AVIP OUT 39 40
01.10 A THRMSTR 1 C2A8
1206 C2A2 A N/A Y(LUMA) Y Y G G
4.7 UF 470 PF
10% 5% J4A2 CONN
D 23 IN HANA_SPDIF_OUT 2 6.3 V
X5R
50 V
X7R XENON AVIP CONNECTOR B N/A C(CHROMA) PR PR R R D

1
805 402 29
1 C2A3 EG2A1 V_AVIP
X807267-001 27 V_AVIP_RET
22 PF ESDB-MLP7
5% C N/A N/A PB PB B B
DIO VID_DACA_OUT 4 VID_DACA_OUT
2 50
NPO
V
402
37 IN 2 VID_DACA_RET
402
D CVBS(COMP) CVBS(COMP) CVBS N/A CVBS CVBS

2
37 IN VID_DACB_OUT 3 VID_DACB_OUT
1 VID_DACB_RET
EXT_PWR_ON 30 EXT_PWR_ON_N OUT 59 60 27 37 61
37 IN VID_DACC_OUT 8 VID_DACC_OUT
6 VID_DACC_RET DDC_CLK 21 HDMI_DDC_CLK BI 23 27 40 55
V_12P0 DDC_DATA 23 HDMI_DDC_DATA BI 23 27 40 55
37 IN VID_DACD_OUT 7 VID_DACD_OUT
5 VID_DACD_RET AV_MODE2 28 AV_MODE2 OUT 27 37
AV_MODE1 24 AV_MODE1 OUT 27 37
VID_HSYNC_OUT 11 20 AV_MODE0
402 1% CH
37 IN VID_HSYNC_OUT AV_MODE0 OUT 27 37
1.82 KOHM

9
1

VID_HSYNC_RET
R3A5

GND<2> 26
37 IN VID_VSYNC_OUT 12 VID_VSYNC_OUT GND<1> 22
2

10 VID_VSYNC_RET GND<0> 18
R3A3 Q3A1
WSS_CNTL_B
25 SPDIF SHIELD<3> 34
WSS_CNTL1 1 2
C 26 IN
5.36 KOHM 1%
3 6
AUD_R_OUT 15
SHIELD<2> 33
32 C
402 CH 33 IN AUD_R_OUT SHIELD<1> V_3P3STBY
5 2 13 AUD_R_RET SHIELD<0> 31
33 IN AUD_L_OUT 16 AUD_L_OUT MTGB<8-1>
R3A4 XSTR 14 AUD_L_RET MTGA<8-1>
26 IN WSS_CNTL0 1 2 4 1 1 R3R2 1 R2N1 1 R3R1 1 R2C3
R3A2 10 KOHM 10 KOHM 10 KOHM 10 KOHM
2 WSS_CNTL_E

4.75 KOHM 1% WSS_CNTL_OUT_R 2 1 WSS_CNTL_OUT 17 WSS_CNTL 5% 5% 5% 5%

402 CH 19
1 KOHM 5% SCART_RGB 2 CH 2 CH 2 CH 2 CH
10 KOHM 5%

EXT_PWR_ON_N 402 402 402 402

301 OHM 1%
CH

402 CH 60 59 37 IN
2 C3A1 37 IN AV_MODE2
2
CH
R3A6

R3A1

X806743-001 TH 37 IN AV_MODE1
75 PF 37 AV_MODE0
5% IN
603

V_3P3 50 V
402
1

1 NPO
402 1 C3A2 1 C2M2 1 C2M1 1 C2C2
SCART_RGB_OUT 470 PF 470 PF 470 PF 470 PF
5% 5% 5% 5%
50 V 50 V 50 V 50 V
2 X7R 2 X7R 2 X7R 2 X7R
R3M3 2 402 402 402 402
26 SCART_RGB 2 1 SCART_RGB_R 1 Q3M1
IN
10 KOHM 5% XSTR
402 CH 3 R3M7 LAYOUT:PLACE CLOSE TO CONNECTOR
B SCART_RGB_OUT_R 1 2
B
402 5% CH

33 OHM 5% EMI CAPS

1
10 KOHM
R3M2

402 CH 1 C3M1
0.01 UF
10%
2

16 V
2 X7R
402

L4A4 L4A2
23 VID_DACA_DP 1 2 VID_DACA_OUT 37 23 VID_DACC_DP 1 2 VID_DACC_OUT 37
R4B20
IN OUT IN OUT 23 IN VID_VSYNC_OUT_R 1 2 VID_VSYNC_OUT OUT 37
IND IND 49.9 OHM 1%
1210 1210

1
402 CH
1

1 R4A5 1 R4A3 EG4A9

EG4A8 1 C4A10 1 C4A3 EG4A6 1 C4A8 1 C4A5
75 OHM 75 OHM X807267-001
X807267-001 1% X807267-001 1%
62 PF 75 PF 62 PF 75 PF ESDB-MLP7
ESDB-MLP7 5% 5% ESDB-MLP7 5% 5%
DIO
2 CH 50 V 50 V DIO
2 CH 50 V 50 V
DIO
402 2 NPO 2 NPO 402 2 NPO 2 NPO 402
402 402 402 402 402 402

2
2

L4A3 L4A1 R3B24

VID_DACB_DP 1 2 VID_DACB_OUT VID_DACD_DP 1 2 VID_DACD_OUT 23 IN VID_HSYNC_OUT_R 1 2 VID_HSYNC_OUT OUT 37
23 IN OUT 37 23 IN OUT 37
49.9 OHM 1%
A

1
IND IND 402 CH
A 1210 1210 EG4A10
1

1 R4A4 X807267-001
EG4A7 1 C4A9 1 C4A6 EG4A5 2 C4A7 2 C4A4
75 OHM 1 R4A2 ESDB-MLP7
X807267-001 1% X807267-001
62 PF 75 PF 75 OHM 62 PF 75 PF DIO
ESDB-MLP7 5% 5% ESDB-MLP7 5% 5%
DIO
2 CH 50 V 50 V DIO
1%
50 V
402
402 2 NPO 2 NPO 2 CH 1 NPO 1 50
NPO
V

2
402 402 402 402 402 402 402
2

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=[CONN, AVIP] DRAWING
Wed Feb 10 16:23:31 2010 CONFIDENTIAL
TRINITY_XDK 37/81 G 1.01

8 7 6 5 4 3 2 1
 CR-38 : @TRINITY_LIB.TRINITY(SCH_1):PAGE38

8 7 6 5 4 3 2 1
CONN, RJ45 USB AUX COMBO + BORON + PWR
V_12P0
RJ45 AUX COMBO J2A1 CONN

RT3A2 TRINITYRJ45AUX
1 2 V12P0_EXPPORT_RJ45 17 V12P0
18
D 01.50 A THRMSTR C2A13
100 UF
C2A11
470 PF
C2A12
4.7 UF
GND3
D
1206 20% 5% 10%
1 16 V 50 V 16 V
FT2M2 FTP ELEC X7R X5R
RDL 402 805
V_5P0
RT1B1 J2A1.16 HAS A DFM REQUIREMENT
2 1 FOR THIEVING PADS 16
V5P0_EXPPORT_RJ45 V5P0
1 C2A10 15 GND2
01.10 A THRMSTR 2 C2A14 2 C2A5
1206 220 UF A DFM REQUIREMENT
20% 470 PF 4.7 UF OF THIEVING PADS 19 SPARE2
1 10 V 5% 10%
FT2M1 FTP ELEC 50 V 6.3 V DFM_THIEVING_PADS_REQUIREMENT3 20 SPARE3
2 RDL 1 X7R 1 X5R
402 805 EXPPORT_RJ45_DN 13
28 BI D-
28 EXPPORT_RJ45_DP 14 D+
BI

1
EG2A3 EG2A2 12 SPARE1
X807267-001 X807267-001 1
ENET_TX_DP LED_LEFT_A
32 IN ESDB-MLP7 ESDB-MLP7 2 LED_LEFT_C

1
1 R2A2 DIO DIO
EG2A4
49.9 OHM 402 402 3
1% X807267-001 LED_RIGHT_A
4

2
ESDB-MLP7 LED_RIGHT_C
2 CH C2A7 EMPTY
402 ENET_TX_TERM 1 2
1 R2A3 402
C 49.9 OHM 0.1 UF 10%
C

2
1% 6.3 V 11 TD+
X5R 10
2 CH 402 TCT
32 IN ENET_TX_DN 402 7 TD-

32 IN ENET_RX_DP 9 RD+
1 R2A4 6

1
RCT
49.9 OHM EG2A5 EG2A6 5
1% RD-
X807267-001 X807267-001
2 CH C2A6 ESDB-MLP7 ESDB-MLP7 V_3P3
402 ENET_RX_TERM 1 2 EMPTY EMPTY FB2M1
8 GND1
1 R2A5 402 402 2 1 V_ENET_CT
49.9 OHM 0.1 UF 10%
6.3 V 1 C2M6 FB 1 C2M5 C2M3 C2M4
2

2
1% 0.5A 603
X5R 4.7 UF 4.7 UF 0.1 UF 0.1 UF
2 CH 402 10% 0.1DCR 10% 10% 10%
402 6.3 V 6.3 V 6.3 V 6.3 V 21 EMI1
32 IN ENET_RX_DN X5R X5R X5R X5R 22
1

EG2A7
2 805 2 805 402 402 EMI2
23 EMI3
X807267-001 24 EMI4
ESDB-MLP7
EMPTY
402
X820106-001 TH

BORON FPM
2

B J5G2 CONN B
V_3P3STBY V_3P3STBY V_3P3STBY V_3P3STBY ST7A1
BORON CONN 2 1 VREG_V12P0_ISENSE_N 58
12
OUT
V_3P3STBY
1 R4G5 1 R3V6 1 R4G4 1 C5G1 2 C5G2 SHORT
100 KOHM 100 KOHM 100 KOHM
2 CH
5%
402
5%
2 CH
402 2 CH
5%
402
100 UF
20%
16 V
ELEC
470 PF
5%
50 V
X7R
POWER 1
R7A1
10 MOHM
2 2
ST7A2
1 VREG_V12P0_ISENSE_P
OUT 58
2 RDL 1 402 1% SHORT
2512
BORONFPMPORT_DN 5 1 CH J7A1 CONN
28 BI D- DB6M2 V_12P0
28 BI BORONFPMPORT_DP 6 D+ DB6M3
1 TRINITY PWR
1 R7A2
DB6N1
4 FT7N1 FTP
1 1 2 V_12P0_IN 5 V12P01
R4G6 SPARE1 6 V12P02
27 OUT BINDSW_N 1 2 BINDSW_N_R 13 BINDSW_N 1 C7B2 1 C7A3 1 C7A2 1 C7A1 1 C7A4 10 MOHM 7
470 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 1% V12P03
10 KOHM 1% R4V1 20% 10% 10% 10% 10% 2512 8 V12P04
BRD_TEMP_N 402 CH 1 2 7 16 V 25 V 25 V 25 V 25 V
BRD_TEMP_N_R FP_TEMP_N CH
23 OUT
0 OHM 5% R4V2 2 POLY
TH 2 X7R
603 2 X7R
603 2 X7R
603 2 X7R
603
23 IN BRD_TEMP_P 402 CH 1 2 BRD_TEMP_P_R 1 FP_TEMP_P
R3V5 0 OHM 5% R6A6
PWRSW_N 1 2 402 CH 27 IN PSU_V12P0_EN 1 2 PSU_V12P0_EN_R 9 PSU_EN
35 27 OUT 1 R6A5 100 OHM 5% 1 C6A2 1 C6A3
10 KOHM 5% 10 KOHM 402 CH
35 OUT PWRSW_N_R 402 CH 8 FP_PWR 5% 0.1 UF 470 PF
2 CH 10% 5%
402 6.3 V 50 V
2 X5R 2 EMPTY
V_5P0STBY 402 402
R4G7
A 35 27 OUT EJECTSW_N 2 1 EJECTSW_N_R 10 ODD_EJECT DB6M1
1
1 10
A
10 KOHM 5% FT6M1 FTP VSB5P0
27 BI BORONFPM_DATA 402 CH 2 C_DATA
27 BI BORONFPM_CLK 3 C_CLK 1 C6A5 1 C6A4 1 C6A1 1 GND1
100 UF 100 UF 2
20% 20% 470 PF GND2
2 C5G5 2 C5G4 2 C5G3 9 GND1 16 V 16 V 5% 3 GND3
470 PF 470 PF 11 ELEC ELEC 50 V 4
470 PF 5% 5% GND2 2 RDL 2 RDL 2 X7R GND4
N: BORONFPMPORT_DX IS A USB DIFFERENTIAL PAIR. 50 V 50 V 14 ME1 402 11 ME1 MTGA[9..1]
5% X7R X7R
50 V 1 1 15 ME2 12 ME2 MTGB[9..1]
1 X7R 402 402 16 ME3
402 17 ME4 X819467-001 TH

X819886-001 TH PROJECT NAME PAGE FAB REV

MICROSOFT
DRAWING
[PAGE_TITLE=CONN, RJ45 AUX COMBO + BORON + PWR] Wed Feb 10 16:23:31 2010 CONFIDENTIAL
TRINITY_XDK 38/81 G 1.01

8 7 6 5 4 3 2 1
 CR-39 : @TRINITY_LIB.TRINITY(SCH_1):PAGE39

8 7 6 5 4 3 2 1
CONN, USB + MEM PORTS + TOSLINK + WAVEPORT
N: ALL DIFFERENTIAL PAIRS ON THIS PAGE ARE USB DIFFERENTIAL PAIRS. TH
V_5P0DUAL J1A2 CONN
V_5P0DUAL
USB TRIPLE

D RT6G1 HORIZONTAL DUAL USB VERTICAL TRIPLE USB CONN

D
2 1 V_GAMEPORT1 RT2M1
01.10 A THRMSTR 1 C6G1 2 C6G2 2 C6G3 2 1 V_EXPPORT_DUAL1 1 V+
1206 220 UF 470 PF 4.7 UF
20% 5% 10% 01.10 A THRMSTR
10 V 50 V 6.3 V 2 C1N5
ELEC X7R X5R 1206 1 C1B9 2 C1A8
2 RDL 1 402 1 805 220 UF 4.7 UF
20% 470 PF 10%
10 V 5%
2 ELEC 1 50 V 1 6.3
X5R
V
28 BI GAMEPORT1_DN RDL X7R
402
805 BOTTOM PORT
28 BI GAMEPORT1_DP
1

1
EG6G1 EG6G2
X807267-001 X807267-001
ESDB-MLP7 ESDB-MLP7
J6G1 USB
DIO DIO EXPPORT_PORT1_DN 2
402 402 1 VBUS USBX2 28 BI DATA -
V_5P0DUAL 2 28 BI EXPPORT_PORT1_DP 3 DATA +
D- 4
2

2
3 GND
D+

1
4 GND EG1A8 EG1A7
RT7V1 X807267-001 X807267-001
2 1 V_GAMEPORT2 5 VBUS ESDB-MLP7 ESDB-MLP7
1 C7G1 6 D- DIO DIO
01.10 A THRMSTR 2 C7G2 2 C7V1 7
1206 220 UF 470 PF D+ 402 402
C 20%
10 V
5% 4.7 UF
10%
8 GND V_5P0DUAL
C

2
50 V
2 ELEC
RDL 1 X7R
402 1 6.3
X5R
V
9 ME
805 10 ME RT1M2
28 BI GAMEPORT2_DN X820108-001 TH 2 1 V_EXPPORT_DUAL2 5 V+
28 BI GAMEPORT2_DP
01.10 A THRMSTR
1

1206 1 C2A9 2 C1A9 2 C1N1

EG7G1 EG7G2 220 UF
X807267-001 X807267-001 20% 470 PF 4.7 UF
ESDB-MLP7 ESDB-MLP7 10 V 5% 10%
50 V
DIO DIO 2 ELEC
RDL 1 X7R 1 6.3
X5R
V
MIDDLE PORT
402 402 402 805
2

V_3P3 WAVE PORT 28

28
BI
BI
EXPPORT_PORT2_DN
EXPPORT_PORT2_DP
6
7
DATA -
DATA +
FB1A1 8 GND

1
1 2 EG1A4 EG1A3
B 0.2A
EMPTY
603 2 2
X807267-001 X807267-001
B
C1A7 C1A1 ESDB-MLP7 ESDB-MLP7
0.5 DCR DIO DIO
470 PF 4.7 UF
5% 10% V_5P0DUAL 402 402
50 V 6.3 V
R1A1 X7R 1 X5R 1 J1A1 CONN

2
1 2 402 805 wavereceptacle
0 OHM 5% 1 VCC GND1 2 RT1M1
WAVEPORT_DN 402 CH 3 5
28 BI D- GND2 2 1 9
WAVEPORT_DP 4 7
V_EXPPORT_DUAL3 V+
28 BI D+ EMI1
6 TBD EMI2 8 01.10 A THRMSTR
9 1206 1 C1A3
ME1 2 C1A6 2 C1A2
1

EG1A1 EG1A2 220 UF

X820104-001 TH 20% 470 PF 4.7 UF
X807267-001 X807267-001 10 V 5% 10%
ESDB-MLP7 ESDB-MLP7 50 V
EMPTY EMPTY
2 ELEC
RDL 1 X7R 1 6.3
X5R
V
402 805
402 402
TOP PORT
2

28 BI EXPPORT_PORT3_DN 10 DATA -
TOSLINK J4A1
TOSLINK
CONN 28 BI EXPPORT_PORT3_DP 11
12
DATA +
GND

1
37 IN V_AVIP 2 VCC EG1A6 EG1A5
A 23 IN HANA_SPDIF_OUT 3
1
VIN X807267-001 X807267-001
13
A
GND ESDB-MLP7 ESDB-MLP7 EMI1
1

EG4A1 DIO DIO 14 EMI2

1 C4A1 4 15
X807267-001 EMI1 402 402 EMI3
22 PF ESDB-MLP7 5 EMI2 16 EMI4
5%

2
50 V DIO
2 NPO 402
402
X802398-001 TH
2

X820107-001

MICROSOFT PROJECT NAME PAGE FAB REV

DRAWING
[PAGE_TITLE=CONN, MEMORY PORTS + GAME PORTS] Wed Feb 10 16:23:31 2010 CONFIDENTIAL
TRINITY_XDK 39/81 G 1.01

8 7 6 5 4 3 2 1
 CR-40 : @TRINITY_LIB.TRINITY(SCH_1):PAGE40

8 7 6 5 4 3 2 1
1
FT3M7 FTP
FT3M1 FTP
1 CONN, HDMI
23 IN HDMI_TX2_DP
23 IN HDMI_TX2_DN

1
D FT3M2 FTP
1 EG3A2
X807267-001
EG3A1
X807267-001
D
1 ESDB-MLP7 ESDB-MLP7
FT3M8 FTP DIO DIO
402 402

2
1
FT3M9 FTP
1
FT3M3 FTP

23 IN HDMI_TX1_DP
23 IN HDMI_TX1_DN

1
EG3A4 EG3A3
1 X807267-001 X807267-001
FT3M4 FTP ESDB-MLP7 ESDB-MLP7
1 DIO DIO
FT3M10 FTP 402 402

2
1
FT3M11 FTP
1
C FT3M5 FTP J3A1 HDR
C
HDMI
23 IN HDMI_TX0_DP 1 TMDS_DATA2_DP
2 TMDS_DATA2_SHD
23 IN HDMI_TX0_DN 3 TMDS_DATA2_DN
4
1

1
1 TMDS_DATA1_DP
FT4M2 FTP EG4A2 EG3A5 5 TMDS_DATA1_SHD
1 X807267-001 X807267-001 6
FT4M7 FTP TMDS_DATA1_DN
ESDB-MLP7 ESDB-MLP7 7 TMDS_DATA0_DP
DIO DIO 8 TMDS_DATA0_SHD
402 402 9 TMDS_DATA0_DN
10
2

2
TMDS_CLK_DP
11 TMDS_CLK_SHD
1 12 TMDS_CLK_DN
FT4M8 FTP
1 HDMI_CEC 13 CEC
1 DB3M1
FT4M3 FTP 14 RESERVED
15 SCL
16 SDA
23 IN HDMI_TXC_DP 17 DDC_CEC_GND
23 IN HDMI_TXC_DN 18 5VCC
19 HOT_PLUG_DET
1
1

EG4A3 23
B FT4M4 FTP
1 EG4A4
X807267-001
X807267-001 22
ME4
ME3 B
1 ESDB-MLP7 21
FT4M9 FTP ESDB-MLP7 ME2
DIO 20
DIO ME1
402
402
2

X806395-002
2

V_5P0STBY
1
FTP FT4M6
R4M6
1 R4M2 1 R4M1 HDMI_HPD_PIN 1 2 HDMI_HPD OUT 23
1 2 KOHM 2 KOHM
FT4M5 FTP 1% 1% 10 KOHM 5%
402 CH
2 CH 2 CH
402 402

1
37 27 23 IN HDMI_DDC_CLK 1 R4M5 EG4M5
55 37 27 23 HDMI_DDC_DATA 47.5 KOHM X807267-001
BI 1%
ESDB-MLP7
1

EG4M2 EG4M1
2 CH DIO
402
1 X807267-001 X807267-001 402
FT4M1 FTP
ESDB-MLP7 ESDB-MLP7

2
DIO DIO
402 402
2

A A
37 IN V_AVIP
1 C2A1
0.1 UF
10%
6.3 V
2 X5R
402

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=CONN, HDMI] DRAWING
Wed Feb 10 16:23:31 2010 CONFIDENTIAL
TRINITY_XDK 40/81 G 1.01

8 7 6 5 4 3 2 1
 CR-41 : @TRINITY_LIB.TRINITY(SCH_1):PAGE41

8 7 6 5 4 3 2 1
CONN, ODD + HDD + MU
C1B11
29 IN HDD_TX_DP 1 2 HDD POWER
D 0.01 UF 10% V_5P0
D
16 V
X7R
402 J5B2
HDD_TX_DP_C 1
FTP FT1N4 RT5A1 1X5HDR2
1 2 V_HDD 1
HDD_TX_DN_C 1
FTP FT1N5 2

1
EG1B4 THRMSTR 1 C4B10 1 C5B17 3

1
HDD_TX_DN 1
C1B10
2
EG1B3 X807267-001 HDD SATA 1206
4.7 UF
10%
0.1 UF
10%
4
29 IN X807267-001 ESDB-MLP7
6.3 V 6.3 V
0.01 UF 10%
ESDB-MLP7 DIO J1B2 2 X5R 2 X5R
16 V DIO 402 SATA 805 402 X819489-001
X7R 402 9
TH

2
402

2
1
2
3
4
5
C1B7 6
29 HDD_RX_DN 1 2 7
OUT
0.01 UF 10%
16 V
8 MEMORY UNIT
C X7R
402 CONN C
HDD_RX_DN_C 1
FTP FT1N6 V_3P3 V_3P3STBY
HDD_RX_DP_C 1
FTP FT1N7
1

1
C1B8 EG1B1 EG1B2
29 HDD_RX_DP 1 2 1 C1D1 1 C1D2
OUT X807267-001 X807267-001
0.01 UF 10% ESDB-MLP7 ESDB-MLP7 4.7 UF 0.1 UF
16 V 1 10% 10% R1D5
DIO DIO FTP FT1N8 6.3 V
X7R
402 402 402
2 X5R 2 6.3
X5R
V 1 2
805 402 0 OHM 5%
402 EMPTY J1D1
2

1 1X6HDR
FT2U2 FTP R1D6
FT2U3 FTP
1 1 2 V_MUPORT 1
0 OHM 5% 2
28 BI MUPORT_DN 402 CH 3
28 BI MUPORT_DP 4
R2C11 5
ODD POWER DECOUPLING 59 55 27 22 BI SMB_DATA 1 2 SMB_DATA_MU_R 6
0 OHM 5%
402 CH CONN
B V_12P0 V_5P0 V_3P3 SMB_CLK
R2C10
1 2 SMB_CLK_MU_R
SMT
B
59 27 IN
0 OHM 5%
402 CH
1 C5A6 C5A8 C5A11 C5A7 C4A14 C5A14
4.7 UF 0.1 UF 4.7 UF 0.1 UF 4.7 UF 0.1 UF
ODD SATA 10%
16 V
10%
25 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
10%
6.3 V
2 X5R X7R X5R X5R X5R X5R
C1B4 805 603 805 402 805 402
29 ODD_TX_DP 1 2 ODD_TX_DP_C 1
IN FTP FT1N2
0.01 UF 10%
16 V
X7R
402

C1B3 J1B1
ODD_TX_DN 1 2 1
29 IN ODD_TX_DN_C
FTP FT1N3
9
SATA
ODD POWER AND CONTROL
0.01 UF 10%
16 V
X7R 1
402 2
3 R4A6
4 27 OUT TRAY_STATUS 1 2 TRAY_STATUS_R
C1B1
29 ODD_RX_DN 1 2 ODD_RX_DN_C 5 100 OHM 5%
OUT 6 402 CH
0.01 UF 10% 7 V_3P3
16 V J4A3
X7R 1 8
V_5P0 1
402 FTP FT1M4 V_12P0 4 3 TRAY_OPEN
A C1B2 CONN 6 5 IN 27
A
29 ODD_RX_DP 1 2 ODD_RX_DP_C 1 8 7 1 C4A11
OUT FTP FT1M3
10 9
0.01 UF 10% 75 PF
16 V 12 11 5%
X7R
402
2 50
NPO
V
1 CONN 402
FTP FT1M5

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=CONN, ODD + HDD + MU] DRAWING
Wed Feb 10 16:23:32 2010 CONFIDENTIAL
TRINITY_XDK 41/81 G 1.01

8 7 6 5 4 3 2 1
 CR-42 : @TRINITY_LIB.TRINITY(SCH_1):PAGE42

8 7 6 5 4 3 2 1
VREG, BLEEDERS

D D

V_5P0STBY V_12P0
C V_5P0DUAL
C
1 R6A7 1 R6A8 1
2.2 KOHM 2.2 KOHM V_12P0 DB1E1
5% 5%
2 CH 2 CH
402 402 1 R1T7 1 R1T6 1 R1T3
R6A9 3 10 KOHM 20 OHM 20 OHM
1 2 BLEEDER_V12P0_B2 1 Q6M1 5% 5% 5%
2 CH 2 CH 2 CH
549 OHM 1% XSTR 402 1206 1206
402 CH 24
BLEEDER_V12P0_C1

BLEEDER_V12P0_C2
BLEEDER_V12P0_LOAD

1 R5M2 1 R6M2 1 R5M1 1 R6M1

BLEEDER_C1

BLEEDER_C2
10 OHM 10 OHM 10 OHM 10 OHM
1% 1% 1% 1%
3 2 CH 2 CH 2 CH 2 CH
Q6A2 805 805 805 805
FET 3
1 3.2 OHM
2 SOT23 1 Q1T2
3
R6A3 XSTR
27 PSU_V12P0_EN 2 1 BLEEDER_V12P0_B1 1 Q6A1 3 2
IN R1T1
B 2.2 KOHM 5%
402 CH
XSTR 22 IN SMC_RST_N 2 1 BLEEDER_B 1 Q1T1 B
2
10 KOHM 5% XSTR
R6A4 402 CH 2
22 IN ANA_V12P0_PWRGD 2 1
2.2 KOHM 5%
402 CH

V_5P0DUAL BLEEDER
V_12P0 & V_5P0 BLEEDERS

A A

MICROSOFT PROJECT NAME PAGE FAB REV

DRAWING
[PAGE_TITLE= VREGS,_BLEEDERS] Wed Feb 10 16:23:32 2010 CONFIDENTIAL
TRINITY_XDK 42/81 G 1.01

8 7 6 5 4 3 2 1
 CR-43 : @TRINITY_LIB.TRINITY(SCH_1):PAGE43

8 7 6 5 4 3 2 1
VREGS, INPUT + OUTPUT FILTERS

D R7P3 D
2 IN CPU_VREG_APS6 1 2 6
R7P4 0 OHM 5%
CPU_VREG_APS5 1 2 402 CH
2 IN 5 VID CODE=1.050V
0 OHM 5% R7P5
CPU_VREG_APS4 402 CH 1 2 4
2 IN
0 OHM 5% V_MEM
R7P6 402 CH
2 IN CPU_VREG_APS3 1 2 3
0 OHM 5% R7P7
CPU_VREG_APS2 402 CH 1 2 2
2 IN
0 OHM 5% 1 R7C15 1 R7C16 1 R7C17 1 R7C18 1 R7C19 1 R7C20
R7P8 402 CH 10 KOHM 10 KOHM 10 KOHM 10 KOHM 10 KOHM 10 KOHM
2 IN CPU_VREG_APS1 1 2 1 5% 5% 5% 5% 5% 5%
0 OHM 5% 2 CH 2 EMPTY 2 CH 2 CH 2 EMPTY 2 CH
402 CH 402 402 402 402 402 402

6 5 4 3 2 1 VREG_CPU_VID<6..1> OUT 44 61

C C

V_12P0
V_CPUCORE INPUT FILTER
L6B1
V_VREG_CPU OUT 44 45
0.45 UH IND
9 A TH
1 C7B1 0.0042 OHM C6B1 C7B3 1 C6B3 1 C6B5
470 UF 470 UF
4.7 UF 20% 20% 4.7 UF 4.7 UF
10% 16 V 16 V 10% 10%
16 V 16 V
2 X5R
POLY
TH
POLY
TH 2 X5R 2 16
X5R
V
1206 1206 1206

B B

1 DB6R2
1 DB6R1
V_CPUCORE V_CPUCORE OUTPUT FILTER 1 FTP FT6R2

OUT

C6C3 C6C1 C5C3 C6C2 C7C12 C7C13

820 UF 820 UF 820 UF 820 UF 820 UF 820 UF
20% 20% 20% 20% 20% 20%
2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V
POLY POLY POLY POLY POLY POLY
RDL RDL RDL RDL RDL RDL
1
FTP FT6R1

A A

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=VREGS, INPUT + OUTPUT FILTERS] DRAWING
Wed Feb 10 16:23:32 2010 CONFIDENTIAL
TRINITY_XDK 43/81 G 1.01

8 7 6 5 4 3 2 1
 CR-44 : @TRINITY_LIB.TRINITY(SCH_1):PAGE44

8 7 6 5 4 3 2 1
VREGS, CPU CONTROLLER
R7C11
43 IN V_VREG_CPU 1 2 VREG_CPU_VCC OUT 44
681 OHM 1%
603 CH R7B5 RRAMP R7C4 C7C10 1 C7C11 VREG_CPU_VCC3_3P3
1 2 VREG_CPU_RAMPADJ_R 1 2 4.7 UF 1 UF
D R7C12 1 KOHM 5% 422 KOHM 1% 10% 10% D
1 2 16 V 16 V 1 C7C9 R7C13 2
681 OHM 1%
402 CH 402 CH X5R 2 X5R 0.1 UF
10 KOHM
603 CH
2 C7P2 1206 603 10% 5%
0.1 UF 6.3 V U7C1 IC CH 1 1
10% 2 X5R 402 FTP FT3T2
VREG_CPU_EN 25 V 402 NCP4201
27 IN 1 X7R 1 VCC3 PWRGD 40 VREG_CPUCORE_VCS_PWRGD 51
1 R7C10 603 30
OUT 27
1 VCC
FT3T3 FTP 10 KOHM VID7 31
5% 11 32 6
VREG_CPU_VID<6..1> IN 43
VREG_CPU_RAMPADJ RAMPADJ VID6
2 CH VID5 33 5
402
6 EN/VTT VID4 34 4 VID'S HAVE INTERNAL PULL DOWNS
VID3 35 3
55 IN PMBUS_CLK 5 SCL VID2 36 2
61 58 57 56 55 35 BI PMBUS_DATA 4 SDA VID1 37 1
VID0 38
R7C7 1 VREG_CPU_SW4 22 SW4
45 IN VREG_CPU_PHASE2 1 2 DB7C2
1 23 39
DB7C3
VREG_CPU_SW3 SW3 PSI_N*
0 OHM 5% R7C9 VREG_CPU_PHASE2_R 24 SW2
VREG_CPU_PHASE1 402 CH 1 2 25 26 VREG_CPU_VCC
45 IN VREG_CPU_PHASE1_R SW1 PWM4 OUT 44
2 KOHM 1% PWM3 27
61 OUT VREG_CPU_CSCOMP 402 CH 18 CSCOMP PWM2 28 VREG_CPU_PWM2 OUT 45
PWM1 29 VREG_CPU_PWM1 OUT 45
61 OUT VREG_CPU_CSSUM 17 CSSUM 21 1
C VREG_CPU_CSREF 16
OD1_N*
ODN_N* 20
VREG_CPU_OD1_N
DB7C1
VREG_CPU_DRV_EN OUT 45 C
61 OUT CSREF
VREG_CPU_FB 15 FB
1 ALERT* 2 VREG_CPU_ALERT_N 1
RTH1 FT7P1 FTP DB7P1
FAULT* 3 VREG_CPU_FAULT_N 1
VREG_CPU_COMP 14 COMP DB7P2
R6C2
1 2 IMON 8 VREG_CPU_IMON
VREG_CPU_FBRTN 13 FBRTN
RT 10 VREG_CPU_RT
603 THRMSTR

VREG_CPU_CSCOMP_R
VREG_CPU_TRDET 12 TRDET
TEMP SENSOR GND 7
RCS2 VREG_CPU_IREF 9 IREF
41
1 R7C5
R7B1 R7C1 GND_SLUG 909 KOHM
1 2 1 2 VREG_CPU_ILIMITFS 19 ILIMITFS 1%
35.7 KOHM 1% CCS2 CCS1 6.81 KOHM 1% 2 CH
RPH2
RPH1 RCS1
402 CH
C7C1 1 1 C7C3 402 CH
NEED TO SET DURING VALIDATION
X817912-001
402
3300 PF 3300 PF
R7B3 2 2 R7B4 2 R7B2 10% 10%
27.4 KOHM 27.4 KOHM 52.3 KOHM 50 V 50 V 2 R7C6
1% 1% 1% X7R 2 2 X7R 121 KOHM
ROSC = 909K
402 402 FOSC = 250KHZ
CH 1 1 CH 1 CH 1%
402 402 402 1 CH
402 PARTS ARE TRIMMED AT FACTORY SUCH THAT VBOOT=1.05V
B B
I2C ADDRESS
1100 000 R/W HEX
WRITE 1100 000 0 0XC0 1 R7C8
READ 1100 000 1 0XC1 1 C7C7 5.76 KOHM
V_CPUCORE 0.1 UF 1%
1 10% 2 CH
FT7P2 FTP 6.3 V
2 X5R 402
PLACE SHORT NEXT TO 402
OUTPUT OF DUAL INDUCTOR
ST6C1 VREG_CPU_FBRTN
1 2 NOTE: VALID UP TO 58A
C7P1 1 C7C6
SHORT 2 1
1000 PF
VENABLE 10%
1000 PF 10% 50 V
CB 50 V 2 X7R
X7R 402
ST6D1 VREG_V_CPUCORE_S R7C14 1
C7C2
2
402
1 1 2 VREG_CPU_FB
2 0 OHM %
SHORT 805 EMPTY 470 PF 5% CFB
1 C7C4
50 V
1 X7R 10 PF
DB7C5 402 5%
1 DB7C6
RB
CA
RA 2 50
NPO
V
R7P1 1
C7C5
2
R7P2 402
1 2 VREG_CPU_COMP_R 1 2
1.1 KOHM 1% 18.2 KOHM1% ST6D2
PLACE SHORT NEXT TO 402 CH 1500 PF 10% 402 CH 1 2
POINT OF LOAD 50 V
X7R
A 402 SHORT A
PLACE SHORT NEXT TO
POINT OF LOAD
R7C2 R7C3
1 2 VREG_CPU_TRDET_R 1 2
43.2 KOHM1% 10 KOHM 5%
402 CH 1 C7B7 402 CH
470 PF
5%
2 50
X7R
V
402

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=VREGS, CPU CONTROLLER] DRAWING
Wed Feb 10 16:23:32 2010 CONFIDENTIAL
TRINITY_XDK 44/81 G 1.01

8 7 6 5 4 3 2 1
 CR-45 : @TRINITY_LIB.TRINITY(SCH_1):PAGE45

8 7 6 5 4 3 2 1
VREG, CPU OUTPUT PHASE 1 & 2
V_VREG_CPU
D 43 IN D
D6B1
R6N1 1N4148 C6N1
1 2 VREG_CPU2_VCC 1 3 VREG_CPU_BST2 1 2 3 1 C7B5 1 C7N1
2.2 OHM 1% 0.01 UF 10%
D Q6B2 4.7 UF
805 CH SOT23 50 V 4.7 UF
DIO 10%
1 C6B4 EMPTY X819086-001 16 V 10%
1 UF
805
DPAK
2 X5R 2 16 V
10% R6N2 C6N2 1 1206 EMPTY
1206 V_CPUCORE
16 V 1 2 VREG_CPU_BST2_R
G S NOM.VOLTAGE: 0.9-1.2V
2 X5R 2.2 OHM 1%
FET
603
805 CH 0.1 UF 10% 2
U6B1 IC 25 V
X7R
MOS DRIVER 603
4 VCC BST 1
44 IN VREG_CPU_PWM2 2 IN DRVH 8 VREG_CPU_DRVH2 VREG_CPU_PHASE2 OUT 44
44 IN VREG_CPU_DRV_EN 3 OD_N* SW 7
1 R6C1
6 PGND DRVL 5 1 OHM
1%
X850497-001 3 3 2 CH
805 V_CPUCORE
D Q6C2 D Q6C1

VREG_CPU_SW2_R
C X819087-001 X819087-001
VREG_CPU_DRVL2 1
DPAK
1
DPAK L6C1 SM EMPTY
1
C
G S G S DUAL INDUCTOR DB7C4
FET FET
2 2 1 4
1 C7C8 L1 L4
2200 PF 3 L3 L2 2
10%
50 V
2 X7R
805
X820048-001
420NH

DCR +/-8%

V_CPUCORE

L6C2 IND
DUAL INDUCTOR

B 2 L2 L3 3
B
4 L4 L1 1

X850592-001
420NH
40 A
D5B1 0.66
1N4148 +/-4%
R5N7 1
C5N5
2
1 2 VREG_CPU1_VCC 1 3 VREG_CPU_BST1
3 1 C6N3 NOTE: THRUHOLE PART IS 2%
2.2 OHM 1% 1 C6B2 IMPROVEMENT ON DCR
805 CH SOT23 0.01 UF 10% D Q6B1 4.7 UF
4.7 UF
1 C5B10 DIO 50 V
EMPTY 10%
10%
16 V
1 UF R5N8 805
C5N6
X819086-001 2 16 V 2 EMPTY
10% DPAK X5R 1206
16 V 1 2 VREG_CPU_BST1_R
1 1206
2 X5R 2.2 OHM 1% S
603 0.1 UF 10% G FET
805 CH 25 V 2
U5B5 IC X7R
MOS DRIVER 603
4 VCC BST 1
44 IN VREG_CPU_PWM1 2 IN DRVH 8 VREG_CPU_DRVH1 VREG_CPU_PHASE1 OUT 44
3 OD_N* SW 7
6 5
1 R5C1
PGND DRVL 1 OHM
1%
X850497-001 3 3 2 CH
805
D Q5C3 D Q5C1

VREG_CPU_SW1_R
A X819087-001 X819087-001 A
DPAK DPAK
VREG_CPU_DRVL1 1 1
G S FET G S FET
2 2
1 C5C1
2200 PF
10%
2 50
X7R
V
805

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=VREGS, CPU OUTPUT PHASE 1,2] DRAWING
Wed Feb 10 16:23:32 2010 CONFIDENTIAL
TRINITY_XDK 45/81 G 1.01

8 7 6 5 4 3 2 1
 CR-46 : @TRINITY_LIB.TRINITY(SCH_1):PAGE46

8 7 6 5 4 3 2 1
VREGS, V5P0 DUAL

D D

V_5P0STBY
V_5P0STBY V_12P0

2 C1N4 1 C2B2
220 UF
1 R1N2 1 R1N1 0.22 UF 20%
10 KOHM 10 KOHM 10% 10 V
6.3 V ELEC
5% 5% 1 X5R 2 RDL
2 CH 2 CH 402 U1B1 IC
C 402 402
SI4501DY V_5P0DUAL C
R1N3 3 S2
2 1 VREG_V5P0_SEL_PGATE 4 G2
10 KOHM 1% VREG_V5P0_SEL_NGATE
402 CH D<3> 5 V_5P0DUAL
VREG_V5P0_SEL_C
2 C1N3 1 C1B12 D<2> 8 NOM.VOLTAGE: 5.00V
Q1N1 D<1> 7
0.22 UF 22 UF D<0> 6 1
10% 20% V_5P0 FTP FT1N1
R1P1 6.3 V
1 EMPTY 2 10 V
EMPTY 2 G1
27 IN VREG_V5P0_SEL 1 2 VREG_V5P0_SEL_B1 VREG_V5P0_SEL_B2 402 1206 1 S1 1
FTP FT1N9
4.75 KOHM1%
FT1P1 FTP
1 402 CH
XSTR 2 R1P2 X801132-002
4.75 KOHM
1%
1 CH
402

B VREG_5P0_SEL
VREG_5P0_SEL NGATE/PGATE V_5P0DUAL B
HIGH LOW V_5P0STBY
LOW HIGH V_5P0

A A

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=VREGS, V5P0 DUAL] DRAWING
Wed Feb 10 16:23:32 2010 CONFIDENTIAL
TRINITY_XDK 46/81 G 1.01

8 7 6 5 4 3 2 1
 CR-47 : @TRINITY_LIB.TRINITY(SCH_1):PAGE47

8 7 6 5 4 3 2 1
VREGS, V5P0
V_12P0
L2B1
V_VREG_V3P3_V5P0 48
OUT
D 0.45 UH IND D
9 A TH
VREG_V3P3_V5P0_VCCO 48
0.0042 OHM OUT
C2E8 1
330 UF 1 C2F3 1 C2F10
20% 2 R1T4 1 R2T3
16 V 10 OHM 10 KOHM 4.7 UF 4.7 UF
POLY 2 1% 5% 10% 10%
TH U1E1 1 OF 2 IC 16 V
CIV1
1 CH
ADP1877 2 CH 2 X5R 2 16 V
EMPTY
805 402 1206 1206
3 VIN PGOOD1 27 VREG_V5P0_PWRGD 27
5
OUT
VREG_V3P3_V5P0_VDL VDL
4 VCCO RR1
R2E6 ST2G2
1 C2E2 1 C1E1 1 C1E2 1 R1T2 RAMP1 29 VREG_V5P0_RAMP 1 2 1 2 VREG_V5P0_ISENSE_P
OUT 56
1 UF 1 UF 1 UF 0 OHM 820 KOHM 5%
10% 10% 10% 5% 402 CH
16 V 16 V 16 V SHORT
2 X5R 2 X5R 2 X5R 2 CH 3
603 603 603 402 D Q2F1
X819086-001 ST2G3
DPAK 1 2 VREG_V5P0_ISENSE_N 56
2 23 1 OUT
VREG_V3P3_V5P0_SYNC SYNC DH1 VREG_V5P0_DH
C 1 R1E12
G S
2
FET SHORT
C
0 OHM
5%
2 EMPTY V_5P0
402 VOLTAGE: 5.09V

C2F1 V_5P0
BST1 25 VREG_V5P0_BST 2 1
R2E7 0.1 UF 10%
1 1 2 VREG_V5P0_TRK 32 TRK1 25 V ST2U1 1
FT2T2 FTP L2F1 DB2G2
0 OHM 5% X7R 2 1 VREG_V5P0_SW_S R2G1
402 CH
1 C2E7 603 1 2 VREG_V5P0_RSENSE 2 1 1
FTP FT2V2
0.22 UF SHORT
10% IND 10 MOHM 1%
6.3 V SW1 24 VREG_V5P0_SW TH 2512 CH 1 C2V5 1 C2V1 1 C2G2 1 C2V4 1 C2G1 1 R2G2 1 C2G5
2 EMPTY 1.6 UH 10 UF 10 UF 10 UF 10 UF 10 UF
150 OHM 820 UF
402 5% 20%
R2E3 0.00375 OHM 20% 20% 20% 20% 20% 6.3 V
VREG_V5P0_EN 2 1 1 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 2 CH POLY
27 IN VREG_V5P0_EN_R EN1 10 A 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY 1206 2 TH
422 KOHM 1% RLIM1 805 805 805 805 805
402 CH 2 C2E6 R2F1 1
1 R2E2 ILIM1 26 VREG_V5P0_ILIM 1 2 3 DB2G4
10 KOHM 0.01 UF D Q2F2
5% 10% 3.48 K 1%
16 V 402 CH
2 CH 1 X7R X819086-001
B 402 402
DPAK B
DL1 21 VREG_V5P0_DL 1
G S FET
RGCS1 2
2 R1F3 ST2G1
22.1 KOHM 2 1
RFREQ 1%
R1E17 1 CH SHORT
2 1 VREG_V3P3_V5P0_FREQ 7 FREQ 402
97.6 KOHM 1%
402 CH ST2U2

VENABLE
22 VREG_V5P0_PGND 2 1
1 R2F7
PGND1 0 OHM
%
SHORT 2 EMPTY
805
VREG_V5P0_FB 56
OUT
RF11
1 R2E4
VREG_V5P0_COMP 30 COMP1 7.5 KOHM
1%
CC11 2 EMPTY 1
1 C2E3 402
FTP FT2T3
3300 PF COMP2 BW=
10% FB1 31 VREG_V5P0_FB_MID 56
50 V COMP1 BW= OUT
CC12
2 X7R
1 C2E4 402 RF12
330 PF 1 R2T4
A
VREG_V5P0_COMP_C

5%
A 2 50 V
NPO VREG_V5P0_SS 28 SS1
1 KOHM
1%
402
CSS1
2 EMPTY
1 C2E5 402
0.047 UF 6 AGND
RC1 10% 33 GNDSLUG
1 R2E5 10 V
11 KOHM
2 X7R
402
1%
2 CH
X817911-002 LCC32
402

MICROSOFT PROJECT NAME PAGE FAB REV

DRAWING
[PAGE_TITLE=VREGS, V5P0] Wed Feb 10 16:23:32 2010 CONFIDENTIAL
TRINITY_XDK 47/81 G 1.01

8 7 6 5 4 3 2 1
 CR-48 : @TRINITY_LIB.TRINITY(SCH_1):PAGE48

8 7 6 5 4 3 2 1
VREGS, V3P3
47 V_VREG_V3P3_V5P0
IN
D 47 IN VREG_V3P3_V5P0_VCCO D
R1E14

1
10 KOHM
5%
U1E1 2 OF 2 IC CH

2
402
ADP1877
PGOOD2 14 VREG_V3P3_PWRGD 27
OUT
RR2
R1E22
RAMP2 12 VREG_V3P3_RAMP 1 2
422 KOHM 1%
402 CH

ST1F1
1 2 VREG_V3P3_ISENSE_P 56
OUT
SHORT
DH2 18 VREG_V3P3_DH CIV2
1 C1U1
R1E15 4.7 UF ST1F3
2 1 VREG_V3P3_TRK 9 TRK2 10% 1 2 VREG_V3P3_ISENSE_N
OUT 56
C 0 OHM
402
5%
CH 7 AMP 2 16
X5R
V
U1F1 FET 1206 SHORT C
1 4
V_3P3
FT1T10 FTP C1F1 ST1U2
GATE0
DRN0 5 V_3P3 VOLTAGE: 3.3V
BST2 16 VREG_V3P3_BST 2 1 2 1 3 SRC0 DRN0 6
VREG_V3P3_EN 8 0.02
27 IN EN2 1
0.1 UF 10% SHORT L1F1 FTP FT2V3
25 V R1F9
X7R 2 GATE1 DRN1 7 VREG_V3P3_SW_S 1 2 VREG_V3P3_RSENSE 1 2 1
DB2G1
603 DRN1 8
1 R1E16 1 SRC1 2.3 UH IND 30 MOHM
10 KOHM 6 A TH 2512 CH 1 C1F9 1 C1F6 1 C1G2 1 C1F3
5% SW2 17 VREG_V3P3_SW 1%
4.7 UF 4.7 UF 4.7 UF 4.7 UF
2 CH X807111-001 SO-8 10% 10% 10% 10%
6.3 V 6.3 V 6.3 V
402 2 X5R 2 X5R 2 X5R 2 6.3
X5R
V
805 805 805 805
RLIM2 1
DB1F2
R1F1 VENABLE
ILIM2 15 VREG_V3P3_ILIM 1 2
4.53 KOHM 1% R2F9 ST1F2
402 CH 2 1 1 2
RGCS2 0 OHM %
R1F2 805 EMPTY SHORT
DL2 20 VREG_V3P3_DL 2 1
B 22.1 KOHM
402
1%
CH B

RR1 VREG_V3P3_FB 56
OUT
ST1U1
PGND2 19 VREG_V3P3_PGND 2 1

SHORT

RF21
1 R1E20
4.53 KOHM
1%
VREG_V3P3_COMP 11 COMP2 2 EMPTY
CC21 402
1
1 C1E3 FTP FT1T9
3300 PF
10% FB2 10 VREG_V3P3_FB_MID 56
CC22
1 C1E4 50 V OUT
2 X7R RF22
120 PF 402
5% 1 R1E19
50 V 1 KOHM
2 NPO 1%
VREG_V3P3_COMP_C

402 VREG_V3P3_SS 13 SS2

2 EMPTY
402
A CSS2
1 C1E5
A
0.047 UF
10%
2 10
X7R
V
RC2 402
1 R1E21 X817911-002 LCC32
7.87 KOHM
1%
2 CH
402

MICROSOFT PROJECT NAME PAGE FAB REV

DRAWING
[PAGE_TITLE=VREGS, V3P3] Wed Feb 10 16:23:33 2010 CONFIDENTIAL
TRINITY_XDK 48/81 G 1.01

8 7 6 5 4 3 2 1
 CR-49 : @TRINITY_LIB.TRINITY(SCH_1):PAGE49

8 7 6 5 4 3 2 1

V_12P0
VREGS, VEDRAM
L7B1
V_VREG_VMEM_VEDRAM OUT 50
0.45 UH IND
9 A TH
D 0.0042 OHM
1 1 C7B8
VREG_VMEM_VEDRAM_VCCO OUT 50 D
C3F8 470 UF
330 UF 20%
20% 16 V 1 C3F1 1 C3F7
16 V POLY 2 R3G2 R3G16 2
POLY 2 2 TH 10 OHM
10 KOHM 4.7 UF 4.7 UF CIV1
TH 5% 10% 10%
1% CH 16 V 16 V
1 CH 1 OF 2 402 1 2 X5R 2 EMPTY
805
U3G1 IC 1206 1206 1
ADP1877 FTP FT3V4

3 VIN PGOOD1 27 VREG_VEDRAM_PWRGD OUT 27

VREG_VMEM_VEDRAM_VDL 5 VDL
4 VCCO RR1
R3F10
1 C3G1 1 C3G3 1 C3V1 RAMP1 29 VREG_VEDRAM_RAMP 1 2 ST4F2
680 KOHM 5% 1 2 VREG_VEDRAM_ISENSE_P OUT 55
1 UF 1 UF 1 UF 402 CH
10% 10% 10%
16 V 16 V 16 V 2 R3F12 1 R3F14 3 SHORT
2 X5R 2 X5R 2 X5R 0 OHM 0 OHM D Q3F1 ST4F4
603 603 603 5% 5% 1 2 VREG_VEDRAM_ISENSE_N OUT 55
1 CH 2 CH X819086-001
402 402
DPAK SHORT
VREG_VMEM_VEDRAM_SYNC 2 SYNC DH1 23 VREG_VEDRAM_DH 1 V_CPUEDRAM
SYNC HIGH=FORCED PWM MODE G S
C FET
SYNC LOW =PULSE SKIP MODE
1 R3F13
2
V_CPUEDRAM C
0 OHM VOLTAGE: 1.075V 1
5% L4F1 FTP FT5T4
2 EMPTY R4F1
402
1 2 VREG_VEDRAM_RSENSE 2 1 1
DB4E3
C3F5 1.7 UH IND 10 MOHM 1%
BST1 25 VREG_VEDRAM_BST 2 1
TH 2512 CH C4E3 C4E6 C4F7
ST3F1 13.8 A 820 UF 820 UF 820 UF
0.1 UF 10% 2 1 VREG_VEDRAM_SW_S 0.0034 OHM 20% 20% 20%
VREG_VEDRAM_TRK 32 TRK1 25 V 2.5 V 2.5 V 2.5 V
X7R POLY POLY EMPTY
603 SHORT RDL RDL RDL

1 SW1 24 VREG_VEDRAM_SW
FT3V1 FTP

27 IN VREG_VEDRAM_EN 1 EN1
1 R3F15 RLIM1 1 C5T52 1 C5E11 1 C4T7 1 C5E10
10 KOHM R3F7 4.7 UF 4.7 UF 4.7 UF 4.7 UF
5% ILIM1 26 VREG_VEDRAM_ILIM 1 2 3 10% 10% 10% 10%
2 CH 3.32 KOHM 1% D Q4F1 2 16 V
2 16 V
2 16 V
2 16 V
402 402 CH EMPTY EMPTY EMPTY EMPTY
1206 1206 1206 1206
X819086-001
B 21 1
DPAK B
DL1 VREG_VEDRAM_DL
G S FET
RGCS1 2
ST4F1
2 R3V1 2 1
22.1 KOHM
RFREQ 1% 1 SHORT
DB4E4
R3G4 1 CH 1 R3F11

VENABLE
2 1 VREG_VEDRAM_FREQ 7 FREQ 402 0 OHM 1 DB4E5
97.6 KOHM 1% %
402 CH ST4U1 2 EMPTY
PGND1 22 VREG_VEDRAM_PGND 2 1 805
VREG_VEDRAM_FB OUT 55
SHORT
RF11
1 R3F8
7.87 KOHM
1%
2 EMPTY
402
VREG_VEDRAM_COMP 30 COMP1
CC11
1 C3F2 1
FTP FT3U1
4700 PF
10% FB1 31 VREG_VEDRAM_FB_MID OUT 55
50 V
CC12
1 C3F3 2 X7R
402
62 PF
VREG_VEDRAM_COMP_C

5% RF12

A 2 50
NPO
V
402
VREG_VEDRAM_SS 28 SS1
1 R3F9
10 KOHM
A
1%
CSS1
2 EMPTY
1 C3F4 6 AGND 402
0.047 UF 33 GNDSLUG
RC1 10%
1 R3F6 10 V
43.2 KOHM 2 X7R
1% 402 X817911-002 LCC32
RC1=120K
2 CH
402

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=[VREGS, VEDRAM] DRAWING
Wed Feb 10 16:23:33 2010 CONFIDENTIAL
TRINITY_XDK 49/81 G 1.01

8 7 6 5 4 3 2 1
 CR-50 : @TRINITY_LIB.TRINITY(SCH_1):PAGE50

8 7 6 5 4 3 2 1
VREGS, VMEM

D V_VREG_VMEM_VEDRAM
D
49 IN
VREG_VMEM_VEDRAM_VCCO CIV2
1 C7F3 1 C7U1
49 IN
2 R3G15 4.7 UF 4.7 UF
10 KOHM 10% 10%
16 V 16 V
5% 2 X5R 2 EMPTY
U3G1 2 OF 2 IC 1 CH 1206 1206
402 1
FTP FT3V5
ADP1877 R3R5
PGOOD2 14 VREG_VMEM_PWRGD_R 1 2 VREG_VMEM_PWRGD_CPU_TRST_N_R OUT 27
0 OHM 5%
RR2 402 CH
R3G13 ST7F2
RAMP2 12 VREG_VMEM_RAMP 1 2 1 2 VREG_VMEM_ISENSE_P OUT 55
680 KOHM 5%
402 CH SHORT
3 ST7F3
D Q7G1 1 2 VREG_VMEM_ISENSE_N OUT 55

X819086-001 SHORT
DPAK
V_MEM
18 1 VOLTAGE: 1.8V
DH2 VREG_VMEM_DH
C 2
R3G5
1VREG_VMEM_TRK 9
G S
2
FET
1 C
TRK2 DB7F1
0 OHM 5% 1
V_MEM
402 CH FTP FT6U1
L7F1 R7F1
1 2 1
FT3V3 FTP C3G9 ST6V2 VREG_VMEM_RSENSE 1 2
BST2 16 VREG_VMEM_BST 2 1 2 1 VREG_VMEM_SW_S
IND 1.7 UH 10 MOHM 1%
27 IN VREG_VMEM_EN 8 EN2 TH 2512 CH C7F2 1 C7F1
0.1 UF 10% SHORT 13.8 A 820 UF
25 V 0.0034 OHM 4.7 UF
1 R3G14 X7R 20% 10%
10 KOHM 603 2.5 V 6.3 V
5% POLY 2 EMPTY
RDL 805 1
2 CH SW2 17 VREG_VMEM_SW DB7F2
402
V_MEM
RLIM2
R3G10
ILIM2 15 VREG_VMEM_ILIM 1 2 3 1 C7R1
330 UF
3.32 KOHM 1% D Q7G2 20%
402 CH 2.5 V
X819086-001 2 EMPTY
B DPAK
SM
B
DL2 20 VREG_VMEM_DL 1
G S FET
2 V_MEM
1 R4G3
RGCS2 22.1 KOHM
1% 1 C4U4
330 UF
2 CH ST7F1 20%
402 2 1 2.5 V
ST6V1 2 EMPTY
1 R3G17 SM

VENABLE
PGND2 19 VREG_VMEM_PGND 2 1 0 OHM SHORT
%
SHORT 2 EMPTY
805

VREG_VMEM_FB OUT 55
RF21
1 R3G11
VREG_VMEM_COMP 11 COMP2 20 KOHM
1%
CC21 2 EMPTY 1
1 C3G6 402
FTP FT3V2
4700 PF
10% FB2 10 VREG_VMEM_FB_MID OUT 55
50 V
2 X7R RF22
CC22
1 C3G7 402
1 R3G12
VREG_VMEM_COMP_C

A 62 PF
5%
13
10 KOHM
1% A
50 V VREG_VMEM_SS SS2
2 NPO 2 EMPTY
402 402
CSS1
1 C3G8
RC2
1 R3V4 0.047 UF
43.2 KOHM 10%
10 V
1% 2 X7R
2 CH 402 X817911-002 LCC32
402

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=[VREGS, VMEM] DRAWING
Wed Feb 10 16:23:33 2010 CONFIDENTIAL
TRINITY_XDK 50/81 G 1.01

8 7 6 5 4 3 2 1
 CR-51 : @TRINITY_LIB.TRINITY(SCH_1):PAGE51

8 7 6 5 4 3 2 1
VREGS, VCS

D D

V_12P0 V_5P0
ST5C1
1 2 VREG_VCS_ISENSE_P OUT 57
L4B1
V_VREG_VCS SHORT
0.45 UH IND 1 C5B21 1 1 C5B19
C4N9 C4N7 9 A TH C4B11 C4B12 C5N11 C4N10 C5N10 820 UF C5B20
1 UF 1 UF 0.0042 OHM 10 UF 10 UF 10 UF 10 UF 10 UF 20% 4.7 UF 4.7 UF
10% 10% 20% 20% 20% 20% 20% 6.3 V 10% 10% ST5C3
16 V 16 V 6.3 V 6.3 V 6.3 V 6.3 V
R4B21 X5R X5R 1 C4B4 1 C4B14 X5R X5R X5R X5R
6.3 V
X5R 2 POLY
TH 2 6.3
X5R
V
2 6.3
X5R
V 1 2 VREG_VCS_ISENSE_N OUT 57
VREG_CPUCORE_VCS_PWRGD 1 2 603 603 4.7 UF 4.7 UF 805 805 805 805 805 805 805
27 44 OUT 10% 10% SHORT
0 OHM 5% 6.3 V 16 V
C 402 EMPTY 2 X5R 2 X5R
805 1206 C
V_CPUCORE V_CPUVCS
U4B3 IC VOLTAGE: 1.25 - 1.3V
ir3638 3
4 VCC D Q5B1 V_CPUVCS
1 R4C13 10
1 KOHM VC
5% 1 VREG_VCS_NC 14 NC X819086-001
DB4P8 DB4P6 DB4N2
1 2 EMPTY 1 VREG_VCS_OCP 3 NC0 R4B4 DPAK
TP 402 TP
DB4P7
1 VREG_VCS_NC1 5 NC1 HDRV 9 VREG_VCS_HDRV 1 2 VREG_VCS_HDRV_R 1 1
FTP FT5R17
R4C14 11 NC2 LDRV 6 G S FET
CPU_SRVID VREG_VCS_RT_PWRGD 2.2 OHM 1%
2 IN 1 2 VREG_VCS_VP 2 VP 805 CH 2 L5C1 R5C2
0 OHM 5% 1 R4C11 1 C4C5 1 R4C17 VREG_VCS_VOUT_L 1 2 VREG_VCS_VOUT 1 2 1
DB5C1
402 CH 1 MOHM
5% 0.1 UF 2 KOHM 1.7 UH IND 10 MOHM 1%
10% 1% TH 2512 CH 1 C5C2
2 CH 6.3 V 3 13.8 A 1 C5P1 1 C5C6
402 2 X5R 2 EMPTY D Q5C2 0.0034 OHM 4.7 UF 4.7 UF
820 UF
402 402 20%
10% 10% 2.5 V
6.3 V 6.3 V POLY
DB4N3
X819086-001 2 X5R 2 X5R 2 RDL
1 VREG_VCS_SS_SD_N 13 SS R4N15 DPAK 805 805
TP
2 C4B7 VREG_VCS_LDRV 1 2 VREG_VCS_LDRV_R 1
G S FET
2.2 OHM 1%
B 0.1 UF
10% 805 CH 2
B
6.3 V
1 X5R
402 PGND 8
VREG_VCS_COMP 12 7
COMP GND

1 R4B11
27.4 KOHM 1 FB
1% VENABLE
2 CH X811812-001
402 SSOP R4B17 R5B13 ST5C2
2 C4B6 1 2 1 2 2 1
VREG_VCS_COMP_R

11 KOHM 1% 0 OHM %
22 PF 402 CH 805 EMPTY 1 DB5B3 SHORT
5%
50 V 1
1 NPO DB5B2
402
R4B19 1 R4B22 C4B13
20 KOHM 1 2 VREG_VCS_RC 1 2 VREG_VCS_FB 57
1 C4B5 1% OUT
EMPTY 2 1.33 KOHM 1% 3300 PF 10%
4700 PF 402 402 EMPTY 50 V
10% EMPTY
2 50
X7R
V 402
603 VREG_VCS_FB_MID OUT 57

A A
GAIN=0.4 WITH R4B17 = 11K, R4B19 = 27.4K
OUTPUT = CPU_SRVID(1+GAIN)

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=VREGS, VCS] DRAWING
Wed Feb 10 16:23:33 2010 CONFIDENTIAL
TRINITY_XDK 51/81 G 1.01

8 7 6 5 4 3 2 1
 CR-52 : @TRINITY_LIB.TRINITY(SCH_1):PAGE52

8 7 6 5 4 3 2 1
VREGS, 1P8+GPUPCIE+SBPCIE+CPUPLL+EFUSE

D D
V_5P0 V_GPUPCIE
NOM.VOLTAGE: 1.5V
TARGET FOR VALHALLA=1.5V

V_3P3 V_GPUPCIE
1 R1D4 1 R1D3 1 R1D2 1 R1D1
6.2 OHM 6.2 OHM 6.2 OHM 6.2 OHM V_1P8 U4E2 IC
1% 1% 1% 1% NOM.VOLTAGE: 1.8V
2 CH 2 CH 2 CH 2 EMPTY NCP1117 R4E11
1210 1210 1210 1210 3 IN OUT 2 V_VREG_GPUPCIE 1 2 1 FTP FT4T1
V_1P8 0 OHM %
U1C1 IC 1 ADJUST/GND OUT/TAB 4 805 CH
1
NCP1117 R1C1 1 C4E11 1 R4E8 1 R4E7 R3T5 DB4E1
V_VREG_1P8_IN 3 IN OUT 2 V_VREG_1P8 1 2 1 FTP FT2T1 1 UF X800501-001 1 KOHM 1 OHM 0 OHM 5%
0 OHM % 10% SOT223 1% 1% 402 CH
1 16 V 1 2 VREG_GPUPCIE_FB
ADJUST/GND 805 CH 2 X5R 1.5V 2 EMPTY 2 CH OUT 58
C1C3 1 1 C1C2 1 C1C1
100 UF
1
DB2E1 603 402 402
X800500-001 0.1 UF
0.1 UF 10% 20% VREG_PCIEX_ADJUST
10% DPAK 25 V 16 V
25 V
2 1.8V
2 X7R 2 ELEC R4E10
X7R 603 RDL 1 C4E13 1 2 VREG_GPUPCIE_FB_MID IN 58
603 0.1 UF 0 OHM 5%
C 10%
6.3 V
402 CH
C
2

VREG_PCIEX_R
EMPTY
402

1 R4E9 1 C4E12
191 OHM
1% 4.7 UF
V_SBPCIE 2 CH
10%
NOM.VOLTAGE: 1.83V 402 2 6.3
X5R
V
805
V_SBPCIE 1
DB3E1
NOTE: THIS WAS SET TO 1.83V TO ACCOMODATE DROP IN FERRITES
R3E5 NOTE: BOTTOM ADJUST RESISTOR
1 2 1 FTP FT3T1 LEFT IN TO REDUCE EFFECT OF ADJUST
0 OHM % PIN CURRENT WHEN USED WITH 1K DIGIPOT
V_3P3 805 CH V_CPUPLL
U4E1 IC V_CPUPLL
NCP1117 R4E4 NOM.VOLTAGE: 1.83V
B 3 IN OUT 2 V_VREG_1P8PLL 1 2 1 FTP FT4T3
B
0 OHM %
1 ADJUST/GND 805 CH 1
DB4E2
1 C4E10 1 R4E6 1 R4E5
1 KOHM 1 OHM
1 UF X819037-001 1% 1%
10% DPAK 2 EMPTY 2 CH R3F4
16 V 402 402
1 2 VREG_CPUPLL_SBPCIE_FB OUT 58
2 X5R 1.8V
0 OHM 5%
603 CH
402
VREG_CPUPLL_ADJUST
R4U4 V_5P0
1 C4F8 1 2 VREG_CPUPLL_SBPCIE_FB_MID IN 58
0 OHM 5%
0.1 UF 402 CH
10%
2 6.3 V
EMPTY 2 C4R2 V_EFUSE
NOM.VOLTAGE: 1.5V
VREG_CPUPLL_R

402 1 UF
10% V_EFUSE
16 V
1 X5R U4R1 IC
603
LD39015
R4R4
1 VIN VOUT 5 VREG_EFUSE_VOUT 1 2 1 FTP FT4R3
0 OHM %
1 R4F2 1 C4E9 2 IN VREG_EFUSE_EN 3 ENABLE GND 2 805 CH 1
453 OHM DB4D1
1% 4.7 UF
2 CH
10%
6.3 V 1 NC 4 C4R1 C4R3
2 FT4R5 FTP 1 UF 0.1 UF
402 X5R 10% 10%
805 16 V 6.3 V
VREG_EFUSE_EN HIGH 2 R4R1 X819038-001 1.5V X5R X5R
A IS 1.8V (V_MEM) 10 KOHM
5%
603 402 A
NOTE: BOTTOM ADJUST RESISTOR 1 CH
LEFT IN TO REDUCE EFFECT OF ADJUST 402
PIN CURRENT WHEN USED WITH 1K DIGIPOT

MICROSOFT PROJECT NAME PAGE FAB REV

DRAWING
[PAGE_TITLE=VREGS, 1P8+GPUPCIE+SBPCIE+CPUPLL+EFUSE] Wed Feb 10 16:23:34 2010 CONFIDENTIAL
TRINITY_XDK 52/81 G 1.01

8 7 6 5 4 3 2 1
 CR-53 : @TRINITY_LIB.TRINITY(SCH_1):PAGE53

8 7 6 5 4 3 2 1
VREGS, STANDBY SWITCHERS

D D

V_5P0STBY 1
V_1P8STBY V_1P8STBY
FT5M3 FTP NOM.VOLTAGE: 1.802V
U5B1 IC
L6A1 SIMPLESWR L5B2 R5B4
1 2 V_VREG_STBY_VIN 4 VIN SW 3 VREG_1P8STBY_SW 1 2 V_1P8STBY_R 1 2 1
DB5B4
2.2 UH IND 0 OHM %
2.2 UH IND V_3P3STBY 1 5 805 CH
1210 1 C5A9 1 C5B18 1 C5B16 ENABLE FB/VO 1.6 A 1210
1.6 A
0.05 OHM
0.05 OHM 10 UF 10 UF 10 UF 1 R5B3 2
20% 20% 20% 10 KOHM
GND R5B17 1
6.3 V 6.3 V 2 1 FTP FT5N2
2 6.3 V VREG_1P8STBY_FB
2 2 1 R5B5 1%
C X5R
805
X5R
805
X5R
805 10 KOHM 2 CH
1% X821327-001 SOT23 475 KOHM
402
1%
CH C
402
2 EMPTY 1 C5B2 1 C5B7 1 C5B6
402 10 UF 4.7 UF 0.1 UF
C5B1 20% 10% 10%
1 R5B2 1 2
2 6.3 V
2 6.3 V
2 25 V
VREG_1P8STBY_EN
237 KOHM X5R EMPTY X7R
1 1% 18 PF 5% 805 805 603
FT5N1 FTP 50 V
2 CH NPO
1 C5N9 402 402
1 UF
10% 1
DB5B5
2 16
X5R
V
603

V_3P3STBY V_3P3STBY
NOM.VOLTAGE: 3.315V
U5A1 IC
SIMPLESWR L5A1 R5A11
4 VIN SW 3 VREG_3P3STBY_SW 1 2 V_3P3STBY_R 1 2 1
DB5B1
2.2 UH IND 0 OHM %
V_1P8STBY 1 ENABLE FB/VO 5 1.6 A 1210 805 CH
B 2
0.05 OHM
B
1 R5A7 GND R5A6
1 R5M6 10 KOHM VREG_3P3STBY_FB 2 1 1 FTP FT5M1
10 KOHM 1% 475 KOHM 1%
X821327-001 SOT23 CH
1% 2 CH 402
2 EMPTY 402
1 C5A2 1 C5A3
402 C5A1 0.1 UF
1 2 10 UF 10%
1 R5A5 20%
VREG_3P3STBY_EN 105 KOHM 1000 PF 10% 2 6.3 V 2 25
X7R
V
1% X5R 603
1 50 V 805
FT5M2 FTP 2 CH X7R
402 402
1 C5M5
1 UF 1
10% DB5A1
16 V
2 X5R
603

A A

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=VREGS, STANDBY SWITCHERS] DRAWING
Wed Feb 10 16:23:34 2010 CONFIDENTIAL
TRINITY_XDK 53/81 G 1.01

8 7 6 5 4 3 2 1
 CR-54 : @TRINITY_LIB.TRINITY(SCH_1):PAGE54

8 7 6 5 4 3 2 1
BOARD LEVEL DECOUPLING
V_5P0

D D
1 C1U3 1 C1T4 1 C1P1 1 C1A10 1 C2A15
V_12P0 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
10% 10% 10% 10% 10%
2 6.3
X5R
V
2 6.3
X5R
V
2 6.3
X5R
V
2 6.3
X5R
V
2 6.3
X5R
V
402 402 402 402 402
1 C3N40 1 C3M5 1 C6N4 1 C7B4
0.01 UF 0.01 UF 0.01 UF 0.01 UF
10% 10% 10% 10%
2 16
X7R
V
2 16
X7R
V
2 16
X7R
V
2 16
X7R
V
402 402 402 402

V_1P8STBY

V_5P0 1 C3T24 1 C3E7 1 C3R21 1 C3C3

V_5P0DUAL 0.1 UF
10%
0.1 UF
10%
0.1 UF
10%
0.1 UF
10%
6.3 V 6.3 V
C 2 6.3 V
X5R 2 X5R 2 X5R 2 6.3
X5R
V

1 C3E6 1 C4P3 1 C4N6 1 C3T23 1 C2V2 1 C3U4

402 402 402 402 C
0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 1 C3G12 1 C3V3 1 C5G8
10% 10% 10% 10% 10% 10% 0.1 UF 0.1 UF 0.1 UF
2 6.3
X5R
V
2 6.3
X5R
V
2 6.3
X5R
V
2 6.3
X5R
V
2 6.3
X5R
V
2 6.3
X5R
V 10% 10% 10%
402 402 402 402 402 402 2 6.3
X5R
V
2 6.3
X5R
V
2 6.3
X5R
V
402 402 402

V_3P3 V_3P3STBY
V_3P3

1 C2U1 1 C3U1 1 C4M1 1 C3T21 1 C3T20 1 C2T19 1 C3P10 1 C4V1 1 C4G1 1 C4N2 1 C3R19
0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 1 C1R1 1 C2N3 1 C2R21 1 C2P1 1 C3R20
10% 10% 10% 10% 10% 10% 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF
6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V 0.1 UF 0.1 UF 0.1 UF 0.1 UF 0.1 UF 10% 10% 10% 10% 10%
2 2 2 2 2 2 10% 10% 10% 10% 10% 6.3 V 6.3 V 6.3 V 6.3 V
X5R
402
X5R
402
X5R
402
X5R
402
X5R
402
X5R
402 2 6.3 V
2 6.3 V
2 6.3 V
2 6.3 V
2 6.3 V 2 X5R 2 X5R 2 X5R 2 X5R 2 6.3
X5R
V
X5R X5R X5R X5R X5R 402 402 402 402 402
402 402 402 402 402

B B
V_1P8
V_1P8STBY

1 C2R22
0.1 UF
10% 1 C4N3 1 C4N5 1 C4N8
6.3 V
2 X5R 0.1 UF 0.1 UF 0.1 UF
402 10% 10% 10%
6.3 V 6.3 V
2 X5R 2 X5R 2 6.3
X5R
V
402 402 402

A A

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=BOARD, DECOUPLE] DRAWING
Wed Feb 10 16:23:34 2010 CONFIDENTIAL
TRINITY_XDK 54/81 G 1.01

8 7 6 5 4 3 2 1
 CR-55 : @TRINITY_LIB.TRINITY(SCH_1):PAGE55

8 7 6 5 4 3 2 1
MARGIN, VMEM + VEDRAM
V_5P0DUAL

D R2B3 D
37 27 23 IN HDMI_DDC_CLK 1 2 PMBUS_CLK
OUT 35 44 55 56 57 58 61
0 OHM 5% 2 C3G5
402 EMPTY 2.2 UF
20% U3V1 IC
R2B1 1 6.3 V
40 37 27 23 BI HDMI_DDC_DATA 1 2 PMBUS_DATA
BI 35 44 55 56 57 58 61 X5R
1 9 PMBUS_CLK
0 OHM 5%
402 VDD SCL IN 55
SDA 7 PMBUS_DATA 35 44 55 56 57 58 61
402 EMPTY 3
BI
WP*
R2B4 50 VREG_VMEM_FB 6 A1 A3 12 VREG_VEDRAM_FB 49
59 27 IN SMB_CLK 1 2 IN IN
0 OHM 5%
R3G8 R3F16
CH 50 IN VREG_VMEM_FB_MID 1 2 VREG_VMEM_FB_MID_R 4 W1 W3 14 VREG_VEDRAM_FB_MID_R 1 2 VREG_VEDRAM_FB_MID
IN 49
402
0 OHM 5% 0 OHM 5%
402 CH 5 B1 B3 13 402 CH
R2B2
59 41 27 22 BI SMB_DATA 1 2 11 8
0 OHM 5%
MARGIN_VMEM_VEDRAM_AD1 AD1 VSS
MARGIN_VMEM_VEDRAM_AD0 2 AD0 DGND 10
402 CH
V_5P0DUAL V_5P0DUAL X819026-001 TSSOP
V_5P0STBY VALUE=10K
DEFAULT=127 (0X7F)
1 R3U3 1 R3G9 SETPOINT1=VMEM 81 (0X51)
C J5B1 1 KOHM
5%
1 KOHM
5%
SETPOINT2=VEDRAM 144 (0X90) C
2X2HDR
2 EMPTY 2 EMPTY AD5252 I2C ADDRESS
1 2 402 402 0101 1 AD1 AD0 R/W HEX
3 4 WRITE 0101 1 0 0 0 0X58
1 R3U1 1 R3G7 READ 0101 1 0 0 1 0X59
1 KOHM 1 KOHM
HDR 5% 5%
2 CH 2 CH
402 402

N: PMBUS HEADER CAN BE USED AS

A RELIABILITY INTERFACE HEADER.

V_5P0DUAL
U3G3 IC
REF3333
1 IN OUT 2

1 C3G11 1 C3G10
B 2.2 UF
20%
GND 3 0.1 UF
10% B
6.3 V
2 X5R X820467-001 2 6.3
X5R
V
402 SC70 402
V_5P0 3.3V +/-0.15%

V_3P3_VREF_VMEM_VEDRAM

2 C3G2 2 C3V2
2.2 UF 2.2 UF
20% 20%
1 6.3 V U3V2 IC 1 6.3 V
X5R X5R
402 AD8213 402 U3G2 IC
8 VAA AD7991
8 VDD
50 VREG_VMEM_ISENSE_P 2 IN2_P OUT2 4
IN VREG_VMEM_ISENSE_N 1 SCL 1 PMBUS_CLK
IN 55
50 IN IN2_N VREG_VMEM_IOUT 6 VIN3/VREF SDA 2 PMBUS_DATA 35 44 55 56 57 58 61
VREG_VMEM_CF2 5 CF2 5
BI
VREG_VEDRAM_IOUT VIN2
4 VIN1
49 VREG_VEDRAM_ISENSE_P 9 IN1_P OUT1 7
IN VREG_VEDRAM_ISENSE_N 10 1 R3G6 1 R3G1 3 VIN0 GND 7
49 IN IN1_N 24.3 KOHM 24.3 KOHM
VREG_VEDRAM_CF1 6 CF1 GND 3 1% 1%
2 CH 2 CH X817914-001 SOT23
402 402
X817913-001 MSOP10
AD7991-0 I2C ADDRESS
C3G4 2 2 C3F6 0101 000 R/W HEX

A 0.22 UF
10%
0.22 UF
10%
WRITE 0101 000 0
READ 0101 000 1
0X50
0X51
A
6.3 V 6.3 V
X5R 1 1 X5R
402 402
PACKAGE IS SOT23-8 OR ALSO CALLED RJ-8

50 VREG_VMEM_FB
IN
49 VREG_VEDRAM_FB
IN

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=MARGIN, VMEM + VEDRAM] DRAWING
Wed Feb 10 16:23:34 2010 CONFIDENTIAL
TRINITY_XDK 55/81 G 1.01

8 7 6 5 4 3 2 1
 CR-56 : @TRINITY_LIB.TRINITY(SCH_1):PAGE56

8 7 6 5 4 3 2 1
MARGIN, V3P3 + V5P0
VREG_V3P3_FB IN 48
V_5P0DUAL

1
D V_P Q1F1 1 R1U5 D
47 IN VREG_V5P0_FB 22.1 KOHM
NC3 X819034-001 1%
2.048V 0.1% 2 CH
1 R2U1 2 C2F4 V_N IC 402

1
V_P Q2F3 ADR5040A

2
35.7 KOHM ADR5043 2.2 UF U1U1 IC
1% 20%
2 CH NC3 X819033-001 1 6.3 V
3.0V 0.1% X5R 1 VDD SCL 9 PMBUS_CLK 55
402 402 7 PMBUS_DATA
IN
V_N IC SDA BI 35 44 55 56 57 58 61
3 WP*

2
VREG_V5P0_FB_A1 6 A1 A3 12 VREG_V3P3_FB_A3
R2T5 R1T19
47 IN VREG_V5P0_FB_MID 1 2 VREG_V5P0_FB_MID_R 4 W1 W3 14 VREG_V3P3_FB_MID_R 1 2 VREG_V3P3_FB_MID IN 48
0 OHM 5% 0 OHM 5%
402 CH 5 B1 B3 13 402 CH
MARGIN_V3P3_V5P0_AD1 11 AD1 VSS 8
MARGIN_V3P3_V5P0_AD0 2 AD0 DGND 10

X819026-001 TSSOP
V_5P0DUAL V_5P0DUAL VALUE=10K
DEFAULT=128 (0X7F)
C 1 R1U4 1 R2F3
SETPOINT1=V5P0 69 (0X45)
SETPOINT2=V3P3 123 (0X7B) C
1 KOHM 1 KOHM
5% 5%
2 EMPTY 2 CH AD5252 I2C ADDRESS
402 402 0101 1 AD1 AD0 R/W HEX
1 R1U3 WRITE 0101 1 0 1 0 0X5A
1 KOHM 1 R2F2 READ 0101 1 0 1 1 0X5B
5% 1 KOHM
5%
2 CH 2 EMPTY
402
402
V_5P0DUAL
U1F3 IC
REF3333
1 IN OUT 2

1 C1F10 1 C1F11
2.2 UF GND 3 0.1 UF
20% 10%
6.3 V
2 X5R X820467-001 2 6.3
X5R
V
402 SC70 402
3.3V +/-0.15%
V_5P0
B B
V_3P3_VREF_V5P0_V3P3

2 C1U2 2 C2F2
2.2 UF
20% U2U1 IC 2.2 UF
6.3 V 20%
1 X5R AD8213 1 6.3 V
U1F2 IC
402 X5R
8 VAA 402
AD7991
8 VDD
47 IN VREG_V5P0_ISENSE_P 2 IN2_P OUT2 4
1 PMBUS_CLK
47 VREG_V5P0_ISENSE_N 1 IN2_N SCL IN 55
IN 5
VREG_V5P0_IOUT 6 VIN3/VREF SDA 2 PMBUS_DATA BI 35 44 55 56 57 58 61
VREG_V5P0_CF2 CF2 VREG_V3P3_IOUT 5 VIN2
4 VIN1
48 IN VREG_V3P3_ISENSE_P 9 IN1_P OUT1 7
3 7
48 VREG_V3P3_ISENSE_N 10 IN1_N VIN0 GND
IN 6 1 R2F5 1 R2F8
VREG_V3P3_CF1 CF1 GND 3 24.3 KOHM 24.3 KOHM
C2F6 2 2 C1F2 1% 1% X818998-001 SOT23
0.22 UF 0.22 UF X817913-001 MSOP10 2 CH 2 CH
10% 10% V_5P0 402 402
6.3 V 6.3 V
X5R 1 1 X5R AD7991-1 I2C ADDRESS
402 402 R2F4 0101 001 R/W HEX
1 2 VREG_V5P0_FB_R WRITE 0101 001 0 0X52
150 OHM 1% READ 0101 001 1 0X53
V_3P3 402 CH

R1F4 PACKAGE IS SOT23-8 OR ALSO CALLED RJ-8

1 2
A 150 OHM 1%
VREG_V3P3_FB_R
A
402 CH
1 R1F6 1 R1F5
221 OHM 221 OHM
1% 1%
2 CH 2 CH
402 402

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=MARGIN, V3P3 + VP50] DRAWING
Wed Feb 10 16:23:34 2010 CONFIDENTIAL
TRINITY_XDK 56/81 G 1.01

8 7 6 5 4 3 2 1
 CR-57 : @TRINITY_LIB.TRINITY(SCH_1):PAGE57

8 7 6 5 4 3 2 1
MARGIN, VREFS + VCS 3
U4B2
VDD AD7992 SCL
IC
10 PMBUS_CLK 55
9 PMBUS_DATA IN
SDA BI 35 44 55 56 57 58
V_5P0STBY 2 C4N4 61
U5B6 IC 2.2 UF
20% 57 MEM_VREFS 4 VIN2/REFIN ALERT/BUSY 8
REF3333 IN
D 1 IN OUT 2 V_3P3_VREF_VCS 1 6.3
X5R
V 5 VIN1 D
402 1 R4N8
1 C5N8 1 C5N7 1 KOHM
5% 6 AS
2.2 UF GND 3 0.1 UF
20% 10% 2 CH
6.3 V 6.3 V 402 AGND2 7
2 X5R X820467-001 2 X5R 1 R4N13 1 CONVST_N* AGND1 2
402 SC70 402 1 KOHM
3.3V +/-0.15% 5%

MARGIN_VREFS_CONVST
2 EMPTY X814249-001 MSOP10
402
MARGIN_VREFS_AS
AD7992-1 I2C ADDRESS
AS=GND 0100011 R/W
VREG_VCS_FB WRITE 0100011 0 0X46
57 51 IN READ 0100011 1 0X47
1 R4N14 1 R4N10 AS=VDD 0100100 R/W HEX
V_5P0 1 KOHM 1 KOHM
5% 5%
2 CH 2 CH
402 402
2 C5B5
2 C5B15 U5B2 IC 2.2 UF
2.2 UF 20%
20% AD8213 1 6.3 V U5N1 IC
8 VAA X5R
C 1 6.3
X5R
V
402
402 3 VDD AD7992 SCL 10 PMBUS_CLK IN 55 C
2 IN2_P OUT2 4 VREG_VCS_IOUT2 SDA 9 PMBUS_DATA BI 35 44 55 56 57 58 61
1 IN2_N
VREG_VCS_CF2 5 CF2
4 VIN2/REFIN ALERT/BUSY 8
51 IN VREG_VCS_ISENSE_P 9 IN1_P OUT1 7 VREG_VCS_IOUT 5 VIN1
51 IN VREG_VCS_ISENSE_N 10 IN1_N
VREG_VCS_CF1 6 CF1 GND 3 R4B2 1 1 R5N2 6
24.3 KOHM 24.3 KOHM AS
VREG_VCS_IN

1% 1%
CH 7
X817913-001 MSOP10 402 2 2 CH AGND2
402 1 CONVST_N* AGND1 2
2 2 C5B8 1 R4B3
C4B1 1 KOHM

MARGIN_VCS_CONVST
0.22 UF 0.22 UF 1 R4B1 5% X814249-001 MSOP10
10% 10% 1 KOHM 2 CH
6.3 V 6.3 V 5% 402
X5R 1 1 X5R 2 CH
402 402 402 MARGIN_VCS_AS AD7992-1 I2C ADDRESS
AS=VDD 0100100 R/W HEX
WRITE 0100100 0 0X48
READ 0100100 1 0X49
1 R4N1 1 R5B6 AS=GND 0100011 R/W
B 1 KOHM
5%
1 KOHM
5% B
2 EMPTY 2 CH
402 402

V_5P0STBY V_MEM

2 C4N1 U4B1 IC
2.2 UF 1 VDD SCL 9 PMBUS_CLK 55
20%
7 PMBUS_DATA IN
1 6.3 V SDA BI 35 44 55 56 57 58 61
X5R 3 WP*
402
6 A1 A3 12 VREG_VCS_FB OUT 51 57
R4N5 R4B18
57 OUT MEM_VREFS 1 2 MEM_VREFS_R 4 W1 W3 14 VREG_VCS_FB_MID_R 1 2 VREG_VCS_FB_MID OUT 51
0 OHM 5% 0 OHM 5%
402 CH 5 B1 B3 13 402 CH
MARGIN_VREFS_AD1 11 AD1 VSS 8
MARGIN_VREFS_AD0 2 AD0 DGND 10

V_5P0STBY V_5P0STBY V_MEM X819026-001 TSSOP

VALUE=10K
DEFAULT=128 (0X7F)
A 1 R4N2
1 KOHM
1 R4N7
1 KOHM
2 R4N4
100 OHM
SETPOINT1=VREFS 63 (0X3F)
SETPOINT2=VCS 140 (0X8C)
A
5% 5% 5%
2 CH 2 CH 1 CH AD5252 I2C ADDRESS
402 402 402 0101 1 AD1 AD0 R/W
MARGIN_VMEM_VREFS_BOT WRITE 0101 1 1 1 0 0X5E
1 R4N3 1 R4N6 READ 0101 1 1 1 1 0X5F
1 KOHM 1 KOHM
5% 5%
1

2 EMPTY 2 EMPTY V_P Q4B1

402 402 ADR510
NC3 X821158-001
1.0V 0.35%
V_N IC PROJECT NAME PAGE FAB REV
MICROSOFT
2

[PAGE_TITLE=MARGIN, VREFS + VCS] DRAWING

Wed Feb 10 16:23:34 2010 CONFIDENTIAL
TRINITY_XDK 57/81 G 1.01

8 7 6 5 4 3 2 1
 CR-58 : @TRINITY_LIB.TRINITY(SCH_1):PAGE58

8 7 6 5 4 3 2 1
MARGIN, VGPUPCIE, VSBPCIE, VCPUPLL, V12P0, TEMP
V_5P0DUAL
V_3P3STBY
U6A1 IC
D INA219 D
4 VS 1 C3E4
1 C6M5 2.2 UF U3E2
20% IC
0.1 UF
10% 2 6.3
X5R
V
1 VDD SCL 9 PMBUS_CLK 55
6.3 V 402 7 PMBUS_DATA IN
2 X5R SDA BI 35 44 55 56 57 58 61
402 3 WP*
R6A10 52 IN VREG_GPUPCIE_FB 6 A1 A3 12 VREG_CPUPLL_SBPCIE_FB IN 52
38 IN VREG_V12P0_ISENSE_P VREG_V12P0_ISENSE_P_R 1 VIN+
1 2 52 OUT VREG_GPUPCIE_FB_MID 4 W1 W3 14 VREG_CPUPLL_SBPCIE_FB_MID OUT 52
10 OHM 1%
402 CH
1 C6A6
1 UF
10% VREG_GPUPCIE_B1 5 B1 B3 13 VREG_CPUPLL_B3
16 V V_5P0DUAL
X5R
R6A11 2 603 MARGIN_GPUPCIE_CPUPLL_AD1 11 AD1 VSS 8
38 IN VREG_V12P0_ISENSE_N VREG_V12P0_ISENSE_N_R 2 VIN- MARGIN_GPUPCIE_CPUPLL_AD0 2 AD0 DGND 10 1 R3F5
1 2 0 OHM
10 OHM 1% 1 R3F2 1 R3E3 5%
402 CH 1 KOHM 1 KOHM X807129-001 TSSOP 2 CH
5% 5% VALUE=1K 402
2 CH 2 EMPTY 1 R3E1 DEFAULT=127 (0X7F)
61 58 57 56 55 44 35 BI PMBUS_DATA 6 SDA 402 402 0 OHM SETPOINT1=GPUPCIE 92(0X5C)
55 IN PMBUS_CLK 5 SCL 5%
SETPOINT2=CPUPLL 124(0X7C)
C VREG_V12P0_A1 8
2 CH
402 C
A1
VREG_V12P0_A0 7 1 R3F3 1 R3E2 AD5252 I2C ADDRESS
A0
1 KOHM 1 KOHM 0101 1 AD1 AD0 R/W HEX
INA219 I2C ADDRESS 1 R6M4 1 R6M3 3 5% 5% WRITE 0101 1 1 0 0 0X5C
1000 000 R/W HEX 0 OHM 0 OHM GND
2 EMPTY 2 CH READ 0101 1 1 0 1 0X5D
5% 5% 402 402
WRITE 1000 000 0 0X80
READ 1000 000 1 0X81
2 CH 2 CH X820501-001
402 402
SOT23-8

V_5P0DUAL V_3P3STBY
U3T1 IC
REF3333
1 IN OUT 2 1 C1G12 1 C1G11 1 C1G13 1 0R1G1
OHM
0.1 UF 100 PF 10 UF 5%
1 C3U3 1 C3U2 10% 5% 20% 2 CH
B 2.2 UF
20%
GND 3 0.1 UF
10%
2 6.3 V
X5R
402
2 50 V
NPO
402
2 6.3
X5R
805
V 402
U1G2 IC B
6.3 V
2 X5R X820467-001 2 6.3
X5R
V
LM95234
402 SC70 402 2 VDD
3.3V +/-0.15% 61 58 57 56 55 44 35 BI PMBUS_DATA 12 SMBDAT NC 1
55 IN PMBUS_CLK 13 SMBCLK
TEMP_RT_A0 9 A0 TCRIT3_N 14 DB_TM_CT3 1 DB1V1
TEMP_RT_D4_P 3 D4+ TCRIT2_N 11 DB_TM_CT2 1 DB1V2
TEMP_RT_D3_P 4 D3+ TCRIT1_N 10 DB_TM_CT1 1 DB1V3
V_3P3_VREF_CPUPLL_PCIE
TEMP_RT_D_N 5 D-
C1G7
1 100 TEMP_RT_D2_P 6 D2+
1 C3E5 PF
5% TEMP_RT_D1_P 7 D1+
2.2 UF 50 V 8
20% NPO GND
2 6.3 V 2 402
X5R U3E1 IC X819406-001 LLP-14
402
3 VDD AD7992 SCL 10 PMBUS_CLK IN 55
SDA 9 PMBUS_DATA BI 35 44 55 56 57 58 61 C1G8
1 100 PF
5%
50 V
52 IN VREG_GPUPCIE_FB 4 VIN2/REFIN ALERT/BUSY 8 NPO
52 VREG_CPUPLL_SBPCIE_FB 5 VIN1 2 402
LM95234 I2C ADDRESS
IN
1001 110 R/W HEX
WRITE 1001 110 0 0X9C
VREG_CPUPLL_PCIE_AS 6 AS READ 1001 110 1 0X9D
C1G9
1 100
AGND2 7 PF
5%
VREG_CPUPLL_PCIE_CONVST_N 1 CONVST_N* AGND1 2 50 V
NPO
A 1 R3U2
1 KOHM
1 R3E4
1 KOHM
2 402 A
5% 5% X820047-001 MSOP10
2 CH 2 CH
402 402
J1G3 C1G10
2X4HDR 1 100 PF SOLDER LUG
AD7992-0 I2C ADDRESS 5%
1 2 50 V DB1F1
0100 001 R/W HEX NPO 1
3 4
WRITE 0100 001 0 0X42 5 6 2 402
READ 0100 001 1 0X43 7 8

HDR
MICROSOFT PROJECT NAME PAGE FAB REV
[PAGE_TITLE=MARGIN, VGPUPCIE, VSBPCIE, VCPUPLL, V12P0, TEMP] DRAWING
Wed Feb 10 16:23:34 2010 CONFIDENTIAL
TRINITY_XDK 58/81 G 1.01

8 7 6 5 4 3 2 1
 CR-59 : @TRINITY_LIB.TRINITY(SCH_1):PAGE59

8 7 6 5 4 3 2 1
XDK, DEBUG CONNECTORS
V_3P3 V_3P3STBY V_5P0STBY
D D

1 C4A12 C2C4 C3D1 1 C2C5 C2C6

0.1 UF 0.1 UF 1 UF 0.1 UF 1 UF
V_5P0STBY 10% 10% 10% 10% 10%
6.3 V 6.3 V 16 V 6.3 V 16 V
2 X5R X5R X5R 2 X5R X5R
402 402 603 402 603
J2C1 J2C3
2X5HDR_10 2X7HDR_14
28 OUT SPI_SS_N 2 1 SPI_MOSI OUT 28 KER_DBG_TXD 2 1 KER_DBG_RXD
SPI_MISO 4 3 SPI_CLK 26 IN OUT 26
28 IN OUT 28 SMC_DBG_TXD 4 3
6 5 27 IN
8 7 27 OUT SMC_DBG_EN 6 5 SMC_RST_XDK_N

9 R2C6 8 7
55 41 22 27 BI SMB_CLK 1 2 SMB_CLK_R 10 9 SMB_DATA_R

100 OHM 5% 12 11 EXT_PWR_ON_DBG

HDR 402 CH 13 R3R13
C2C3 1 2 SMC_RST_N 22
0.1 UF IN
10% HDR 100 OHM 5%
6.3 V 402 CH
X5R
402 R2C7
1 2 SMB_DATA
C 100 OHM 5%
BI 22 27 41 55
C
402 CH
R2C4
1 2 EXT_PWR_ON_N OUT 37 60 27 61
1 KOHM 5%
402 CH

B B

A A

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=XDK. DEBUG CONN] DRAWING
Wed Feb 10 16:23:35 2010 CONFIDENTIAL
TRINITY_XDK 59/81 G 1.01

8 7 6 5 4 3 2 1
 CR-60 : @TRINITY_LIB.TRINITY(SCH_1):PAGE60

8 7 6 5 4 3 2 1
XDK DEBUG

D GCPU JTAG HEADER D

J4C1
2X4HDR
60 5 OUT CPU_TDI 1 2 CPU_TMS OUT 5 60
5 IN CPU_TDO 3 4 GPU_TRST_N IN 5
60 5 OUT CPU_TCLK 5 6
5 IN CPU_TRST_N_R 7 8 GPU_TRST_ED_N IN 5

HDR

GCPU EEPROM HEADER

J4D1
2X3HDR
5 OUT GPU_SROM_CLK_R 1 2 GPU_SROM_SI IN 5
5 OUT GPU_SROM_SO_R 3 4 GPU_SROM_WP_N OUT 5
5 OUT GPU_SROM_CS_N_R 5 6

HDR

C HANA JTAG HEADER

C
J3C1
2X3HDR
22 OUT HANA_TDI 1 2 HANA_TMS OUT 22
22 IN HANA_TDO 3 4 HANA_TRST IN 22
22 OUT HANA_TCLK 5 6

HDR

SB JTAG HEADER

J3G1
2X3HDR
26 OUT SB_TDI 1 2 SB_TMS OUT 26
26 IN SB_TDO 3 4 SB_TRST IN 26
26 OUT SB_TCLK 5 6

HDR
B V_5P0
B
1
D4D1
GREEN
SM
2 LED
R4D3
CPU_CHECKSTOP_N_LED 1 2 CPU_CHECKSTOP_N_LED_C
V_3P3STBY
825 OHM 1%
V_MEM 402 CH
2 R4E3
3 10 KOHM
R4C9 5%
1 2 CPU_CHECKSTOP_N_LED_B 1 Q4D2 1 CH
1 C4C4 2 R4C6 402
10 KOHM 1 KOHM 5% XSTR
0.1 UF 5% 402 CH 2
10% 1 EMPTY SMC_CPU_CHKSTOP_DETECT BI 27
6.3 V 402
2 X5R 3
402 R4C4
1 2 SMC_CPU_CHKSTOP_DETECT_B 1 Q4D1
1 KOHM 5% XSTR
R4C10 J4C2 402 CH 2
2 IN CPU_RST_V1P1_N 2 1 CPU_RST_N_2_R

1 KOHM 5%
2X5HDR R4C7
402 EMPTY 2 1 CPU_CHECKSTOP_N_R 1 2 CPU_CHECKSTOP_N IN 2
60 5 OUT CPU_TMS 4 3 0 OHM 5%
5 OUT CPU_TRST_N 6 5 402 CH
A 5 IN CPU_TDO
CPU_TDI
8
10
7
9
CPU_TCLK
EXT_PWR_ON_N OUT 5 60 A
60 5 OUT OUT 37 59 27 61

1 C4C3 HDR
0.1 UF
10%
6.3 V
2 X5R
402

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=XDK, DEBUG TITAN] DRAWING
Wed Feb 10 16:23:35 2010 CONFIDENTIAL
TRINITY_XDK 60/81 G 1.01

8 7 6 5 4 3 2 1
 CR-61 : @TRINITY_LIB.TRINITY(SCH_1):PAGE61

8 7 6 5 4 3 2 1
DEBUG BOARD, SPYDER CONN

D D

ALL STP POINTS SHALL BE ADDED TO TOP SIDE IN LAYOUT

V_MEM

1
STP7E1

1
C STP7E2
C
43 IN VREG_CPU_VID<1..6>
V_CPUVCS 1 1
STP7C7
23 IN CPU_TEMP_P 1
STP4C3 STP4C1
1 CPU_TEMP_N OUT 4 23 2 1
STP7C6
3 1
1 STP7C5
STP5D1 R4P2 R4P1 4 1
STP7C4
1 2 1 2 5 1
STP7C3
0 OHM 5% 0 OHM 5% 6 1
1 STP7C2
STP5D2 402 EMPTY 402 EMPTY

EDRAM_TEMP_P 1 STP4C4
1 EDRAM_TEMP_N OUT 4 23
23 IN STP4C6 VREG_CPU_CSSUM 1
44 IN STP7B1
R4P5 R4P4 44 VREG_CPU_CSCOMP 1
1 2 1 2 IN VREG_CPU_CSREF 1
STP7C1
44 IN STP7N1
V_CPUEDRAM 0 OHM 5%
0 OHM 5%
402 EMPTY
402 EMPTY
1
STP4E2
GPU_TEMP_P 1 STP4C2
1 GPU_TEMP_N OUT 4 23 60 59 37 IN EXT_PWR_ON_N 1
STP3C1
23 IN STP4C5
R4P6 R4P3
B 1
STP4E1 1 2 1 2
B
0 OHM 5% 58 57 56 55 44 35 PMBUS_DATA 1
0 OHM 5% 402 EMPTY BI STP5B1
402 EMPTY 55 IN PMBUS_CLK 1
STP5B2

V_CPUCORE

1
STP6C1

1
STP6C2

V_CPUPLL

1
STP4E3

A A

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=DEBUG BOARD, SPYDER CONN] DRAWING
Wed Feb 10 16:23:35 2010 CONFIDENTIAL
TRINITY_XDK 61/81 G 1.01

8 7 6 5 4 3 2 1
 CR-62 : @TRINITY_LIB.TRINITY(SCH_1):PAGE62

8 7 6 5 4 3 2 1
LABELS AND MOUNTING

D D
INTELLIGENT SERIAL NUMBER TARGET.
LB2B1
LABEL

1
1375X250_TARGET
X801181-001

WEST PCB MOUNTING HOLES EAST PCB MOUNTING HOLES

EDGE EDGE EDGE
MTG1B1 MTG4G1 MTG7G1
MTG_HOLE MTG_HOLE MTG_HOLE
C NC9 9 NC9 9 NC9 9 C
EMPTY EMPTY EMPTY
GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8
EDGE
MTG1G1
MTG_HOLE
NC9 9

EMPTY
GND=1,2,3,4,5,6,7,8

B HEAT SINK MOUNTING HOLES B

STD STD
MTG4F1 MTG6F1
MTG_HOLE MTG_HOLE
NC9 9 NC9 9

EMPTY EMPTY
GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8

STD STD
MTG4D1 MTG6D1
MTG_HOLE MTG_HOLE
NC9 9 NC9 9

EMPTY EMPTY
GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8

A A

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=LABELS AND MOUNTING] DRAWING
Wed Feb 10 16:23:35 2010 CONFIDENTIAL
TRINITY_XDK 62/81 G 1.01

8 7 6 5 4 3 2 1
CR-63 : @TRINITY_LIB.TRINITY(SCH_1):PAGE63

MICROSOFT PROJECT NAME PAGE REV

TRINITY_XDK 63/81 1.01
CONFIDENTIAL
CR-64 : @TRINITY_LIB.TRINITY(SCH_1):PAGE64

WAVE USB RJ45 HDMI TOSLINK POWER

CONN TRIPPLE
CONN
AUX
CONN
CONN CONN
CLOCK DIAGRAM CONN

AVIP CONN

I2S_MCLK (12.288MHZ)
AUDIO
ENET
I2S_BCLK (3.072MHZ) DAC
PHY

FAN
CONN
XTAL

HDD ODD PWR

SATA CONN
CONN 27 MHZ
STANDBY
HDD PWR SWITCHERS
ODD CONN VR
ENET_CLK (25MHZ)
SATA
CONN
STBY_CLK (48MHZ)

SATA_CLK_REF (25MHZ)
CPU
VCS
SATA_CLK_DP/DN (100MHZ) HANA VR
VR

PCIEX_CLK_DP/DN (100MHZ) CPU_CLK_DP/DN (100MHZ)

AUD_CLK (24.576MHZ) GPU_CLK_DP/DN (100MHZ)

PIX_CLK_OUT_DP/DN (100MHZ)
V5P0
DUAL
VR

V1P8 MA_CLK1_DP/DN (800MHZ)

VR

MA_CLK0_DP/DN (800MHZ)
MEM

GCPU A & B

CLAM
FLASH MB_CLK1_DP/DN (800MHZ)

MB_CLK0_DP/DN (800MHZ)
PSB VEFUSE
VR

V5P0
V3P3 VGPUPCIE
VR VR

MC_CLK1_DP/DN (800MHZ)

MC_CLK0_DP/DN (800MHZ)

MD_CLK1_DP/DN (800MHZ)

MD_CLK0_DP/DN (800MHZ)
VSBPCIE
VR

VEDRAM
VMEM
VR

MEM C & D CLAM

TILT

PWR EJECT
BUTTON BUTTON BORON FPM IR 2 X GAME CONN

DRAWING
TRINITY_FAB_A MICROSOFT PROJECT NAME PAGE REV
<PAGE_TITLE=CLOCK DIAGRAM> Wed Feb 10 16:23:35 2010
CONFIDENTIAL
TRINITY_XDK 64/81 1.01
CR-65 : @TRINITY_LIB.TRINITY(SCH_1):PAGE65

WAVE USB RJ45 HDMI TOSLINK POWER

CONN TRIPPLE
CONN
AUX
CONN
EXT_PWR_ON_N
CONN CONN
RESET/ENABLE DIAGRAM CONN

AVIP CONN

AUD_RST_N AUDIO
ENET
DAC
PHY

FAN
PSU_V12P0_EN
CONN

HDD ODD PWR STANDBY

SATA CONN SWITCHERS
CONN VR
ENET_RST_N

HDD PWR
ODD CONN
SATA
CONN CPU
VR
ANA_CLK_OE

ANA_RST_N

SMC_RST_N
HANA VCS
VR

DEBUG
CONN

V5P0
EXT_PWR_ON_N
DUAL
VR
SMC_DBG_EN

SMC_RST_N
V1P8
VR
MEM_RST

VREG_CPU_EN MEM
MEM_SCAN_EN
VREG_CPU_PWRGD

CPU_RST_N
GCPU MEM_SCAN_TOP_EN
A & B

CPU_PWRGD CLAM
FLASH
MEM_SCAN_BOT_EN
PSB GPU_RST_N

GPU_RST_DONE

VREG_V5P0_EN VREG_EFUSE_EN
V5P0 VEFUSE
V3P3 VR
VREG_V3P3_EN
VR

VGPUPCIE
VR

MEM_SCAN_TOP_EN

MEM_SCAN_BOT_EN
VSBPCIE
VR

MEM_SCAN_EN
VREG_VEDRAM_EN

MEM_RST
VEDRAM
VMEM
VREG_VMEM_EN
VR

MEM C & D CLAM

TILT

PWR EJECT
BUTTON BUTTON BORON FPM IR 2 X GAME CONN

DRAWING
TRINITY_FAB_A MICROSOFT PROJECT NAME PAGE REV
<PAGE_TITLE=CLOCK DIAGRAM> Wed Feb 10 16:23:35 2010
CONFIDENTIAL
TRINITY_XDK 65/81 1.01
 CR-66 : @TRINITY_LIB.TRINITY(SCH_1):PAGE66

8 7 6 5 4 3 2 1
REFERENCE TABLE

D D

N: MICREL STUFFED BY DEFAULT

REF DES TO STUFF DIGITAL POTENTIOMETERS

MICREL ATHEROS VOLTAGE RAIL STEPS STEP SIZE I2C R/W ADDRESSES
C2C8 C2C8 VMEM 256 0.007031V W: 01011000 0X58, R: 01011001 0X59

C2C9 C2C9 VEDRAM 256 0.004199V W: 01011000 0X58, R: 01011001 0X59

C2D1 C2C10 V5P0 256 0.011719V W: 01011010 0X5A, R: 01011011 0X5B

C2D3 C2D2 V3P3 256 0.008V W: 01011010 0X5A, R: 01011011 0X5B

C C2P2 C2D3 VREF 256 0.007031V W: 01011110 0X5E, R: 01011111 0X5F C
C2P3 C2D4 VCS 256 ?V W: 01011110 0X5E, R: 01011111 0X5F

C2P4 C2D5 GPUPCIE 256 0.005859V W: 01011100 0X5C, R: 01011101 0X5D

C2P5 C2P2 CPUPLL_SBPCIE 256 0.007148V W: 01011100 0X5C, R: 01011101 0X5D

C2R5 C2P4

C2R6 C2P5

FB2C1 C2R3

R2D1 FB2C1

R2D2 FB2R1

R2D3 R2D2
ANALOG TO DIGITAL CONVERTERS
R2D4 R2D4
VOLTAGE RAIL STEPS STEP SIZE I2C R/W ADDRESSES
B R2D6 R2R1 VMEM 4096 0.001221V W: 01010000 0X50, R: 01010001 0X51
B
R2R10 R2R10 VEDRAM 4096 0.001221V W: 01010000 0X50, R: 01010001 0X51

R2R2 R2R11 V5P0 4096 0.000806V W: 01010010 0X52, R: 01010011 0X53

R2R4 R2R12 V3P3 4096 0.000806V W: 01010010 0X52, R: 01010011 0X53

R2R8 R2R13 VCS 4096 0.000806V W: 01001000 0X48, R: 01001001 0X49

U2D1 R2R15 MEM_VREF 4096 0.000806V W: 01000110 0X46, R: 01000111 0X47

R2R3 GPUPCIE 4096 0.000806V W: 01000010 0X42, R: 01000011 0X43

R2R5 CPUPLL_SBPCIE 4096 0.000806V W: 01000010 0X42, R: 01000011 0X43

R2R6

R2R7

R2R9

U2D1

N: FOR MICREL U2D1 IS P/N X819763-001

N: FOR ATHEROS U2D1 IS P/N X820024-001
A A

DRAWING MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=REFERENCE TABLES] Wed Feb 10 16:23:35 2010
CONFIDENTIAL
TRINITY_XDK 66/81 G 1.01

8 7 6 5 4 3 2 1
 CR-67 : @TRINITY_LIB.TRINITY(SCH_1):PAGE67

8 7 6 5 4 3 2 1
TRINITY DOC TRACKER

D D
DOC # DESCRIPTION
H08752 TRINITY CONSOLE MONITORING AND MARGINING
H08772 TRINITY CONSOLE FAN DRIVER / THERMAL ALGORITHM
H09297 TRINITY HS PWM FAN SPECIFICATION
H07617 TRINITY VEJLE THERMAL DESIGN AND QUAL SPECIFICATION
H05204 TRINITY PCB TECHNOLOGY SPECIFICATION
H08753 TRINITY CONSOLE HDD SPECIFICATION
H08938 ODD COMP SPEC
H08939 ODD ATA INTERFACE SPEC
H02235 ODD AP MEDIA SPECIFICATION
H08771 TRINITY CONSOLE TEST HOOK SPECIFICATION
DFM GUIDELINES
H08756 TRINITY CONSOLE USB SPECIFICATION
H08762 TRINITY CONSOLE V_5P0 REGULATOR SPECIFICATION
TRINITY CONSOLE V_5P0DUAL SPECIFICATION
TRINITY CONSOLE BLEEDER SPECIFICATION
H08759 TRINITY CONSOLE V_CPUVCS REGULATOR SPECIFICATION
H08760 TRINITY CONSOLE V_3P3STBY REGULATOR SPECIFICATION
H08761 TRINITY CONSOLE V_1P8STBY REGULATOR SPECIFICATION
H08763 TRINITY CONSOLE V_3P3 REGULATOR SPECIFICATION
C H08764
H08765
TRINITY CONSOLE V_MEM REGULATOR SPECIFICATION
TRINITY CONSOLE V_EDRAM REGULATOR SPECIFICATION C
H08766 TRINITY CONSOLE LINEAR REGULATOR SPECIFICATION
H08767 TRINITY CONSOLE VR ARCHITECTURE
H08758 TRINITY CONSOLE V_CPUCORE REGULATOR SPECIFICATION
SMC POR FLOWCHART
H08768 TRINITY CONSOLE SYSTEM MANAGEMENT SPECIFICATION
H08773 TRINITY CONSOLE DVD EJECT CAPACITIVE TOUCH SPECIFICATION
H09553 TRINITY CONSOLE WIFI MODULE SPECIFICATION
H08777 TRINITY CONSOLE SPECIFICATION TEMPLATE
H08776 TRINITY CONSOLE FPM REQUIREMENTS DOCUMENT
H08754 TRINITY CONSOLE AUDIO / VIDEO SPECIFICATION
H08757 TRINITY CONSOLE IR SPECIFICATION
H08770 TRINITY CONSOLE TILT SWITCH SPECIFICATION
H08775 TRINITY CONSOLE FPM LED DISPLAY SPECIFICATION
H08774 TRINITY CONSOLE EMI/ESD/SAFETY SPECIFICATION
H08676 CONSOLE USAGE MODEL AND RELIABILITY BUDGET
H08750 TRINITY CONSOLE PLATFORM DESIGN GUIDE
H08778 TRINITY CONSOLE POWER BUDGET
H08780 TRINITY CONSOLE ACOUSTICS MODEL
H09169 TRINITY RJ45 + AUX INTERFACE AND CONNECTOR SPEC
CONSOLE RELIABILITY SPECIFICATION
B H08751
H08769
TRINITY CONSOLE FLASH SPECIFICATION
TRINITY CONSOLE PLL SPECIFICATION B
H08755 TRINITY CONSOLE ETHERNET SPECIFICATION
H08945 TRINITY DC CABLE AND CONNECTOR SPEC H08945
H08946 TRINITY PSU SPECS H08946

A A

MICROSOFT PROJECT NAME PAGE FAB REV

[PAGE_TITLE=DOC TRACKER] CONFIDENTIAL
TRINITY_XDK 67/81 G 1.01

8 7 6 5 4 3 2 1
Title: Basenet Report CAL_TEMP_P 23A4 CPU_VDDS0_DN 6D8 FAN_OP1_DP 23A7
Design: trinity CAPX 35C4 CPU_VDDS0_DP 6D8 FAN_PULLUP 36C2
Date: Feb 10 16:21:00 2010 CAPY 35C4 CPU_VDDS1_DN 6D8 FLSH_ALE 28C2 34B5
CAPZ 35C4 CPU_VDDS1_DP 6D8 FLSH_CE_N 28C2 34B5
Base nets and synonyms for CORE_HF_BGR_PLL 2A1 CPU_VGATE 2B7 FLSH_CLE 28C2 34B5
trinity_lib.TRINITY(@trinity_lib.trinity( CPU_CHECKSTOP_N 2D1 60A2 CPU_VREG_APS1 2C1 43C7 FLSH_DATA<7..0> 28C7 34C8
sch_1)) CPU_CHECKSTOP_N_LED 60B5 CPU_VREG_APS2 2C1 43D7 FLSH_NC38 34C2
Base Signal CPU_CHECKSTOP_N_LED_B 60A4 CPU_VREG_APS3 2C1 43D7 FLSH_READY 34C1 28B7
Location([Zone][dir]) CPU_CHECKSTOP_N_LED_C 60B4 CPU_VREG_APS4 2C1 43D7 FLSH_RE_N 28C2 34B5
CPU_CHECKSTOP_N_R 60A5 CPU_VREG_APS5 2C1 43D7 FLSH_WE_N 28C2 34B5
ACCELEROMETER_INT 35C4 CPU_CLK_DN 22D1 2C7 CPU_VREG_APS6 2C1 43D7 FLSH_WP_N 28C7 34B5
ANA_CLK_OE 27D1 22C8 CPU_CLK_DN_R 22C4 DBG_LED0 27A8 GAMEPORT1_DN 28B2 39D8
ANA_CLK_OE_R 22C6 CPU_CLK_DN_R2 2C7 DB_TM_CT1 58B1 GAMEPORT1_DP 28B2 39D8
ANA_RST_N 27D1 22D7 CPU_CLK_DP 22D1 2C7 DB_TM_CT2 58B1 GAMEPORT2_DN 28B2 39C8
ANA_V12P0_PWRGD 22D3 27D1 42B8 CPU_CLK_DP_R 22C4 DB_TM_CT3 58B1 GAMEPORT2_DP 28B2 39C8
ANA_VID_INT 23D1 26B2 CPU_CLK_DP_R2 2C7 DFM_THIEVING_PADS_REQUIREMENT3 38D5 GND_DECOUPLE 32A5
AUD_CLK 22A1 29C7 CPU_CORE_HF_CLKOUT_DN 6D1 ECB_CLK_BYP 26D6 GPU_CLK_DN 22D1 4D8
AUD_CLK_R 22B4 CPU_CORE_HF_CLKOUT_DP 6D1 ECB_CLK_SEL 26D6 GPU_CLK_DN_C 4C8
AUD_L_OUT 33C1 37C7 CPU_DBG0_POST0 3A5 EDRAM_PSRO_DOUT 2B7 GPU_CLK_DN_R 22C4
AUD_RDY_BSBY 26A2 35A3 CPU_DBG1_POST1 3A5 EDRAM_TEMP_N 4B8 61B3 23A8 GPU_CLK_DN_R2 4D6
AUD_RST_N 26B2 33B7 CPU_DBG2_POST2 3A5 EDRAM_TEMP_P 23A1 4B8 61B6 GPU_CLK_DP 22D1 4D8
AUD_R_OUT 33B1 37C7 CPU_DBG3_POST3 3A5 EJECTSW_N 38A8 27C1 35A3 GPU_CLK_DP_C 4D8
AUD_SPI_CLK 26A6 35A7 CPU_DBG4_POST4 3A5 EJECTSW_N_R 38A6 GPU_CLK_DP_R 22C4
AUD_SPI_MISO 35A3 26A6 CPU_DBG5_POST5 3A5 ENET_1.8VEXT 32C5 GPU_CLK_DP_R2 4D6
AUD_SPI_MOSI 26A4 35A7 CPU_DBG6_POST6 3A5 ENET_ACT_N 32A3 GPU_DBG_RST_EN 2B7
AUD_SSB 26A1 35A7 CPU_DBG7_POST7 3A5 ENET_CLK 22A1 32B8 GPU_HSYNC_OUT 4B1 23C8
AUD_VOUTL 33B4 CPU_DBG8_RST0 3A5 ENET_CLK_R 22C4 GPU_PIX_CLK_1X 4C2 23D8
AUD_VOUTL_R 33B3 CPU_DBG9_RST1 3A5 ENET_LINK_N 32A3 GPU_RST_DONE 4D2 27C1
AUD_VOUTR 33B4 CPU_DBG10_RST2 3A5 ENET_REF_CLK_OUT 32B5 GPU_RST_DONE_R 27C4
AUD_VOUTR_R 33B3 CPU_DBG11_GPU_HB_TP 3A5 ENET_REXT 32B5 GPU_RST_N 27A1 4C8
AV_MODE0 37C3 27B8 37B3 CPU_DBG12_CPUCLK0_TP 3A5 ENET_RSTN_R 32A5 GPU_SROM_CLK_R 60C8 5B1
AV_MODE0_R 27B6 CPU_DBG13_CPUCLK1_TP 3A5 ENET_RST_N 26B2 32A8 32B8 GPU_SROM_CS 5C4
AV_MODE1 37C3 27B8 37C3 CPU_DBG14_GPUCLK0_TP 3A5 ENET_RX_DN 32A8 38B8 GPU_SROM_CS_N_R 60C8 5B1
AV_MODE1_R 27B6 CPU_DBG15_GPUCLK1_TP 3A5 ENET_RX_DP 32A8 38C8 GPU_SROM_EN 5C4
AV_MODE2 37C3 27B8 37C3 CPU_DBG_RST_EN 2B7 ENET_RX_TERM 38C7 GPU_SROM_SCLK 5C4
AV_MODE2_R 27B6 CPU_DBG_TBCLK0 3D7 ENET_TX_DN 32A1 38C8 GPU_SROM_SI 5B1 60C6
BINDSW_N 38A8 27C1 CPU_DBG_TBCLK1 3D7 ENET_TX_DP 32A1 38C8 GPU_SROM_SO 5C4
BINDSW_N_R 38A6 CPU_DLL_SNIF_OUT 3D7 ENET_TX_TERM 38C7 GPU_SROM_SO_R 60C8 5B1
BLEEDER_B 42B2 CPU_DLL_SNIF_OUT_TP 3D5 EN_TEST0_N 27A6 GPU_SROM_WP_N 60C6 5B1
BLEEDER_C1 42B2 CPU_EXT_CLK_EN 2B7 EN_TEST1_N 27A6 GPU_TEMP_N 4B8 61B3 23A8
BLEEDER_C2 42B2 CPU_LIMIT_BYPASS 2B1 EXPPORT_PORT1_DN 28B7 39C4 GPU_TEMP_P 23A1 4C8 61B6
BLEEDER_V12P0_B1 42B7 CPU_PLL_BYPASS 2B1 EXPPORT_PORT1_DP 28B7 39C4 GPU_TRST_ED_N 5B8 60D6
BLEEDER_V12P0_B2 42C5 CPU_PSRO0_OUT 2B7 EXPPORT_PORT2_DN 28B7 39B4 GPU_TRST_N 5B8 60D6
BLEEDER_V12P0_C1 42B6 CPU_PWRGD 27A1 2D7 EXPPORT_PORT2_DP 28B7 39B4 GPU_VSYNC_OUT 4B1 23C8
BLEEDER_V12P0_C2 42B6 CPU_RST_N 27B1 2D7 EXPPORT_PORT3_DN 28A7 39A4 HANA_AV_CLK 22B4
BLEEDER_V12P0_LOAD 42B5 CPU_RST_N_2_R 60A6 EXPPORT_PORT3_DP 28B7 39A4 HANA_CLK_DRV_RSET1 22C6
BMA_PS_R 35C5 CPU_RST_V1P1_N 2D1 60A7 EXPPORT_RJ45_DN 28B7 38C5 HANA_CLK_DRV_RSET2 22C6
BND_GAP_CAP 23A5 CPU_SRVID 2B1 51B8 EXPPORT_RJ45_DP 28B7 38C5 HANA_DAC_RSET 23C6
BORONFPMPORT_DN 28C2 38B8 CPU_TCLK 5C8 60A2 60D8 EXT_PWR_ON_DBG 59C3 HANA_OP2_DN 23A2 23B6
BORONFPMPORT_DP 28C2 38B8 CPU_TDI 5C8 60A7 60D8 EXT_PWR_ON_N 37D3 59C1 60A2 27C8 HANA_OP2_DP 23B6
BORONFPM_CLK 27A1 38A8 CPU_TDO 5C8 60A7 60D8 37C3 61B2 HANA_OP2_OUT 23A4
BORONFPM_DATA 27A1 38A8 CPU_TEMP_N 4B8 61C3 23A8 EXT_PWR_ON_R 27C6 HANA_PIX_CLK_2X_DN 22B1 4C8
BRD_TEMP_N 23C2 38A8 23A8 CPU_TEMP_P 23A1 4B8 61C6 FAN1_FDBK 36B4 23A6 HANA_PIX_CLK_2X_DN_R 22C4
BRD_TEMP_N_R 38A6 CPU_TINIT 2A6 FAN1_FDBK_R 36B6 HANA_PIX_CLK_2X_DP 22B1 4C8
BRD_TEMP_P 23A1 23C2 38A8 CPU_TMS 5C8 60A7 60D6 FAN1_OUT 23A2 36C6 HANA_PIX_CLK_2X_DP_R 22C4
BRD_TEMP_P_R 38A6 CPU_TRST_N 5C8 60A7 FAN1_Q1_C 36C5 HANA_POR_BYPASS 22D6
CAL_TEMP_N 23A1 23A8 CPU_TRST_N_R 5C8 60D8 FAN1_Q1_E 36C5 HANA_SPDIF_OUT 23A2 37D8 39A8
MICROSOFT PROJECT NAME PAGE REV
TRINITY_XDK 68/81 1.01
CONFIDENTIAL
HANA_TCLK 60C8 22B8 MARGIN_GPUPCIE_CPUPLL_AD0 58C4 MA_DQ30 12D8 14D4 15C5 MB_DQ28 12D4 16C5 17C5
HANA_TDI 60C8 22B8 MARGIN_GPUPCIE_CPUPLL_AD1 58C4 MA_DQ31 12D8 14D4 15C5 MB_DQ29 12D4 16C5 17C5
HANA_TDO 22B8 60C8 MARGIN_V3P3_V5P0_AD0 56C6 MA_RAS_N 12B5 14B8 15B8 MB_DQ30 12D4 16C5 17C5
HANA_TMS 60C6 22B8 MARGIN_V3P3_V5P0_AD1 56C6 MA_RDQS0 14B4 15B5 12B8 MB_DQ31 12D4 16D5 17C5
HANA_TRST 22B8 60C6 MARGIN_VCS_AS 57B5 MA_RDQS1 14B4 15B5 12C8 MB_RAS_N 12B1 16B8 17B8
HANA_V_12P0_DET 22D6 MARGIN_VCS_CONVST 57B4 MA_RDQS2 14C4 15C5 12C8 MB_RDQS0 16B5 17B5 12B4
HANA_V_12P0_DET_R 22D5 MARGIN_VMEM_VEDRAM_AD0 55C4 MA_RDQS3 14C4 15C5 12D8 MB_RDQS1 16B5 17B5 12C4
HANA_XTAL_BYPASS 22C6 MARGIN_VMEM_VEDRAM_AD1 55C4 MA_VREF0 12A7 MB_RDQS2 16C5 17C5 12C4
HANA_XTAL_IN 22C6 MARGIN_VMEM_VREFS_BOT 57A6 MA_WDQS0 12A6 12B8 14B4 15B5 MB_RDQS3 16C5 17C5 12D4
HANA_XTAL_OUT 22C6 MARGIN_VREFS_AD0 57A6 MA_WDQS1 12B6 12C8 14B4 15B5 MB_VREF0 12A3
HANA_XTAL_VSS_CAP 22C6 MARGIN_VREFS_AD1 57A6 MA_WDQS2 12C8 14C4 15C5 MB_WDQS0 12A2 12B4 16B5 17B5
HBEDB_CLK_BYP 26D6 MARGIN_VREFS_AS 57D4 MA_WDQS3 12D8 14C4 15C5 MB_WDQS1 12B2 12C4 16B5 17B5
HBEDB_CLK_SEL 26D6 MARGIN_VREFS_CONVST 57C4 MA_WE_N 12B5 14B8 15B8 MB_WDQS2 12C4 16C5 17C5
HDD_RX_DN 41C8 29B7 MA_A<11..0> 12C5 14C8 15C8 MA_ZQ_BOT 15B5 MB_WDQS3 12D4 16C5 17C5
HDD_RX_DN_C 41C6 MA_BA<2..0> 12C5 14C8 15C8 MA_ZQ_TOP 14B5 MB_WE_N 12B1 16B8 17B8
HDD_RX_DP 41C8 29B7 MA_CAS_N 12B5 14B8 15B8 MB_A<11..0> 12C1 16C8 17C8 MB_ZQ_BOT 17A5
HDD_RX_DP_C 41C6 MA_CKE 12B5 14B8 15B8 MB_BA<2..0> 12C1 16B8 17B8 MB_ZQ_TOP 16A5
HDD_TX_DN 29A1 41D8 MA_CLK0_DN 12C5 14D8 MB_CAS_N 12B1 16B8 17B8 MC_A<11..0> 13C5 18C8 19C8
HDD_TX_DN_C 41D6 MA_CLK0_DP 12C5 14D8 MB_CKE 12B1 16B8 17B8 MC_BA<2..0> 13C5 18B8 19B8
HDD_TX_DP 29A1 41D8 MA_CLK1_DN 12C5 15D8 MB_CLK0_DN 12C1 16C8 MC_CAS_N 13B5 18B8 19B8
HDD_TX_DP_C 41D6 MA_CLK1_DP 12C5 15D8 MB_CLK0_DP 12C1 16D8 MC_CKE 13C5 18B8 19B8
HDMI_CEC 40B3 MA_CS0_N 12B5 14B8 MB_CLK1_DN 12C1 17C8 MC_CLK0_DN 13C5 18D8
HDMI_DDC_CLK 23A2 27B8 37D3 40A8 MA_CS1_N 12B5 14B8 15B8 MB_CLK1_DP 12C1 17D8 MC_CLK0_DP 13C5 18D8
55D8 MA_DM0 12B8 14B4 15B5 MB_CS0_N 12B1 16B8 MC_CLK1_DN 13C5 19D8
HDMI_DDC_DATA 23A2 27C8 37C3 40A8 MA_DM1 12C8 14B4 15B5 MB_CS1_N 12B1 16B8 17B8 MC_CLK1_DP 13D5 19D8
55D8 MA_DM2 12C8 14C4 15C5 MB_DM0 12B4 16B5 17B5 MC_CS0_N 13B5 18B8
HDMI_EXT_SWING 23C4 MA_DM3 12D8 14C4 15C5 MB_DM1 12C4 16B5 17B5 MC_CS1_N 13B5 18B8 19B8
HDMI_HPD 40A1 23C8 MA_DQ0 12B8 14B4 15B5 MB_DM2 12C4 16C5 17C5 MC_DM0 13B8 18B4 19B4
HDMI_HPD_PIN 40A3 MA_DQ1 12B8 14B4 15B5 MB_DM3 12D4 16C5 17C5 MC_DM1 13C8 18B4 19B4
HDMI_TX0_DN 23A1 40C8 MA_DQ2 12B8 14B4 15B5 MB_DQ0 12B4 16B5 17B5 MC_DM2 13C8 18C4 19C4
HDMI_TX0_DP 23B1 40C8 MA_DQ3 12B8 14B4 15B5 MB_DQ1 12B4 16B5 17B5 MC_DM3 13D8 18C4 19C4
HDMI_TX0_DP_R 23B2 MA_DQ4 12B6 12B8 14B4 15B5 MB_DQ2 12B4 16B5 17B5 MC_DQ0 13B8 18B4 19B4
HDMI_TX1_DN 23B1 40C8 MA_DQ5 12B8 14B4 15C5 MB_DQ3 12B4 16B5 17B5 MC_DQ1 13B8 18B4 19B4
HDMI_TX1_DP 23B1 40D8 MA_DQ6 12B8 14B4 15C5 MB_DQ4 12B2 12B4 16B5 17B5 MC_DQ2 13B8 18B4 19B4
HDMI_TX1_DP_R 23B2 MA_DQ7 12B8 14B4 15C5 MB_DQ5 12B4 16B5 17B5 MC_DQ3 13B8 18B4 19B4
HDMI_TX2_DN 23B1 40D8 MA_DQ8 12C8 14B4 15B5 MB_DQ6 12B4 16B5 17B5 MC_DQ4 13B6 13B8 18B4 19B4
HDMI_TX2_DP 23B1 40D8 MA_DQ9 12C8 14B4 15B5 MB_DQ7 12B4 16B5 17B5 MC_DQ5 13B8 18B4 19B4
HDMI_TX2_DP_R 23B2 MA_DQ10 12C8 14B4 15B5 MB_DQ8 12C4 16B5 17B5 MC_DQ6 13B8 18B4 19B4
HDMI_TXC_DN 23B1 40B8 MA_DQ11 12C8 14B4 15B5 MB_DQ9 12C4 16B5 17B5 MC_DQ7 13B8 18B4 19C4
HDMI_TXC_DP 23C1 40B8 MA_DQ12 12B6 12C8 14B4 15B5 MB_DQ10 12C4 16B5 17B5 MC_DQ8 13C8 18B4 19B4
HDMI_TXC_DP_R 23C2 MA_DQ13 12C8 14B4 15B5 MB_DQ11 12C4 16B5 17B5 MC_DQ9 13C8 18B4 19B4
I2S_BCLK 29B1 23C8 33B7 MA_DQ14 12C8 14C4 15B5 MB_DQ12 12B2 12C4 16B5 17B5 MC_DQ10 13C8 18B4 19B4
I2S_BCLK_R 29B4 MA_DQ15 12C8 14C4 15B5 MB_DQ13 12C4 16B5 17B5 MC_DQ11 13C8 18B4 19B4
I2S_MCLK 29B1 33B7 MA_DQ16 12C8 14C4 15C5 MB_DQ14 12C4 16B5 17B5 MC_DQ12 13B6 13C8 18B4 19B4
I2S_MCLK_R 29B4 MA_DQ17 12C8 14C4 15C5 MB_DQ15 12C4 16B5 17B5 MC_DQ13 13C8 18B4 19B4
I2S_SD 29B1 23B8 33B7 MA_DQ18 12C8 14C4 15C5 MB_DQ16 12C4 16C5 17C5 MC_DQ14 13C8 18C4 19B4
I2S_SD1 23B6 MA_DQ19 12C8 14C4 15C5 MB_DQ17 12C4 16C5 17C5 MC_DQ15 13C8 18C4 19B4
I2S_SD2 23B6 MA_DQ20 12C8 14C4 15D5 MB_DQ18 12C4 16C5 17C5 MC_DQ16 13C8 18C4 19C4
I2S_SD3 23B6 MA_DQ21 12C8 14C4 15D5 MB_DQ19 12C4 16C5 17C5 MC_DQ17 13C8 18C4 19C4
I2S_SD_R 29B4 MA_DQ22 12C8 14C4 15D5 MB_DQ20 12C4 16C5 17C5 MC_DQ18 13C8 18C4 19C4
I2S_WS 29B1 23C8 33B7 MA_DQ23 12C8 14C4 15D5 MB_DQ21 12C4 16C5 17C5 MC_DQ19 13C8 18C4 19C4
I2S_WS_R 29B4 MA_DQ24 12D8 14C4 15C5 MB_DQ22 12C4 16C5 17C5 MC_DQ20 13C8 18C4 19C4
IR_DATA 35B5 27A8 MA_DQ25 12D8 14C4 15C5 MB_DQ23 12C4 16C5 17D5 MC_DQ21 13C8 18C4 19C4
KER_DBG_RXD 59C1 26C7 MA_DQ26 12D8 14C4 15C5 MB_DQ24 12D4 16C5 17C5 MC_DQ22 13C8 18C4 19D4
KER_DBG_TXD 26C1 59C5 MA_DQ27 12D8 14C4 15C5 MB_DQ25 12D4 16C5 17C5 MC_DQ23 13D8 18C4 19D4
KER_DBG_TXD_R 26C3 MA_DQ28 12D8 14C4 15C5 MB_DQ26 12D4 16C5 17C5 MC_DQ24 13D8 18C4 19C4
LVLCNT 37C7 MA_DQ29 12D8 14D4 15C5 MB_DQ27 12D4 16C5 17C5 MC_DQ25 13D8 18C4 19C4
MICROSOFT PROJECT NAME PAGE REV
TRINITY_XDK 69/81 1.01
CONFIDENTIAL
MC_DQ26 13D8 18C4 19C4 MD_DQ24 13D4 20C4 21C5 MII_TXD2 29C1 32A8 SATA_CLK_DN 22B1 26D7
MC_DQ27 13D8 18C4 19C4 MD_DQ25 13D4 20C4 21C5 MII_TXD3 29C1 32B8 SATA_CLK_DN_R 22C4
MC_DQ28 13D8 18C4 19C4 MD_DQ26 13D4 20C4 21C5 MII_TXEN 29C1 32B8 SATA_CLK_DP 22C1 26D7
MC_DQ29 13D8 18D4 19C4 MD_DQ27 13D4 20D4 21C5 MII_TX_CLK 32B1 29D7 SATA_CLK_DP_R 22C4
MC_DQ30 13D8 18D4 19C4 MD_DQ28 13D4 20D4 21C5 MII_TX_CLK_R 29D6 SATA_CLK_REF 22B1 26D7
MC_DQ31 13D8 18D4 19C4 MD_DQ29 13D4 20D4 21C5 MUPORT_DN 28C2 41B3 SATA_CLK_REF_R 22C4
MC_RAS_N 13B5 18B8 19B8 MD_DQ30 13D4 20D4 21C5 MUPORT_DP 28C2 41B3 SATA_CLK_SEL 26D6
MC_RDQS0 18B4 19B4 13B8 MD_DQ31 13D4 20D4 21C5 NET_241_I118_B 39B6 SATA_RBIAS 29A6
MC_RDQS1 18B4 19B4 13C8 MD_RAS_N 13B1 20B8 21B8 NET_259_I6_VIN1 57D3 SB_GPIO<0..15> 26B1 26B5
MC_RDQS2 18C4 19C4 13C8 MD_RDQS0 20B4 21B5 13B4 ODD_RX_DN 41A8 29B7 SB_GPIO<11> 26A4
MC_RDQS3 18C4 19C4 13D8 MD_RDQS1 20B4 21B5 13C4 ODD_RX_DN_C 41A7 SB_GPIO<14> 26A2
MC_VREF0 13A7 MD_RDQS2 20C4 21C5 13C4 ODD_RX_DP 41A8 29B7 SB_GPIO<15> 26A8
MC_WDQS0 13B5 13B8 18B4 19B4 MD_RDQS3 20C4 21C5 13D4 ODD_RX_DP_C 41A7 SB_GPIO_RESERVED6 26B2 26A8
MC_WDQS1 13B5 13C8 18B4 19B4 MD_VREF0 13A3 ODD_TX_DN 29A1 41A8 SB_GPIO_RESERVED16 26B3
MC_WDQS2 13C8 18C4 19C4 MD_WDQS0 13B4 20B4 21B5 ODD_TX_DN_C 41A7 SB_GPIO_RESERVED17 26B3
MC_WDQS3 13D8 18C4 19C4 MD_WDQS1 13B2 13C4 20B4 21B5 ODD_TX_DP 29A1 41B8 SB_GPIO_RESERVED18 26B3
MC_WE_N 13B5 18B8 19B8 MD_WDQS2 13C4 20C4 21C5 ODD_TX_DP_C 41B7 SB_GPIO_RESERVED19 26B3
MC_ZQ_BOT 19B5 MD_WDQS3 13D4 20C4 21C5 PCIEX_CLK_DN 22C1 26C7 SB_GPIO_RESERVED20 26B3
MC_ZQ_TOP 18B5 MD_WE_N 13B1 20B8 21B8 PCIEX_CLK_DN_R 22C4 SB_GPIO_RESERVED21 26B3
MD_A<11..0> 13C1 20C8 21C8 MD_ZQ_BOT 21B5 PCIEX_CLK_DP 22C1 26C7 SB_GPIO_RESERVED22 26B3
MD_BA<2..0> 13C1 20C8 21B8 MD_ZQ_TOP 20B5 PCIEX_CLK_DP_R 22C4 SB_GPIO_RESERVED23 26B3
MD_CAS_N 13B1 20B8 21B8 MEM_A_VREF0 15A6 14B8 15B8 PCIEX_INT 26B2 26A6 SB_GPIO_RESERVED24 26B3
MD_CKE 13C1 20B8 21B8 MEM_A_VREF1 14A6 14B8 15B8 PEX_GPU_SB_L0_DN 4C2 26C7 SB_GPIO_RESERVED25 26C3
MD_CLK0_DN 13C1 20D8 MEM_B_VREF0 17A6 16B8 17B8 PEX_GPU_SB_L0_DN_C 4C4 SB_GPIO_RESERVED26 26C3
MD_CLK0_DP 13C1 20D8 MEM_B_VREF1 16A6 16B8 17B8 PEX_GPU_SB_L0_DP 4C2 26C7 SB_GPIO_RESERVED27 26C3
MD_CLK1_DN 13C1 21D8 MEM_CALA 4A6 PEX_GPU_SB_L0_DP_C 4C4 SB_GPIO_RESERVED28 26C3
MD_CLK1_DP 13D1 21D8 MEM_CALB 4A6 PEX_GPU_SB_L1_DN 4C2 26C7 SB_GPIO_RESERVED29 26C3
MD_CS0_N 13B1 20B8 MEM_C_VREF0 19A6 18B8 19B8 PEX_GPU_SB_L1_DN_C 4C4 SB_GPIO_RESERVED30 26C3
MD_CS1_N 13B1 20B8 21B8 MEM_C_VREF1 18A6 18B8 19B8 PEX_GPU_SB_L1_DP 4D2 26C7 SB_GPIO_RESERVED31 26C3
MD_DM0 13B4 20B4 21B5 MEM_D_VREF0 21A6 20B8 21B8 PEX_GPU_SB_L1_DP_C 4D4 SB_MAIN_PWRGD 27B1 27D8
MD_DM1 13C4 20B4 21B5 MEM_D_VREF1 20A6 20B8 21B8 PEX_RBIAS0 26C6 SB_MAIN_PWRGD_R 27B4
MD_DM2 13C4 20C4 21C5 MEM_RST 4B1 14D8 15D8 16C8 PEX_RBIAS1 26C6 SB_RST_N 27A1 27D8
MD_DM3 13D4 20C4 21C5 17C8 18D8 19C8 20D8 21D8 PEX_RCAL 4C6 SB_SPDIF_OUT 29B1 23C8
MD_DQ0 13B4 20B4 21B5 MEM_SCAN_BOT_EN 4A1 15B8 17B8 19B8 PEX_SB_GPU_L0_DN 26C1 4C8 SB_TCLK 60B8 26A6
MD_DQ1 13B4 20B4 21B5 21B8 PEX_SB_GPU_L0_DN_C 26C3 SB_TDI 60B8 26A6
MD_DQ2 13B4 20B4 21B5 MEM_SCAN_BOT_EN_N 4A4 PEX_SB_GPU_L0_DP 26D1 4C8 SB_TDO 26A6 60B8
MD_DQ3 13B4 20B4 21B5 MEM_SCAN_EN 4A1 14B8 15B8 16B8 PEX_SB_GPU_L0_DP_C 26D3 SB_TMS 60B6 26A6
MD_DQ4 13B4 20B4 21B5 17B8 18B8 19B8 20B8 21B8 PEX_SB_GPU_L1_DN 26D1 4C8 SB_TRST 26A6 60B6
MD_DQ5 13B4 20B4 21B5 MEM_SCAN_TOP_EN 4A1 14B8 16B8 18B8 PEX_SB_GPU_L1_DN_C 26D3 SB_USB_RBIAS 28A6
MD_DQ6 13B4 20B4 21C5 20B8 PEX_SB_GPU_L1_DP 26D1 4C8 SCART_RGB 26B2 37B8
MD_DQ7 13B4 20B4 21C5 MEM_VREFS 57A6 57D4 PEX_SB_GPU_L1_DP_C 26D3 SCART_RGB_OUT 37B6
MD_DQ8 13C4 20B4 21B5 MEM_VREFS_R 57A6 PIX_DATA<14..0> 4C2 23D8 SCART_RGB_OUT_R 37B7
MD_DQ9 13C4 20B4 21B5 MII_COL 32C1 29C7 PMBUS_CLK 55D6 35C8 44C8 55A2 SCART_RGB_R 37B7
MD_DQ10 13C4 20B4 21B5 MII_CRS 32C1 29C7 55D1 56B1 56D4 57B2 57C2 57D1 58A5 58B4 SMB_CLK 27B8 59C5 22B8 41B3
MD_DQ11 13C4 20B4 21B5 MII_MDC_CLK_OUT 29D1 32B8 58C8 58D1 61B2 55D8
MD_DQ12 13B2 13C4 20C4 21B5 MII_MDC_CLK_OUT_R 29D4 PMBUS_CLK_FET 35C6 SMB_CLK_MU_R 41B2
MD_DQ13 13C4 20C4 21B5 MII_MDIO 29C8 32B8 PMBUS_DATA 35C8 44C8 55A2 55D1 SMB_CLK_R 59C4
MD_DQ14 13C4 20C4 21B5 MII_RXD0 32A1 29C7 55D6 56B1 56D3 57A2 57C2 57D1 58A5 58B4 SMB_DATA 22B8 27B8 41B3 55C8
MD_DQ15 13C4 20C4 21B5 MII_RXD1 32A1 29C7 58C8 58D1 61B2 59C1
MD_DQ16 13C4 20C4 21C5 MII_RXD2 32A1 29C7 PMBUS_DATA_FET 35C6 SMB_DATA_MU_R 41B2
MD_DQ17 13C4 20C4 21C5 MII_RXD3 32B1 29C7 POST_IN<0..4> 3C4 SMB_DATA_R 59C3
MD_DQ18 13C4 20C4 21C5 MII_RXDV 32C1 29C7 PSU_V12P0_EN 27D1 38A4 42B8 SMC_CPU_CHKSTOP_DETECT 27C8 60A2
MD_DQ19 13C4 20C4 21C5 MII_RXER 32B1 29C7 PSU_V12P0_EN_R 38A2 SMC_CPU_CHKSTOP_DETECT_B 60A4
MD_DQ20 13C4 20C4 21C5 MII_RX_CLK 32B1 29D7 PWRSW_N 38A8 27D1 35A3 SMC_DBG_EN 59C5 27C8
MD_DQ21 13C4 20C4 21D5 MII_RX_CLK_R 29D6 PWRSW_N_R 38A8 35B3 SMC_DBG_TXD 27D1 59C5
MD_DQ22 13C4 20C4 21D5 MII_TXD0 29C1 32A8 RESISTOR0_DN 2B7 SMC_DBG_TXD_R 27D4
MD_DQ23 13D4 20C4 21D5 MII_TXD1 29C1 32A8 RESISTOR0_DP 2B7 SMC_HDMI_HPD 22D3 27B8
MICROSOFT PROJECT NAME PAGE REV
TRINITY_XDK 70/81 1.01
CONFIDENTIAL
SMC_PWM0 27A1 23A8 VREG_CPU2_VCC 45D7 VREG_PCIEX_R 52C2 VREG_V5P0_SW 47B5
SMC_PWM1 27A1 36A6 VREG_CPUCORE_VCS_PWRGD 44D1 51C8 27C1 VREG_V3P3_BST 48C5 VREG_V5P0_SW_S 47C4
SMC_PWM1_R 36A3 VREG_CPUPLL_ADJUST 52B8 VREG_V3P3_CF1 56A6 VREG_V5P0_TRK 47C7
SMC_RST_N 22D3 27D8 42B3 59C1 VREG_CPUPLL_B3 58C2 VREG_V3P3_COMP 48A8 VREG_V12P0_A0 58C6
SMC_RST_N_R 22D4 VREG_CPUPLL_PCIE_AS 58A7 VREG_V3P3_COMP_C 48A7 VREG_V12P0_A1 58C6
SMC_RST_XDK_N 59C3 VREG_CPUPLL_PCIE_CONVST_N 58A7 VREG_V3P3_DH 48C5 VREG_V12P0_ISENSE_N 38B1 58C8
SPDIF_R 29B4 VREG_CPUPLL_R 52A6 VREG_V3P3_DL 48B5 VREG_V12P0_ISENSE_N_R 58C6
SPI_CLK 59C6 28D7 VREG_CPUPLL_SBPCIE_FB 52B5 58A8 58D1 VREG_V3P3_EN 27D1 48C8 VREG_V12P0_ISENSE_P 38B1 58D8
SPI_MISO 28D2 59C8 VREG_CPUPLL_SBPCIE_FB_MID 58D1 52B5 VREG_V3P3_FB 48B1 56D1 VREG_V12P0_ISENSE_P_R 58D6
SPI_MISO_R 28D4 VREG_CPU_ALERT_N 44C2 VREG_V3P3_FB_A3 56D4 VREG_VCS_CF1 57C7
SPI_MOSI 59D6 28D7 VREG_CPU_BST1 45B5 VREG_V3P3_FB_MID 48A1 56C1 VREG_VCS_CF2 57C7
SPI_SS_N 59D8 28D7 VREG_CPU_BST1_R 45A5 VREG_V3P3_FB_MID_R 56C4 VREG_VCS_COMP 51B6
SPKR_DRIVE_N 35A3 VREG_CPU_BST2 45D5 VREG_V3P3_FB_R 56A4 VREG_VCS_COMP_R 51A6
SPKR_DRIVE_P 35A3 VREG_CPU_BST2_R 45D5 VREG_V3P3_ILIM 48B5 VREG_VCS_FB 51A1 57A2 57C8
STBY_CLK 22A1 27D8 VREG_CPU_COMP 44C4 VREG_V3P3_IOUT 56A5 VREG_VCS_FB_MID 51A1 57A2
STBY_CLK_R 22C4 VREG_CPU_COMP_R 44A6 VREG_V3P3_ISENSE_N 48C1 56A7 VREG_VCS_FB_MID_R 57A4
TEMP_RSET 23A5 VREG_CPU_CSCOMP 44C8 61B2 VREG_V3P3_ISENSE_P 48C1 56A7 VREG_VCS_HDRV 51C5
TEMP_RT_A0 58B2 VREG_CPU_CSCOMP_R 44B6 VREG_V3P3_PGND 48B5 VREG_VCS_HDRV_R 51C4
TEMP_RT_D1_P 58B2 VREG_CPU_CSREF 44C8 61B2 VREG_V3P3_PWRGD 48D1 27A8 VREG_VCS_IN 57B7
TEMP_RT_D2_P 58B2 VREG_CPU_CSSUM 44C8 61B2 VREG_V3P3_RAMP 48D5 VREG_VCS_IOUT 57C6
TEMP_RT_D3_P 58B2 VREG_CPU_DRVH1 45A5 VREG_V3P3_RSENSE 48C3 VREG_VCS_IOUT2 57C6
TEMP_RT_D4_P 58B2 VREG_CPU_DRVH2 45C5 VREG_V3P3_SS 48A7 VREG_VCS_ISENSE_N 51C1 57C8
TEMP_RT_D_N 58B2 VREG_CPU_DRVL1 45A5 VREG_V3P3_SW 48C5 VREG_VCS_ISENSE_P 51C1 57C8
TILTSW_N 35D1 27C1 VREG_CPU_DRVL2 45C5 VREG_V3P3_SW_S 48C3 VREG_VCS_LDRV 51B5
TILTSW_N_R 35D2 VREG_CPU_DRV_EN 44C1 45C8 VREG_V3P3_TRK 48C7 VREG_VCS_LDRV_R 51B4
TILTSW_N_R2 35C4 VREG_CPU_EN 27C1 44D8 VREG_V3P3_V5P0_FREQ 47B7 VREG_VCS_NC 51C6
TRAY_OPEN 27C8 41A1 VREG_CPU_FAULT_N 44C2 VREG_V3P3_V5P0_SYNC 47C7 VREG_VCS_NC1 51C6
TRAY_OPEN_R 27C6 VREG_CPU_FB 44A6 44C4 VREG_V3P3_V5P0_VCCO 47D1 48D8 VREG_VCS_OCP 51C6
TRAY_STATUS 41A4 27C8 VREG_CPU_FBRTN 44B3 44C4 VREG_V3P3_V5P0_VDL 47D7 VREG_VCS_RC 51A5
TRAY_STATUS_R 41A3 VREG_CPU_ILIMITFS 44B4 VREG_V5P0_BST 47C5 VREG_VCS_RT_PWRGD 51C6
V5P0_EXPPORT_RJ45 38D5 VREG_CPU_IMON 44C2 VREG_V5P0_CF2 56A6 VREG_VCS_SS_SD_N 51B6
V12P0_EXPPORT_RJ45 38D5 VREG_CPU_IREF 44C4 VREG_V5P0_COMP 47A8 VREG_VCS_VOUT 51B3
VDDA_V3P3_V2P5OP 32C5 VREG_CPU_OD1_N 44C2 VREG_V5P0_COMP_C 47A8 VREG_VCS_VOUT_L 51B3
VDD_V3P3_V2P5IP 32C5 VREG_CPU_PHASE1 45A1 44C8 VREG_V5P0_DH 47C5 VREG_VCS_VP 51C6
VID_DACA_DN 23D4 VREG_CPU_PHASE1_R 44C4 VREG_V5P0_DL 47B5 VREG_VEDRAM_BST 49C5
VID_DACA_DP 23D1 37A8 VREG_CPU_PHASE2 45C1 44C8 VREG_V5P0_EN 27C1 47B8 VREG_VEDRAM_CF1 55A6
VID_DACA_OUT 37A6 37D7 VREG_CPU_PHASE2_R 44C4 VREG_V5P0_EN_R 47B7 VREG_VEDRAM_COMP 49A7
VID_DACB_DN 23D4 VREG_CPU_PWM1 44C1 45A8 VREG_V5P0_FB 47A1 56D8 VREG_VEDRAM_COMP_C 49A7
VID_DACB_DP 23D1 37A8 VREG_CPU_PWM2 44C1 45C8 VREG_V5P0_FB_A1 56D6 VREG_VEDRAM_DH 49C5
VID_DACB_OUT 37A6 37D7 VREG_CPU_RAMPADJ 44D4 VREG_V5P0_FB_MID 47A1 56C8 VREG_VEDRAM_DL 49B5
VID_DACC_DN 23D4 VREG_CPU_RAMPADJ_R 44D5 VREG_V5P0_FB_MID_R 56C6 VREG_VEDRAM_EN 27D1 49B8
VID_DACC_DP 23D1 37A6 VREG_CPU_RT 44C2 VREG_V5P0_FB_R 56A4 VREG_VEDRAM_FB 49B1 55A7 55D1
VID_DACC_OUT 37A3 37D7 VREG_CPU_SW1_R 45A2 VREG_V5P0_ILIM 47B5 VREG_VEDRAM_FB_MID 49A1 55C1
VID_DACD_DN 23D4 VREG_CPU_SW2_R 45C3 VREG_V5P0_IOUT 56B5 VREG_VEDRAM_FB_MID_R 55C3
VID_DACD_DP 23D1 37A6 VREG_CPU_SW3 44C4 VREG_V5P0_ISENSE_N 47C1 56B7 VREG_VEDRAM_FREQ 49B7
VID_DACD_OUT 37A3 37C7 VREG_CPU_SW4 44C4 VREG_V5P0_ISENSE_P 47C1 56B7 VREG_VEDRAM_ILIM 49B5
VID_HSYNC_OUT 37A1 37C7 VREG_CPU_TRDET 44C4 VREG_V5P0_PGND 47B5 VREG_VEDRAM_IOUT 55A5
VID_HSYNC_OUT_R 23C1 37A3 VREG_CPU_TRDET_R 44A6 VREG_V5P0_PWRGD 47D1 27B8 VREG_VEDRAM_ISENSE_N 49C1 55A7
VID_VSYNC_OUT 37A1 37C7 VREG_CPU_VCC 44C1 44D1 VREG_V5P0_RAMP 47C5 VREG_VEDRAM_ISENSE_P 49C1 55A7
VID_VSYNC_OUT_R 23C1 37A3 VREG_CPU_VCC3_3P3 44D3 VREG_V5P0_RSENSE 47C3 VREG_VEDRAM_PGND 49B5
VREG_1P8STBY_EN 53C6 VREG_CPU_VID<6..1> 43C2 44D1 61C2 VREG_V5P0_SEL 27C1 46C7 VREG_VEDRAM_PWRGD 49D1 27D1
VREG_1P8STBY_FB 53C4 VREG_EFUSE_EN 2B1 52A4 VREG_V5P0_SEL_B1 46C6 VREG_VEDRAM_RAMP 49C5
VREG_1P8STBY_SW 53C4 VREG_EFUSE_VOUT 52A2 VREG_V5P0_SEL_B2 46C5 VREG_VEDRAM_RSENSE 49C3
VREG_3P3STBY_EN 53B6 VREG_GPUPCIE_B1 58C4 VREG_V5P0_SEL_C 46C6 VREG_VEDRAM_SS 49A7
VREG_3P3STBY_FB 53B4 VREG_GPUPCIE_FB 52C1 58A8 58D5 VREG_V5P0_SEL_NGATE 46C5 VREG_VEDRAM_SW 49B5
VREG_3P3STBY_SW 53B4 VREG_GPUPCIE_FB_MID 58D5 52C1 VREG_V5P0_SEL_PGATE 46C5 VREG_VEDRAM_SW_S 49C4
VREG_CPU1_VCC 45B7 VREG_PCIEX_ADJUST 52C3 VREG_V5P0_SS 47A7 VREG_VEDRAM_TRK 49C7
MICROSOFT PROJECT NAME PAGE REV
TRINITY_XDK 71/81 1.01
CONFIDENTIAL
VREG_VMEM_BST 50C5 V_CMPAVSS_SATA 31B6
VREG_VMEM_CF2 55A6 V_CPU_CORE_HF_GNDA_PLL 6A4
VREG_VMEM_COMP 50A8 V_CPU_CORE_HF_VDDA_PLL 6B4
VREG_VMEM_COMP_C 50A7 V_CPU_GNDA_RNG 6B4
VREG_VMEM_DH 50C5 V_CPU_PVDDA_ED 6B4
VREG_VMEM_DL 50B5 V_CPU_PVDDA_HS 6C4
VREG_VMEM_EN 27C1 50C8 V_CPU_PVDDA_MEM 6D4
VREG_VMEM_FB 50A1 55A7 55D6 V_CPU_PVDDA_PEX 6C4
VREG_VMEM_FB_MID 50A1 55C6 V_CPU_PVSSA_ED 6B4
VREG_VMEM_FB_MID_R 55C4 V_CPU_PVSSA_HS 6C4
VREG_VMEM_ILIM 50B5 V_CPU_PVSSA_MEM 6C4
VREG_VMEM_IOUT 55A5 V_CPU_PVSSA_PEX 6C4
VREG_VMEM_ISENSE_N 50C1 55A7 V_CPU_VDDA_RNG 6B4
VREG_VMEM_ISENSE_P 50C1 55A7 V_CPU_VDD_VTTA 6A4
VREG_VMEM_PGND 50B5 V_ENET 32D5
VREG_VMEM_PWRGD_CPU_TRST_N_R 27C8 50D1 V_ENET_CT 38C4
VREG_VMEM_PWRGD_R 50D5 V_EXPPORT_DUAL1 39D2
VREG_VMEM_RAMP 50C5 V_EXPPORT_DUAL2 39C2
VREG_VMEM_RSENSE 50C3 V_EXPPORT_DUAL3 39B2
VREG_VMEM_SS 50A7 V_FAN1 36C5
VREG_VMEM_SW 50B5 V_GAMEPORT1 39D6
VREG_VMEM_SW_S 50C4 V_GAMEPORT2 39C6
VREG_VMEM_TRK 50C7 V_GPU_GNDA_PLL 6A4
VREG_VMEM_VEDRAM_SYNC 49C7 V_GPU_VDDA_PLL 6A4
VREG_VMEM_VEDRAM_VCCO 49D1 50D8 V_HANA_VAA_DAC33M 24C5
VREG_VMEM_VEDRAM_VDL 49D7 V_HANA_VAA_RTS33S 24C5
VREG_V_CPUCORE_S 44A8 V_HANA_VAA_XTAL_33S 24B5
V_1P8STBY_R 53C3 V_HANA_VDD18S 25D3
V_3P3STBY_R 53B3 V_HANA_VDDIO_33S_AVCC 25C6
V_3P3_VREF_CPUPLL_PCIE 58B7 V_HANA_VDDIO_33S_PVCC0 25B6
V_3P3_VREF_V5P0_V3P3 56B3 V_HDD 41D2
V_3P3_VREF_VCS 57D5 V_IR 35C6
V_3P3_VREF_VMEM_VEDRAM 55B3 V_MUPORT 41B2
V_12P0_IN 38A2 V_VDD18_USB 30C6
V_AUD 33D4 V_VDD33_USB 30A6
V_AUD_BIAS 33C4 V_VDD_PEX_FB 31D6
V_AUD_FILT_N 33A4 V_VDD_SATA 31B6
V_AUD_FILT_P 33C4 V_VREG_1P8 52C6
V_AUD_FLYN_N 33B4 V_VREG_1P8PLL 52B7
V_AUD_FLYN_P 33B4 V_VREG_1P8_IN 52C8
V_AUD_FLYP_N 33C4 V_VREG_CPU 43B2 44D8 45D8
V_AUD_FLYP_P 33C4 V_VREG_GPUPCIE 52D3
V_AVDD0_SATA 31B6 V_VREG_STBY_VIN 53C6
V_AVDD1_SATA 31C6 V_VREG_V3P3_V5P0 47D1 48D8
V_AVDD_PEX 31D6 V_VREG_VCS 51C5
V_AVDD_USB 30D6 V_VREG_VMEM_VEDRAM 49D1 50D8
V_AVIP 37D3 39A8 40A8 WAVEPORT_DN 28B2 39B8
V_AVSS0_SATA 31B6 WAVEPORT_DP 28B2 39B8
V_AVSS1_SATA 31C6 WSS_CNTL0 26B2 37C8
V_AVSS_PEX 31D6 WSS_CNTL1 26B2 37C8
V_AVSS_USB 30D6 WSS_CNTL_B 37C7
V_BMA 35D6 WSS_CNTL_E 37C7
V_CMPAVDD18_USB 30C6 WSS_CNTL_OUT 37C6
V_CMPAVDD33_USB 30A6 WSS_CNTL_OUT_R 37C7
V_CMPAVDD_SATA 31B6 XUSB_CLK_BYP 26D6
V_CMPAVSS18_USB 30C6 XUSB_CLK_SEL 26D6
V_CMPAVSS33_USB 30A6
MICROSOFT PROJECT NAME PAGE REV
TRINITY_XDK 72/81 1.01
CONFIDENTIAL
Title: Cref Part Report C1U1 CAPN_1206 [48C3] C2N4 CAPN_402 [35D5] C3A9 CAPN_603 [33B3]
Design: trinity C1U2 CAPN_402 [56B6] C2N5 CAPN_402 [35D6] C3A10 CAPN_402 [33A3]
Date: Feb 10 16:21:00 2010 C1U3 CAPN_402 [54D3] C2P1 CAPN_402 [54B4] C3B1 CAPN_402 [23B2]
C2A1 CAPN_402 [40A7] C2P2 CAPN_805 [32C5] C3B2 CAPN_402 [23B2]
C2A2 CAPN_402 [37D6] C2P3 CAPN_805 [32C6] C3B3 CAPN_402 [23B2]
C1A1 CAPN_805 [39B6] C2A3 CAPN_402 [37D8] C2P4 CAPN_402 [32C7] C3B4 CAPN_402 [23C2]
C1A2 CAPN_805 [39B2] C2A5 CAPN_805 [38D5] C2P5 CAPN_402 [32C7] C3B5 CAPN_402 [22D8]
C1A3 CAP_P_RDL [39B3] C2A6 CAPN_402 [38C6] C2R3 CAPN_603 [32A6] C3B6 CAPN_402 [22D8]
C1A6 CAPN_402 [39B2] C2A7 CAPN_402 [38C6] C2R5 CAPN_402 [32B5] C3B7 CAPN_402 [22A2]
C1A7 CAPN_402 [39B6] C2A8 CAPN_805 [37D6] C2R6 CAPN_805 [32C6] C3B8 CAPN_402 [22A1]
C1A8 CAPN_402 [39D2] C2A9 CAP_P_RDL [39C3] C2R7 CAPN_805 [31A2] C3B9 CAPN_402 [22B1]
C1A9 CAPN_402 [39C2] C2A10 CAP_P_RDL [38D6] C2R8 CAPN_402 [23D6] C3B10 CAPN_402 [22A1]
C1A10 CAPN_402 [54D2] C2A11 CAPN_402 [38D6] C2R9 CAPN_402 [31B2] C3B11 CAPN_603 [33D6]
C1B1 CAPN_402 [41A7] C2A12 CAPN_805 [38D5] C2R10 CAPN_805 [31B8] C3B12 CAPN_402 [33D6]
C1B2 CAPN_402 [41A7] C2A13 CAP_P_RDL [38D6] C2R11 CAPN_402 [31B3] C3C1 CAPN_805 [24A7]
C1B3 CAPN_402 [41A7] C2A14 CAPN_402 [38D6] C2R12 CAPN_402 [31B3] C3C2 CAPN_805 [24A7]
C1B4 CAPN_402 [41B7] C2A15 CAPN_402 [54D1] C2R13 CAPN_402 [31B2] C3C3 CAPN_402 [54C1]
C1B7 CAPN_402 [41C7] C2B2 CAP_P_RDL [46C4] C2R14 CAPN_402 [31D1] C3D1 CAPN_603 [59D3]
C1B8 CAPN_402 [41C7] C2B3 CAPN_402 [26B1] C2R15 CAPN_603 [31B7] C3D2 CAPN_402 [26D2]
C1B9 CAP_P_RDL [39D3] C2C2 CAPN_402 [37B1] C2R16 CAPN_402 [31B7] C3E1 CAPN_402 [26D2]
C1B10 CAPN_402 [41D7] C2C3 CAPN_402 [59C7] C2R17 CAPN_603 [31C2] C3E2 CAPN_402 [26C2]
C1B11 CAPN_402 [41D7] C2C4 CAPN_402 [59D3] C2R18 CAPN_402 [31B7] C3E3 CAPN_402 [26D2]
C1B12 CAPN_1206 [46C4] C2C5 CAPN_402 [59D2] C2R19 CAPN_603 [31B7] C3E4 CAPN_402 [58D4]
C1C1 CAP_P_RDL [52C6] C2C6 CAPN_603 [59D2] C2R20 CAPN_402 [31D2] C3E5 CAPN_402 [58B7]
C1C2 CAPN_603 [52C6] C2C7 CAPN_402 [26B1] C2R21 CAPN_402 [54B4] C3E6 CAPN_402 [54C7]
C1C3 CAPN_603 [52C7] C2C8 CAPN_805 [32C8] C2R22 CAPN_402 [54B7] C3E7 CAPN_402 [54C2]
C1D1 CAPN_805 [41C3] C2C9 CAPN_805 [32C8] C2T1 CAPN_805 [31A7] C3F1 CAPN_1206 [49D3]
C1D2 CAPN_402 [41C2] C2C10 CAPN_805 [32C6] C2T2 CAPN_402 [31A6] C3F2 CAPN_402 [49A7]
C1E1 CAPN_603 [47C8] C2D1 CAPN_603 [32C5] C2T3 CAPN_402 [31A6] C3F3 CAPN_402 [49A8]
C1E2 CAPN_603 [47C8] C2D2 CAPN_402 [32C5] C2T4 CAPN_402 [31D1] C3F4 CAPN_402 [49A7]
C1E3 CAPN_402 [48A7] C2D3 CAPN_402 [32C8] C2T5 CAPN_402 [31A7] C3F5 CAPN_603 [49C5]
C1E4 CAPN_402 [48A8] C2D4 CAPN_603 [32A5] C2T6 CAPN_402 [30C2] C3F6 CAPN_402 [55A6]
C1E5 CAPN_402 [48A7] C2D5 CAPN_603 [32C6] C2T7 CAPN_805 [31B8] C3F7 CAPN_1206 [49D3]
C1F1 CAPN_603 [48C5] C2E1 CAPN_402 [29A6] C2T8 CAPN_603 [31A7] C3F8 CAP_P_TH [49D8]
C1F2 CAPN_402 [56A6] C2E2 CAPN_603 [47C8] C2T9 CAPN_603 [31C2] C3G1 CAPN_603 [49C8]
C1F3 CAPN_805 [48C1] C2E3 CAPN_402 [47A8] C2T10 CAPN_402 [30C6] C3G2 CAPN_402 [55B6]
C1F6 CAPN_805 [48C2] C2E4 CAPN_402 [47A8] C2T11 CAPN_402 [30C6] C3G3 CAPN_603 [49C8]
C1F9 CAPN_805 [48C2] C2E5 CAPN_402 [47A7] C2T12 CAPN_805 [31C2] C3G4 CAPN_402 [55A6]
C1F10 CAPN_402 [56B4] C2E6 CAPN_402 [47B7] C2T13 CAPN_402 [28A6] C3G5 CAPN_402 [55D4]
C1F11 CAPN_402 [56B2] C2E7 CAPN_402 [47B7] C2T14 CAPN_402 [30C7] C3G6 CAPN_402 [50A7]
C1G2 CAPN_805 [48C1] C2E8 CAP_P_TH [47D8] C2T15 CAPN_805 [30C7] C3G7 CAPN_402 [50A8]
C1G7 CAPN_402 [58B3] C2F1 CAPN_603 [47C5] C2T16 CAPN_805 [30C8] C3G8 CAPN_402 [50A7]
C1G8 CAPN_402 [58A3] C2F2 CAPN_402 [56B4] C2T18 CAPN_402 [34C4] C3G9 CAPN_603 [50C5]
C1G9 CAPN_402 [58A3] C2F3 CAPN_1206 [47D4] C2T19 CAPN_402 [54B6] C3G10 CAPN_402 [55B3]
C1G10 CAPN_402 [58A3] C2F4 CAPN_402 [56D6] C2U1 CAPN_402 [54B7] C3G11 CAPN_402 [55B4]
C1G11 CAPN_402 [58B3] C2F6 CAPN_402 [56A6] C2V1 CAPN_805 [47B2] C3G12 CAPN_402 [54C5]
C1G12 CAPN_402 [58B4] C2F10 CAPN_1206 [47D3] C2V2 CAPN_402 [54C6] C3G13 CAPN_1206 [35A7]
C1G13 CAPN_805 [58B3] C2G1 CAPN_805 [47B2] C2V4 CAPN_805 [47B2] C3G14 CAPN_1206 [35A6]
C1N1 CAPN_805 [39C2] C2G2 CAPN_805 [47B2] C2V5 CAPN_805 [47B3] C3M1 CAPN_402 [37B6]
C1N3 CAPN_402 [46C5] C2G5 CAP_P_TH [47B1] C3A1 CAPN_402 [37B6] C3M2 CAPN_805 [33A3]
C1N4 CAPN_402 [46C4] C2M1 CAPN_402 [37B2] C3A2 CAPN_402 [37B2] C3M3 CAPN_805 [33A3]
C1N5 CAPN_805 [39D2] C2M2 CAPN_402 [37B2] C3A3 CAPN_402 [33B3] C3M4 CAPN_603 [33C3]
C1P1 CAPN_402 [54D2] C2M3 CAPN_402 [38B4] C3A4 CAPN_402 [33B3] C3M5 CAPN_402 [54D7]
C1R1 CAPN_402 [54B5] C2M4 CAPN_402 [38B3] C3A5 CAPN_402 [33D3] C3M6 CAPN_603 [33C3]
C1T2 CAPN_805 [34C5] C2M5 CAPN_805 [38B4] C3A6 CAPN_603 [33D3] C3N1 CAPN_805 [25C8]
C1T3 CAPN_402 [34C5] C2M6 CAPN_805 [38B5] C3A7 CAPN_402 [33D6] C3N2 CAPN_805 [25B8]
C1T4 CAPN_402 [54D2] C2N3 CAPN_402 [54B5] C3A8 CAPN_402 [33C3] C3N3 CAPN_805 [25C7]
MICROSOFT PROJECT NAME PAGE REV
TRINITY_XDK 73/81 1.01
CONFIDENTIAL
C3N4 CAPN_805 [25B7] C3R10 CAPN_402 [31D3] C4B1 CAPN_402 [57B7] C5A2 CAPN_805 [53B3]
C3N5 CAPN_805 [24A7] C3R11 CAPN_402 [31D3] C4B2 CAPN_402 [22D6] C5A3 CAPN_603 [53B3]
C3N6 CAPN_402 [25C7] C3R12 CAPN_402 [30C2] C4B3 CAPN_402 [23A6] C5A6 CAPN_805 [41B5]
C3N7 CAPN_402 [25C7] C3R13 CAPN_402 [30C1] C4B4 CAPN_805 [51C5] C5A7 CAPN_402 [41B4]
C3N8 CAPN_402 [25C8] C3R14 CAPN_402 [26C8] C4B5 CAPN_603 [51A6] C5A8 CAPN_603 [41B5]
C3N9 CAPN_402 [25B7] C3R15 CAPN_402 [31D7] C4B6 CAPN_402 [51A7] C5A9 CAPN_805 [53C8]
C3N10 CAPN_402 [25C6] C3R16 CAPN_603 [31D7] C4B7 CAPN_402 [51B6] C5A11 CAPN_805 [41B5]
C3N11 CAPN_402 [25C6] C3R17 CAPN_402 [31D1] C4B10 CAPN_805 [41D2] C5A12 CAPN_603 [36C3]
C3N12 CAPN_402 [25C8] C3R18 CAPN_402 [31D2] C4B11 CAPN_805 [51C5] C5A14 CAPN_402 [41B4]
C3N13 CAPN_805 [24C7] C3R19 CAPN_402 [54B1] C4B12 CAPN_805 [51C4] C5A15 CAPN_603 [36C3]
C3N14 CAPN_402 [24A4] C3R20 CAPN_402 [54B4] C4B13 CAPN_402 [51A4] C5B1 CAPN_402 [53C4]
C3N15 CAPN_402 [24A6] C3R21 CAPN_402 [54C2] C4B14 CAPN_1206 [51C5] C5B2 CAPN_805 [53C3]
C3N16 CAPN_402 [24A6] C3T1 CAPN_402 [31C6] C4C1 CAPN_402 [23A2] C5B5 CAPN_402 [57C5]
C3N17 CAPN_402 [24B6] C3T2 CAPN_805 [31D8] C4C2 CAPN_402 [4B6] C5B6 CAPN_603 [53C3]
C3N18 CAPN_402 [25C1] C3T3 CAPN_402 [31C7] C4C3 CAPN_402 [60A6] C5B7 CAPN_805 [53C3]
C3N19 CAPN_402 [25C2] C3T4 CAPN_603 [30A7] C4C4 CAPN_402 [60A5] C5B8 CAPN_402 [57B7]
C3N20 CAPN_402 [24C6] C3T5 CAPN_805 [31C7] C4C5 CAPN_402 [51B6] C5B10 CAPN_603 [45A7]
C3N21 CAPN_402 [24A5] C3T6 CAPN_402 [30C2] C4C6 CAPN_402 [4B6] C5B15 CAPN_402 [57C7]
C3N22 CAPN_805 [24A8] C3T7 CAPN_402 [30A7] C4C7 CAPN_402 [4B6] C5B16 CAPN_805 [53C7]
C3N23 CAPN_805 [24C6] C3T8 CAPN_402 [23D7] C4C8 CAPN_402 [5B7] C5B17 CAPN_402 [41D2]
C3N24 CAPN_402 [24A5] C3T9 CAPN_402 [30A6] C4E1 CAPN_402 [4D6] C5B18 CAPN_805 [53C7]
C3N25 CAPN_402 [24A3] C3T10 CAPN_402 [30C7] C4E2 CAPN_402 [4D6] C5B19 CAPN_805 [51C2]
C3N26 CAPN_402 [24A5] C3T11 CAPN_402 [30D6] C4E3 CAP_P_RDL [49C2] C5B20 CAPN_805 [51C3]
C3N27 CAPN_402 [24C5] C3T12 CAPN_402 [30A7] C4E6 CAP_P_RDL [49C2] C5B21 CAP_P_TH [51C3]
C3N28 CAPN_402 [24A3] C3T13 CAPN_603 [30C7] C4E9 CAPN_805 [52A6] C5C1 CAPN_805 [45A2]
C3N29 CAPN_402 [25C3] C3T14 CAPN_603 [30D7] C4E10 CAPN_603 [52B8] C5C2 CAP_P_RDL [51B1]
C3N30 CAPN_402 [25C3] C3T15 CAPN_603 [30A7] C4E11 CAPN_603 [52C4] C5C3 CAP_P_RDL [43A5]
C3N31 CAPN_402 [25C2] C3T16 CAPN_402 [23D8] C4E12 CAPN_805 [52C2] C5C6 CAPN_805 [51B1]
C3N32 CAPN_402 [24A4] C3T17 CAPN_805 [30D8] C4E13 CAPN_402 [52C3] C5D1 CAPN_805 [9D1]
C3N33 CAPN_402 [25C3] C3T18 CAPN_402 [23D8] C4F7 CAP_P_RDL [49C1] C5D2 CAPN_805 [9B7]
C3N34 CAPN_805 [24A6] C3T19 CAPN_805 [30A8] C4F8 CAPN_402 [52A7] C5D3 CAPN_805 [9C7]
C3N35 CAPN_402 [24A1] C3T20 CAPN_402 [54B6] C4G1 CAPN_402 [54B2] C5D4 CAPN_805 [9C1]
C3N36 CAPN_805 [24C6] C3T21 CAPN_402 [54B6] C4M1 CAPN_402 [54B7] C5D5 CAPN_805 [9C5]
C3N37 CAPN_805 [24C7] C3T23 CAPN_402 [54C6] C4N1 CAPN_402 [57B5] C5D6 CAPN_805 [9C5]
C3N38 CAPN_402 [24C6] C3T24 CAPN_402 [54C3] C4N2 CAPN_402 [54B2] C5D7 CAPN_805 [9C5]
C3N39 CAPN_402 [25C2] C3U1 CAPN_402 [54B7] C4N3 CAPN_402 [54B5] C5D8 CAPN_805 [9C7]
C3N40 CAPN_402 [54D7] C3U2 CAPN_402 [58B6] C4N4 CAPN_402 [57D4] C5D9 CAPN_805 [9B5]
C3N41 CAPN_603 [33C3] C3U3 CAPN_402 [58B7] C4N5 CAPN_402 [54B5] C5D10 CAPN_805 [9B5]
C3P1 CAPN_402 [25D3] C3U4 CAPN_402 [54C6] C4N6 CAPN_402 [54C7] C5D11 CAPN_805 [9B5]
C3P2 CAPN_402 [24A4] C3V1 CAPN_603 [49C8] C4N7 CAPN_603 [51C6] C5D12 CAPN_805 [9B8]
C3P3 CAPN_805 [25D2] C3V2 CAPN_402 [55B4] C4N8 CAPN_402 [54B4] C5D13 CAPN_805 [9D7]
C3P4 CAPN_805 [25D1] C3V3 CAPN_402 [54C5] C4N9 CAPN_603 [51C6] C5D14 CAPN_805 [9C7]
C3P5 CAPN_402 [24A5] C3V4 CAPN_402 [35A6] C4N10 CAPN_805 [51C4] C5E1 CAPN_402 [4C3]
C3P6 CAPN_402 [24A3] C3V5 CAPN_402 [35A6] C4P1 CAPN_402 [36C6] C5E2 CAPN_402 [4D3]
C3P7 CAPN_402 [24A2] C3V6 CAPN_402 [35A5] C4P2 CAPN_402 [23A6] C5E3 CAPN_402 [4C3]
C3P8 CAPN_402 [24A2] C4A1 CAPN_402 [39A7] C4P3 CAPN_402 [54C7] C5E4 CAPN_402 [4C3]
C3P9 CAPN_402 [24A2] C4A3 CAPN_402 [37A7] C4R1 CAPN_603 [52A2] C5E5 CAPN_805 [9C3]
C3P10 CAPN_402 [54B3] C4A4 CAPN_402 [37A4] C4R2 CAPN_603 [52A4] C5E6 CAPN_805 [9D3]
C3R1 CAPN_402 [30A2] C4A5 CAPN_402 [37A4] C4R3 CAPN_402 [52A2] C5E7 CAPN_805 [9C3]
C3R2 CAPN_603 [27D6] C4A6 CAPN_402 [37A7] C4R4 CAPN_402 [5C1] C5E8 CAPN_805 [9B3]
C3R3 CAPN_603 [31A2] C4A7 CAPN_402 [37A4] C4T1 CAPN_603 [2D5] C5E9 CAPN_805 [9B3]
C3R4 CAPN_402 [30A2] C4A8 CAPN_402 [37A4] C4T3 CAPN_805 [9A3] C5E10 CAPN_1206 [49B1]
C3R5 CAPN_805 [30A8] C4A9 CAPN_402 [37A7] C4T4 CAPN_805 [9A3] C5E11 CAPN_1206 [49B2]
C3R6 CAPN_402 [31B2] C4A10 CAPN_402 [37A7] C4T7 CAPN_1206 [49B1] C5F1 CAPN_402 [19A7]
C3R7 CAPN_402 [31D3] C4A11 CAPN_402 [41A2] C4U4 CAP_P_SM [50B2] C5F2 CAPN_402 [20A2]
C3R8 CAPN_402 [31D2] C4A12 CAPN_402 [59D4] C4V1 CAPN_402 [54B2] C5F3 CAPN_402 [20A2]
C3R9 CAPN_402 [26C7] C4A14 CAPN_805 [41B4] C5A1 CAPN_402 [53B4] C5F4 CAPN_402 [20A3]
MICROSOFT PROJECT NAME PAGE REV
TRINITY_XDK 74/81 1.01
CONFIDENTIAL
C5F5 CAPN_402 [20A1] C5R35 CAPN_402 [9D2] C5T28 CAPN_402 [11C4] C6F2 CAPN_402 [18A2]
C5F6 CAPN_402 [20A1] C5R36 CAPN_402 [10A5] C5T29 CAPN_402 [11B5] C6F3 CAPN_402 [21A7]
C5F7 CAPN_402 [20A3] C5R37 CAPN_402 [10C4] C5T30 CAPN_402 [11B5] C6F4 CAPN_402 [18A3]
C5F8 CAPN_402 [20A1] C5R38 CAPN_402 [10B6] C5T31 CAPN_402 [9C4] C6F5 CAPN_402 [18A2]
C5F9 CAPN_402 [20A3] C5R39 CAPN_402 [10C6] C5T32 CAPN_402 [9C4] C6F6 CAPN_402 [21A5]
C5F10 CAPN_805 [18A4] C5R40 CAPN_402 [10C6] C5T33 CAPN_805 [9A5] C6F7 CAPN_402 [18A1]
C5G1 CAP_P_RDL [38B6] C5R41 CAPN_402 [11B4] C5T34 CAPN_805 [9B3] C6F8 CAPN_402 [18A3]
C5G2 CAPN_402 [38B5] C5R42 CAPN_805 [6B6] C5T35 CAPN_805 [9C3] C6F9 CAPN_402 [18A1]
C5G3 CAPN_402 [38A5] C5R43 CAPN_402 [9C2] C5T36 CAPN_402 [4A5] C6F10 CAPN_402 [18A3]
C5G4 CAPN_402 [38A6] C5R44 CAPN_402 [11B5] C5T37 CAPN_402 [13A6] C6F11 CAPN_805 [20A4]
C5G5 CAPN_402 [38A6] C5R45 CAPN_402 [10A4] C5T38 CAPN_402 [13A1] C6G1 CAP_P_RDL [39D7]
C5G6 CAPN_805 [35B6] C5R46 CAPN_402 [10B4] C5T39 CAPN_402 [13A2] C6G2 CAPN_402 [39D7]
C5G7 CAPN_402 [35B6] C5R47 CAPN_402 [11B5] C5T41 CAPN_402 [13A5] C6G3 CAPN_805 [39D7]
C5G8 CAPN_402 [54C4] C5R48 CAPN_402 [11B5] C5T42 CAPN_402 [13A2] C6M5 CAPN_402 [58D6]
C5M5 CAPN_603 [53A6] C5R49 CAPN_402 [10C4] C5T43 CAPN_805 [9B3] C6N1 CAPN_805 [45D5]
C5N5 CAPN_805 [45B5] C5R50 CAPN_402 [9B2] C5T44 CAPN_402 [13A1] C6N2 CAPN_603 [45D5]
C5N6 CAPN_603 [45A5] C5R51 CAPN_402 [10B3] C5T45 CAPN_402 [13A2] C6N3 CAPN_1206 [45B3]
C5N7 CAPN_402 [57D5] C5R52 CAPN_402 [11C4] C5T46 CAPN_402 [13A5] C6N4 CAPN_402 [54D7]
C5N8 CAPN_402 [57D7] C5R53 CAPN_402 [11C5] C5T47 CAPN_402 [13A5] C6R1 CAPN_805 [9B6]
C5N9 CAPN_603 [53C6] C5R54 CAPN_805 [6B6] C5T48 CAPN_402 [13A2] C6R2 CAPN_805 [9B8]
C5N10 CAPN_805 [51C4] C5R55 CAPN_402 [10B3] C5T49 CAPN_402 [13A5] C6R3 CAPN_805 [9C8]
C5N11 CAPN_805 [51C4] C5R56 CAPN_402 [11A5] C5T50 CAPN_402 [13A6] C6R4 CAPN_805 [9D8]
C5P1 CAPN_805 [51B2] C5R57 CAPN_402 [10B4] C5T52 CAPN_1206 [49B2] C6R5 CAPN_805 [9A8]
C5R1 CAPN_805 [9C1] C5R58 CAPN_402 [9C2] C5U1 CAPN_402 [18A5] C6R6 CAPN_805 [9C6]
C5R2 CAPN_805 [9A6] C5R59 CAPN_402 [10C3] C5U2 CAPN_805 [13A6] C6R7 CAPN_805 [9B6]
C5R3 CAPN_805 [9B6] C5R60 CAPN_402 [10C5] C5U3 CAPN_402 [21A2] C6R8 CAPN_402 [11D5]
C5R4 CAPN_805 [9C1] C5R61 CAPN_402 [10C5] C5U4 CAPN_402 [21A3] C6R9 CAPN_402 [11B6]
C5R5 CAPN_805 [9B7] C5R62 CAPN_402 [10B3] C5U5 CAPN_402 [21A3] C6R10 CAPN_402 [11B6]
C5R6 CAPN_805 [9B7] C5R63 CAPN_402 [10C3] C5U6 CAPN_402 [21A2] C6R11 CAPN_402 [12A2]
C5R7 CAPN_805 [9C6] C5R64 CAPN_402 [10B4] C5U7 CAPN_402 [21A2] C6R12 CAPN_402 [11B3]
C5R8 CAPN_805 [9D6] C5T1 CAPN_402 [9B2] C5U8 CAPN_402 [21A3] C6R13 CAPN_402 [11C3]
C5R9 CAPN_805 [9D5] C5T2 CAPN_402 [11B3] C5U9 CAPN_402 [18A7] C6R14 CAPN_402 [11B3]
C5R10 CAPN_805 [9C8] C5T3 CAPN_402 [11C3] C5U10 CAPN_402 [21A1] C6R15 CAPN_402 [10B4]
C5R11 CAPN_603 [2D5] C5T4 CAPN_805 [6A5] C5U11 CAPN_402 [21A1] C6R16 CAPN_402 [12A2]
C5R12 CAPN_805 [9B8] C5T5 CAPN_402 [11B3] C5U12 CAPN_402 [21A6] C6R17 CAPN_402 [10A3]
C5R13 CAPN_805 [9A7] C5T6 CAPN_402 [6A4] C6A1 CAPN_402 [38A3] C6R18 CAPN_402 [10A3]
C5R14 CAPN_805 [6D5] C5T7 CAPN_402 [9C2] C6A2 CAPN_402 [38A2] C6R19 CAPN_402 [11C5]
C5R15 CAPN_805 [9C8] C5T8 CAPN_402 [10C4] C6A3 CAPN_402 [38A2] C6R20 CAPN_402 [10A4]
C5R16 CAPN_805 [9B7] C5T9 CAPN_805 [6C5] C6A4 CAP_P_RDL [38A3] C6R21 CAPN_402 [10B4]
C5R17 CAPN_805 [6C5] C5T10 CAPN_402 [10D4] C6A5 CAP_P_RDL [38A3] C6R22 CAPN_402 [11C5]
C5R18 CAPN_805 [9B5] C5T11 CAPN_402 [10A5] C6A6 CAPN_603 [58C6] C6R23 CAPN_402 [12A1]
C5R19 CAPN_402 [11A6] C5T12 CAPN_402 [10D6] C6A7 CAP_P_RDL [36C3] C6R24 CAPN_402 [11B4]
C5R20 CAPN_402 [11B6] C5T13 CAPN_805 [6B5] C6B1 CAP_P_TH [43B5] C6R25 CAPN_402 [10C5]
C5R21 CAPN_402 [11C3] C5T14 CAPN_402 [11D3] C6B2 CAPN_1206 [45A3] C6R26 CAPN_402 [11A5]
C5R22 CAPN_402 [11A6] C5T15 CAPN_402 [11C4] C6B3 CAPN_1206 [43B4] C6R27 CAPN_402 [12A3]
C5R23 CAPN_402 [11A6] C5T16 CAPN_402 [11C3] C6B4 CAPN_603 [45D7] C6R28 CAPN_402 [10B5]
C5R24 CAPN_402 [11B5] C5T17 CAPN_402 [10D4] C6B5 CAPN_1206 [43B4] C6R29 CAPN_402 [11A5]
C5R25 CAPN_402 [11D6] C5T18 CAPN_402 [11A4] C6C1 CAP_P_RDL [43A6] C6R30 CAPN_402 [11A4]
C5R26 CAPN_402 [10D5] C5T19 CAPN_402 [11C6] C6C2 CAP_P_RDL [43A5] C6R31 CAPN_402 [10B6]
C5R27 CAPN_402 [10C3] C5T20 CAPN_402 [9B4] C6C3 CAP_P_RDL [43A6] C6R32 CAPN_402 [11A5]
C5R28 CAPN_402 [10C3] C5T21 CAPN_402 [9A4] C6D1 CAPN_805 [9A8] C6R33 CAPN_402 [10C4]
C5R29 CAPN_402 [11A5] C5T22 CAPN_402 [9B4] C6D2 CAPN_805 [9A7] C6R34 CAPN_402 [11C5]
C5R30 CAPN_402 [11D4] C5T23 CAPN_402 [9B4] C6D3 CAPN_805 [9C6] C6R35 CAPN_402 [11C5]
C5R31 CAPN_805 [6A6] C5T24 CAPN_402 [9C4] C6D4 CAPN_805 [9C6] C6R36 CAPN_402 [10D3]
C5R32 CAPN_402 [10B5] C5T25 CAPN_402 [9A4] C6D5 CAPN_805 [9B8] C6R37 CAPN_402 [10C4]
C5R33 CAPN_402 [10C6] C5T26 CAPN_402 [9D4] C6D6 CAPN_805 [9A6] C6R38 CAPN_402 [10A6]
C5R34 CAPN_402 [11B3] C5T27 CAPN_402 [9B4] C6F1 CAPN_402 [18A2] C6R39 CAPN_402 [11D5]
MICROSOFT PROJECT NAME PAGE REV
TRINITY_XDK 75/81 1.01
CONFIDENTIAL
C6R40 CAPN_402 [11A3] C7B7 CAPN_402 [44A6] C7T3 CAPN_402 [15A1] DB4D1 DBPAD_TP [52A1]
C6R41 CAPN_402 [11A3] C7B8 CAP_P_TH [49D8] C7T4 CAPN_402 [15A2] DB4E1 DBPAD_TP [52C1]
C6R42 CAPN_402 [10C4] C7C1 CAPN_402 [44B5] C7T5 CAPN_402 [15A3] DB4E2 DBPAD_TP [52B5]
C6R43 CAPN_402 [10A6] C7C2 CAPN_402 [44A7] C7T6 CAPN_402 [15A1] DB4E3 DBPAD_TP [49C1]
C6R44 CAPN_402 [10A4] C7C3 CAPN_402 [44B5] C7T7 CAPN_402 [14A7] DB4E4 DBPAD_TP [49B3]
C6R45 CAPN_402 [10C4] C7C4 CAPN_402 [44A5] C7T8 CAPN_402 [15A2] DB4E5 DBPAD_TP [49B3]
C6R46 CAPN_402 [12A1] C7C5 CAPN_402 [44A7] C7T9 CAPN_402 [15A3] DB4N2 DBPAD_TP [51C6]
C6T2 CAPN_402 [11B4] C7C6 CAPN_402 [44A2] C7T10 CAPN_402 [21A5] DB4N3 DBPAD_TP [51B6]
C6T3 CAPN_402 [11C5] C7C7 CAPN_402 [44B2] C7T11 CAPN_402 [15A2] DB4N4 DBPAD_TP [23A2]
C6T4 CAPN_402 [11A5] C7C8 CAPN_805 [45C3] C7T12 CAPN_402 [15A3] DB4N5 DBPAD_TP [23A2]
C6T5 CAPN_402 [11D3] C7C9 CAPN_402 [44D3] C7U1 CAPN_1206 [50D3] DB4N6 DBPAD_TP [23A2]
C6T6 CAPN_402 [10B5] C7C10 CAPN_1206 [44D5] C7V1 CAPN_805 [39C7] DB4N7 DBPAD_TP [23A2]
C6T7 CAPN_402 [10C6] C7C11 CAPN_603 [44D4] D4A1 DIODE_SOT23 [36C5] DB4P6 DBPAD_TP [51C6]
C6T8 CAPN_402 [10B4] C7C12 CAP_P_RDL [43A4] D4D1 LED_SM [60B5] DB4P7 DBPAD_TP [51C6]
C6T9 CAPN_402 [11C3] C7C13 CAP_P_RDL [43A4] D5B1 DIODE_SOT23 [45B6] DB4P8 DBPAD_TP [51C8]
C6T10 CAPN_402 [12A6] C7D7 CAPN_402 [16A1] D6B1 DIODE_SOT23 [45D6] DB4R1 DBPAD_TP [5C4]
C6T11 CAPN_402 [10C4] C7D8 CAPN_402 [16A1] DB1E1 DBPAD_TP [42C1] DB5A1 DBPAD_TP [53A3]
C6T12 CAPN_402 [10B6] C7D9 CAPN_402 [16A3] DB1F1 DBPAD_TP [58A2] DB5B1 DBPAD_TP [53B1]
C6T13 CAPN_402 [11A3] C7D10 CAPN_402 [16A2] DB1F2 DBPAD_TP [48B1] DB5B2 DBPAD_TP [51A3]
C6T14 CAPN_402 [10A4] C7D11 CAPN_805 [16A4] DB1V1 DBPAD_TP [58B1] DB5B3 DBPAD_TP [51A3]
C6T15 CAPN_402 [11C6] C7D12 CAPN_402 [17A7] DB1V2 DBPAD_TP [58B1] DB5B4 DBPAD_TP [53C1]
C6T16 CAPN_402 [11A4] C7D13 CAPN_402 [16A3] DB1V3 DBPAD_TP [58B1] DB5B5 DBPAD_TP [53C3]
C6T17 CAPN_402 [11A3] C7D14 CAPN_402 [16A2] DB2E1 DBPAD_TP [52C5] DB5C1 DBPAD_TP [51B1]
C6T18 CAPN_402 [11C6] C7D15 CAPN_402 [21A4] DB2G1 DBPAD_TP [48C1] DB5R5 DBPAD_TP [6B5]
C6T19 CAPN_402 [11C3] C7E1 CAPN_402 [21A4] DB2G2 DBPAD_TP [47C1] DB6M1 DBPAD_TP [38A4]
C6T20 CAPN_402 [10C5] C7E2 CAPN_402 [16A2] DB2G3 DBPAD_TP [27A8] DB6M2 DBPAD_TP [38B4]
C6T22 CAPN_805 [9A5] C7E3 CAPN_402 [16A3] DB2G4 DBPAD_TP [47B1] DB6M3 DBPAD_TP [38B4]
C6T23 CAPN_805 [9A5] C7E4 CAPN_402 [14A1] DB2N1 DBPAD_TP [35C4] DB6N1 DBPAD_TP [38A4]
C6T24 CAPN_402 [11A3] C7E5 CAPN_402 [14A2] DB2N2 DBPAD_TP [35C4] DB6R1 DBPAD_TP [43B3]
C6T25 CAPN_402 [11B3] C7E6 CAPN_402 [14A3] DB2N3 DBPAD_TP [35C4] DB6R2 DBPAD_TP [43B3]
C6T26 CAPN_402 [13A2] C7E7 CAPN_402 [14A1] DB2R1 DBPAD_TP [32B5] DB7C1 DBPAD_TP [44C2]
C6T27 CAPN_402 [12A6] C7E8 CAPN_805 [14A4] DB2R2 DBPAD_TP [26B3] DB7C2 DBPAD_TP [44C4]
C6T28 CAPN_402 [13A5] C7E9 CAPN_402 [15A7] DB2R3 DBPAD_TP [26B3] DB7C3 DBPAD_TP [44C4]
C6T29 CAPN_402 [12A5] C7E10 CAPN_402 [14A2] DB2R4 DBPAD_TP [26B3] DB7C4 DBPAD_TP [45C1]
C6T30 CAPN_805 [12A2] C7E11 CAPN_402 [14A3] DB2R5 DBPAD_TP [26B3] DB7C5 DBPAD_TP [44A8]
C6T31 CAPN_402 [13A1] C7E12 CAPN_402 [21A5] DB2R6 DBPAD_TP [26B3] DB7C6 DBPAD_TP [44A8]
C6T32 CAPN_402 [12A5] C7E13 CAPN_402 [14A2] DB2R7 DBPAD_TP [26B3] DB7F1 DBPAD_TP [50C2]
C6T33 CAPN_402 [13A5] C7E14 CAPN_402 [14A3] DB2R8 DBPAD_TP [26D6] DB7F2 DBPAD_TP [50B2]
C6U1 CAPN_402 [19A2] C7F1 CAPN_805 [50C2] DB2R9 DBPAD_TP [26B3] DB7P1 DBPAD_TP [44C2]
C6U2 CAPN_402 [19A2] C7F2 CAP_P_RDL [50C2] DB2R10 DBPAD_TP [26B3] DB7P2 DBPAD_TP [44C2]
C6U3 CAPN_402 [19A3] C7F3 CAPN_1206 [50D3] DB2R11 DBPAD_TP [26C3] EG1A1 ESDGUARD_402 [39A7]
C6U4 CAPN_402 [19A2] C7G1 CAP_P_RDL [39C7] DB2R12 DBPAD_TP [26C3] EG1A2 ESDGUARD_402 [39A7]
C6U5 CAPN_402 [19A1] C7G2 CAPN_402 [39C7] DB2R13 DBPAD_TP [26C3] EG1A3 ESDGUARD_402 [39B2]
C6U6 CAPN_402 [19A3] C7N1 CAPN_1206 [45D3] DB2R14 DBPAD_TP [26C3] EG1A4 ESDGUARD_402 [39B3]
C6U7 CAPN_402 [20A7] C7P1 CAPN_402 [44A5] DB2R15 DBPAD_TP [26A3] EG1A5 ESDGUARD_402 [39A2]
C6U8 CAPN_402 [19A1] C7P2 CAPN_603 [44D6] DB2R16 DBPAD_TP [26A3] EG1A6 ESDGUARD_402 [39A3]
C6U9 CAPN_402 [19A3] C7R1 CAP_P_SM [50B2] DB3E1 DBPAD_TP [52B5] EG1A7 ESDGUARD_402 [39C2]
C6U10 CAPN_402 [21A6] C7R2 CAPN_402 [17A1] DB3M1 DBPAD_TP [40B3] EG1A8 ESDGUARD_402 [39C3]
C7A1 CAPN_603 [38A3] C7R3 CAPN_402 [17A1] DB3P1 DBPAD_TP [23A6] EG1B1 ESDGUARD_402 [41C7]
C7A2 CAPN_603 [38A3] C7R4 CAPN_402 [17A3] DB3R1 DBPAD_TP [26B3] EG1B2 ESDGUARD_402 [41C6]
C7A3 CAPN_603 [38A3] C7R5 CAPN_402 [17A2] DB3R2 DBPAD_TP [26D6] EG1B3 ESDGUARD_402 [41D7]
C7A4 CAPN_603 [38A2] C7R6 CAPN_402 [16A7] DB3R3 DBPAD_TP [26C3] EG1B4 ESDGUARD_402 [41D6]
C7B1 CAPN_1206 [43B6] C7R7 CAPN_402 [17A3] DB3R4 DBPAD_TP [26C3] EG2A1 ESDGUARD_402 [37D7]
C7B2 CAP_P_TH [38A3] C7R8 CAPN_402 [17A2] DB3R5 DBPAD_TP [26C3] EG2A2 ESDGUARD_402 [38C4]
C7B3 CAP_P_TH [43B5] C7R9 CAPN_402 [21A4] DB3R6 DBPAD_TP [27A6] EG2A3 ESDGUARD_402 [38C5]
C7B4 CAPN_402 [54D6] C7T1 CAPN_402 [17A2] DB3R7 DBPAD_TP [27A6] EG2A4 ESDGUARD_402 [38C6]
C7B5 CAPN_1206 [45D3] C7T2 CAPN_402 [17A3] DB3T1 DBPAD_TP [26D6] EG2A5 ESDGUARD_402 [38C6]
MICROSOFT PROJECT NAME PAGE REV
TRINITY_XDK 76/81 1.01
CONFIDENTIAL
EG2A6 ESDGUARD_402 [38C6] FT1N2 FTPAD_TP [41B7] FT3P3 FTPAD_TP [22B1] FT4R4 FTPAD_TP [3B4]
EG2A7 ESDGUARD_402 [38B6] FT1N3 FTPAD_TP [41A7] FT3P4 FTPAD_TP [22B1] FT4R5 FTPAD_TP [52A4]
EG3A1 ESDGUARD_402 [40D6] FT1N4 FTPAD_TP [41D5] FT3P5 FTPAD_TP [22B8] FT4R6 FTPAD_TP [3B4]
EG3A2 ESDGUARD_402 [40D7] FT1N5 FTPAD_TP [41D5] FT3P6 FTPAD_TP [22B8] FT4R7 FTPAD_TP [3B4]
EG3A3 ESDGUARD_402 [40C6] FT1N6 FTPAD_TP [41C5] FT3P7 FTPAD_TP [22B8] FT4R8 FTPAD_TP [3B4]
EG3A4 ESDGUARD_402 [40C7] FT1N7 FTPAD_TP [41C5] FT3P8 FTPAD_TP [22B8] FT4R9 FTPAD_TP [3B4]
EG3A5 ESDGUARD_402 [40C6] FT1N8 FTPAD_TP [41C5] FT3P9 FTPAD_TP [22B8] FT4R10 FTPAD_TP [27B6]
EG4A1 ESDGUARD_402 [39A7] FT1N9 FTPAD_TP [46C2] FT3R1 FTPAD_TP [22D3] FT4T1 FTPAD_TP [52D1]
EG4A2 ESDGUARD_402 [40C7] FT1P1 FTPAD_TP [46B7] FT3R3 FTPAD_TP [22D3] FT4T2 FTPAD_TP [2B8]
EG4A3 ESDGUARD_402 [40B6] FT1T1 FTPAD_TP [34C8] FT3R4 FTPAD_TP [27C8] FT4T3 FTPAD_TP [52B5]
EG4A4 ESDGUARD_402 [40B7] FT1T2 FTPAD_TP [34C8] FT3R5 FTPAD_TP [27B8] FT5M1 FTPAD_TP [53B3]
EG4A5 ESDGUARD_402 [37A5] FT1T3 FTPAD_TP [34C8] FT3R6 FTPAD_TP [27B8] FT5M2 FTPAD_TP [53B6]
EG4A6 ESDGUARD_402 [37A5] FT1T4 FTPAD_TP [34C8] FT3R9 FTPAD_TP [27A6] FT5M3 FTPAD_TP [53C7]
EG4A7 ESDGUARD_402 [37A8] FT1T5 FTPAD_TP [34C8] FT3R10 FTPAD_TP [22C1] FT5N1 FTPAD_TP [53C6]
EG4A8 ESDGUARD_402 [37A8] FT1T6 FTPAD_TP [34C8] FT3R11 FTPAD_TP [22C1] FT5N2 FTPAD_TP [53C3]
EG4A9 ESDGUARD_402 [37A2] FT1T7 FTPAD_TP [34C8] FT3R12 FTPAD_TP [27B1] FT5P1 FTPAD_TP [3C6]
EG4A10 ESDGUARD_402 [37A2] FT1T8 FTPAD_TP [34C8] FT3R13 FTPAD_TP [22C8] FT5P2 FTPAD_TP [3C6]
EG4M1 ESDGUARD_402 [40A6] FT1T9 FTPAD_TP [48A1] FT3R14 FTPAD_TP [22D7] FT5R1 FTPAD_TP [3A4]
EG4M2 ESDGUARD_402 [40A7] FT1T10 FTPAD_TP [48C8] FT3R15 FTPAD_TP [27D8] FT5R2 FTPAD_TP [3A4]
EG4M5 ESDGUARD_402 [40A2] FT1T11 FTPAD_TP [34C4] FT3R16 FTPAD_TP [4D2] FT5R3 FTPAD_TP [3A4]
EG6G1 ESDGUARD_402 [39C7] FT2M1 FTPAD_TP [38D7] FT3R17 FTPAD_TP [4C7] FT5R4 FTPAD_TP [3A4]
EG6G2 ESDGUARD_402 [39C7] FT2M2 FTPAD_TP [38D7] FT3T1 FTPAD_TP [52B5] FT5R5 FTPAD_TP [3A4]
EG7G1 ESDGUARD_402 [39C7] FT2P2 FTPAD_TP [22B1] FT3T2 FTPAD_TP [44D1] FT5R6 FTPAD_TP [3A4]
EG7G2 ESDGUARD_402 [39C7] FT2R1 FTPAD_TP [22A1] FT3T3 FTPAD_TP [44D8] FT5R7 FTPAD_TP [3A4]
FB1A1 FERRITE_603 [39B7] FT2R2 FTPAD_TP [26A3] FT3T4 FTPAD_TP [26B5] FT5R8 FTPAD_TP [3A4]
FB2C1 FERRITE_603 [32D8] FT2R3 FTPAD_TP [22B1] FT3T5 FTPAD_TP [26B5] FT5R9 FTPAD_TP [3A4]
FB2M1 FERRITE_603 [38C4] FT2R4 FTPAD_TP [22C1] FT3T6 FTPAD_TP [26B5] FT5R10 FTPAD_TP [3A4]
FB2R1 FERRITE_603 [32C5] FT2R5 FTPAD_TP [22A1] FT3T7 FTPAD_TP [26B5] FT5R11 FTPAD_TP [3A4]
FB2R2 FERRITE_603 [31B7] FT2R6 FTPAD_TP [35A7] FT3T8 FTPAD_TP [26A5] FT5R12 FTPAD_TP [3A4]
FB2R3 FERRITE_603 [31C7] FT2R7 FTPAD_TP [35A3] FT3U1 FTPAD_TP [49A1] FT5R13 FTPAD_TP [3A4]
FB2T1 FERRITE_603 [31A7] FT2T1 FTPAD_TP [52C5] FT3V1 FTPAD_TP [49B8] FT5R14 FTPAD_TP [3A4]
FB2T2 FERRITE_603 [31B7] FT2T2 FTPAD_TP [47C8] FT3V2 FTPAD_TP [50A1] FT5R15 FTPAD_TP [3A4]
FB2T3 FERRITE_603 [30C7] FT2T3 FTPAD_TP [47A1] FT3V3 FTPAD_TP [50C8] FT5R16 FTPAD_TP [3A4]
FB3A1 FERRITE_603 [33B2] FT2T4 FTPAD_TP [35A7] FT3V4 FTPAD_TP [49D2] FT5R17 FTPAD_TP [51C1]
FB3A2 FERRITE_603 [33C2] FT2T5 FTPAD_TP [35A7] FT3V5 FTPAD_TP [50D2] FT5R18 FTPAD_TP [2D6]
FB3N1 FERRITE_603 [25C8] FT2U2 FTPAD_TP [41B3] FT3V6 FTPAD_TP [35A2] FT5T2 FTPAD_TP [3D6]
FB3N2 FERRITE_603 [25B8] FT2U3 FTPAD_TP [41B3] FT3V7 FTPAD_TP [35A2] FT5T4 FTPAD_TP [49C1]
FB3N3 FERRITE_603 [24C6] FT2V1 FTPAD_TP [27A8] FT4M1 FTPAD_TP [40A7] FT6M1 FTPAD_TP [38A4]
FB3N4 FERRITE_603 [24C6] FT2V2 FTPAD_TP [47C1] FT4M2 FTPAD_TP [40C7] FT6R1 FTPAD_TP [43A3]
FB3P1 FERRITE_603 [25D2] FT2V3 FTPAD_TP [48C1] FT4M3 FTPAD_TP [40B7] FT6R2 FTPAD_TP [43A3]
FB3R1 FERRITE_603 [30A7] FT2V4 FTPAD_TP [35A3] FT4M4 FTPAD_TP [40B7] FT6U1 FTPAD_TP [50C2]
FB3R2 FERRITE_603 [31D7] FT3M1 FTPAD_TP [40D7] FT4M5 FTPAD_TP [40A7] FT7N1 FTPAD_TP [38A4]
FB3T1 FERRITE_603 [30C8] FT3M2 FTPAD_TP [40D7] FT4M6 FTPAD_TP [40B2] FT7P1 FTPAD_TP [44C5]
FB3T2 FERRITE_603 [30D7] FT3M3 FTPAD_TP [40D7] FT4M7 FTPAD_TP [40C7] FT7P2 FTPAD_TP [44B5]
FB3T3 FERRITE_603 [30A7] FT3M4 FTPAD_TP [40C7] FT4M8 FTPAD_TP [40B7] FT7P3 FTPAD_TP [2C2]
FB5R1 FERRITE_603 [6D6] FT3M5 FTPAD_TP [40C7] FT4M9 FTPAD_TP [40B7] FT7P4 FTPAD_TP [2C2]
FB5R2 FERRITE_603 [6C6] FT3M6 FTPAD_TP [33B7] FT4N1 FTPAD_TP [23A6] FT7P5 FTPAD_TP [2C2]
FB5R3 FERRITE_603 [6A6] FT3M7 FTPAD_TP [40D7] FT4N2 FTPAD_TP [23A6] FT7P6 FTPAD_TP [2C2]
FB5R4 FERRITE_603 [6B6] FT3M8 FTPAD_TP [40D7] FT4P1 FTPAD_TP [5B7] FT7P7 FTPAD_TP [2C2]
FB5R5 FERRITE_603 [6B6] FT3M9 FTPAD_TP [40D7] FT4P2 FTPAD_TP [5B7] FT7P8 FTPAD_TP [2C2]
FB5T1 FERRITE_603 [6A6] FT3M10 FTPAD_TP [40C7] FT4P4 FTPAD_TP [5C7] J1A1 WAVERECEPTACLE_TH [39B5]
FB5T2 FERRITE_603 [6C6] FT3M11 FTPAD_TP [40C7] FT4P5 FTPAD_TP [5C7] J1A2 USBTRIPLE_TH [39C1]
FB5T3 FERRITE_603 [6B6] FT3N1 FTPAD_TP [22B4] FT4P6 FTPAD_TP [5C7] J1B1 1X7SATA_TH [41A6]
FT1M3 FTPAD_TP [41A7] FT3N2 FTPAD_TP [22A1] FT4P7 FTPAD_TP [5C7] J1B2 1X7SATA_TH [41C5]
FT1M4 FTPAD_TP [41A7] FT3N3 FTPAD_TP [33D7] FT4P8 FTPAD_TP [5C7] J1D1 1X6HDR_SMT [41B1]
FT1M5 FTPAD_TP [41A6] FT3P1 FTPAD_TP [22D7] FT4R2 FTPAD_TP [2D6] J1F1 1X2HDR_TH [35A1]
FT1N1 FTPAD_TP [46C2] FT3P2 FTPAD_TP [22D3] FT4R3 FTPAD_TP [52A1] J1G3 2X4HDR_TH [58A3]
MICROSOFT PROJECT NAME PAGE REV
TRINITY_XDK 77/81 1.01
CONFIDENTIAL
J2A1 TRINITYRJ45AUX_TH [38B3] Q3F1 FET_VREG_DPAK [49C4] R1T4 RESN_805 [47D8] R2E2 RESN_402 [47B8]
J2C1 2X5HDR10_TH [59C7] Q3M1 PNP_SOT23 [37B7] R1T5 RESN_402 [34C5] R2E3 RESN_402 [47B7]
J2C3 2X7HDR14_TH [59C3] Q4A1 NPN_SOT23 [36C5] R1T6 RESN_1206 [42C2] R2E4 RESN_402 [47A3]
J3A1 HDMI_1X19HDR [40B2] Q4B1 ADR510_SOT23 [57A5] R1T7 RESN_402 [42C2] R2E5 RESN_402 [47A8]
J3C1 2X3HDR_TH [60C7] Q4D1 NPN_SOT23 [60A3] R1T8 RESN_402 [34B7] R2E6 RESN_402 [47C4]
J3G1 2X3HDR_TH [60B7] Q4D2 NPN_SOT23 [60A4] R1T9 RESN_402 [34C6] R2E7 RESN_402 [47C7]
J4A1 TOSLINK_TX_TH [39A5] Q4F1 FET_VREG_DPAK [49B4] R1T10 RESN_402 [34C6] R2E8 RESN_402 [26A5]
J4A2 XENONAVIP_TH [37C5] Q4G1 PNP_SOT23 [23C1] R1T11 RESN_402 [34B7] R2E9 RESN_402 [26A7]
J4A3 2X6HDR2_TH [41A2] Q5A2 PNP_DPAK [36C5] R1T12 RESN_402 [34B6] R2F1 RESN_402 [47B5]
J4C1 2X4HDR_TH [60D7] Q5B1 FET_VREG_DPAK [51C3] R1T13 RESN_402 [34B6] R2F2 RESN_402 [56C6]
J4C2 2X5HDR_TH [60A6] Q5C1 FET_VREG_DPAK [45A3] R1T14 RESN_402 [34C2] R2F3 RESN_402 [56C6]
J4D1 2X3HDR_TH [60C7] Q5C2 FET_VREG_DPAK [51B3] R1T15 RESN_402 [34B6] R2F4 RESN_402 [56A5]
J5A4 1X4HDR_TH [36C2] Q5C3 FET_VREG_DPAK [45A4] R1T16 RESN_402 [34B6] R2F5 RESN_402 [56A4]
J5B1 2X2HDR_TH [55C6] Q6A1 NPN_SOT23 [42B6] R1T17 RESN_402 [34B5] R2F7 RESN_805 [47A3]
J5B2 1X5HDR2_TH [41D1] Q6A2 FET_SOT23 [42B6] R1T18 RESN_402 [34B5] R2F8 RESN_402 [56A4]
J5G2 XENONRF_BORON_TH [38A5] Q6B1 FET_VREG_DPAK [45A4] R1T19 RESN_402 [56C3] R2F9 RESN_805 [48B3]
J6G1 USBDUALHORIZONTAL_ [39C5] Q6B2 FET_VREG_DPAK [45D4] R1U3 RESN_402 [56C7] R2G1 RESN_2512 [47C3]
TH Q6C1 FET_VREG_DPAK [45C3] R1U4 RESN_402 [56C7] R2G2 RESN_1206 [47B1]
J7A1 TRINITYPWR_TH [38A1] Q6C2 FET_VREG_DPAK [45C4] R1U5 RESN_402 [56D2] R2G3 RESN_402 [26A3]
L1F1 INDUCTOR_TH [48C3] Q6M1 PNP_2C_SOT223 [42C4] R2A2 RESN_402 [38C7] R2G4 RESN_402 [26A3]
L2B1 INDUCTOR_TH [47D8] Q7G1 FET_VREG_DPAK [50C4] R2A3 RESN_402 [38C7] R2G5 RESN_402 [26A3]
L2F1 INDUCTOR_TH [47C4] Q7G2 FET_VREG_DPAK [50B4] R2A4 RESN_402 [38C7] R2G21 RESN_402 [26A1]
L4A1 INDUCTOR_1210 [37A4] R1A1 RESN_402 [39B7] R2A5 RESN_402 [38B7] R2N1 RESN_402 [37C2]
L4A2 INDUCTOR_1210 [37A4] R1C1 RESN_805 [52C6] R2B1 RESN_402 [55D7] R2N2 RESN_402 [35C7]
L4A3 INDUCTOR_1210 [37A7] R1D1 RESN_1210 [52D7] R2B2 RESN_402 [55C7] R2N3 RESN_402 [35C7]
L4A4 INDUCTOR_1210 [37A7] R1D2 RESN_1210 [52D8] R2B3 RESN_402 [55D7] R2N4 RESN_402 [35D5]
L4B1 INDUCTOR_TH [51C5] R1D3 RESN_1210 [52D8] R2B4 RESN_402 [55D7] R2N5 RESN_402 [35D6]
L4F1 INDUCTOR_TH [49C3] R1D4 RESN_1210 [52D8] R2C1 RESN_402 [27D3] R2N6 RESN_402 [35D6]
L5A1 INDUCTOR_1210 [53B4] R1D5 RESN_402 [41C2] R2C3 RESN_402 [37C1] R2N7 RESN_402 [35D4]
L5B2 INDUCTOR_1210 [53C4] R1D6 RESN_402 [41B2] R2C4 RESN_402 [59C2] R2N8 RESN_402 [35C3]
L5C1 INDUCTOR_TH [51B3] R1E12 RESN_402 [47C7] R2C5 RESN_402 [27C6] R2R1 RESN_402 [32B6]
L6A1 INDUCTOR_1210 [53C8] R1E14 RESN_402 [48D5] R2C6 RESN_402 [59C4] R2R2 RESN_402 [32C6]
L6B1 INDUCTOR_TH [43B5] R1E15 RESN_402 [48C7] R2C7 RESN_402 [59C2] R2R3 RESN_402 [32C6]
L6C1 IND_2MODE_SM [45C1] R1E16 RESN_402 [48C7] R2C8 RESN_402 [28D3] R2R4 RESN_402 [32A6]
L6C2 IND_2MODE_TH [45B1] R1E17 RESN_402 [47B7] R2C9 RESN_402 [26C2] R2R5 RESN_402 [32B6]
L7B1 INDUCTOR_TH [49D8] R1E19 RESN_402 [48A3] R2C10 RESN_402 [41B2] R2R6 RESN_402 [32A7]
L7F1 INDUCTOR_TH [50C3] R1E20 RESN_402 [48A3] R2C11 RESN_402 [41B2] R2R7 RESN_402 [32C2]
LB2B1 LABEL_SM [62D5] R1E21 RESN_402 [48A7] R2D1 RESN_402 [32B6] R2R8 RESN_402 [32A7]
MTG1B1 STD_MTG_HOLE_TH [62C6] R1E22 RESN_402 [48D4] R2D2 RESN_402 [32B7] R2R9 RESN_402 [32C3]
MTG1G1 STD_MTG_HOLE_TH [62C6] R1F1 RESN_402 [48B5] R2D3 RESN_402 [32A6] R2R10 RESN_402 [32C3]
MTG4D1 STD_MTG_HOLE_TH [62A6] R1F2 RESN_402 [48B4] R2D4 RESN_402 [32C2] R2R11 RESN_402 [32A2]
MTG4F1 STD_MTG_HOLE_TH [62B6] R1F3 RESN_402 [47B4] R2D5 RESN_402 [29B2] R2R12 RESN_402 [32C1]
MTG4G1 STD_MTG_HOLE_TH [62C5] R1F4 RESN_402 [56A5] R2D6 RESN_402 [32C6] R2R13 RESN_402 [32A2]
MTG6D1 STD_MTG_HOLE_TH [62A4] R1F5 RESN_402 [56A4] R2D7 RESN_402 [29D6] R2R14 RESN_402 [29B4]
MTG6F1 STD_MTG_HOLE_TH [62B4] R1F6 RESN_402 [56A5] R2D8 RESN_402 [29D6] R2R15 RESN_402 [32C2]
MTG7G1 STD_MTG_HOLE_TH [62C3] R1F9 RESN_2512 [48C2] R2D9 RESN_402 [29B2] R2R16 RESN_402 [29B3]
Q1F1 SHUNT_3PIN_SOT23 [56D3] R1G1 RESN_402 [58B3] R2D10 RESN_402 [29B3] R2R17 RESN_402 [29B4]
Q1N1 MBT3904DUAL_SOT [46C5] R1N1 RESN_402 [46C5] R2D11 RESN_402 [29B2] R2R18 RESN_402 [29B3]
Q1N2 FET_SOT23 [35C7] R1N2 RESN_402 [46C6] R2D12 RESN_402 [29B3] R2R19 RESN_402 [26D7]
Q1N3 FET_SOT23 [35C7] R1N3 RESN_402 [46C5] R2D13 RESN_402 [29D3] R2R20 RESN_402 [26B7]
Q1T1 NPN_SOT23 [42B2] R1N4 RESN_402 [35D6] R2D14 RESN_402 [26B7] R2R21 RESN_402 [26B8]
Q1T2 NPN_SOT23 [42B2] R1N5 RESN_402 [35D7] R2D15 RESN_402 [26B8] R2R22 RESN_402 [26B8]
Q2F1 FET_VREG_DPAK [47C4] R1P1 RESN_402 [46C6] R2D16 RESN_402 [26B8] R2R23 RESN_402 [26C7]
Q2F2 FET_VREG_DPAK [47B4] R1P2 RESN_402 [46B5] R2D17 RESN_402 [26B8] R2R24 RESN_402 [26B8]
Q2F3 SHUNT_3PIN_SOT23 [56D7] R1T1 RESN_402 [42B3] R2D18 RESN_402 [26B7] R2R25 RESN_402 [26B7]
Q2N1 NPN_SOT23 [35C4] R1T2 RESN_402 [47C7] R2D19 RESN_402 [26A5] R2R26 RESN_402 [26A7]
Q3A1 MBT3904DUAL_SOT [37C7] R1T3 RESN_1206 [42C1] R2E1 RESN_402 [29A6] R2T1 RESN_402 [28B6]
MICROSOFT PROJECT NAME PAGE REV
TRINITY_XDK 78/81 1.01
CONFIDENTIAL
R2T2 RESN_402 [28A6] R3D8 RESN_402 [26A7] R3R4 RESN_402 [27B6] R4B21 RESN_402 [51C7]
R2T3 RESN_402 [47D5] R3D9 RESN_402 [26A1] R3R5 RESN_402 [50D3] R4B22 RESN_402 [51A5]
R2T4 RESN_402 [47A3] R3D10 RESN_402 [26A1] R3R6 RESN_402 [27C6] R4C1 RESN_402 [23A7]
R2T5 RESN_402 [56C6] R3E1 RESN_402 [58C4] R3R7 RESN_402 [26B7] R4C2 RESN_402 [23A5]
R2U1 RESN_402 [56D7] R3E2 RESN_402 [58C5] R3R8 RESN_402 [26B6] R4C3 RESN_402 [5C6]
R3A1 RESN_402 [37C7] R3E3 RESN_402 [58C5] R3R9 RESN_402 [26B7] R4C4 RESN_402 [60A4]
R3A2 RESN_402 [37C6] R3E4 RESN_402 [58A7] R3R11 RESN_402 [35B6] R4C5 RESN_402 [5B7]
R3A3 RESN_402 [37C8] R3E5 RESN_805 [52B6] R3R13 RESN_402 [59C2] R4C6 RESN_402 [60A5]
R3A4 RESN_402 [37C8] R3F2 RESN_402 [58C5] R3R14 RESN_402 [26D8] R4C7 RESN_402 [60A4]
R3A5 RESN_402 [37C7] R3F3 RESN_402 [58C5] R3R15 RESN_402 [22D4] R4C8 RESN_402 [5B7]
R3A6 RESN_603 [37C7] R3F4 RESN_402 [52B6] R3R16 RESN_402 [22D4] R4C9 RESN_402 [60A4]
R3A8 RESN_402 [33B3] R3F5 RESN_402 [58C2] R3R17 RESN_402 [27B6] R4C10 RESN_402 [60A6]
R3A9 RESN_402 [33B3] R3F6 RESN_402 [49A7] R3R18 RESN_402 [27B6] R4C11 RESN_402 [51B7]
R3A10 RESN_402 [33B2] R3F7 RESN_402 [49B4] R3R19 RESN_402 [27C2] R4C13 RESN_402 [51C7]
R3A11 RESN_402 [33B2] R3F8 RESN_402 [49A3] R3R20 RESN_402 [27B2] R4C14 RESN_402 [51B7]
R3B2 RESN_402 [23C3] R3F9 RESN_402 [49A3] R3R21 RESN_402 [27B3] R4C17 RESN_402 [51B6]
R3B3 RESN_402 [22D6] R3F10 RESN_402 [49C4] R3R22 RESN_402 [26C7] R4D1 RESN_402 [2C6]
R3B4 RESN_402 [23B6] R3F11 RESN_805 [49B3] R3R23 RESN_402 [27B2] R4D2 RESN_402 [2C6]
R3B5 RESN_603 [23B1] R3F12 RESN_402 [49C7] R3R24 RESN_402 [26C8] R4D3 RESN_402 [60B4]
R3B6 RESN_603 [23B1] R3F13 RESN_402 [49C7] R3T1 RESN_805 [31D7] R4D4 RESN_402 [2D4]
R3B7 RESN_603 [23B1] R3F14 RESN_402 [49C7] R3T2 RESN_402 [27A3] R4D5 RESN_402 [2D4]
R3B8 RESN_603 [23C1] R3F15 RESN_402 [49B7] R3T3 RESN_402 [27A2] R4E1 RESN_402 [4D7]
R3B9 RESN_402 [22D8] R3F16 RESN_402 [55C2] R3T4 RESN_402 [26D8] R4E2 RESN_402 [4D7]
R3B10 RESN_402 [22C7] R3G1 RESN_402 [55A4] R3T5 RESN_402 [52C2] R4E3 RESN_402 [60A3]
R3B11 RESN_402 [22C7] R3G2 RESN_805 [49D7] R3U1 RESN_402 [55C5] R4E4 RESN_805 [52B6]
R3B12 RESN_402 [22A3] R3G4 RESN_402 [49B7] R3U2 RESN_402 [58A8] R4E5 RESN_402 [52B6]
R3B13 RESN_402 [22A2] R3G5 RESN_402 [50C7] R3U3 RESN_402 [55C5] R4E6 RESN_402 [52B7]
R3B14 RESN_402 [22B2] R3G6 RESN_402 [55A4] R3V1 RESN_402 [49B4] R4E7 RESN_402 [52C2]
R3B15 RESN_402 [22A3] R3G7 RESN_402 [55C5] R3V4 RESN_402 [50A7] R4E8 RESN_402 [52C3]
R3B16 RESN_402 [22B2] R3G8 RESN_402 [55C5] R3V5 RESN_402 [38A7] R4E9 RESN_402 [52C3]
R3B17 RESN_402 [22B2] R3G9 RESN_402 [55C5] R3V6 RESN_402 [38B6] R4E10 RESN_402 [52C2]
R3B18 RESN_402 [22C2] R3G10 RESN_402 [50B5] R4A1 RESN_402 [36C5] R4E11 RESN_805 [52D2]
R3B19 RESN_402 [22C2] R3G11 RESN_402 [50A3] R4A2 RESN_402 [37A5] R4F1 RESN_2512 [49C2]
R3B20 RESN_402 [22C2] R3G12 RESN_402 [50A3] R4A3 RESN_402 [37A5] R4F2 RESN_402 [52A7]
R3B21 RESN_402 [22C2] R3G13 RESN_402 [50C4] R4A4 RESN_402 [37A7] R4G3 RESN_402 [50B4]
R3B22 RESN_805 [33D6] R3G14 RESN_402 [50B8] R4A5 RESN_402 [37A7] R4G4 RESN_402 [38B6]
R3B24 RESN_402 [37A2] R3G15 RESN_402 [50D5] R4A6 RESN_402 [41A3] R4G5 RESN_402 [38B7]
R3C1 RESN_402 [22C2] R3G16 RESN_402 [49D5] R4A7 RESN_402 [36C5] R4G6 RESN_402 [38A7]
R3C2 RESN_402 [22C2] R3G17 RESN_805 [50A3] R4B1 RESN_402 [57B7] R4G7 RESN_402 [38A7]
R3C3 RESN_402 [22C2] R3G18 RESN_402 [26A7] R4B2 RESN_402 [57C5] R4M1 RESN_402 [40A6]
R3C4 RESN_402 [22D2] R3G19 RESN_402 [26A7] R4B3 RESN_402 [57B5] R4M2 RESN_402 [40A7]
R3C5 RESN_402 [22D2] R3G20 RESN_402 [26A5] R4B4 RESN_805 [51C4] R4M5 RESN_402 [40A3]
R3C6 RESN_402 [22D2] R3M1 RESN_402 [27B6] R4B6 RESN_402 [22D5] R4M6 RESN_402 [40A2]
R3C7 RESN_402 [22C2] R3M2 RESN_402 [37B7] R4B7 RESN_402 [22D6] R4N1 RESN_402 [57B5]
R3C8 RESN_402 [22D2] R3M3 RESN_402 [37B7] R4B8 RESN_402 [23D2] R4N2 RESN_402 [57A7]
R3C9 RESN_402 [22D2] R3M6 RESN_402 [33B5] R4B9 RESN_402 [23D2] R4N3 RESN_402 [57A7]
R3C10 RESN_402 [22D2] R3M7 RESN_402 [37B6] R4B10 RESN_402 [23C6] R4N4 RESN_402 [57A6]
R3C11 RESN_402 [22B3] R3N3 RESN_402 [23B6] R4B11 RESN_402 [51B6] R4N5 RESN_402 [57A6]
R3C12 RESN_402 [22B3] R3N4 RESN_402 [23B6] R4B12 RESN_402 [23D3] R4N6 RESN_402 [57A6]
R3C13 RESN_402 [22B2] R3N5 RESN_402 [22B4] R4B13 RESN_402 [23D3] R4N7 RESN_402 [57A6]
R3C14 RESN_402 [22B2] R3N6 RESN_402 [24B6] R4B14 RESN_402 [23A3] R4N8 RESN_402 [57D4]
R3D1 RESN_402 [27A7] R3N7 RESN_402 [22C8] R4B15 RESN_402 [23A7] R4N10 RESN_402 [57C4]
R3D2 RESN_402 [27A7] R3N8 RESN_402 [22C7] R4B16 RESN_402 [22D7] R4N13 RESN_402 [57D4]
R3D3 RESN_402 [26B7] R3P1 RESN_402 [22C7] R4B17 RESN_402 [51B4] R4N14 RESN_402 [57C4]
R3D4 RESN_402 [26B6] R3R1 RESN_402 [37C2] R4B18 RESN_402 [57A3] R4N15 RESN_805 [51B4]
R3D5 RESN_402 [26B7] R3R2 RESN_402 [37C2] R4B19 RESN_402 [51A5] R4P1 RESN_402 [61C4]
R3D7 RESN_402 [26A8] R3R3 RESN_402 [27B6] R4B20 RESN_402 [37A2] R4P2 RESN_402 [61C5]
MICROSOFT PROJECT NAME PAGE REV
TRINITY_XDK 79/81 1.01
CONFIDENTIAL
R4P3 RESN_402 [61B4] R5T2 RESN_402 [13A7] R7B4 RESN_402 [44B7] RT2M1 THERMISTOR_1206 [39D3]
R4P4 RESN_402 [61B4] R5T3 RESN_402 [13A7] R7B5 RESN_402 [44D6] RT3A1 THERMISTOR_1206 [37D7]
R4P5 RESN_402 [61B5] R5T4 RESN_402 [13A3] R7C1 RESN_402 [44B4] RT3A2 THERMISTOR_1206 [38D6]
R4P6 RESN_402 [61B5] R5T5 RESN_402 [13A3] R7C2 RESN_402 [44A7] RT5A1 THERMISTOR_1206 [41D3]
R4P9 RESN_402 [5C7] R5T6 RESN_402 [13B5] R7C3 RESN_402 [44A5] RT6G1 THERMISTOR_1206 [39D8]
R4R1 RESN_402 [52A3] R5T7 RESN_402 [13B5] R7C4 RESN_402 [44D5] RT7V1 THERMISTOR_1206 [39C8]
R4R2 RESN_402 [5C4] R5U1 RESN_402 [19A5] R7C5 RESN_402 [44B2] ST1F1 SHORT_SM [48C2]
R4R3 RESN_402 [3C3] R5U2 RESN_402 [19D7] R7C6 RESN_402 [44B4] ST1F2 SHORT_SM [48B2]
R4R4 RESN_805 [52A1] R5U3 RESN_402 [19D7] R7C7 RESN_402 [44C6] ST1F3 SHORT_SM [48C2]
R4R5 RESN_402 [3C3] R5U4 RESN_402 [18A7] R7C8 RESN_402 [44B1] ST1U1 SHORT_SM [48B4]
R4R6 RESN_402 [3C3] R5U5 RESN_402 [18A7] R7C9 RESN_402 [44C6] ST1U2 SHORT_SM [48C4]
R4R7 RESN_402 [5C4] R5U6 RESN_402 [4A4] R7C10 RESN_402 [44D6] ST2G1 SHORT_SM [47B3]
R4R8 RESN_402 [3C3] R6A3 RESN_402 [42B7] R7C11 RESN_603 [44D6] ST2G2 SHORT_SM [47C2]
R4R9 RESN_402 [5C4] R6A4 RESN_402 [42B7] R7C12 RESN_603 [44D6] ST2G3 SHORT_SM [47C2]
R4R10 RESN_402 [5B3] R6A5 RESN_402 [38A3] R7C13 RESN_402 [44D2] ST2R1 SHORT_SM [31B7]
R4R11 RESN_402 [5C4] R6A6 RESN_402 [38A2] R7C14 RESN_805 [44A7] ST2R2 SHORT_SM [31B7]
R4R12 RESN_402 [5C3] R6A7 RESN_402 [42C6] R7C15 RESN_402 [43C5] ST2T1 SHORT_SM [31A7]
R4R13 RESN_402 [3C2] R6A8 RESN_402 [42C6] R7C16 RESN_402 [43C5] ST2T2 SHORT_SM [30C8]
R4T5 RESN_402 [2B8] R6A9 RESN_402 [42C5] R7C17 RESN_402 [43C4] ST2U1 SHORT_SM [47C4]
R4T6 RESN_402 [2B8] R6A10 RESN_402 [58D7] R7C18 RESN_402 [43C4] ST2U2 SHORT_SM [47B4]
R4U4 RESN_402 [52B6] R6A11 RESN_402 [58C7] R7C19 RESN_402 [43C4] ST3C1 SHORT_SM [23A6]
R4V1 RESN_402 [38A7] R6C1 RESN_805 [45C3] R7C20 RESN_402 [43C3] ST3C2 SHORT_SM [23A6]
R4V2 RESN_402 [38A7] R6C2 THERMISTOR_603 [44C6] R7D2 RESN_402 [16D7] ST3C3 SHORT_SM [23A6]
R5A3 RESN_402 [36C2] R6F1 RESN_402 [21A8] R7D3 RESN_402 [16D7] ST3C4 SHORT_SM [23A6]
R5A5 RESN_402 [53B5] R6F2 RESN_402 [21A8] R7D4 RESN_402 [17A7] ST3C5 SHORT_SM [23A6]
R5A6 RESN_402 [53B4] R6F3 RESN_402 [20D7] R7D5 RESN_402 [17A7] ST3F1 SHORT_SM [49C4]
R5A7 RESN_402 [53B6] R6F4 RESN_402 [20D7] R7E1 RESN_402 [16A5] ST3R1 SHORT_SM [31D7]
R5A9 RESN_805 [36C3] R6F5 RESN_402 [20A5] R7E2 RESN_402 [4A2] ST3T1 SHORT_SM [30D7]
R5A10 RESN_402 [36A3] R6F6 RESN_402 [4A3] R7E4 RESN_402 [14D7] ST3T2 SHORT_SM [30A7]
R5A11 RESN_805 [53B3] R6G1 RESN_402 [35C6] R7E5 RESN_402 [14D7] ST4F1 SHORT_TRACE [49B2]
R5B2 RESN_402 [53C5] R6M1 RESN_805 [42B4] R7E6 RESN_402 [15A8] ST4F2 SHORT_SM [49C2]
R5B3 RESN_402 [53C6] R6M2 RESN_805 [42B5] R7E7 RESN_402 [15A8] ST4F4 SHORT_SM [49C2]
R5B4 RESN_805 [53C3] R6M3 RESN_402 [58C6] R7E8 RESN_402 [14A5] ST4U1 SHORT_TRACE [49B4]
R5B5 RESN_402 [53C6] R6M4 RESN_402 [58C7] R7F1 RESN_2512 [50C2] ST5C1 SHORT_SM [51C2]
R5B6 RESN_402 [57B4] R6N1 RESN_805 [45D7] R7P1 RESN_402 [44A7] ST5C2 SHORT_TRACE [51B3]
R5B13 RESN_805 [51B3] R6N2 RESN_805 [45D5] R7P2 RESN_402 [44A6] ST5C3 SHORT_SM [51C2]
R5B17 RESN_402 [53C4] R6R1 RESN_402 [12B1] R7P3 RESN_402 [43D6] ST5R1 SHORT_SM [6C6]
R5C1 RESN_805 [45A2] R6R2 RESN_402 [12B1] R7P4 RESN_402 [43D6] ST5R2 SHORT_SM [6C6]
R5C2 RESN_2512 [51B2] R6T1 RESN_402 [12A3] R7P5 RESN_402 [43D6] ST5R3 SHORT_SM [6A6]
R5F1 RESN_402 [19A7] R6T2 RESN_402 [12A3] R7P6 RESN_402 [43D6] ST5R4 SHORT_SM [6A6]
R5F2 RESN_402 [19A7] R6T3 RESN_402 [4A6] R7P7 RESN_402 [43D6] ST5R5 SHORT_SM [6B6]
R5F3 RESN_402 [18D7] R6T4 RESN_402 [12A7] R7P8 RESN_402 [43C6] ST5T1 SHORT_SM [6C6]
R5F4 RESN_402 [18D7] R6T5 RESN_402 [12A7] R7R1 RESN_402 [17D7] ST5T2 SHORT_SM [6B6]
R5F5 RESN_402 [18A5] R6T6 RESN_402 [4A6] R7R2 RESN_402 [16A8] ST6C1 SHORT_SM [44B8]
R5G1 RESN_402 [35D2] R6T7 RESN_402 [12B5] R7R3 RESN_402 [17D7] ST6D1 SHORT_SM [44A8]
R5G2 RESN_402 [35D2] R6T8 RESN_402 [12B5] R7R4 RESN_402 [16A8] ST6D2 SHORT_SM [44A5]
R5M1 RESN_805 [42B5] R6T9 RESN_402 [13B1] R7R6 RESN_402 [4A3] ST6V1 SHORT_TRACE [50B4]
R5M2 RESN_805 [42B5] R6U1 RESN_402 [21A5] R7T1 RESN_402 [17A5] ST6V2 SHORT_TRACE [50C4]
R5M3 RESN_402 [36B5] R6U2 RESN_402 [21D7] R7T2 RESN_402 [15D7] ST7A1 SHORT_SM [38B2]
R5M4 RESN_402 [36B5] R6U3 RESN_402 [21D7] R7T3 RESN_402 [15D7] ST7A2 SHORT_SM [38B2]
R5M5 RESN_402 [36B5] R6U4 RESN_402 [20A8] R7T4 RESN_402 [14A7] ST7F1 SHORT_SM [50B2]
R5M6 RESN_402 [53B6] R6U5 RESN_402 [20A8] R7T5 RESN_402 [14A7] ST7F2 SHORT_SM [50C2]
R5N2 RESN_402 [57C5] R7A1 RESN_2512 [38B2] R7T6 RESN_402 [15A5] ST7F3 SHORT_SM [50C2]
R5N7 RESN_805 [45B7] R7A2 RESN_2512 [38A2] R7T7 RESN_402 [4A3] STP3C1 STP_TP [61B1]
R5N8 RESN_805 [45A5] R7B1 RESN_402 [44B6] RT1B1 THERMISTOR_1206 [38D6] STP4C1 STP_TP [61C4]
R5R1 RESN_402 [2A6] R7B2 RESN_402 [44B6] RT1M1 THERMISTOR_1206 [39B3] STP4C2 STP_TP [61B4]
R5T1 RESN_402 [4C6] R7B3 RESN_402 [44B7] RT1M2 THERMISTOR_1206 [39C3] STP4C3 STP_TP [61C5]
MICROSOFT PROJECT NAME PAGE REV
TRINITY_XDK 80/81 1.01
CONFIDENTIAL
STP4C4 STP_TP [61B4] U3G3 REF3333_SC70 [55B4]
STP4C5 STP_TP [61B5] U3G4 ISD2130_QFN21 [35A4]
STP4C6 STP_TP [61B5] U3T1 REF3333_SC70 [58B7]
STP4E1 STP_TP [61B7] U3V1 AD5252_TSSOP [55C4]
STP4E2 STP_TP [61B7] U3V2 AD8213_MSOP10 [55A5]
STP4E3 STP_TP [61A8] U4B1 AD5252_TSSOP [57A5]
STP5B1 STP_TP [61B1] U4B2 AD7992_MSOP10 [57D3]
STP5B2 STP_TP [61B1] U4B3 IR3638_SSOP [51B5]
STP5D1 STP_TP [61C7] U4E1 NCP1117_DPAK [52B7]
STP5D2 STP_TP [61C7] U4E2 NCP1117_SOT223 [52D3]
STP6C1 STP_TP [61B7] U4R1 LD39015_SOT23-5 [52A3]
STP6C2 STP_TP [61A7] U4R2 AT25020A_SOI8 [5C2]
STP7B1 STP_TP [61B1] U5A1 SIMPLESWR_SOT23 [53B5]
STP7C1 STP_TP [61B1] U5B1 SIMPLESWR_SOT23 [53C5]
STP7C2 STP_TP [61C1] U5B2 AD8213_MSOP10 [57C6]
STP7C3 STP_TP [61C1] U5B5 MOSDRIVER_SOI8 [45A6]
STP7C4 STP_TP [61C1] U5B6 REF3333_SC70 [57D6]
STP7C5 STP_TP [61C1] U5E1 VALHALLA_1_BGA_2 [2C4]
STP7C6 STP_TP [61C1] U5E1 VALHALLA_1_BGA_2 [3C5]
STP7C7 STP_TP [61C1] U5E1 VALHALLA_1_BGA_2 [4A5]
STP7E1 STP_TP [61C7] U5E1 VALHALLA_1_BGA_2 [5C5]
STP7E2 STP_TP [61C7] U5E1 VALHALLA_1_BGA_2 [6C3]
STP7N1 STP_TP [61B1] U5E1 VALHALLA_1_BGA_2 [7B6 7A8 7C8
U1B1 SI4501DY_SO8 [46C3] 7B4 7B1]
U1C1 NCP1117_DPAK [52C7] U5E1 VALHALLA_1_BGA_2 [8B2 8B4 8B7]
U1E1 ADP1877_LCC32 [47A6] U5E1 VALHALLA_1_BGA_2 [12C3 12C7]
U1E1 ADP1877_LCC32 [48A7] U5E1 VALHALLA_1_BGA_2 [13C6 13C3]
U1E2 NAND_TSOP [34B3] U5F1 GDDR136_1GBIT_BGA1 [18C2 18C6]
U1F1 FET_VREG_DUAL_1_SO [48C4] 36
-8 U5N1 AD7992_MSOP10 [57C4]
U1F2 AD7991_SOT23 [56B3] U5U1 GDDR136_1GBIT_BGA1 [19C6 19C2]
U1F3 REF3333_SC70 [56B3] 36
U1F5 TRSET_9920_TH [35B1] U5U2 74LVC1G06_SC70 [4A3]
U1G2 LM95234_LLP-14 [58B2] U6A1 INA219_SOT23-8 [58C6]
U1G3 TRSET_9920_SMT [35B1] U6B1 MOSDRIVER_SOI8 [45C6]
U1U1 AD5252_TSSOP [56C5] U6F1 GDDR136_1GBIT_BGA1 [20C6 20C2]
U2D1 ETHERNETPHY_KSZ804 [32A5] 36
1NL_AR8032_QFN U6G1 IR_WHOLDER_TH [35B7]
U2N1 BMAX20_LGA12 [35C5] U6U1 GDDR136_1GBIT_BGA1 [21C6 21C2]
U2U1 AD8213_MSOP10 [56B5] 36
U3A5 AUDIODAC_CSS4354_W [33A5] U7C1 NCP4201_LCC40 [44C3]
M1824_QFN25 U7D1 GDDR136_1GBIT_BGA1 [16C2 16B6]
U3B2 HANA_BGA225 [22C5] 36
U3B2 HANA_BGA225 [23C4] U7E1 GDDR136_1GBIT_BGA1 [14C2 14C6]
U3B2 HANA_BGA225 [24C4] 36
U3B2 HANA_BGA225 [25B4] U7R1 GDDR136_1GBIT_BGA1 [17B6 17C2]
U3D1 SB_BGA [26C4] 36
U3D1 SB_BGA [27C5] U7T1 GDDR136_1GBIT_BGA1 [15C6 15C2]
U3D1 SB_BGA [28C5] 36
U3D1 SB_BGA [29C5] Y3B1 CRYSTAL_SM [22D8]
U3D1 SB_BGA [30C4]
U3D1 SB_BGA [31B5]
U3E1 AD7992_MSOP10 [58A6]
U3E2 AD5252_TSSOP [58C4]
U3G1 ADP1877_LCC32 [49A6]
U3G1 ADP1877_LCC32 [50A7]
U3G2 AD7991_SOT23 [55A3]
MICROSOFT PROJECT NAME PAGE REV
TRINITY_XDK 81/81 1.01
CONFIDENTIAL