R. V. R. & J. C.

COLLEGE OF ENGINEERING
(AUTONOMOUS)
CHANDRAMOULIPURAM :: CHOWDAVARAM :: GUNTUR – 522019

DEPARTMENT OF ELECTRICAL & ELECTRONICS

ENGINEERING

EE-252- Electronic Devices & Digital

Electronics Laboratory Manual/ Record
Name of the student :
Register No :
Semester :

R.V.R & J.C.COLLEGE OF ENGINEERING

(AUTONOMOUS)

CHOWDAVARAM:: GUNTUR-522019

This is to certify that this is a bonafide record of the work done in ……………………….

………………………………………………………….………………………………….

Laboratory by.....................................…………………………… during the academic

year 2021 – 2022.

Number of experiments completed :

Staff In-Charge Head of the Department

 PARTICULARS OF EXPERIMENTS PERFORMED
Date Of Date Of
S.No Name Of the Experiment Page No Remarks
Experiment Submission
 PARTICULARS OF EXPERIMENTS PERFORMED
Date Of Date Of
S.No Name Of the Experiment Page No Remarks
Experiment Submission
1. DESCRIPTION:
The Experiments in the Lab have been divided into two major portions:

i. Analog Electronics &

ii. Digital Electronics.

Analog Electronics experiments have been designed to study all basic

electronic devices and their characteristics, applications. Using these devices the small
electronic circuits can be designed and tested. Students can perform practical on P-N
junction diode, Zener Diode, rectifiers and filters, transistor biasing etc.,
Digital Electronics experiments have been designed to familiarize students
with the Combinational Digital Logic Design and Sequential Digital Logic Design
through the implementation of Digital Logic Circuits using ICs of basic logic gates
and some simple digital logic circuits. The two logic states are designated “0” (low)
and “1” (high) and defined electronically by fixed voltage levels. The low-state is
usually the reference or ground potential in the circuit and the high-state is some
positive voltage such as +5 V.

2. COURSE OUTCOMES:
With a Sufficient practical and problem solving background the student will be able to
1. Obtain the characteristics of devices like p-n Junction diode, zener diode, BJT in CE, CB
configurations, JFET, UJT, Design the self bias circuit.
2. Design the Zener voltage regulator to meet the specifications.
3. Design Combinational logic circuits such as adders, subtractors, Code converters,
decoders, multiplexers.
4. Design Sequential logic circuits such as flip-flops, shift registers, synchronous and
asynchronous counters.

1
3. LIST OF EQUIPMENT :
MAJOR EQUIPMENT DESCRIPTION OF MAJOR EQUIPMENT
An oscilloscope is a test instrument which allows us to look at
the 'shape' of electrical signals by displaying a graph of
voltage against time on its screen. It is like a voltmeter with
the valuable extra function of showing how the voltage varies
CRO with time.
A regulated power supply is an embedded circuit; it converts
unregulated AC into a constant DC. These 0-30 Volt/5 Amps
DC Regulated Power Supplies are made from very high
quality raw material which ensures hassle free work
performance at its user end. These 0-30 Volt/5 Amps DC
Regulated Power Regulated Power Supplies are widely finds its applications in
Supplies various electrical sectors.
+5V DC Fixed Power Fixed Output Voltage of +5V.
Supply Max. Input Voltage: 230V AC ±1 0%, 50Hz, Single Phase.
Digital Multimeters are great diagnostic tools used for a
variety of jobs. They can be used to diagnose and find
electrical faults in automotive and home electrical circuits,
appliances, electronic devices and light switches. A digital
multimeter is a small handheld device with a digital display
and two probes. They are used to touch different parts of a
circuit and test it. The results are displayed on the digital
readout. A digital multimeter has its own power source. They
Digital Multi-meters can test for continuity, voltage, amps, and ohms.
A function generator for producing an output signal which
varies as a prescribed mathematical function of an input signal.
The generator comprises a bank of like amplifying channels
whose inputs are connected in shunt relation, the input signal
Function Generators being applied concurrently to all channels.
This is a way of making a temporary circuit, for testing
purposes or to try out an idea. No soldering is required and all
the components can be re-used afterwards. It is easy to change
connections and replace components. Almost all the
Electronics Club projects started life on a breadboard to check
Bread Board that the circuit worked as intended.

2
4. LIST OF COMPONENTS :

4.1 RESISTORS:
100k 47k 330k 2.2k 5.6k 3.3k
1kΩ 10kΩ Ω 15kΩ Ω 22kΩ 33kΩ Ω Ω Ω Ω
56k 4.7k 470k 6.8k 15k 1.5k 150k 220k
Ω Ω Ω Ω Ω Ω Ω Ω 38kΩ 220Ω 100Ω
33Ω 47Ω 680Ω 56Ω 47Ω 470Ω 22Ω 1MΩ 2MΩ    
4.2 CAPACITORS:
0.1µf 0.01µf 0.02µf 0.002µf 0.03 µf 0.003 µf 0.005 µf 0.5 µf
100pf 10pf 10µf16v 50µf25v 4.7µf63v 2.2µf63v 22µf25v
4.3 DIODES:
Diode Number Description
1N4001 Silicon Diode
1N4007 Silicon Diode
0A79 Germanium Diode
FZ901 Zener Diode
4.4 TRANSISTORS:
Transistor Number Description
BC107 NPN Transistor
2N2369 Uni Junction Transistor
2N2646 Uni Junction Transistor
BFW10/11 Junction Field Effect Transistor
4.5 IC’s:
IC Number Description of IC
7400 Quad 2 input NAND Gate
7402 Quad 2 input NOR Gate
7404 Hex NOT Gate
7486 Quad 2 input EX-OR Gate
7410 Tri Three Input NAND Gate
4.6 METERS (ANALOG/DIGITAL)
(0-500)μA
(0-25)mA
(0-50)mA
Ammeters
(0-100)mA
(0-200)mA
(0-1000)mA
Voltmeters (0-30)V

5. LIST OF EXPERIMENTS
3
1. Characteristics of PN Junction and Zener diode.
2. Characteristics of Transistor in Common Emitter configuration.
3. Realization of Gates using Universal Building Block(NAND Only).
4. Design of Combinational Logic Circuits like Half-adder, Half subtractor, Full-adder
and Full-subtractor.
5. Realization of gates using discrete components.
6. Characteristics of Junction Field Effect Transistor.
7. Characteristics of Uni junction Transistor.
8. Study of Half wave rectifier & Full wave rectifier with and without filters.
9. Design of Code converters (Binary to Gray).
10. Verification of Truth Tables of Flip Flops using Gates.

4
6. DESCRIPTION OF EQUIPMENT & COMPONENTS

6.1 TYPES OF CIRCUIT BOARDS

6.1.1Breadboard:
This is a way of making a temporary circuit, for testing purposes or to try out an
idea. No soldering is required and all the components can be re-used afterwards. It is easy to
change connections and replace components. Almost all the Electronics Club projects started
life on a breadboard to check that the circuit worked as intended.

Fig.1 (a): Bread board (b) Internal Connection Details

A real breadboard is shown in Fig. 1(a) and the internal connection details
on its rear side are shown in Fig. 1(b).

Connecting the Logic Gate ICs (Integrated Circuits)

5
 The ICs we will be using will all have a similar setup. The pictures below
are for the 7400 NAND gate. Be sure to look carefully at each experiment to double-
check the connections before you turn the power on!
As shown in Fig.2, the IC must be inserted in the breadboard so that
it "spans" across the centre divider and all the pins are separated. The semi-
circular notch on the top of the IC goes at the LEFT side. 5V power is connected to
pin 14 (top left) and ground is connected to pin 7 (bottom right)

Fig.2 Connecting IC

7. RESISTOR:

A Resistor is a passive two-terminal electrical component that implements

electrical resistance as a circuit element. The current through a resistor is in direct
proportion to the voltage across the resistor's terminals. This relationship is
represented by Ohm's law:
I=V/R
Where I is the current through the conductor in units of amperes, V is the potential difference
measured across the conductor in units of volts, and R is the resistance of the conductor in
units of ohms.

7.1 COLOUR CODING OF RESISTOR

Because carbon resistors are small physically, they are color coded to
mark their R value in ohms. The value is normally written as 4 band, 5 band or 6 band
code. In memorizing the colors, note that the darkest color, black and brown are the
for the lowest numbers, zero and one, through lighter colors to white for nine.

6
The numbers to the Colour are identified in the following sequence which is remembered as
BBROY GREAT BRITAN VERY GOOD WIFE (BBROYGBVGW)
Color Name Number
BLACK 0
BROWN 1
RED 2
ORANGE 3
YELLOW 4
GREEN 5
BLUE 6
VIOLET 7
GRAY 8
WHITE 9
GOLD 5%
SILVER 10%

Resistor color coding values

Fig.3 Resistor Color Code Diagram (4Band)

7.1.1 Examples on How to Calculate the Resistor Colour Code

Example 1:-

7
 The first band is red for 2
and the next band is violet for 7. The
red multiplier in the third band
means add two zeroes to
27.Therefore, this Resistance value is 2700Ω with tolerance ±5%. The resistor
tolerance means the amount by which the actual Resistance can be different form the
color-coded value. For instance, the alone value 2700Ω resistor with ±5% tolerance
can have resistance 5 percent above or below the coded value.
This Resistance, therefore, is between 2565Ω and 2835Ω. the calculations are as follows:
5 percent of 2700 is 0.05 x 2700 = 135
For +5 percent, the value is               2700 + 135=2835Ω
For -5 percent, the value is                2700 – 135 = 2566Ω
Example 2:-

The first band is green for 5 and the next band is blue for 6. The orange
multiplier in the third band means add three zeroes to 56.Therefore, this Resistance
value is 56000Ω with tolerance ±10%. For instance, the alone value 56000Ω resistor
with ±10% tolerance can have resistance 10 percent above or below the coded value.
This Resistance, therefore, is between 61600Ω and 50400Ω. The calculations are as follows:
10 percent of 2700 is 0.1 x 56000 = 5600
For +10 percent, the value is               56000 + 5600=61600Ω
For -10 percent, the value is                56000 – 5600 = 50400Ω

8. CIRCUIT SYMBOLS
S.NO COMPONENT NAME CIRCUIT SYMBOL
1 WIRE

2 WIRES JOINED

3 WIRES NOT JOINED

4 CELL

8
5 BATTERY

6 DC SUPPLY

7 AC SUPPLY

8 FUSE

9 EARTH(GROUND)

ON/OFF
10
SWITCH(SPST)
2 WAY
11
SWITCH(SPDT)

12 RESISTOR

VARIABLE RESISTOR
13
(RHEOSTAT)

14 INDUCTOR

15 VARIABLE INDUCTOR

16 CAPACITOR

9
 17 VARIABLE CAPACITOR

18 DIODE

19 LED (LIGHT EMITTING DIODE)

20 ZENER DIODE

21 TRANSISTOR -NPN

22 TRANSISTOR -PNP

23 VOLTMETER

24 AMMETER

9. PIN CONFIGURATION OF IC’S

IC 7400 - Quad 2 input NAND Gate

10
IC 7486 - Quad 2 input EX-OR Gate

IC 7404 - Hex NOT Gate

11
 IC 7410 - Tri Three Input NAND Gate

Exp No : 1
Characteristics of P-N Junction and zener diodes

12
Aim of the experiment :-

a) To obtain forward and reverse bias characteristics of silicon and germanium diodes. From
the characteristics, obtain (i) cut-in-voltage voltage
(ii) Static forward resistance &
(iii) Dynamic forward resistance.
b) To obtain forward and reverse bias characteristics of a zener diode. From the
characteristics, obtain the zener break down voltage.

Apparatus:-

S.No Apparatus/Component Range/ Number Quantity

1 DC Regulated Power Supply(RPS) (0-30)V 1 No
2 Silicon diode IN4001 1 No
3 Germanium diode 0A79 1 No
4 Zener diode FZ 9.1 1 No

5 Resistance 1KΩ 1 No

6 DC Ammeter (0-25) mA 1 No

(0-500) µA 1 No

7 Multimeter 1 No
8 Bread Board 1 No

13
Circuit Diagram:-

a) To obtain forward and reverse bias characteristics of silicon and germanium diodes.

Fig 1(a)

Fig 1(b)

b) To obtain forward and reverse bias characteristics of a zener diode

Fig 1(c)

14
 Fig 1(d)

Theory:-

PN Junction Diode:-

A diode is a two terminal device. This consists of an anode and a cathode. A

semiconductor diode is made up of a p-type semiconductor and an n-type
semiconductor. This is a unilateral and non-linear device i.e., it conducts in only one
direction and the current does not vary in linearly with the voltage. A diode conducts
when it is in forward bias (i.e. when its anode is at a higher potential than its cathode).
It does not conduct when in reverse bias (i.e. when its anode is at a lower potential
than its cathode).
V-I characteristics of p-n junction diode
The V-I characteristics or voltage-current characteristics of the p-n junction
diode is shown in the below figure. The X-Axis in the below figure represents the
amount of voltage applied across the p-n junction diode whereas the Y- Axis
represents the amount of current flows in the p-n junction diode.

 Forward V-I characteristics of p-n junction diode

15
 Fig 1(e)
In forward biased p-n junction diode, VF represents the forward voltage
whereas IF represents the forward current. If the external voltage applied on the
silicon diode is less than 0.7 volts, the silicon diode allows only a small electric
current. However, this small electric current is considered as negligible.           
When the external voltage applied on the silicon diode reaches 0.7 volts (si)
and 0.3 volts (ge), the p-n Junction diode starts allowing large electric current through
it. At this point, a small increase in voltage increases the electric current rapidly. The
forward voltage at which the silicon diode starts allowing large electric current is
called cut-in voltage. The cut-in voltage for silicon diode is approximately 0.7
volts.     

                   

 Reverse V-I characteristics of p-n junction diode

Fig 1(f)
In reverse biased p-n junction
diode, VR represent s the reverse voltage
whereas IR represen ts the reverse current. If the
external reverse voltage applied on the p-n
junction diode is increased, the free electrons from the n-type semiconductor and the
holes from the p-type semiconductor are moved away from the p-n junction. This
increases the width of depletion region.
The wide depletion region of reverse biased p-n junction diode completely
blocks the majority charge carrier current. However, it allows the minority charge
carrier current. The free electrons (minority carriers) in the p-type semiconductor and
the holes (minority carriers) in the n-type semiconductor carry the electric
current. The electric current, which is carried by the minority charge carriers in the p-
n junction diode, is called reverse current. 
In n-type and p-type semiconductors, very small number of minority charge
carriers is present. Hence, a small voltage applied on the diode pushes all the minority
carriers towards the junction. Thus, further increase in the external voltage does not
increase the electric current. This electric current is called reverse saturation current.
In other words, the voltage or point at which the electric current reaches its maximum
level and further increase in voltage does not increase the electric current is called
reverse saturation current. 
At a given operating point we can determine the static resistance (R d) and Dynamic
resistance (rd) of the diode from its characteristic. The static resistance is defined as the ratio
of the dc voltage to dc current at the operating point. The dynamic resistance is the ratio of a

16
small change in voltage to a small change in current near the operating point (linear portion
of the diode).
ZENER DIODE :-

The symbol for a zener diode is Instead of a straight line representing the
cathode, the zener diode has a bent line that reminds you of the letter Z (for zener). A
zener diode is a silicon pn junction device that is designed for operation in the
reverse-breakdown region. The breakdown voltage of a zener diode is set by carefully
controlling the doping level during manufacture. Recall, from the discussion of the
diode characteristic that when a diode reaches reverse breakdown, its voltage remains
almost constant even though the current changes drastically, and this is the key to
zener diode operation.

Fig 1(g)

 Zener Breakdown

Zener diodes are designed to operate in reverse breakdown. Two types of

reverse breakdown in a zener diode are avalanche and zener. The avalanche effect,
occurs in both rectifier and zener diodes at a sufficiently high reverse voltage. Zener
breakdown occurs in a zener diode at low reverse voltages. A zener diode is heavily
doped to reduce the breakdown voltage. This causes a very thin depletion region. As a
result, an intense electric field exists within the depletion region. Near the zener
breakdown voltage (VZ), the field is intense enough to pull electrons from their
valence bands and create current. Zener diodes with breakdown voltages of less than
approximately 5 V operate predominately in zener breakdown. Those with breakdown
voltages greater than approximately 5 V operate predominately in avalanche
breakdown. Both types, however, are called zener diodes. Zeners are commercially
available with breakdown voltages from less than 1 V to more than 250 V with
specified tolerances from 1% to 20%.

 Breakdown Characteristics

17
 Fig 1(h)

Fig 1(h) shows the reverse portion of a zener diode’s characteristic curve.
Notice that as the reverse voltage (VR) is increased, the reverse current (IR) remains
extremely small up to the “knee” of the curve. The reverse current is also called the
zener current, IZ. At this point, the breakdown effect begins; the internal zener
resistance, also called zener impedance (ZZ), begins to decrease as the reverse current
increases rapidly. From the bottom of the knee, the zener breakdown voltage (VZ)
remains essentially constant although it increases slightly as the zener current, IZ,
increases. Zener Regulation. The ability to keep the reverse voltage across its
terminals essentially constant is the key feature of the zener diode. A zener diode
operating in breakdown acts as a voltage regulator because it maintains a nearly
constant voltage across its terminals over a specified range of reverse-current values.
A minimum value of reverse current, IZK, must be maintained in order to keep the
diode in breakdown for voltage regulation. You can see on the curve in Figure that
when the reverse current is reduced below the knee of the curve, the voltage decreases
drastically and regulation is lost. Also, there is a maximum current, IZM, above which
the diode may be damaged due to excessive power dissipation. So, basically, the zener
diode maintains a nearly constant voltage across its terminals for values of reverse
current ranging from IZK to IZM.

Procedure:-

I . Forward Bias Characteristics of Silicon and Germanium diode:-

1. Connect the circuit diagram as per Fig-1(a) using silicon diode.

2. Connect the multimeter across the diode.
3. Now increase the voltage across the diode in steps from zero volts and note down the
resulting current through the diode in the table-1.
4. Take the readings until a diode current is 20mA.
5. Repeat the same by replacing the silicon diode with a germanium diode.
6. Draw the graph between voltage across diode Vs current through diode
II. Reverse Bias Characteristics of Silicon and Germanium diode:-

1. Connect the circuit diagram as per Fig 1(b) using silicon diode
2. Connect the multimeter across the diode.
3. Now vary the DC supply such that the voltage across the diode increases in steps and
note down the corresponding diode current against each voltage in the table-2.
4. Continue up to a voltage of 20V across the diode.
5. Draw graph between voltages across the diode Vs current through the diode.
III. Forward bias Characteristics of zener diode :-

1. Connect the circuit diagram as per Fig 1(c)

2. Increase the DC supply and note the voltage across the diode in steps and note down
the corresponding diode current against the voltage in the table-3.
3. Take the readings up to a diode current of 20mA.
4. Draw graph between voltage across diode Vs current through diode.
IV. Reverse bias Characteristics of zener diode:-

18
 1. Connect the circuit diagram as per Fig 1(d)
2. Start the DC supply from zero volt and increase the DC supply and note the voltage
across the diode in steps and note down the corresponding diode current against the
voltage in the table-3.
3. Take the readings up to a diode current of 20mA.
4. Draw graph between voltages across diode Vs current through diode.

Tabular forms:-

Table-1:-
Forward bias Characteristics of Silicon and Germanium diode

Silicon Diode Germanium Diode

S.No Voltage across Current through Voltage across Current through
Diode(V) Diode(mA) Diode(V) Diode(mA)
1
2
3
4
5
6
7
8
9
10
11
12
13

Table-2:-

19
 Reverse Bias Characteristics of Silicon and Germanium diode

Silicon Diode Germanium Diode

S.No Voltage across Current through Voltage across Current through
Diode(V) Diode(µA) Diode(V) Diode(µA)
1
2
3
4
5
6
7
8
9
Table-3:-
Forward & Reverse bias Characteristics of zener diode

Zener Diode
Forward Bias Reverse Bias
S.No
Voltage across Current through Voltage across Current through
Diode(V) Diode(mA) Diode(V) Diode(mA)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

20
Model Graph:-

a) For silicon and gemaneum diodes

Fig 1(i)

b) For zener diode

Calculations:-

1. Cut-in-voltage:- The point where the through the junction starts increasing rapidly is the
cut-in-voltage.

2. Static forward resistance: R= V/I

21
3. Dynamic forward resistance: rf= ∆V/∆I

Precautions:-

1. Check the wires for continuity before use.

2. Keep the power supplies at zero volts before start.
3. Check no loose connections exist.

Result:-

1. Cut-in-voltage of Si =
Ge =
2. Statis forward resistance R for Si =
Ge =
3. Dynamic forward resistance r for Si =
Ge =
4. Observed Breakdown voltage (Vz) of zener diode=

Viva Questions:-

1. What is cut-in-voltage?
2. Define static resistance & dynamic resistance?
3. What is Peak Inverse Voltage?
4. Why leakage current is more for germanium diodes?
5. Mention few applications of Zener diode?
6. Why Zener diode is called as a zener regulator?
7. Can a zener diode be used as a rectifier diode?
8. What is difference between normal p-n junction diode and Zener diode?

22
 Exp No : 2
Characteristics of Transistor in Common Emitter
configuration
23
Aim of the experiment:-

To conduct experiment on a given BJT and obtain its (i) Input Characteristics &
(ii) Output characteristics.
Find the h-parameters of CE configuration from the characteristics.

Apparatus:-

S.No Apparatus/Component Range/ Number Quantity

1 Dual DC Regulated Power (0-30)V 1 No
Supply(RPS)
2 Transistor BC107 1 No
3 Resistance 1KΩ
4 DC Ammeter (0-100) mA 1 No
(0-500) µA 1 No
5 Multimeter 1 No
6 Bread Board 1 No

Circuit Diagram:-

24
 Fig 1(a)
Theory:-

A transistor is a three terminal active device. The three terminals are emitter,
base and collector, represented by E, B, and C respectively. The emitter and collector
are the same type of semiconductor and base is of the other type semiconductor. If E
and C are of p-type and B is of n-type, then the transistor is called as pnp transistor.
Similarly, If E and C are of n-type and B is of p-type, then the transistor is called as
npn transistor.
There are two junctions. One junction is between the emitter and the base,
which is called emitter junction or the emitter-base junction or input junction. The
other junction is between the collector and the base, which is called collector junction
or collector base junction or output junction. The direction of the arrow head in the
transistor symbol indicates the direction of the emitter current (conventional electric
current) when the emitter junction is forward biased.
There are three regions of operation in a transistor. They are active region,
cutoff region and saturation region. In active region the transistor acts as an amplifier.
The output varies linearly with the input if the transistor is in active region. To make
the transistor work in this region the input junction is forward biased and the output
junction is reverse biased. In cutoff region the transistor acts as an open switch. The
currents flowing through the transistor are reverse saturation currents and are very
small and are negligible if the transistor is in cutoff region. To make the transistor
work in this region the input junction is reverse biased and the output junction is also
reverse biased. In saturation the transistor acts as a closed switch. To make the
transistor work in this region the input junction is forward biased and the output
junction is also forward biased.
The transistor can be connected in three configurations by using one of the
three terminals as common to both the input port and the output port. If the common
terminal is base then the transistor is said to be in common base or CB configuration.
Similarly, common emitter or CE configuration has emitter as common to both input
and output and common collector or CC or emitter follower has collector terminal and
common terminal to both the input and output ports. The common-emitter (CE)
configuration has the emitter as the common terminal, or ground, to an ac signal. CE
amplifiers exhibit high voltage gain and high current gain

25
 Summary of BJT Characteristics for different configurations

Configurations
Characteristics
Common Base Common Emitter Common Collector
Lo Me Hig
Input Impedance
w dium h
Ver Hig
Output Impedance Low
y High h
180
Phase Angle 0o o 0o
Hig Me
Voltage Gain Low
h dium
Lo Me Hig
Current Gain
w dium h
Lo Ver Med
Power Gain
w y High ium

The CB Configuration is only used in single stage amplifier circuits such as

microphone pre-amplifier or RF radio amplifiers due to its very good high frequency
response. The Emitter follower (CC) configuration is very useful for impedance
matching applications because of the very high input impedance and it has relatively
low output impedance.
The CE configuration is the most widely used configuration because it gives
both voltage and current gains. The input for the CE configuration is given between
base and the emitter and the output is taken between collector and emitter. This type
of configuration is mostly used in the applications of transistor based amplifiers. The
input current and voltage are designed as IB and VBE and the output current and
voltages are called IC and VCE respectively.
In this configuration the emitter current is equal to the sum of small base current and the
large collector current. i.e. IE  = IC + IB. We know that the ratio between collector current and
emitter current gives current gain and it is called alpha in Common Base configuration
similarly the ratio between collector current and base current gives the current gain and it is
called beta in common emitter configuration.
The input characteristics are obtained between input current IB and input
voltage VBE with constant output voltage VCE. The output characteristics are obtained
between the output current IC and output voltage VCE with constant input current IB.
Procedure:-

Output Characteristics:-

1. Connect the circuit diagram as per the Fig.1(a).

2. Keep VBB and VCC in zero volts before switching ON the supply.
3. Keep IB=100µA by varying VBB smoothly by fine control.
4. Now vary Vcc such that VCE is 0.5V and see that IB is still 100µA.
5. Note down the collector current Ic and tabulate in table-1.
6. Now vary Vcc such thet VCE =1V and note the resulting collector current Ic. See that
IB is still 100µA.

26
 7. Now repeat the above step for VCE in steps of 0.5V upto 7.5V and note down the
resulting Ic in the tabular form.
8. Now bring back VBB and Vcc to zero.
9. Set IB = 150µA by varying VBB smoothly with fine control and repeat the above steps
(1 to 7 keeping IB = 150µA constant)
10. Repeat the step 9 with IB = 200µA.
11. Draw the graph VCE Vs Ic against IB constant and find out hfe and hoe as in Fig1(b).

Input Characteristics:-

1. Keep VBB and Vcc in zero volts.

2. Set Vcc such that VCE =1.0V and keep it constant.
3. Now vary VBB smoothly such that VBE has its first value at IB=5µA.After that vary VBE
in steps of 0.02V and note down the resulting base current I B for each step in the
table-2. Continue upto a base current of 250µA.
4. Repeat the above step for VCE = 1.5V and 2.0V respectively.
5. Draw graph VBE Vs IB against VCE constant.
6. From the graphs calculate hie and hre as in Fig 1(c).

Tabular form:-

Table-1:-
Output Characteristics

IB= IB= IB=

S.No
VCE (V) IC (mA) VCE (V) IC (mA) VCE (V) IC (mA)
1
2
3
4
5
6
7

Table-2:-
Input Characteristics

VCE= VCE= VCE=

S.No
VBE (V) IB (µA) VBE (V) IB (µA) VBE (V) IB (µA)
1
2
3

27
 4

5
6

7
8
9

Model Graph:-

Input Characteristics:-

Fig 1(b)

Output Characteristics:-

28
 Fig 1(c)

Calculations:-

1. Calculation of hfe : - At some VCE value draw a vertical line on the output
characteristics in fig.2. Find IC2, IC1, IB1 and IB2. Then

(IC2-IC1) mA
hfe = ------------------- / VCE constant
(IB1- IB2) µA

2. Calculation of hoe: - Construct a triangle around the vertical line drawn above on
any of the output characteristics as shown in the fig.2. Find ΔVCE, ΔIC then

ΔIC
hoe = ----------- / IB constant
ΔVCE

29
 3. Calculation of hre :-Draw a horizontal line with some IB=constant value in
fig.2. Find out from the graph VBE2, VBE1, VCE2 and VCE1. Then

(VBE2- VBE1) V
hre = ------------------------- / IB constant
(VCE2- VCE1) V

4. Calculation of hie :- Construct a triangle around IB =constant line, on anyone of the

input characteristics. Then from the characteristics in fig.2 find out ΔVBE and ΔIB.
ΔVBE
hie= ---------- / VCE constant
ΔIB

Result:- hie = ,hre= , hfe= ,hoe=

Precautions:-

1. Keep the VBB and VCC in zero position for each step.
2. Test the continuity of the wires used before use.
3. All the contacts must be very tight and no loose connections must exist.
4. All input variations must be with fine control and all readings must be read
accurately.

Viva Questions:-

1. What is a transistor & Draw the symbol of a transistor. What does the arrow indicate?
2. What is term biasing means in case of transistor?
3. What are the various regions of operation of transistor & what are the regions in which the
transistor operates when it is used as a switch?
4. Why CE configuration is most common?
5. What is Beta?
6. What happens to leakage current with temperature in a transistor (silicon)?
7. Emitter resistance of a common emitter amplifier stabilizes the dc operating point against
variations in which parameter
8. Why h-parameters are specified for a transistor?

30
 Exp No : 3
Realization of gates using universal building blocks
(NAND Only)

31
Aim of the experiment: -To realize and verify the truth tables of AND, OR, NOT, NAND,
NOR and EX-OR gates using NAND gates (IC 7400).

Apparatus:-

S.No Apparatus/Component Range/ Number Quantity

1 Fixed DC power supply 5V 1 No
2 Dual DC regulated power supply (0-30)V 1 No
3 LED’s As Required
4 IC 7400 1 No
5 Bread Board 1 No

Circuit Diagram:-

AND GATE: - TRUTH TABLE:-

A B Y
0 0 0
0 1 0
1 0 0
1 1 1

Fig 1(a)

ORGATE: - TRUTH TABLE:-

A B Y
0 0 0
0 1 1
1 0 1
1 1 1

Fig 1(b)

NOTGATE: - TRUTH TABLE:-

A Y
0 1
1 0

Fig 1(c)

32
NAND GATE: - TRUTH TABLE:-

A B Y
0 0 1
0 1 1
1 0 1
1 1 0
Fig 1(d)

NORGATE: - TRUTH TABLE:-

A B Y
0 0 1
0 1 0
1 0 0
1 1 0

Fig 1(e)

EX-ORGATE: - TRUTH TABLE:-

A B Y
0 0 0
0 1 1
1 0 1
1 1 0

Fig 1(f)

33
Pin Diagram:-

Fig 1(g)

Theory:-

NAND stands for NOT AND. An AND gate followed by a NOT circuit makes it a
NAND gate. Figure below Shows the circuit symbol of a two-input NAND gate.

The truth table of a NAND gate is obtained from the truth table of an AND gate by
complementing the output entries. The output of a NAND gate is logic ‘0’ when all its
inputs are logic ‘1’. For all other input combinations, the output is logic ‘1’. NAND gate
operation is logically expressed as

NOR stands for NOT OR. An OR gate followed by a NOT circuit makes it a NOR
gate.Figure below Shows the circuit symbol of a two-input NOR gate.

The truth table of a NOR gate is obtained from the truth table of an OR gate by
complementing the output entries. The output of a NOR gate is a logic ‘1’ when all its
inputs are logic ‘0’. For all other input combinations, the output is logic ‘0’. The output of
a two-input NOR gate is logically expressed as

AND,OR and NOT gates are the three basic logic gates as they together can be used
to construct the logic circuit for any given Boolean expression. NOR and NAND gates
have the property that they individually can be used to hardware-implement a logic circuit

34
 corresponding to any given Boolean expression. That is, it is possible to use either only
NAND gates or only NOR gates to implement any Boolean expression. This is so because
a combination of NAND gates or a combination of NOR gates can be used to perform
functions of any of the basic logic gates. It is for this reason that NAND and NOR gates
are universal gates.

Procedure:-

1. Connect the OR gate using NAND gate as per the circuit diagram shown in Fig 1(a).
2. Apply +5V and GND of fixed dc power supply as Vcc and ground at pins 14 and 7 of
IC7400.
3. Apply 5 volts for logic ‘1’ level and 0 volts for logic ‘0’ level at the input terminals of
the gate.
4. Apply inputs to the gate from the DC regulated power supply as per the truth table.
5. Note down the outputs of the logic gate using LED for each combination of inputs.
6. Verify the observed values with corresponding values in the truth table.
7. Repeat steps 2, 3, 4 & 5 for all other logic gates.

Precautions:-

1. All the connections should be made properly.

2. It should be care that the values of the components of the circuit is does not exceed to
their ratings (maximum value).
3. Before the circuit connection it should be check out working condition of all the
Components.

Result:-
Different logic gates are constructed and their truth tables are verified

Viva Questions:-

1. What is the maximum no of out puts in a logic gate can have?

2. Whatdo u mean by level logic?
3. Give the truth table for EX-NOR (EX-OR+NOT) and realize using NAND gates.
4. Realize the logic function f = ABC + ABC + ABC using NAND gates?
5. Realize AOI gates by using NOR gate.
6. Why NAND and NOR gates are called as universal gates.
7. Write the expression for EX-OR operation and obtain
(i) The truth table
(ii) Realize this operation using AND, OR, NOT gates.
(iii) Realize this operation using only NOR gates.
8. Draw truth table, Boolean expression and implement it by using NAND gate for the
following:
(a) X is a 1 only if A is a 1 and B is a 1 or if A is 0 and B is a 0.

35
(b) X is a 0 if any of the three variables A, B and C are 1’s. X is a 1 for all other
conditions.

Exp No : 4
Design Of Code Converter

36
Aim of the experiment:-

To design the code converter which converts 4-bit binary to gray code.

Apparatus:-

S.No Apparatus/Component Range/ Number Quantity

1 Fixed DC power supply 5V 1 No
2 LED’s As Required
3 IC 7486 1 No
4 Bread Board 1 No

Circuit Diagram:-

Fig 1(a)

PinDiagram:-

Fig 1(b)

37
Theory:-

A code converter is a combinational logic circuit that changes data presented

in one type of binary code to another type of binary code. A general block diagram of
a code converter is shown in Fig 1(c).

Fig 1(c)

Design procedure

1. The block diagram of a 4-bit binary to gray code converter is shown in Fig 1(d). If has
four inputs (B3 B2 B1 B0) representing 4-bit binary numbers and four outputs (G 3 G2
G1 G0) representing 4-bit gray code.

Fig 1(d)

2. Truth table for binary to gray code converters is tabulated in Table-1.

3. From the truth table, the logic expressions for the gray code outputs can be written as
G3 = ∑ (8, 9, 10, 11, 12, 13, 14, 15)
G2 = ∑ (4, 5, 6, 7, 8, 9, 10, 11)
G1 = ∑ (2, 3, 4, 5, 10, 11, 12, 13)
G0 = ∑ (1, 2, 5, 6, 9, 10, 13, 14).
4. The above expressions can be simplified using K-map

Map for G3:

From the octet, we get
G 3 = B3

38
 Map for G2:
From the two quads, we get
G2 = B3' B2 + B3 B2'
= B3 B2.

Map for G1:

From the two quads, we get
G1 = B2 B1' + B2' B1
= B2 B1

Map for G0:

From the two quads, we get
G0 = B1'B0 + B1B0'
= B1 B0

5. Now the above expressions can be implemented using X-OR gates to yield the desired
code converter circuit shown in Fig 1(a).

Procedure:-

1. Connect the circuit diagram as shown in figure using IC7486.

2. Apply 5 volts for logic ‘1’ level and 0 volts for logic ‘0’ level at the input terminals of
the gate. Also apply +5V and GND of fixed dc power supply as Vcc and ground at
pins 14 and 7 of IC7486.
3. Apply inputs to the gate from the DC regulated power supply as per the truth table-1.
4. Note down the outputs of the logic gate using multimeter or LED for each
combination of inputs.
5. Verify the observed values with corresponding values in the truth table-1.

39
Truth table:-

Table-1
Binary Code (Input) Gray Code(Output)
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

Precautions:-

1. The open circuit voltage of the power supply must be exactly 5 volts.
2. Correct components should be connected on the breadboard with proper polarities.

Result:-

Binary to gray code converter designed and verified.

Viva Questions:-

1. What is the advantage of Gray code?

2. What is meant by distance in cyclic codes?
3. What is the Classification of the binary codes?
4. What is meant by error detecting and correcting codes?
5. Represent decimal digits from 0 to 9 by using Excess-3 code.
6. What is meant by Self complementing BCD codes?
7. What are the character codes?
8. Design the circuit which converts from ----------- code to --------- code.

40
 Exp No : 5
Realization of gates using discrete components

41
Aim of the experiment:-To realize and verify the truth tables of OR, AND, NOT, NAND
and NOR gates using the discrete components such as diodes and transistors.

Apparatus:-

S.No Apparatus/Component Range/ Number Quantity

1 Fixed DC power supply 5V 1 No
2 Transistors BC 107 1 No
3 Silicon diodes 1N4001 2
4 Resistors 220Ω 1 No
1KΩ 1 No
10KΩ 1 No
100KΩ 1 No
5 LED’s As Required
7 Bread Board 1 No

Circuit Diagram:-

OR GATE:- TRUTH TABLE :-

A B Y
0 0 0
0 1 1
1 0 1
1 1 1

Fig 1(a)
ANDGATE: - TRUTH TABLE :-

A B Y
0 0 0
0 1 0
1 0 0
1 1 1

42
 Fig 1(b)

NOTGATE: - TRUTH TABLE:-

A Y
0 1
1 0

Fig 1(c)

NANDGATE: - TRUTH TABLE:-

A B Y
0 0 1
0 1 1
1 0 1
1 1 0

Fig 1(d)
NOR GATE: - TRUTH TABLE:-

A B Y
0 0 1
0 1 0
1 0 0
1 1 0

43
 Fig 1(e)
Theory:-

AND GATE:-

An AND gate requires two or more inputs and produce only one output. The
AND gate produces an output of logic 1 state when each of the inputs are at logic 1
state and also produces an output of logic 0 state even if any of its inputs are at logic 0
state.
Discrete AND gates may be realized by using diodes or transistors. The inputs
represented as A and B may be either 0V or +5V correspondingly. The output is
represented by Y. In the diode of AND gate, when both the inputs are of same value,
A=+5V and B= +5V, then the diodes are in OFF condition. As a result, no current
flows through the resistor and there will not be any voltage drop across the resistor.
Here the output will be Y=+5V. Similarly, when both the inputs such as A and B are
equal to 0V, then the corresponding diodes such as either D1 or D2 or both the diodes
are at ON state and act as short circuits. Here the output will be Y corresponds to 0V.

OR GATE:-

Similar to AND gate, an OR gate may also have two or more inputs but
produce only one output. The OR gate produces an output of logic 1 state even if any
of its inputs is in logic 1 state and also produces an output of logic 0 state if any of its
inputs is in logic 0 state. OR gate is also called as any or all gate. It is also called as an
inclusive OR gate because it consists of the condition of ‘both the inputs can be
present’.  

Discrete OR gates may be realized by using diodes or transistors. The inputs

represented as A and B may be either 0V or +5V correspondingly. The output is
represented by Y. In the diode of OR gate, when both the inputs are of same value,
A=0V and B= 0V, then both the diodes are in OFF condition. As a result, no current
flows through the resistor and there will not be any voltage drop across the resistor.
Here the output will be Y=0V. Similarly, when both the inputs or either the inputs
such as A and B are equal to +5V, then the corresponding diodes either D1 or D2 or
both the diodes are at ON state and act as short circuits. Here the output will be Y
corresponds to +5V.

NOT GATE:-

The NOT gate is also called as an inverter, simply because it changes the input
to its opposite. The NOT gate is having only one input and one corresponding output.
It is a device whose output is always the compliment of the given input. That means,
the NOT gate produces an output of logic 1 state when the input is of logic 0 state and
also produce the output of logic 0 state when the input is of logic 1 state.
Discrete NOT gate may be realized by using transistors. The input represented
as A may be either 0V or +5V correspondingly. The output is represented by Y. When
the input A = 0V, then the transistor Q1 will be reverse biased and therefore it
remains OFF. As a result no current flows through the resistor and thereby there will

44
 not be any voltage drop across the resistor. As a result, the output voltage Y
corresponds to +5V. When the input A= +5V, transistor Q1 is ON and the output
voltage Y=Vce(sat) corresponds to 0V. 

NAND GATE:-

NAND gate is a combination of an AND gate and a NOT gate.The output of

the NAND gate is at logic 0 level only when each of the inputs assumes a logic 1
level. The NAND and NOR are also called as universal building blocks. Both NAND
and NOR has the ability to perform three basic logic functions such as AND, OR and
NOT.
Discrete NAND gates may be realized by using diodes and transistors. The
two inputs are represented by A and B. The output is represented by Y.  When the
input A and B= +5V, then both the diodes D1 and D2 are OFF. The transistor Q1 gets
enough base drive from the supply through resistor and therefore transistor Q1 is ON
and the output Y=Vce(sat) corresponds to 0V. Similarly when inputs either A=0V or
B=0V or when both inputs are equal to 0V, at that time the transistor Q1 is OFF and
therefore, output voltage Y= +5V.

NOR GATE:-

NOR gate is a combination of an OR gate and a NOT gate. The output is logic
1 level, only when each of its inputs assumes a logic 0 level. For any other
combination of inputs, the output is a logic 0 level. 

Discrete NOR gates may be realized by using diodes and transistors.The two
inputs are represented by A and B. The output is represented by Y.  When the input A
and B= 0V, then both the diodes D1 and D2 are OFF. Hence the transistor Q1 will be
reverse biased and therefore it remains OFF. As a result no current flows through the
resistor and thereby there will not be any voltage drop across the resistor. As a result,
the output voltage Y corresponds to +5V. When one of the input is equal to +5V,then
one diode is ON, Hencethe transistor Q1 is ON. As a result, the output voltage Y
corresponds to +0V.

Procedure:-

1. Connect the OR gate as per the circuit diagram shown in figure.

2. Apply 5 volts for logic ‘1’ level and 0 volts for logic ‘0’ level.
3. Apply inputs to the gate from the +5V DC regulated power supply as per the
corresponding truth table.
4. Note down the outputs of the logic gate using LED for each combination of inputs.
5. Verify the observed values with corresponding values in the truth table.
6. Repeat steps 2, 3, 4 & 5 for all other logic gates.

Precautions:-

45
 4. All the connections should be made properly.
5. It should be care that the values of the components of the circuit is does not exceed to
their ratings (maximum value).
6. Before the circuit connection it should be check out working condition of all the
Component.

Result :-
Different logic gates are constructed and their truth tables are verified

Viva Questions:-

1. Define the term ‘Digital Circuits’ and ‘Logic Family’.

2. What is a truth table?
3. What is a positive logic system and negative logic system?
4. Write the function of diode and transistor in gates?
5. What is meant by integrated circuit (IC) and ‘chip’?
6. What is CMOS? Why its use in digital circuit is advantageous?
7. Classify the logic families on the basis of polarity of charge carriers used for current
conduction
8. Define FAN IN and FAN OUT of a logic gate.

46
 Exp No : 6
Characteristics of Junction Field Effect Transistor

47
Aim of the experiment:-

To conduct an experiment on a given JFET and obtain its

(i) Drain characteristics and
(ii) Transfer characteristics. Find rd, gm and µ from the characteristics.

Apparatus:-

S.No Apparatus/Component Range/ Number Quantity

1 DC Regulated Power Supply(RPS) (0-30)V 1 No

2 JFET BFW 10 or 11 1 No

3 DC Ammeter (0-25) mA 1 No

4 Multimeter 1 No

5 Bread Board 1 No

Circuit Diagram:-

Theory:-

48
 A bipolar junction transistor (BJT) is a current controlled device i.e., output
characteristics of the device are controlled by base current and not by base voltage.
However, in a field effect transistor (FET), the output characteristics are controlled by
input voltage (i.e., electric field) and not by input current. This is probably the biggest
difference between BJT and FET.
There are two basic types of field effect transistors:
(i) Junction field effect transistor (JFET)
(ii) Metal oxide semiconductor field effect transistor (MOSFET)

The two pn junctions at the sides form two depletion layers. The current conduction
by charge carriers (i.e. free electrons in this case) is through the channel between the two
depletion layers and out of the drain. The width and hence *resistance of this channel can
be controlled by changing the input voltage VGS. The greater the reverse voltage VGS, the
wider will be the depletion layers and narrower will be the conducting channel. The
narrower channel means greater resistance and hence source to drain current decreases.
Reverse will happen should VGS decrease. Thus JFET operates on the principle that width
and hence resistance of the conducting channel can be varied by changing the reverse
voltage VGS. In other words, the magnitude of drain current (I D) can be changed by
altering VGS.

Working:-

(i) When a voltage VDS is applied between drain and source terminals and voltage on the
gate is zero, the two pn junctions at the sides of the bar establish depletion layers. The
electrons will flow from source to drain through a channel between the depletion layers.
The size of these layers determines the width of the channel and hence the current
conduction through the bar.
(ii) When a reverse voltage VGS is applied between the gate and source, the width of the
depletion layers is increased. This reduces the width of conducting channel, thereby
increasing the resistance of n-type bar. Consequently, the current from source to drain is
decreased. On the other hand, if the reverse voltage on the gate is decreased, the width of
the depletion layers also decreases. This increases the width of the conducting channel
and hence source to drain current.

It is clear from the above discussion that current from source to drain can be
controlled by the application of potential (i.e. electric field) on the gate. For this reason,
the device is called field effect transistor. It may be noted that a p-channel JFET operates
in the same manner as an n -channel JFET except that channel current carriers will be the
holes instead of electrons and the polarities of VGS and VDS are reversed.

 Drain dynamic resistance rd = (ΔVDS/ ΔID) with VGS = constant

 Mutual Conductance gm = (ΔID/ ΔVGS) with VDS = constant
 Amplification μ = (ΔVDS/ΔVGS) with ID = constant

These parameters are related by equation μ = rd x gm

Procedure:-

Drain Characteristics:-
49
 1. Connect the circuit diagram as per fig.1.
2. Start with VGG and VDD keeping at zero volts.
3. Keep VGG such that VGS=0V
4. Now vary VDD such that VDS varies in steps of 1V upto 10V and note down the
corresponding drain current ID and tabulate in table-1.
5. Repeat the above experiment with VGS = -1V and -2V and tabulate the readings.
6. Draw a graph VDS Vs ID against VGS as parameter on a graph as in fig.2.
7. From the graph calculate rd.

Transfer Characteristics:-

1. Set VGG and VDD at zero volts.

2. keep VDS = 1V
3. Vary VGG such that VGS =0V in first step and note down ID value. Now vary VGS in
steps of 0.5V and note down the corresponding drain current ID and tabulate the
readings. Finally note down the value of VGS at which ID =0
4. Repeat the above experiment for VDS =3V and 5V and tabulate the readings in table-2
5. Draw graph between VGS Vs ID as VDS parameter as in graph fig.3
6. From the graph find gm
7. Now µ=gm x rd.

Tabular forms:-

Table-1:-
Drain Characteristics

VGS= VGS=
VGS=
S.No VDS (V)
ID(mA) ID(mA)
ID(mA)
1

50
 7

10

Table-2:-
Transfer Characteristics

VGS= VGS= VGS=

S.No -VGS (V)
ID(mA) ID(mA) ID(mA)
1
2
3
4
5
6
7
8
9
10
11
12

Model Graphs:-
Drain Characteristics:-

51
Transfer Characteristics:-

Calculations:-

1. Calculation of rd:-

Construct a triangle on one of the drain characteristics for a particular VGS in the active
region. Find ΔVDS and ΔID, then

52
 ΔVDS
rd = ------------ / VGS=constant
ΔID

2. Calculation of gm:-
Construct a triangle on one of the transfer characteristics for a particular VDS.
Find ΔVGS and ΔID then
ΔID
gm = ---------- / VDS=constant
ΔVGS

3. Calculation of µ:-

Now µ = gm x rd

Results:-

1. Drain resistance (rd) =

2. Transfer conductance (gm) =
3. Gain factor : (µ) =

Precautions:-

1. Test the continuity of the wires used before use.

2. All the contacts must be very tight and no loose connections must exist.
3. All readings must be accurately noted.
4. For a good JFET ID will be 7 to 11mA at VGS=0V. If not change the JFET.

Viva Questions:-

1. What are the advantages of FET over BJT?

2. Why input resistance in MOSFET amplifiers is more than FET amplifiers?
3. What is uni polar device?
4. What is pinch-off voltage?

53
5. What are the applications of FET’s?
6. What is (i) Enhancement mode and (ii) Depletion mode?
7. Draw the symbol of JFET?
8. Write the equation of FET ID in terms of VGS and VP.

Exp No : 7
Characteristics of Uni-Junction Transistor

54
Aim of the experiment:-
To conduct an experiment on a given UJT and find its input negative
resistance characteristics. Also, find its intrinsic stand-off ratio.

Apparatus:-

S.No Apparatus/Component Range/ Number Quantity

1 DC Regulated Power Supply(RPS) (0-30)V 1 No
2 UJT 2N2646 1 No

3 Resistors 1KΩ, 100Ω 1 No each

4 DC Ammeter (0-25) mA 1 No

5 Multimeter 1 No

6 Bread Board 1 No

Circuit Diagram:-

55
 Fig 1(a)
Theory:-

A unijunction transistor (abbreviated as UJT) is a three-terminal

semiconductor switching device. This device has a unique characteristic that when it
is triggered, the emitter current increases regenerative until it is limited by emitter
power supply. Due to this characteristic, the unijunction transistor can be employed in
a variety of applications e.g., switching, pulse generator, saw-tooth generator etc.

Operation:
The device has normally B2 positive w.r.t. B1.
(i) If voltage VBB is applied between B2 and B1 with emitter open , a voltage gradient is
established along the n-type bar. Since the emitter is located nearer to B2, more than half
of VBB appears between the emitter and B1. The voltage V1 between emitter and B1
establishes a reverse bias on the pn junction and the emitter current is cut off. Of course,
a small leakage current flows from B2 to emitter due to minority carriers.

(ii) If a positive voltage is applied at the emitter, the pn junction will remain reverse biased
so long as the input voltage is less than V1. If the input voltage to the emitter exceeds
V1, the pn junction becomes forward biased. Under these conditions, holes are injected
from p-type material into the n-type bar. These holes are repelled by positive B2 terminal
and they are attracted towards B1 terminal of the bar. This accumulation of holes in the
emitter to B1 region results in the decrease of resistance in this section of the bar. The
result is that internal voltage drop from emitter to B1 is decreased and hence the emitter
current IE increases. As more holes are injected, a condition of saturation will eventually
be reached. At this point, the emitter current is limited by emitter power supply only. The
device is now in the ON state.

(iii)If a negative pulse is applied to the emitter, the pn junction is reverse biased and the
emitter current is cut off. The device is then said to be in the OFF state.

Characteristics of UJT:

Fig 1(b). shows the curve between emitter voltage (VE) and emitter current (IE ) of a UJT at a
given voltage VBB between the bases. This is known as the emitter characteristic of UJT. The
following points may be noted from the characteristics:

56
(i) Initially, in the cut-off region, as VE increases from zero, slight leakage current flows
fromterminal B2 to the emitter. This current is due to the minority carriers in the reverse
biased diode.
(ii) Above a certain value of VE,forward IE begins to flow, increasing until the peak voltage
VP and current IP are reached at point P.
(iii)After the peak point P, an attempt to increase VE is followed by a sudden increase in
emitter current IE with a corresponding decrease in VE. This is a negative resistance
portion of the curve because with increase in IE, VE decreases. The device, therefore,
has a negative resistance region which is stable enough to be used with a great deal of
reliability in many areas e.g., trigger circuits, sawtooth generators, timing circuits .
(iv) The negative portion of the curve lasts until the valley point V is reached with valley-
point voltage VV and valley-point current IV. After the valley point the device is driven
to saturation

Fig 1(b)

Procedure:-

1. Connect the circuit diagram as per Fig.1(a).

2. Keep VEE and VB at zero before start.
3. Adjust VB such that VBB is equal to zero volts.
4. Vary VEE slowly such that VE varies in steps of 0.1V. Note down corresponding IE
against each voltage in table-1. Conduct the experiment until the ammeter current IE is
20mA.
5. Now start again with VEE and VB equal to zero volts.
6. Adjust VB such that VBB is 5V and keep it constant.
7. Now vary VEE slowly. No emitter current will be there until a peak value of 3 to 4 V
of VE. After VE reaching a peak value, it suddenly drops consequent to conduction of
emitter current IE.
8. Note down very accurately the peak value of VE
9. Now vary VEE for various values of IE in proper steps upto an emitter current of 20mA
(10 readings) and note down the corresponding VE. Tabulate the readings in table-1.
10. Now adjust VB such that VBB=10V and repeat steps 7 to 9. Now the peak value of VE
will be around 6 to 7V. Tabulate the readings very accurately in the table-1.
11. Draw a graph VE Vs IE against VBB as parameter as in fig.2.
57
 12. Compute the intrinsic stand-off ratio from the formula.

Vp - VD
η = ----------------
VBB

When VD=0.6V, Vp is the peak value to VE for a particular VBB.

Tabular forms:-

Table-1:-

VBB = VBB = VBB =

S.No
VE(V) IE(mA) VE(V) IE(mA) VE(V) IE(mA)
1

58
 7

10

11

12

13

Model Graph:-

59
 Fig 1(c)

Results:-

Intrinsic Stand-off ratio = η =

Precautions:-

1. Test the continuity of the wires used before use.

2. All the contacts must be very tight and no loose connections must exist.
3. All readings must be accurately read.

Viva Questions:-

1. Expand UJT?
2. Write the features of UJT?
3. What is negative resistance?
4. Draw the characteristic of UJT and mark the negative resistance region?
5. What are the applications of UJT?
6. What is the difference between BJT and UJT?
7. Define Intrinsic Stand-off ratio?
8. What is the difference between UJT and FET?

60
 Exp No : 8
Study of full wave bridge rectifier with and
without filters.

Aim of the experiment:-

a) To examine the input and output waveforms of Full Wave Bridge Rectifier with and
without Filter. Also calculate the ripple factor, Efficiency, Regulation and Peak inverse
voltage.

Apparatus:-

S.No Apparatus/Component Range/ Number Quantity

1 Transformer (0-12)V 1 No
2 Silicon diode IN4001 4 No’s
3 Capacitor 10μf/4.7μf 1 No
4 Resistance 1KΩ 1 No

61
 5 CRO 1No

7 Multimeter 1 No
8 Bread Board 1 No

Circuit Diagram:-

Theory :-

The circuit of a center-tapped full wave rectifier uses two diodes

D1&D2.During positive half cycle of secondary voltage (input voltage), the diode D1
is forward biased and D2is reverse biased. So the diode D1 conducts and current
flows through load resistor RL.
During negative half cycle, diode D2 becomes forward biased and D1 reverse
biased. Now, D2 conducts and current flows through the load resistor R L in the same
direction. There is a continuous current flow through the load resistor R L, during both
the half cycles and will get unidirectional current as show in the model graph. The
difference between full wave and half wave rectification is that a full wave rectifier
allows unidirectional (one way) current to the load during the entire 360 degrees of
the input signal and half-wave rectifier allows this only during one half cycle (180
degree).
Procedure:-
1) Connect the circuit as per the circuit diagram without capacitor filter.
2) Connect CRO across the input terminals & load terminals.
3) Note down the peak to peak value Vp-p of the signal observed on the CRO.
4) Measure both ac and dc voltages at the output side the rectifier by using DMM.
5) Find the theoretical value of the dc voltage by using the formula Vdc=2Vm/П.
6) Calculate the ripple factor, Efficiency, Regulation & Peak Inverse Voltage.
7) Repeat step-2 to step-5 by placing the capacitor filter across the load.

Tabular forms:-

Input Wave Output Waveform

62
 form Without Filter With Filter (C= )
Amplitude(Vp-p)

Time Period(T Sec)

Frequency(Hz)

AC Voltage (VAC) DC Voltage (VDC)

With out Filter

With Filter (C= )

Model Graph:-

Theoretical Calculations:-

Without Filter:-

1) VM=Vp-p/2

2V M
2) The DC Voltage: VDC=
π

63
 VM
3) The root mean square value of output: VRMS=
√2

√
2
V ( RMS )
4) The ripple Factor: γ = −1
Vo( DC )2

5) Regulation %R= ( V NLM −V M

VM )
∗100.

Po (dc)
6) % Efficiency(η): η¿ *100
Pi ( ac )

Where Pi(ac) = VRMS2 /RL & Po(dc) = VDC2 /RL

7) Peak Inverse Voltage (PIV) =VM .

With Filter:-

V P− P
1) The DC Voltage: VDC=VM –
2

64
 V P− P
2) The root mean square value of output: VRMS=
2√3

1
3) Ripple Factor= 4 √ 3 fCR (Theoritical) Where f=50Hz,R=1KΩ,C= ------µF.

√
2
V ( RMS )
Ripple Factor: γ = 2
−1 (Practical)
Vo(DC )

4) Regulation %R= ( V NLM −V M

VM )
∗100.

Po (dc)
5) % Efficiency(η): η¿ *100
Pi ( ac )

Where Pi(ac) = Vrms2 /RL & Po(dc) = Vdc2 /RL

6) Peak Inverse Voltage (PIV) =Vm

Precautions:-

1) While doing the experiment do not exceed the ratings of the diode. This may lead to
damage the diode.
2) Connect CRO using probes properly as shown in the circuit diagram.

65
3) Do not switch ON the power supply unless you have checked the circuit connections as per
the circuit diagram.

Result:-

The rectified output voltage of full wave bridge rectifier with and without capacitor filter is
observed.

Ripple factor (Without Filter) :

Ripple factor (With Filter) :
Efficiency (Without Filter) :
Efficiency (With Filter) :
Regulation (Without Filter) :
Regulation (With Filter) :
Peak Inverse Voltage :

Viva Questions:-

1. What is the purpose of a rectifier?

2. Why filter is used in a rectifier?
3. What are the advantages of half wave rectifier?
4. Define Ripple factor and Efficiency. State the ideal values.
5. Define PIV. Give the PIV of Half wave rectifier.
6. What is the PIV of a diode full wave bridge rectifier circuit?
7. What is the purpose of a filter in dc power supply?
8. What is TUF? Give the TUF of half wave, full wave-center tapped and bridge rectifier.

66
 Exp No : 9
Design of Combinational Logic Circuits

Aim of the experiment:-

To realize the following combinational circuits using NAND gate(IC 7400) &
EX-OR gate(IC 7486) and verify their truth tables.
(i) Half adder (ii) Half Subtractor (iii) Full adder (iv) Full Subtractor

67
 Apparatus:-

S.No Apparatus/Component Range/ Number Quantity

1 Fixed DC power supply 5V 1 No
2 LED’s As Required
7486 1 No
3 IC
7400 1 No
4 Bread Board 1 No

Circuit Diagram:-

Half Adder:-

Fig1(a)

Half Subtractor:-

Fig1(b)

Full Adder:-

68
 Fig1(c)

Full Subtractor:-

Fig1(d)

Pin Configuration:-

IC7400(NAND GATE)

IC7486(EX-OR GATE)

69
Theory:-
In combinational circuits, the outputs at any instant of time depend upon the outputs
present at that instant of time. This means that there is no memory in these circuits .The
various combinational circuits are half adder, full adder, half subtractor, full subtractor etc.
The block diagram of a combinational circuit with m inputs and n outputs is shown in
Fig.2.

Fig 2

Combinational circuit Design Procedure

It involves following steps:
Step 1: From the word description of the problem, identify the inputs and outputs and draw a
block diagram.
Step 2: Make a truth table based on problem statement which completely describes the
operations of circuit for different combinations of inputs.
Step 3: Simplified output functions are obtained by algebraic manipulation, k-map method or
tabular method.
Step 4: Implement the simplified expression using logic gates

Adders

70
Half Adder:
The most common arithmetic operation in digital systems is the addition of two binary digits.
The combinational circuit that performs this operation is called a half-adder. It has two
inputs A and B. that are two 1-bit members, and two output SUM (S) and CARRY (C)
produced by addition of two bits. The Circuit diagram of Half Adder is shown in Fig1 (a).The
truth table of Half Adder is shown in table-1. The sum output is 1 when any of inputs (A and
B) is 1 and the carry output is 1 when both the inputs are 1.
Full Adder:
Full adder is a combinational circuit that performs the addition of three binary digits. A half
adder has only two inputs and there is no provision to add to a carry coming from the lower
bits when a multi bit addition is performed. For this purpose a third input terminal is added
and this circuit is used to add An, Bn and Cn-1, where An and Bn are the nth order bits of the
numbers A and B respectively and Cn-1 is the carry generated from the addition of (n-1)th
order bits. This circuit ie referred to as full adder and it is shown in Fig 1(c).The truth table of
Full Adder is shown in table-3.

Subtractors
Half Subtractor:
The half subtractor is a combinational circuit which is used to perform the subtraction of two
bits. It has two inputs, A (minuend) and B (subtrahend) and two outputs DIFFERENCE (D)
and BORROW (B0). [The symbol for borrow (B0) is taken to avoid confusion with input
variable B] produced by subtractor of two bits. The Circuit diagram of Half Subtractor is
shown in Fig1 (b).The truth table of Half Subtractor is shown in table-2.The difference output
is 0 if A = B and 1 if A ≠ B; the borrow output is 1 whenever A < B. If A < B, the subtraction
is done by borrowing 1 from the next higher order bit.
Full subtractor:
Full subtractor is a combinational circuit that performs the subtraction of three binary digits.
Full subtractor is a circuit for performing multi bit subtraction where a borrow from the
previous bit position may also be there. A full subtractor will have these inputs A n(minuend),
Bn(subtrahend) and Cn-1(borrow from the previous stage) and two outputs D n(difference) and
Cn(Borrow). The Circuit diagram of Full Subtractor is shown in Fig1 (d).The truth table of
Full Subtractor is shown in table-4.

Procedure:-

71
 1. Connect the half adder as per the circuit diagram shown in figure.
2. Apply 5 volts for logic ‘1’ level and 0 volts for logic ‘0’ level at the input terminals of
the gate. Also apply +5V and GND of fixed dc power supply as Vcc and ground at
pins 14 and 7 of IC 7400 and IC 7486.
3. Apply inputs to the gate from the DC regulated power supply as per the truth table-I
4. Note down the outputs of the logic gate using multimeter or LED for each
combination of inputs.
5. Verify the observed values with corresponding values in the truth table-1.
6. Repeat steps 2, 3, 4 & 5 for half subtractor, full adder and full subtractor.

Truth Tables:-

Table-1 Table-2

1. Half Adder:- 2.Half Subtractor:-

A B Difference (D) Borrow (B0)

A B Sum (S) Carry (C) 0 0 0 0
0 0 0 0 0 1 1 1
0 1 1 0 1 0 1 0
1 0 1 0 1 1 0 0
1 1 0 1

S=⊕ and C=AB D=⊕ and B=A’B’

Table-3

3. Full Adder:-

Sum Carry
A B C
(S) (C0)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

S=(⊕⊕C and C=AB+C(A⊕B)

72
Table-4

4. Full Subtractor:-

Difference Borrow
A B C
(D) (B0)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

D= (⊕⊕C and B= A’B+ (A’+B) C

Result:-

Truth tables of all the above combinational circuits are verified.

Precautions:-

1. The open circuit voltage of the power supply must be exactly 5 volts.
2. Correct components should be connected on the breadboard with proper polarities.

Viva Quaetions:-

1. What is meant by Combinational circuit?

2. What is the difference between carry and borrow?
3. Give the design procedures for the designing of a combinational circuit.
4. Define half adder.
5. Define binary adder.
6. What are the Applications of Full adder and Full subtractor?
7. Draw the half adder and full adder circuits using AND, OR, EX_OR gates.
8. Define full subtractor.

73
 Exp No : 10
Verification of Truth Tables of Flip-Flops using
Gates

74
Aim of the experiment:-
To study the operation of SR, JK, D and J flip-flops and to verify the truth tables
using gates.

Apparatus:-

S.No Apparatus/Component Range/ Number Quantity

1 Fixed DC power supply 5V 1 No
2 LED’s As Required
3 IC 7404,7400,7410 1 No
4 Bread Board 1 No

Circuit Diagram:-

SR Flip Flop :-

Fig1 (a) Fig1 (b)

JK Flip Flop :-

Fig1(c) Fig1(d)

75
D Flip Flop :-

Fig1(e) Fig1(f)

T Flip Flop :-

Fig1(g) Fig1(h)

PinDiagram:-

IC7404(NOT GATE)

76
 Fig1(i)

IC7410 (3- Input NAND GATE)

Fig1(j)

IC7400 (2- Input NAND GATE)

Fig1(k)
Theory:-

Latches and flip-flops are the basic elements for storing information. One latch
or flip-flop can store one bit of information. The main difference between latches and
flip-flops is that for latches, their outputs are constantly affected by their inputs as
long as the enable signal is asserted. In other words, when they are enabled, their
content changes immediately when their inputs change. Flip-flops, on the other hand,
have their content change only either at the rising or falling edge of the enable signal.
This enable signal is usually the controlling clock signal. After the rising or falling
edge of the clock, the flip-flop content remains constant even if the input changes.

77
 There are basically four main types of latches and flip-flops: SR, D, JK, and T.
the major differences in these flip-flop types are the number of inputs they have and
how they change state. For each type, there are also different variations that enhance
their operations.

S-R Flip Flop

It is basically S-R latch using NAND gates with an additional enable input. It
is also called as level triggered SR-FF. For this, circuit in output will take place if and
only if the enable input (E) is made active. In short this circuit will operate as an S-R
latch if E = 1 but there is no change in the output if E = 0.The Circuit Diagram &
Block Diagram is shown in Fig1 (a) & 1(b) respectively. The Truth Table is shown in
Truth table-1.
Below Table summarizes the operation of SR flip-flop for all types of input possibilities.
S.No Condition Operation
1 CLK = 0 Latch is disabled. Hence no change in output.
2 S=R=0 If S = R = 0 then output of NAND gates 3 and 4 are forced
(No change State) to become 1.Hence R' and S' both will be equal to 1. Since S'
and R' are the input of the basic S-R latch using NAND
gates, there will be no change in the state of outputs.
3 S = 0, R = 1 Since S = 0, output of NAND-3 i.e. R' = 1 and E = 1 the
(RESET State) output of NAND-4 i.e. S' = 0.Hence Q n+1 = 0 and Qn+1 bar =
1. This is reset condition.
4 S = 1, R = 0 Output of NAND-3 i.e. R' = 0 and output of NAND-4 i.e. S'
(SET State) = 1.Hence output of S-R NAND latch is Qn+1 = 1 and
Qn+1 bar = 0. This is the reset condition.
5 S = 1, R = 1 As S = 1, R = 1 and E = 1, the output of NAND gates 3 and
(Invalid State) 4 both are 0 i.e. S' = R' = 0.Hence the Race condition will
occur in the basic NAND latch.

JK Flip Flop
Problem of SR flip-flop to lead to indeterminate state when S = R = 1, is
eliminated in JK flip-flops. In JK the indeterminate state of SR flip-flop is now
modified and is defined as TOGGLED STATE (i.e. its own complement state) when
both the inputs are HIGH i.e. 1. The Circuit Diagram & Block Diagram is shown in
Fig1 (c) & 1(d) respectively. The Truth Table is shown in Truth table-3.
Below Table summarizes the operation of JK flip-flop for all types of input possibilities.
S.No Condition Operation
1 CLK = 0 Latch is disabled. Hence no change in output.
2 J=K=0 When both J and K are 0, the clock pulse has no effect on the
(No change State) output and the output of the flip-flop is the same as
its previous value. This is because when both the J and K are
0, the output of their respective NAND gates are 0.
3 J=0 & K=1 When J=0, the output of the NAND gate corresponding to J
(RESET State) becomes 0 (i.e.) S=0 and R=1. Therefore Q’ becomes 1. This
condition will reset the flip-flop. This represents the RESET
state of Flip-flop
4 J= 1 & K=0 When J=1 and K=0, the NAND gate corresponding to K
(SET State) becomes 0 (i.e.) S=1 and R=0. Therefore Q becomes 1. This
condition will set the Flip-flop. This represents the SET state

78
 of Flip-flop.
5 J=K=1 When J=K=1, the output to complement again and again. This
(Toggle State) complement operation continues until the Clock pulse goes
back to 0. Since this condition is undesirable, we have to find
a way to eliminate this condition. This undesirable behavior
can be eliminated by Edge triggering of JK flip-flop or by
using master slave JK Flip-flops.

D Flip Flop

The SR flip-flop has two inputs S and R. At any time to store a bit, we must
activate both the inputs simultaneously. This may be troubling in some applications.
Use of only one data line is convenient in such applications. Moreover the forbidden
input combination S = R =1 may occur unintentionally, thus leading the flip-flop to
indeterminate state.
In order to deal such issues, SR flip-flop is further modified as shown in Fig.
The resultant flip-flop is referred as D flip-flop. The D flip-flop has only one input
labelled D (called as Data input). An external NOT (inverter) gate is used to ensure
that S and R inputs are always complement to each other. Thus to store information in
this flip-flop, only one signal has to be generated. The Circuit Diagram & Block
Diagram is shown in Fig1 (e) & 1(f) respectively. The Truth Table is shown in Truth
table-2.

Below Table summarizes the operation of D flip-flop for all types of input possibilities.
S.No Condition Operation
1 CLK = 0 Latch is disabled. Hence no change in output.
2 CLK = 1 and D = 0 If D = 0 then S = 0 and R = 1. Hence irrespective of the
present state, the next state is Qn+1 = 0 and Qn+1’ = 1. This is
the reset condition.
3 CLK = 1 and D = 1 If D = 1, then S = 1 and R = 0. This will set the latch and
Qn+1 = 1 and Qn+1’= 0 irrespective of the present state.
Toggle Flip Flop / T Flip Flop
Toggle flip flop is basically a JK flip flop with J and K terminals permanently
connected together. It has only input denoted by T as shown in the Symbol Diagram.
The Circuit Diagram & Block Diagram is shown in Fig1 (g) & 1(h) respectively. The
Truth Table is shown in Truth table-4.
Below Table summarizes the operation of T flip-flop for all types of input possibilities.
S.No Condition Operation
1 CLK = 0 Latch is disabled. Hence no change in output.
2 CLK = 1 and T=0 If T = 0 then J = K = 0.The output Q and Q’ won't change
3 CLK = 1 and T = 1 If T = 1 then J = K = 1.Output will toggle corresponding to
every leading edge of clock signal.

Procedure:-

(a) SR Flip Flop:-

1. Connect the circuit as shown in fig.1

2. Apply 5 volts supply between 7 and 14 pins (Vcc and ground) of IC
3. Apply 5 Volts for logic 1 and 0 volts for logic 0 level.
79
 4. Apply clock using pulse generator.
5. Verify the working of SR Flip Flop as per truth table-1.

(b) D Flip Flop:-

1. Connect a NOT gate between S and R inputs as shown in fig.2(use 7404 IC to

obtain not gate and give supply to 7404 IC also)
2. Apply 5 volts supply between 7 and 14 pins (Vcc and ground) of IC
3. Apply 5 Volts for logic 1 and 0 volts for logic 0 level.
4. Apply clock using pulse generator.
5. Verify the working of D Flip Flop as per truth table-2.
(c) JK Flip Flop:-

1. Connect the circuit as shown in fig.3

2. Apply 5 volts supply between 7 and 14 pins (Vcc and ground) of IC
3. Apply 5 Volts for logic 1 and 0 volts for logic 0 level.
4. Apply clock using pulse generator.
5. Verify the working of JK Flip Flop as per truth table-3.
(d) T Flip Flop:-

1. Short the J and K inputs (to obtain T input) as shown in fig.4

2. Apply 5 volts supply between 7 and 14 pins (Vcc and ground) of IC
3. Apply 5 Volts for logic 1 and 0 volts for logic 0 level.
4. Apply clock using pulse generator.
5. Verify the working of T Flip Flop as per truth table-4.

Truth tables:-
Truthtable-1:-
Inputs Outputs
CLK S R Qn+1 (Qn+1)’
L X X Qn Qn’
H L L Qn Qn’
H L H L H
H H L H L
H H H * *
Truthtable-2:-

Inputs Outputs
CLK D Qn+1 (Qn+1)’
L X Qn Qn’
H L L H
H H H L
Truthtable-3:-
Inputs Outputs
CLK J K Qn+1 (Qn+1)’
L X X Qn Qn’
H L L Qn Qn’

80
 H L H L H
H H L H L
H H H Qn’ Qn
Truthtable-4:-
Inputs Outputs
CLK T Qn+1 (Qn+1)’
L X Qn Qn’
H L Qn Qn’
H H Qn’ Qn
Result:-

Truth tables of all flip-flops circuits are verified.

Precautions:-

1. Correct IC’s should be placed on the breadboard using pin diagram.

2. The open circuit voltage of the power supply should be exactly 5 volts.

Viva Questions:-

1. What is meant by race around condition?

2. What are the applications of JK and T flip-flops?
3. Define Flip Flop
4. Define Rise Time and Fall Time.
5. Define Propagation Delay.
6. List various types of flip flops.
7. What do you mean by present state?
8. What do you mean by Next state?

81