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Mechatronics Lab Manual - (01!10!2020)

The document contains 11 experiments related to designing and simulating basic logic gates and combination circuits. Each experiment includes a Boolean expression, truth table, and circuit diagram for logic gates like NOT, OR, AND, NOR, NAND, XOR and XNOR. Experiments 8 and 9 cover Demorgan's theorems. Experiments 10 and 11 describe combination circuits with 4 inputs and 1 output, combining logic gates using '+' and '.' operators. The document appears to be a laboratory manual for a Mechatronics course.

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Shreyas Huilgol
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140 views24 pages

Mechatronics Lab Manual - (01!10!2020)

The document contains 11 experiments related to designing and simulating basic logic gates and combination circuits. Each experiment includes a Boolean expression, truth table, and circuit diagram for logic gates like NOT, OR, AND, NOR, NAND, XOR and XNOR. Experiments 8 and 9 cover Demorgan's theorems. Experiments 10 and 11 describe combination circuits with 4 inputs and 1 output, combining logic gates using '+' and '.' operators. The document appears to be a laboratory manual for a Mechatronics course.

Uploaded by

Shreyas Huilgol
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 24

K.L.E’S. SMT.C.I.

MUNAVALLI POLYTECHNIC, VIDYANAGAR, HUBLI-31


MECHANICAL ENGINEERING DEPARTMENT

MECHATRONICS LABORATORY MANUAL

SEMESTER: V

STAFF INCHARGE:

1. SHRI.SHIVAKUMAR YARASHI—B.E.,

PREPARED BY:

1. SHRI.SHIVAKUMAR YARASHI—B.E.,

Page | 1
MECHATRONICS LABORATORY
K.L.E’S. SMT.C.I.MUNAVALLI POLYTECHNIC, VIDYANAGAR, HUBLI-31
MECHANICAL ENGINEERING DEPARTMENT
EXPERIMENT 1:- Design and Simulate NOT GATE with Truth Table and Circuit
Diagram is having 1 input and 1 output.

NOT GATE

_
1. BOOLEAN EXPRESSION: Y=A

2. TRUTH TABLE: Input Output


_
A Y=A
0 1
1 0

3. CIRCUIT DIAGRAM:

Page | 2
MECHATRONICS LABORATORY
K.L.E’S. SMT.C.I.MUNAVALLI POLYTECHNIC, VIDYANAGAR, HUBLI-31
MECHANICAL ENGINEERING DEPARTMENT
EXPERIMENT 2:- Design and Simulate OR GATE with Truth Table and Circuit
Diagram is having 2 inputs and 1 output.

OR GATE

1. BOOLEAN EXPRESSION: Y=A+B

2. TRUTH TABLE: Input Output


A B Y=A+B
0 0 0
0 1 1
1 0 1
1 1 1

3. CIRCUIT DIAGRAM:

Page | 3
MECHATRONICS LABORATORY
K.L.E’S. SMT.C.I.MUNAVALLI POLYTECHNIC, VIDYANAGAR, HUBLI-31
MECHANICAL ENGINEERING DEPARTMENT
EXPERIMENT 3:- Design and Simulate AND GATE with Truth Table and
Circuit Diagram is having 2 inputs and 1 output.

AND GATE

1. BOOLEAN EXPRESSION: Y=A.B

2. TRUTH TABLE: Input Output


A B Y=A.B
0 0 0
0 1 0
1 0 0
1 1 1

3. CIRCUIT DIAGRAM:

Page | 4
MECHATRONICS LABORATORY
K.L.E’S. SMT.C.I.MUNAVALLI POLYTECHNIC, VIDYANAGAR, HUBLI-31
MECHANICAL ENGINEERING DEPARTMENT
EXPERIMENT 4:- Design and Simulate NOR GATE with Truth Table andCircuit
Diagram is having 2 inputs and 1 output.

NOR GATE

____
1. BOOLEAN EXPRESSION: Y=A+B

2. TRUTH TABLE: Input Output


____
A B Y=A+B Y=A+B
0 0 0 1
0 1 1 0
1 0 1 0
1 1 1 0

3. CIRCUIT DIAGRAM:

Page | 5
MECHATRONICS LABORATORY
K.L.E’S. SMT.C.I.MUNAVALLI POLYTECHNIC, VIDYANAGAR, HUBLI-31
MECHANICAL ENGINEERING DEPARTMENT
EXPERIMENT 5:- Design and Simulate NAND GATE with Truth Table and
Circuit Diagram is having 2 inputs and 1 output.

NAND GATE

____
1. BOOLEAN EXPRESSION: Y=A.B

2. TRUTH TABLE: Input Output


____
A B Y=A.B Y=A.B
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0

3. CIRCUIT DIAGRAM:

Page | 6
MECHATRONICS LABORATORY
K.L.E’S. SMT.C.I.MUNAVALLI POLYTECHNIC, VIDYANAGAR, HUBLI-31
MECHANICAL ENGINEERING DEPARTMENT
EXPERIMENT 6:- Design and Simulate X-OR GATE with Truth Table and Circuit
Diagram is having 2 inputs and 1 output.

X-OR GATE

1. BOOLEAN EXPRESSION: Y=AϴB

2. TRUTH TABLE: Input Output


A B Y=AϴB
0 0 0
0 1 1
1 0 1
1 1 0

3. CIRCUIT DIAGRAM:

Page | 7
MECHATRONICS LABORATORY
K.L.E’S. SMT.C.I.MUNAVALLI POLYTECHNIC, VIDYANAGAR, HUBLI-31
MECHANICAL ENGINEERING DEPARTMENT
EXPERIMENT 7:- Design and Simulate X-NOR GATE with Truth Table and
Circuit Diagram is having 2 inputs and 1 output.

X-NOR GATE

_____
1. BOOLEAN EXPRESSION: Y=AϴB

2. TRUTH TABLE: Input Output


_____
A B Y=AϴB Y=AϴB
0 0 0 1
0 1 1 0
1 0 1 0
1 1 0 1

3. CIRCUIT DIAGRAM:

Page | 8
MECHATRONICS LABORATORY
K.L.E’S. SMT.C.I.MUNAVALLI POLYTECHNIC, VIDYANAGAR, HUBLI-31
MECHANICAL ENGINEERING DEPARTMENT
EXPERIMENT 8:- Design and Simulate DEMORGAN’S FIRST THEOREM with
Truth Table and Circuit Diagram is having 2 inputs and 1 output.

DEMORGAN’S FIRST THEOREM

____ _ _
1. BOOLEAN EXPRESSION: A+B=A.B

2. TRUTH TABLE: Input Output


_ _ _____ _ _
A B A+B A B A+B A.B
0 0 0 1 1 1 1
0 1 1 1 0 0 0
1 0 1 0 1 0 0
1 1 1 0 0 0 0
LHS = RHS

3. CIRCUIT DIAGRAM:

Page | 9
MECHATRONICS LABORATORY
K.L.E’S. SMT.C.I.MUNAVALLI POLYTECHNIC, VIDYANAGAR, HUBLI-31
MECHANICAL ENGINEERING DEPARTMENT
EXPERIMENT 9:- Design and Simulate DEMORGAN’S SECOND THEOREM with
Truth Table and Circuit Diagram is having 2 inputs and 1 output.

DEMORGAN’S SECOND THEOREM

____ _ _
1. BOOLEAN EXPRESSION: A.B=A+B

2. TRUTH TABLE: Input Output


_ _ ____ _ _
A B A.B A B A.B A+B
0 0 0 1 1 1 1
0 1 0 1 0 1 1
1 0 0 0 1 1 1
1 1 1 0 0 0 0
LHS = RHS

3. CIRCUIT DIAGRAM:

Page | 10
MECHATRONICS LABORATORY
K.L.E’S. SMT.C.I.MUNAVALLI POLYTECHNIC, VIDYANAGAR, HUBLI-31
MECHANICAL ENGINEERING DEPARTMENT
EXPERIMENT 10:- Design and Simulate COMBINATION CIRCUIT-1with Truth
Table and Circuit Diagram is having 4 inputs and 1 output.

COMBINATION CIRCUIT-1

1. BOOLEAN EXPRESSION: Y=(A.B)+(C.D)

2. TRUTH TABLE: Input Output


A B C D A.B C.D Y=(A.B)+(C.D)
0 0 0 0 0 0 0
0 0 0 1 0 0 0
0 0 1 0 0 0 0
0 0 1 1 0 1 1
0 1 0 0 0 0 0
0 1 0 1 0 0 0
0 1 1 0 0 0 0
0 1 1 1 0 1 1
1. CIRCUIT DIAGRAM:

Page | 11
MECHATRONICS LABORATORY
K.L.E’S. SMT.C.I.MUNAVALLI POLYTECHNIC, VIDYANAGAR, HUBLI-31
MECHANICAL ENGINEERING DEPARTMENT
EXPERIMENT 11:- Design and Simulate COMBINATION CIRCUIT-2 with Truth
Table and Circuit Diagram is having 4 inputs and 1 output.

COMBINATION CIRCUIT-2

3. BOOLEAN EXPRESSION: Y=(A+B).(C+D)

4. TRUTH TABLE: Input Output


A B C D A+B C+D Y=(A+B).(C+D)
0 0 0 0 0 0 0
0 0 0 1 0 1 0
0 0 1 0 0 1 0
0 0 1 1 0 1 0
0 1 0 0 1 0 0
0 1 0 1 1 1 1
0 1 1 0 1 1 1
0 1 1 1 1 1 1
2. CIRCUIT DIAGRAM:

Page | 12
MECHATRONICS LABORATORY
K.L.E’S. SMT.C.I.MUNAVALLI POLYTECHNIC, VIDYANAGAR, HUBLI-31
MECHANICAL ENGINEERING DEPARTMENT
EXPERIMENT 12:- Design and Simulate J-K FLIP-FLOP with Truth Table and
Circuit Diagram is having 2 inputs and 1 output.

J-K FLIP-FLOP

1. BOOLEAN EXPRESSION:

2. TRUTH TABLE: Input Output

CLOCK J K Q Q’ STATE
1 0 0 NC NC NO CHANGE
1 0 1 0 1 RESET (Q=0)
1 1 0 1 0 SET (Q=1)
1 1 1 1/0 1/0 TOGGLE

3. CIRCUIT DIAGRAM:

Page | 13
MECHATRONICS LABORATORY
K.L.E’S. SMT.C.I.MUNAVALLI POLYTECHNIC, VIDYANAGAR, HUBLI-31
MECHANICAL ENGINEERING DEPARTMENT
EXPERIMENT 13:- Design and Simulate R-S FLIP-FLOP with Truth Table and
Circuit Diagram is having 2 inputs and 1 output.

R-S FLIP-FLOP

1. BOOLEAN EXPRESSION:

2. TRUTH TABLE: Input Output

R S Q Q’ STATE
0 0 NC NC NO CHANGE
0 1 1 0 SET (Q=1)
1 0 0 1 RESET (Q=0)
1 1 ? ? FORBIDDEN (No Output)

3. CIRCUIT DIAGRAM:

Page | 14
MECHATRONICS LABORATORY
K.L.E’S. SMT.C.I.MUNAVALLI POLYTECHNIC, VIDYANAGAR, HUBLI-31
MECHANICAL ENGINEERING DEPARTMENT
EXPERIMENT 14:-Draw the Ladder Rungs PLC-OR GATE to represent either of
the two normally open switches to be closed for the coil to be energized.

PLC--OR GATE

1. BOOLEAN EXPRESSION: Y=A+B

2. TRUTH TABLE: Input Output


A B Y=A+B
0 0 0
0 1 1
1 0 1
1 1 1

3. CIRCUIT DIAGRAM:

Page | 15
MECHATRONICS LABORATORY
K.L.E’S. SMT.C.I.MUNAVALLI POLYTECHNIC, VIDYANAGAR, HUBLI-31
MECHANICAL ENGINEERING DEPARTMENT
EXPERIMENT 15:-Draw the Ladder Rungs PLC-AND GATE to represent two
normally open & both have to be closed for the coil to be energized.

PLC--AND GATE

1. BOOLEAN EXPRESSION: Y=A.B

2. TRUTH TABLE: Input Output


A B Y=A.B
0 0 0
0 1 0
1 0 0
1 1 1

3. CIRCUIT DIAGRAM:

Page | 16
MECHATRONICS LABORATORY
K.L.E’S. SMT.C.I.MUNAVALLI POLYTECHNIC, VIDYANAGAR, HUBLI-31
MECHANICAL ENGINEERING DEPARTMENT
EXPERIMENT 16:- Design and Simulate PLC-Ladder Diagram for TIMING
CIRCUIT that will switch ON 5s and OFF 5s with Circuit Diagram is having 2
inputs and 2 outputs.

PLC-LADDER DIAGRAM-TIMING CIRCUIT

1. CIRCUIT DIAGRAM:

Page | 17
MECHATRONICS LABORATORY
K.L.E’S. SMT.C.I.MUNAVALLI POLYTECHNIC, VIDYANAGAR, HUBLI-31
MECHANICAL ENGINEERING DEPARTMENT
EXPERIMENT 17:- Design and Simulate PLC-Ladder Diagram for DOMESTIC
WASHING MACHINEOperation to switch PUMP ON for 8s, HEATER ON for
5s,DRUM FORWARD & REVERSE for 5s, and DRAIN ON for 5s with Circuit
Diagram is having 1 input and 4 outputs.

PLC-LADDER DIAGRAM-DOMESTIC WASHING MACHINE

1. CIRCUIT DIAGRAM:

Page | 18
MECHATRONICS LABORATORY
K.L.E’S. SMT.C.I.MUNAVALLI POLYTECHNIC, VIDYANAGAR, HUBLI-31
MECHANICAL ENGINEERING DEPARTMENT
EXPERIMENT 18:- Design and Simulate PLC-Ladder Diagram for GARAGE
DOOR Operation with Circuit Diagram is having 5 inputs and 2 outputs.

PLC-LADDER DIAGRAM-GARAGE DOOR

1. CIRCUIT DIAGRAM:

Page | 19
MECHATRONICS LABORATORY
K.L.E’S. SMT.C.I.MUNAVALLI POLYTECHNIC, VIDYANAGAR, HUBLI-31
MECHANICAL ENGINEERING DEPARTMENT
EXPERIMENT 19:- Design and Simulate PLC-Ladder Diagram for CAR PARKING
Operation with Circuit Diagram is having 3 inputs and 6 outputs.

PLC-LADDER DIAGRAM-CAR PARKING

1. CIRCUIT DIAGRAM:

Page | 20
MECHATRONICS LABORATORY
K.L.E’S. SMT.C.I.MUNAVALLI POLYTECHNIC, VIDYANAGAR, HUBLI-31
MECHANICAL ENGINEERING DEPARTMENT

Page | 21
MECHATRONICS LABORATORY
K.L.E’S. SMT.C.I.MUNAVALLI POLYTECHNIC, VIDYANAGAR, HUBLI-31
MECHANICAL ENGINEERING DEPARTMENT

Page | 22
MECHATRONICS LABORATORY
K.L.E’S. SMT.C.I.MUNAVALLI POLYTECHNIC, VIDYANAGAR, HUBLI-31
MECHANICAL ENGINEERING DEPARTMENT

Page | 23
MECHATRONICS LABORATORY
K.L.E’S. SMT.C.I.MUNAVALLI POLYTECHNIC, VIDYANAGAR, HUBLI-31
MECHANICAL ENGINEERING DEPARTMENT

Page | 24
MECHATRONICS LABORATORY

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