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Experiment 1:: Design All Gates Using VHDL

The document describes three experiments using VHDL to design and verify basic logic gates, half/full adders, and a 4:1 multiplexer. In Experiment 1, VHDL code is written to implement AND, OR, and XOR gates. Experiment 2 implements a half adder and full adder. Experiment 3 implements a 4:1 multiplexer. The code is tested in a simulator to verify the circuit operation and hardware implementation.

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Puneet Arya
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112 views6 pages

Experiment 1:: Design All Gates Using VHDL

The document describes three experiments using VHDL to design and verify basic logic gates, half/full adders, and a 4:1 multiplexer. In Experiment 1, VHDL code is written to implement AND, OR, and XOR gates. Experiment 2 implements a half adder and full adder. Experiment 3 implements a 4:1 multiplexer. The code is tested in a simulator to verify the circuit operation and hardware implementation.

Uploaded by

Puneet Arya
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Experiment 1: Design all gates using VHDL

// Design and verify for the operation of AND gate

// Software used: Active HDL 5.2

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity and_2 is

port(

a : in STD_LOGIC;

b : in STD_LOGIC;

c : out STD_LOGIC

);

end and_2;

--}} End of automatically maintained section

architecture and_2_dataflow of and_2 is

begin

c <= a and b;

end and_2_dataflow;

// Waveform
// Design and verify for the operation of OR gate

// Software used: Active HDL 5.2

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity or_2 is

port(

a : in STD_LOGIC;

b : in STD_LOGIC;

c : out STD_LOGIC

);

end or_2;

--}} End of automatically maintained section

architecture or_2_dataflow of or_2 is

begin

c <= a or b;

end or_2_dataflow;

// Waveform
// Design and verify for the operation of XOR gate

// Software used: Active HDL 5.2

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity xor_2 is

port(

a : in STD_LOGIC;

b : in STD_LOGIC;

c : out STD_LOGIC

);

end xor_2;

--}} End of automatically maintained section

architecture xor_2_dataflow of xor_2 is

begin

c <= a xor b;

end xor_2_dataflow;

// Waveform
Experiment 2: Write VHDL programs for the following circuits, check the
waveforms and hardware generated
// Design and verify the operation of a half adder

// Software used: Active HDL 5.2

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity half_adder is

port(

A : in STD_LOGIC;

B : in STD_LOGIC;

Sum : out STD_LOGIC;

Carry : out STD_LOGIC

);

end half_adder;

--}} End of automatically maintained section

architecture half_adder_dataflow of half_adder is

begin

Sum <= A xor B;

Carry <= A and B;

end half_adder_dataflow;
// Design and verify the operation of a full adder

// Software used: Active HDL 5.2

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity full_adder is

port(

A : in STD_LOGIC;

B : in STD_LOGIC;

Cin : in STD_LOGIC;

Sum : out STD_LOGIC;

Carry : out STD_LOGIC

);

end full_adder;

--}} End of automatically maintained section

architecture full_adder_dataflow of full_adder is

begin

Sum <= A xor B xor Cin;

Carry <= (A and B) or (B and Cin) or (Cin and A);

end full_adder_dataflow;
Experiment 3: Write a VHDL program and check the waveform and hardware
generated for a 4:1 multiplexer.
library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity multiplexer4_1 is

port(

i0 : in STD_LOGIC;

i1 : in STD_LOGIC;

i2 : in STD_LOGIC;

i3 : in STD_LOGIC;

sel : in STD_LOGIC_VECTOR(2 downto 0);

bitout : out STD_LOGIC

);

end multiplexer4_1;

--}} End of automatically maintained section

architecture multiplexer4_1_dataflow of multiplexer4_1 is

begin

bitout<= i0 when sel(1)='0' and sel(0)='0' else

i1 when sel(1)='0' and sel(0)='1' else

i2 when sel(1)='1' and sel(0)='0' else

i3;

end multiplexer4_1_dataflow;

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