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A. Single Cycle Micro-Architecture of Isa-Membound That Minimizes Cycle Time Using The Provided Hooks

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jakiraka

The document discusses several aspects of ISA design including: 1. Implementing a single-cycle microarchitecture for a memory-bound ISA using provided hooks to minimize cycle time. 2. Implementing a triple load/accumulate instruction using the fewest standard MIPS instructions. 3. The pros and cons of encoding different numbers of loads per instruction, such as good code density but little ability for parallelism with multiple loads per instruction. 4. Altering the ISA to work without a register file by completing instruction encodings and redefining semantics.

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A. Single Cycle Micro-Architecture of Isa-Membound That Minimizes Cycle Time Using The Provided Hooks

Uploaded by

jakiraka
43 views5 pages
The document discusses several aspects of ISA design including: 1. Implementing a single-cycle microarchitecture for a memory-bound ISA using provided hooks to minimize cycle time. 2. Implementing a triple load/accumulate instruction using the fewest standard MIPS instructions. 3. The pros and cons of encoding different numbers of loads per instruction, such as good code density but little ability for parallelism with multiple loads per instruction. 4. Altering the ISA to work without a register file by completing instruction encodings and redefining semantics.

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bh345

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The document discusses several aspects of ISA design including: 1. Implementing a single-cycle microarchitecture for a memory-bound ISA using provided hooks to minimize cycle time. 2. Implementing a triple load/accumulate instruction using the fewest standard MIPS instructions. 3. The pros and cons of encoding different numbers of loads per instruction, such as good code density but little ability for parallelism with multiple loads per instruction. 4. Altering the ISA to work without a register file by completing instruction encodings and redefining semantics.

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43 views5 pages

A. Single Cycle Micro-Architecture of Isa-Membound That Minimizes Cycle Time Using The Provided Hooks

Uploaded by

jakiraka
The document discusses several aspects of ISA design including: 1. Implementing a single-cycle microarchitecture for a memory-bound ISA using provided hooks to minimize cycle time. 2. Implementing a triple load/accumulate instruction using the fewest standard MIPS instructions. 3. The pros and cons of encoding different numbers of loads per instruction, such as good code density but little ability for parallelism with multiple loads per instruction. 4. Altering the ISA to work without a register file by completing instruction encodings and redefining semantics.

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BH345

QUESTION 1: ISA DESIGN

a. Single Cycle Micro-architecture of ISA-MemBound that minimizes cycle time using the
provided hooks.

b. Implementing the TrplLoadAcc instruction using the least amount of standard MIPS instructions.

Using MemRead instead of MemtoReg is fine since the first is only

asserted for lw instructions and the second is asserted for the lws also when output data lines from

memory is to be connected to the Write Data lines of the register file. This is not the case for ALUSrc

since this is asserted for I-type instructions also as well as the memory access instruction.

Critical path = 200+50+100+200+50 = 600ps (for lw)

The path between the adders and the pc can tolerate more delays because they do not lie within the

critical path. Any unit within the critical path (ALU, Register, Data memory) would benefit by
optimizing the hardware, this would make the critical path shorter

c. Pros and cons of encoding different number of loads per instruction

I. Pros

Good code density, that is, implicit operand addressing

Low hardware requirements

It is easy to write a simpler compiler to stack architecture

II. Cons

There is little ability for parallelism or pipelining

Data is not always at the top of the stack when needed, so additional instructions like TOP and SWAP are
needed.

It’s difficult to write an optimizing compiler for stack architectures

d. Altering the ISA to work without a register file by completing the encodings and redefining the
instruction semantics

Instruction Opcode Semantics

MvAcc 00 000

Iw 01 001

Is 10 010

TrpldAcc 11 011

2
QUESTION 2: PIPELINING AND DEPENDENCY

a. Identifying all dependence/hazards in the program independent of any microarchitectural details

When the instructions are executed in a pipeline processor, then data dependency conduction will occur,
which means that 11 tries to read the data before 12, resulting to incorrect values.

Operand forwarding should be used to correct the issue, use the interface register present between the
stages to hold intermediate output so that dependent output can access new value from the interface
register directly.

b. Type Instruction

Type Instruction Register ALU Data Register Total


Memory Read Operation Memory Write

R-format 4 1 3 0 1 9

lw 4 1 3 4 1 13

sw 4 1 3 4 0 12

beq 4 1 3 0 0 8

j 4 0 0 0 0 4

- Each instruction needs a total of five cycles for execution.


- One instruction begins on every clock cycle for the first five cycles.
- One instruction completes on each cycle from that time on.

3
QUESTION 3: CACHE

Considering this sequence:

sub $2, $1,$3

and $12,$2,$5

or $13,$6,$2

add $14,$2,$2

sw $15,100($2)

Pass register numbers along pipeline

n e.g., ID/EX.RegisterRs = register number for Rs

sitting in ID/EX pipeline register

n ALU operand register numbers in EX stage

are given by

n ID/EX.RegisterRs, ID/EX.RegisterRt

n Data hazards when

1a. EX/MEM.RegisterRd = ID/EX.RegisterRs

1b. EX/MEM.RegisterRd = ID/EX.RegisterRt

2a. MEM/WB.RegisterRd = ID/EX.RegisterRs

2b. MEM/WB.RegisterRd = ID/EX.RegisterRt

EX hazard

n if (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0)

and (EX/MEM.RegisterRd = ID/EX.RegisterRs))

ForwardA = 10

n if (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0)

and (EX/MEM.RegisterRd = ID/EX.RegisterRt))

ForwardB = 10

n MEM hazard
4
n if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0)

and (MEM/WB.RegisterRd = ID/EX.RegisterRs))

ForwardA = 01

n if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0)

and (MEM/WB.RegisterRd

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