1

Experimental study of self biased Switched

Capacitor Structure for LC-VCO
P. Purushothama Chary § , Rizwan Shaik Peerla § , Pula Bhanuteja, Bibhudatta Sahoo, and Ashudeb Dutta

Tank and Cross coupled Varactor SCA ON SCA OFF

Abstract—This brief presents an experimental switched-cap
structure that has better quality factor during OFF state and
improves in-band phase noise of an LC voltage controlled RV RON ROFF
oscillator (VCO). Fabricated in UMC 65 nm CMOS technology, CC L RP
CV CON COFF
the structure achieves better quality factor over a bandwidth of
1.54 to 2.54 GHz, with a minimum value of -124.5 dBc/Hz at 1
MHz offset, while consuming 10 mW of power with a FoM of
Tank and Cross coupled Varactor SCA ON SCA OFF
182.5 dB.
Index Terms—Voltage Controlled Oscillator, phase noise, 1 1 1
switched capacitor, Phase Locked Loop. CC L RP RVCV2wo2 CV RONCON2wo2 CON ROFFCOFF2wo2 COFF

I. I NTRODUCTION
In present times the demand for highly integrated multi-
Figure 1. LC oscillator tank with two switches added with switch on and
standard and multi-band transceivers has accelerated. This is other off.
as a consequence of the rapid growth of prevalent wireless
communication such as Bluetooth, 802.11a/b/g, long-term
evolution (LTE), and so on. A wide tuning range phase-
locked loop (PLL) with better phase noise and low current
consumption is an essential building block in multi-standard The VCO contributes to the phase noise spectrum of the
wireless transceivers. Furthermore, as each standard has its PLL above the loop bandwidth, whereas the charge pump (CP)
own set of specifications, the implementation of a multi- dominates most to the phase noise from the loop bandwidth
standard PLL has become every designer’s challenge. For down to 3 kHz, where the reference noise starts to prevail
instance, narrow bandwidth systems such as enhanced data [3]. So, in applications which need lower loop bandwidth,
rate for GSM evolution (EDGE) and global system for mobile design of VCO becomes crucial. One of the most effective
communications (GSM) require low out-of-band phase noise, ways to achieve wide tuning range and low tuning sensitivity
while wide bandwidth systems such as LTE demand low in- at the same time in a wideband VCO is to use a switched-
band phase noise [1]. Present day research has focused on the capacitor array (SCA) while keeping the varactor size small
execution of multi-standard PLLs capable of satisfying these in LC tank. The SCA was first presented in [4] as a single
aspects. ended structure. The ON resistance of the switches causes
In order to operate at all the frequency bands of these degradation of the phase noise. This problem was significantly
standards, the synthesizer needs to cover the frequency range. reduced by differential structure [5]. In ON state, the resistance
The loop bandwidth of the PLL is made tunable for the sake is halved, thus doubling the quality factor (Q) of the structure.
of obtaining optimum phase noise in each standard. Among In OFF state, big resistance sets the DC potential of the
these standards, GSM and 802.11a have the most stringent far- oscillator output and makes sure that the switch is completely
out and close-in phase noise requirement respectively [1]. For OFF at all times. Later, resistor was replaced by transistors
GSM, the spot phase noise requirement at 1.6-MHz frequency in [6], but the DC potential in OFF state is set to ground,
offset is 130.6 dBc/Hz [2]. While for 802.11a, the required making the switch vulnerable and not completely OFF all the
in-band phase noise should be approximately -90 dBc/Hz time. This drawback is overcome in [7], by setting the DC
with a loop bandwidth of 100 kHz [2]. Since the settling potential to a certain value where the switch is completely
time requirements for some applications such as EVA radio OFF.
and some wireless standards such as Bluetooth and 802.11b
are relatively relaxed (≈ 200 µs), a narrow loop bandwidth This paper is organized as follows. Section II overviews
of around 40kHz is chosen to have a better spur rejection. the VCO phase noise models and impact of quality factor on
Moreover, the phase noise (PN) of the synthesizer should be close-in phase noise followed by different types of switched-
as low as possible to suppress the adjacent channel power cap structures evolved over time. The proposed switched-cap
leakage. These requirements are used to set the synthesizer structure and VCO quality factor using this structure analyzed
phase noise design target. in Section III. Section IV summarizes this paper with all the
design details and measurement results followed by conclusion
§ These two authors contribute equally to the work. in Section V.
 2

VOP
II. OVERVIEW CSW CSW
CSW VX M1 VY
For better grasp of phase noise of an oscillator, the phase VON VOP
B M1 M2
noise equations from Leeson’s and Hajimiri models are needed M3
B
to be understood. Then the major factors contributing in-band
(a) (b)
phase noise can be noted.
B B

A. VCO Phase Noise VB

M4
RB
M5
VB
RB
CSW CSW
The phase noise of the VCO according to Leeson’s and VON
VX M1 VY
VOP
Hajimiri model is given by, M2 M3
"  2 # B
F.k.T.B 1 fo
L{fm } = 10.log . 2. (1) (c)
2.Ps fm 2.Ql
Figure 2. Different switched-cap structures used (a) single ended (d) differ-
and ential and (c) resistive biased

i2
Γ2 Σ ∆f
n

L(fm ) = rms . (2)

8π 2 fm
2 q2
max
the stability and loop bandwidth of the phased locked loop
(PLL). More the required frequency coverage, more number
Where F is the noise factor = 1,
of switched-caps needed. So, switched-caps play an important
k is the Boltzmann’s constant in Joules/Kelvin,
role in phase noise of the VCO.
T is the absolute temperature in Kelvins = 298 K,
B is the bandwidth = 1 Hz,
Ps is the RF output power, B. VCO Switched Cap Network: An Overview
fm is the offset frequency,
The most crucial performance metrics are the Q factor of the
fo is the oscillation frequency,
switched-cap at the operating frequency, and the ratio between
Ql is the loaded quality factor
maximum and minimum capacitance [5]. The Q factor of
the switched-cap is significant because the total Q factor of
Keeping fo fixed in Eq. (1), and considering the tank shown
the VCO limits the phase noise of an oscillator, and the
in Fig. 1, Ql of the LC tank can be calculated as [8],
capacitance ratio is critical as it decides the achievable tuning
range [5].
1 ωo .L1 The circuit has ON and OFF states. When the transistor is
= (3)
Ql RP k RV .C12 .ω2 k RON .C12 .ω2 k ROF F .C12 2 switched ON for the structure shown in Fig. 2 (a), as no dc
V o ON o OF F .ωo
current flows through the capacitor and through the transistor,
therefore, the transistor operates in triode region, and can be
"
1 1
= ωo .L1 + RV .CV2 .ωo2 + RON .CON
2
.ωo2 represented by a resistor equal to RON . The Q factor of the
Ql RP
# (4) resulting circuit is given as,
2 2
+ROF F .COF F .ωo 1
QswON = (7)
ωo .RON .CON

1 1 1 Cv 1 CON When the transistor is switched OFF, the transistor resis-

= + . + . tance is dominated by the capacitance from drain to body and
Qtotal QL Qv CT QswON CT
(5) gate. The capacitance of the switched-cap seen by the VCO
1 COF F
+ . when the transistor is OFF, COF F , is the series connection
QswOF F CT
between the capacitor being switched and the parasitic capac-
And in Eq. (2) Γrms ≈ 1/2 for differential noise sources, itance Cd of the transistor. The Q factor in OFF state is given
i2n
Σ ∆f is the sum of the current noise densities of the differential in Eq. (8). A wide transistor increases the Q factor but limits
equivalent of individual noise sources and qmax is the total the tuning range, leading to a compromise [5].
charge swing of the tank given by [9],
1
QswOF F = (8)
Q2l .Ltank .Ibias ωo .ROF F .COF F
qmax = Ctank .Ibias .Rtank = (6)
Rtank In order to overcome this situation, two extra switches are
We can see from Eq (1) and (2) that Ql plays a vital role added to change it to differential structure shown in Fig. 2 (b).
in the VCO phase noise. The impact of Ql on the phase noise During ON state, the differential nature of the structure reduces
is an inverse relation. So higher the Q factor, better the phase the equivalent RON by half, thus doubling the Q factor. In OFF
noise. state, the nodes VX and VY travel below zero for half clock
In wide-band VCO design, The varactors tuning is limited to cycle [10]. So when nodes VOP and VON are negative enough,
10s or 100s of MHz range. This is calculated keeping in mind transistors M2 and M3 turn partially ON. Due to small sizes
 3

VB
RB
OFF STATE
RB
VB
B B
ON STATE

CSW R1/2 R1/2 CSW CSW CP1 CP1 CSW

VON VOP VON VOP

CP4 CP5 CP2 CP3

R2 R3
M4 M5

CSW CSW CSW CSW CSW

VON VON VON VON VON VON
VX M1 VY
CP4 R2 CP4 R1/2
CSW CSW
C1
CSW
VON VOP
R1/2 R1/2
RB
CP= CP1 + CP2 RB
RB

M2 M3
B
Figure 3. RC equivalent of the resistive biased structure in ON and OFF
states
Figure 4. Circuit of the experimental switched-cap structure

of M2 and M3 and operating in saturation region, the flicker

noise of these transistors generate significant phase noise [10]. the equivalent series capacitance is around CSW . The final Q
To avoid the aforementioned issues, the design was modified factor of this structure is given as,
as shown in Fig. 2 (c). Here VX and VY nodes are tied to a DC 1 1
voltage VB through a large resistor RB . The resistor doesn’t QOF F = = (13)
ωo .ROF F .COF F ωo .RB .CSW
effect the Q factor of the VCO, but the noise modulates the
One major observation from the above analysis is that Q1
junction capacitance of M1 − M3 slightly altering the tank
plays an important role in deciding the final series capacitance.
resonance frequency. The RC equivalent for this resistor biased
This depends upon the RC parallel combination formed by the
structure in ON and OFF state is shown in Fig. 3.
structure. Here the resistor value depends upon the designer.
This resistance has to be optimally chosen keeping it’s impact
III. P ROPOSED S TRUCTURE on phase noise. Generally it’s around kept around few KΩs.
To recognize the switched-cap structural importance, one Thus, the capacitor plays a key role in obtaining a better Q
needs to consider it’s impact on the total Q factor on the LC factor. By making the resistor parallel to CSW in OFF state,
tank. The total Q factor of a VCO is gives as the Q factor is improved multi-folds. The proposed structure
does the same as shown in Fig. 4. The p-MOS transistors M4
1 1 1 and M5 is connected to the output node of the VCO. The RC
= + (9)
Ql QLtank QCtank equivalent of the proposed structure in ON and OFF state is
Where QLtank is the inductor quality factor and QCtank shown in Fig. 5.
is the quality factor because of all the capacitance added in In ON state, the QON of the proposed structure remains
the tank. For negligible effect on the VCO phase noise, the the same with a small parasitic capacitance added at the VCO
second term in Eq. (9) must be almost 20 times less than the output node. Firstly, this does not effect the wide-band VCO
first [10]. In wideband VCOs, at all frequencies, achieving this bandwidth operating at less than 5 GHz. And secondly, this
is challenging. load effect can be eliminated by adjusting the CSW a little.
Now, firstly, the equivalent Q factor of the resistor biased During OFF state, we do the parallel to series conversion and
structure is analyzed from Fig. 3. In ON state, The switched- find out the equivalent OFF Q factor of the structure. Let Q2
cap (CSW ) is in series with the switch resistance (R1 /2), since is the Q factor of the parallel combination between CSW and
RB << R1 /2. The Q factor in this scenario is given as, R4 and is given as,

1 2 Q2 = ωo .R4 .CSW (14)

QON = = (10)
ωo .RON .CON ωo .R1 .CSW
1 + Q22
 
In OFF state, we observe that the resistor RB is tied to an C2 = CSW (15)
ac ground, making it parallel to the parasitic capacitance CP Q22
(CP = CP 1 +CP 2 ). After parallel to series conversion and fur- As CSW is few 10s or 100s of fF and R4 is the ON resis-
ther analysis, final Q factor is calculated. The expressions are tance p-MOS. R4 is approximately around 500Ω. Q2 > 1 in
given below. Let Q1 be the Q factor for parallel combination frequency of operation (1.5 GHz to 2.5 GHz). So C2 >> CP ,
of CP and RB . thereby the equivalent series capacitance is around CP . The
final Q factor of this structure is given as,
Q1 = ωo .RB .CP (11)
1 1
QOF F = = (16)
ωo .ROF F .COF F ωo .R4 .CP
1 + Q21
 
C1 = CP (12) Comparing Eq. (13) and (16), one can deduce the improve-
Q21 ment in the Q factor of the switched-cap due to the proposed
As CP is few fF and RB is in KΩs, Q1 << 1 in frequency structure. Q factor and VCO phase noise simulation results for
of operation (1.5 GHz to 2.5 GHz). So C1 >> CSW , thereby both structures are shown in Fig. 6 and Fig. 7 respectively.
 4

R4 R5
OFF STATE
ON STATE

CSW R1/2 R1/2 CSW CSW CP1 CP1 CSW

VON VOP VON VOP

CP4 R2 R3 CP5 CP2 CP3

CSW CSW CSW R4

VON VON VON VON VON
CSW
R4 R4
CP4 R2 CP4 R1/2 VON
R1/2 R1/2
C2
CP
CP= CP1 + CP2 CP

Figure 5. RC equivalent of the experimental switched-cap structure in ON

and OFF states

(a) Chip micrograph (b) VCO test setup

80 Figure 9. Chip micrograph with the area covered by VCO is shown in (a)
70 and the measurement setup is shown in (b).
60 Self Bias
Quality factor

109
50 2.6

40
2.4
30

Frequency (GHz)
Resistor Bias 2.2
20

10
2
0
1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5
1.8
Frequency (GHz) 109

1.6

0 0.5 1 1.5 2 2.5

Figure 6. Simulation result of Q factors when both switched-cap structures VTUNE (V)
are in OFF state

Figure 10. Measured tuning curves of the VCO showing a frequency coverage
of 1.54 to 2.54 GHz.
-40

-50

-60

-70
X 10000
Y -71.69
IV. M EASUREMENT R ESULTS
Phase Noise (dBc/Hz)

-80 The circuit diagram shown in Fig. 8 is implemented in UMC

-90
X 100000
Y -99.02
65 nm CMOS technology. The Die showing area covered by
-100

-110
LC-VCO is shown in Fig. 9 (a). The Die area is 1 mm x 0.6
-120
X 1000000
Y -121.8 mm, in which the core VCO area is 0.8 mm x 0.5 mm. To
-130 verify the proposed structure, phase noise is evaluated using
-140
an Agilent EXA N9010A signal analyzer and a Aplab LD3205
-150
103 104 105
Frequency (Hz)
106 107 dual DC power supply regulator. The test setup is shown in
Fig. 9 (b). The measured tuning range (TR) is from 1.54 GHz
to 2.54 GHz shown Fig. 10. Figures 11 and 12 show the
Figure 7. Simulation result of VCO phase noise of both switched-cap measured phase noise at 1.54 GHz and 2.5 GHz respectively.
structures in OFF state At both these carrier frequencies, drawing 10 mW from 2.5-
V supply of the main oscillator, it achieves -103.85 and -
95.83 dBc/Hz at 100 kHz offset respectively. Finally, Table
SCA
Vdd I compares the proposed VCO phase noise with the state of
B0 Varactors
B0

MP1 MP2
VTUNE
art VCO phase noise.
M9 M10 C C
MSW0
VON VOP VON M3 M4 VOP
CSW CSW
CSW0
M7
B0
M8
CSW0 SCA R R V. C ONCLUSION
VDD
L
2
B4 B4
VON

Cvar VTUNE Cvar

VOP

C
VTUNE
C
This paper explores the opportunity to provide another
VON
M13
MSW4
M14
Varactors
VON

R
M5 M6

R
VOP
alternative to resistor biased switched capacitor structure. The
VOP
CSW4
M11 M12
CSW4
MN1 MN2
VDD experimental switched capacitor bank used in the VCO is
B4
discussed. It’s Q factor improvement compared to resistive
biased structure is shown. The overall LC tank quality factor
Figure 8. Complete LC oscillator circuit using 5 bit experimental switched- and phase noise for both structures is shown. The measurement
cap structure results are shown for out-of-band phase noise (100 KHz
offset).
 5

Table I
P ERFORMANCE S UMMARY COMPARING WITH OTHER WIDE - BAND VCO S AND PLL S

Supply (V) Tech. (nm) Oscillator Fvco (GHz) PN (dBc/Hz)a Area (mm2 ) Pow. (mW) FoM (dB)b
This Work 2.5 65 LC-VCO 1.54-2.54 -124.5 1 10 182.5
[11] 2 180 LC-VCO 1-2.4 -121 0.36 21 175.4
[12] 1.2 65 LC-VCO 1.6-2.6 -124 0.13 14.5 180.7
[13] 0.35 22 Transformer 4-5 -115 0.19 0.44 190.6
[14] 1.8 28 LC-VCO 2.7-7 -118 0.07 11 175.1
[15] 1.8 180 DCO 2.8-3.2 -116 0.62 5 172.6
[16] 2.5/1.2 65 DCO 2.8-3.8 -101 0.44 6.2 164
a Phase Noise at 1 MHz offset
vco 2
FoM = 10 log10 [ F∆F
b

1mW

P ower
] − P haseN oise(dBc/Hz)

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