California State University, Northridge

Electrical and Computer

Engineering Department
By Christian Gil & Edgar Siles

CMOS
Digital Electronics
Laboratory Report
Contents

Lab 1. CMOS Inverters Voltage Transfer Characteristics (VTC)

Lab 2. Design, Simulation and Experimental Test of

CMOS Two-Input NAND Gate

Lab 3. Design, Simulation and Experimental Test of

CMOS Ring Oscillation and Clock Generation

Lab 4. Design, Simulation and Experimental Test of

CMOS Transmission Gate

Lab 5 & 6. Design, Simulation and Experimental Test of CMOS D-Latch and
CMOS NAND based S-R Latch

Lab 7. Design, Simulation and Experimental Test of 4x4 NOR ROM Array

Lab 8. Design, Simulation and Experimental Test of CMOS Seven Ring

Voltage Control Oscillator

Lab 9. Design, Simulation and Experimental Test of Cascode Voltage

Switch Logic
 Digital Electronics
Laboratory Course Objective and Description

This advanced digital electronics lab deals with models of electronic nonlinear devices and their
analysis. This advanced lab will pursue design, analysis and test of digital electronic circuits with the help of
discrete components and Integrated Circuits (IC) including VLSI circuits. This lab course will emphasizes
specifically on the design, analysis and experimental test of CMOS Ring Oscillation and Clock Generation,
CMOS Inverters and their Voltage Transfer Characteristics, CMOS Two-Input NAND Gate, CMOS
Transmission Gate, CMOS D-Latch and CMOS NAND based S-R Latch, 4x4 NOR ROM Array, CMOS Seven
Ring Voltage Control Oscillator, and Cascode Voltage Switch Logic.

Extensive hardware experimental circuit designs will be examined with the help of discrete components
and/or IC designs, and PSpice simulations will be used to examine and explain the basic building blocks of
advanced digital electronics circuits design and analysis. The main focus is on design, analysis and test of
Engineering and Computer Science real system problems and solutions. This advanced digital electronic
circuits design, analysis and test labs provide the student with the basic knowledge necessary to understand the
operation and application of CMOS Inverters, CMOS Oscillators, CMOS Logic Gates, CMOS Latches, and
CMOS Switching Circuits for various applications based on the discrete components and advanced VLSI
systems technology design point of view.
 CMOS INVERTERS VOLTAGE TRANSFER CHARACTERISTICS (VTC)

Christian Gil and Edgar Siles

California State University, Northridge, College of Engineering and

Computer Science, Electrical and Computer Engineering Department
Christian.gil.85@my.csun.edu, edgarsiles88@yahoo.com

Abstract: the input. When the input is low the PMOS will be
activated as shown in table 1. Table 1 though does
The construction of the CMOS inverter which uses not explain that when the channel is ON there are
paired transistors to create the inversion of the different regions which it can be in. These regions
input is described in this paper. Using PMOS and are the either Saturation or Triode.
NMOS transistors will allow for the pulling down
or pulling up the output depending on the current Channel OFF channel ON
input.
Vgsp > VTp
Vgs < VT
or,
Keywords: PMOS or,
Vin > VT +
Vin < VT + VCC
Inverters, CMOS, NMOS, PMOS VCC
Vgsn < VTn Vgs > VT
1.1. INTRODUCTION NMOS or, or,
Vin < VTn Vin > VTn
The typical CMOS inverter is shown in
figure 1.1 where the inputs of both the PMOS and
the NMOS are connected together and sent the Table 1. Relationship between gate-source voltage,
same input to their gates. Vgs, and the threshold voltage, VT, for CMOS
Operations

All above information regarding the CMOS

inverter can be translated into figure 1.2 and for
each operation region, the modes of the transistors
are annotated — off, res(istive), or sat(urated). The
res annotate is another name for the triode region.
All these modes depict how much current is
progressing through the channel where the most
current is during the saturation region.
The dotted line shown in figure 1.2 depicts
when both transistors are on and dispensing the
most current they can. A common practice for the
construction of CMOS inverters is to try and make
the transition from when the NMOS is in saturation
Fig. 1.1 A CMOS Inverter Circuit and PMOS is in triode to the when the NMOS is in
Triode and PMOS is in Saturation to be as quick as
The way the inverter works is shown in possible.
figure 1.2 in a curve that depicts the output verses
 1.2. PROCEDURES, SIMULATION AND
EXPERIMENTAL SET-UP

For this experiment we first simulated the

inverter with parameters that are supposed to be
similar to that of the CD4007. Testing the circuit at
different frequencies required that we use the
VPULSE part from the PSPICE library. VPULSE
will allow for use to input a square wave for our
circuit. We also used the MbreakP part to represent
the PMOS and the MbreakN to represent the
NMOS. These were used because they allow the
user to edit all their parameters easily. The circuit
is shown in figure 1.4 with all the connections.

For complete testing we simulated and

tested our circuit at three different frequencies. We
chose to run the input at 800 KHz, 1 MHz and 1.2
Fig. 1.2 Sample CMOS Inverter Voltage Transfer MHz frequencies. This was easily accomplished
Characteristic (VTC) with the practical circuit by simply changing the
frequency on the Function Generator. In order to
In this laboratory experiments CD4007 change the frequency of the VPULSE in pspice a
CMOS chip is used. It is a 14 pin chip that is few more calculations are needed.
doesn’t require power or ground to be used. Even
though this chip doesn’t need power for the whole
chip it does need power for individual PMOS
transistors ad it needs ground for the individual
NMOS transistors.

Fig. 1.3 CD4007 Pin Layout

Fig. 1.4 A CMOS Inverter Circuit
The first calculation needed is figuring out the is only used if you wanted the first pulse to be
period needed for the frequency that is being delayed a certain amount of time before it starts.
tested. The equation for frequency is:
1.3 SIMULATION AND
Equation 1.1: F=1/p : p = period EXPERIMENTAL RESULTS
Once all the diagrams were constructed in PSPICE
Moving the p and f over and the equation can then and on the solder-less breadboard our results are
be solved for the period which is what VPULSE shown in the following figures. Figure 1.5 and 1.6
requires. For our frequencies we obtained the shows the results of our first test, running the input
periods: at 800 kHz. At this speed our inverter looks like it
is able to switch with relative quickness and with
1.25e-6 seconds for 800 KHz little noise.

1.0e-6 seconds for 1 MHz

.833e-6 seconds for 1.2 MHz

The next component of VPULSE that needed to be

calculated was the PW, which represents the Pulse
Width. This component is used to determine the Fig. 1.5. Sample Simulation Input/Output Results
duty cycle of the square wave. For this lab the duty
cycle needed to just be 50%, this required that the
period just be divided by two.

The last components that needed to be calculated

were the TR and TF, which represent Time Rise
and Time Fall, respectively. The equation for to
calculate these are:

Equation 1.2 TF, TR = (1/6)(PW).

These gave us the values:

800 KHz  .1041e-6 s

1 MHz  .0833e-6 s Figure 1.6: Practical results of 800 kHz.

1.2 MHz  .069445e-6 s

The TR and TF are calculated like this in order to

provide a more accurate simulation, because in real
life parts no chip will be able to switch from high
to low or low to high instantly.

The rest of the values needed for VPULSE are just

the voltages wanted and the TD (Time Delay). TD Figure 1.7: Simulation of inverter at 1 MHz.
 shows the inverter running at the same speed but
looking fine. This shows how something can work
in simulation but is not really practical in real life.

Figure 1.8: Practical inverter at 1 MHz.

Figure 1.11: Simulated Inverter’s VTC Curve

Figure 1.9: Simulation inverter at 1.2 MHz

Figure 1.12: Simulation VTC curve with VM =

VDD/2

Figure 1.10: Practical Inverter at 1.2 MHz.

Figure 1.10 represents our built inverter that

is being run at 1.2 MHz and it shows that is not
able to switch as fast anymore compared to when
the input was at 800 kHz. This is due to the
limitations of the chip we are using. Figure 1.9
Figure 1.13: Practical VTC curve or inverter.
 Figures 1.11 through 1.13 represent the the output at about half of VDD which is what we
inverter’s VTC curve which means its Voltage wanted.
Transfer Characteristic. These relate to figure 1.2 1.4. DISCUSSION AND
which shows the theoretical VTC curve. In figure CONCLUSION:
1.11 the PSPICE simulation shows that the VM
cross section is around 2.75 volts. When designing In conclusion the first experiment worked
an inverter the ideal inverter will have the VM be as planned. It was able to invert the input with
at VDD/2, which with our VDD being 5 volts minimal delay and with minimum noise
should be 2.5 volts. To fix this increasing the width interference. We did notice that as we increased the
parameter of the NMOS in the PSPICE simulation frequency the output’s switching was delayed and
will cause the pulling down of the input to occur there was a shift from when the input changed to
faster and sooner. Doubling the width from 30um when the output changed.
to 60um is equivalent to putting another NMOS One of the questions that was answered by
transistor in parallel with the original NMOS. The this experiment was that the Switching Threshold
result of doing that is shown in figure 1.12. The would move closer to Ground when the NMOS
VM was changed to around 2.5 volts, which is the width is increased.
same as our VDD/2.
REFERENCES
Finally Figure 1.13 shows the practical
version of the VTC curve. After sizing our NMOS 1. “Circuit Design Layout and Simulation”, R.
to twice the original size it was able to pull down Jacob Baker, second edition, Wiley & Sons,
the output faster. It also shows that VM is crossing INC (2005)
 DESIGN, SIMULATION AND EXPERIMENTAL TEST OF
CMOS TWO-INPUT NAND GATE

Edgar Siles & Christian Gil

California State University, Northridge, College of Engineering and

Computer Science, Electrical and Computer Engineering Department
Edgarsiles88@yahoo.com, Christiangil88@gmail.com

Abstract:

Using the inverter characteristics a Nand

gate will be created and prove its functionality. It
will explore the pull up and pull down network on
which the system is based upon and how these
behave on the PMOS and NMOS. It will also focus
on the effects of sizing, with its effect on the gate
behavior.

Keywords: Two [2] input Nand gate, Pull Up/Pull

Down network, CMOS NAND gate.

2.1 INTRODUCTION

The experiment is to design a 2-input CMOS

Nand gate based on the CMOS inverter and its
characteristics. Using the properties of the inverter
we are able to create a network of NMOS and
PMOS transistors to create logic [Fig. 2.1]. This
Fig. 2.1 CMOS Two-Input NAND Gate
allows the creation of any of the logic gates, to
illustrate we build a Nand gate. This gate is an
The Nand gate is represented by the convention
important one because this is a universal gate,
diagram shown in Fig. 2.2. The experiment will
meaning we can create any logic function using
also analyze the “worst case” scenario in which the
only this gate. Its logic function is (A*B)’, which is
propagation delay is extended because of the
what the design must satisfy [Table 1].
conditions the PMOS and NMOS are interacting.
TABLE 1
Two-Input NAND Gate Logic

A B Ᾱ’ B’ (A*B)’ A’+B’
0 0 1 1 1 1
0 1 1 0 1 1
1 0 0 1 1 1
1 1 0 0 0 0 Fig. 2.2 Two-Input NAND Gate
2.2 PROCEDURES, SIMULATION AND results when analyzed on ORCAD PSPICE. These
EXPERIMENTAL SET-UP verify the proper functionality of the design at the
various frequency at which it was tested with
The Nand gates is composed of a pull up and accompanying results. The gate was tested with
pull down network, composed of PMOS and three frequencies: 0.8, 1 and 1.2 MHz in
NMOS transistors respectively. When designed in conjunction with half the test frequency to produce
the Nand manner the width of the PMOS channel all the logic scenarios, inputs A and B respectively.
is larger than that of the NMOS, causing the gate to In Fig. 2.3 it is seen that there is two frequencies
not have a desired VDD/2 threshold. This led to the that are used as inputs the respective A and B
sizing of the NMOS network to match the PMOS inputs running at 0.8 MHz and 0.4 MHz.
and have an equal voltage drop across the two Following are the result from the design, in Fig.
networks. 2.4, where there are three graphs. The top is the
The Nand gate accepts two inputs and with their highest frequency, the second is half of the first,
combinations the Nand gate turns on or off the and the third is the result obtained from the Nand
NMOS and PMOS, creating paths to VDD or gate.
ground hence creating the logic. Because these are V16
5Vdc
networks that interact with each other, there is
cases where the networks in parallel and its Mbreakpd1
Mbreakpd0
components are not all on or off at the same time 0
M22
causing the “worst case” scenario. This is when the V1 = 5 V15 M21
V2 = 0
path of the current through a network is giving the TD = 0
TR = .667u
correct logic, but because of the input TF = .667u
PW = 4u
combinations not all the transistors are operating, PER = 8u
M20
causing smaller channels or longer paths. When 0
such case occurs it is identified as the “worst case” V1 = 5 V17 Mbreaknd0
V2 = 0
because the propagation delay is increased, which TD = 0
TR = .33333u
is not desirable. For this design the worst case TF = .33333u
PW = 2u
condition is when one of the PMOS transistors is PER = 4u
0 M23
on and the other off lowering the width of the
channel. Mbreaknd1

The procedure involved designing a static 2 input

CMOS Nand gate based on the CMOS inverter. 0
Then it had to be tested for the logic functionality
of the design so it satisfies the Nand gate Fig. 2.3 Two-Input NAND Gate at 0.8 MHz
properties. When completed, the NMOS and
PMOS pull strength is both networks must match
for the “worst case.” Lastly, simulate the Voltage
Transfer Characteristic (VTC) of the design to
verify the functionality of the switching.
The simulation set up was to design the desired
gates, their simulation was first evaluated to
analyze the gate’s functionality. Fig. 2.3 through
Fig. 2.8 are the Nand gate simulations with their
 Fig. 2.4 Two-Input NAND Gate at 0.8 MHz Fig. 2.6 Two-Input NAND Gate at 1.0 MHz
[Units of Each Plot: 0-5V vs. 0-18µs] [Units of Each Plot: 0-5V vs. 0-22µs]

In Fig. 2.5 it is seen that there is two frequencies In Fig. 2.7 it is seen that there is two frequencies
that are used as inputs the respective A and B that are used as inputs the respective A and B
inputs running at 1.0 MHz and 0.5 MHz. inputs running at 1.2 MHz and 0.6 MHz.
Following are the result from the design, in Fig. Following are the result from the design, in Fig.
2.6, where there are three graphs. The top is the 2.8, where there are three graphs. The top is the
highest frequency, the second is half of the first, highest frequency, the second is half of the first,
and the third is the result obtained from the Nand and the third is the result obtained from the Nand
gate. gate output.
V10
5Vdc V13
Mbreakpd1 5Vdc
Mbreakpd0
Mbreakpd1
M14 0 Mbreakpd0
V1 = 5 V9 M13
M18 0
V2 = 0 M17
TD = 0 V12
V1 = 5
TR = .8u V2 = 0
TF = .8u TD = 0
PW = 5u TR = 1u
PER = 10u TF = 1u
PW = 6u
M11 PER = 12u M16
V1 = 5
0 V11 0
V2 = 0 V1 = 5 V14
TD = 0 Mbreaknd0 V2 = 0 Mbreaknd0
TR = .41667u TD = 0
TF = .416667u TR = .5u
TF = .5u
PW = 2.5u PW = 3u
PER = 5u PER = 6u
0 0 M19
M15
Mbreaknd1
Mbreaknd1

0
0
Fig. 2.7 Two-Input NAND Gate at 0.8 MHz
Fig. 2.5 Two-Input NAND Gate at 1.0 MHz
 Fig. 2.10 Two-Input NAND Gate at 0.8 MHz
[Units of Each Plot: 0-5V vs. 0-18µs]
Fig. 2.8 Two-Input NAND Gate at 0.8 MHz
[Units of Each Plot: 0-5V vs. 0-25µs]
Fig. 2.10 illustrates the input frequency to
the Nand gate and the D flip-flop. The second plot
When deciding the actual implementation
show how the flip-flop cuts the frequency in half
of the design, there was an issue on obtaining two
and becomes the second input to the Nand. The
signals from separate function generators that
third plot illustrates the resulting waveform from
would be synchronized. To solve the issues, the
both inputs after the Nand gate logic. Table 2
idea of using a D-Flip flop was presented. The flip-
shows the logic proved from all the simulations
flop is use the signal from the signal generator and
half the frequency, keeping both signals
TABLE 2
synchronized. Fig.2.9 show the implementation of
Illustrates the simulation logic.
this method and how it is used to get synchronized
Input A Input B Output Correct
signals
[Half
V2
Frequency]
5Vdc
Low [0] Low [0] High [1] Yes
Mbreakpd0
Mbreakpd1
0 High [1] Low [0] High [1] Yes
M3 Low [0] High [1] High [1] Yes
4

U1A V
M2
V1 = 5 V1 High [1] High [1] Low [0] Yes
PRE

V2 = 0 2 5
TD = 0 D Q
TR = .667u 3 6 V
CLR

TF = .667u CLK Q
PW = 4u
PER = 8u 7474 M1 V
1

0
Mbreaknd0
2.3 SIMULATION AND
EXPERIMENTAL RESULTS

M4 Once all the simulation were correct, the

Mbreaknd1
implementation step followed, this meant building
the design in Fig. 2.9 and changing the input to the
test frequencies, verifying for correctness. The
0 following are the results obtained from the
Fig. 2.9 Two-Input NAND Gate at with the flip- implementation and their analysis in relation to the
flop as the frequency divider. Nand gate response to high frequencies.
Fig. 2.11 Illustrates the result of the the flip-flop as
the frequency divider. Yellow is output, blue is
input Fig. 2.13 The two-Input NAND Gate output at 0.8
MHz
The first thing to implement in making the
design is creating the frequencies that will be used Once it was proven that the design works at
for the testing of the logic. Using the flip-flop low frequencies, higher frequencies were
methodology, Fig. 2.11 illustrates the results from implemented. Fig. 2.13 illustrates the results at 0.8
that circuit. As observed the output takes one MHz with the respective test frequencies and
whole cycle of the input before changing states results. In Fig. 2.14 the results at 1.0 MHz with the
therefore being half the input and synchronized. respective test frequencies and results and finally
Next the functionality of the Nand gate was tested, Fig. 2.15 illustrates the results at 1.2 MHz with the
as in the simulation, at low frequencies for respective test frequencies and results obtained.
reliability issues. Fig. 2.12 illustrates the results.

Fig. 2.14 The two-Input NAND Gate output at 1

Fig. 2.12 The two-Input NAND Gate output at low MHz
frequencies.
Fig. 2.15 The two-Input NAND Gate output at 1.2
MHz with sizing
Fig. 2.17 The two-Input NAND Gate output at 1.2
MHz
2.4. DISCUSSION AND CONCLUSION: 2.5. QUESTIONS & ANSWERS:

The Nand gate constructed provided the 1. Why would the sizes of the transistors for the
proper results with those of the simulation. A 1um model inverter that produces a Vm =Vdd/2,
factor of great importance is transistor sizing. Fig. not produce a Vm = Vdd/2 for the 2-input Nand
2.18 illustrates the output result of the Nand gate at gate?
a high frequency without sizing. As observed the
current that flows is not enough to obtain desired
results and begins to charge prematurely. As can be
observed all simulations agree with the
implementation and illustrate the importance of
sizing and the relation between the pull up and pull
down network in CMOS technology.

Fig. 2.16 The two-Input NAND switching Fig. 2.18 The two-Input NAND Gate output at 1.2
threshold MHz without sizing
 The Nor gate would be sized the same way
That is due to the fact that the 2-input Nand as the Nand gate, but with the difference that the
gate consist of a pull up and pull down network to pull up network would be the one with the sizing.
implement its logic. When arranged in this way, This is due to them being complements of each
the width of the channel gets lager when arranged other because of duality [2]
in parallel. This causes more current to flow
creating a smaller resistance for the network that REFERENCES
has more elements in parallel and therefore moving [1] Sedra/Smith, Microelectronic circuits 6th
the Vm value away from Vdd/2.[1] edition.
[2] Harvard, http://people.seas.harvard.edu/
2. Estimate the sizing of the transistors for a 4- ~jones/es154/lectures/lecture_7/MOS/mos_logic.ht
input Nand gate for both a switching threshold of ml
Vdd/2 and worst case. [3] Josh Tynjala, http://logic.ly/lessons/nand-gate/.
A 4-input Nand gate would require a pull 2012
down network 2 times larger than that of the 2-
input Nand gate.
3. Explain how the transistor of a 3-input CMOS
Nor gate would be sized for both switching
threshold and worst case.
 CMOS Ring Oscillation and Clock Generation

Christian Gil and Edgar Siles

California State University, Northridge, College of Engineering and

Computer Science, Electrical and Computer Engineering Department
Christiangil88@gmail.com, edgarsiles88@yahoo.com

Abstract:

The basic concept of a CMOS inverter is

that it will invert the given input, but what will
happen if there are multiple inverters cascaded
together? Using cascaded inverters to create a
clock is one possibility from oscillators. This paper
will explain how to connect the inverters and how
many needed to get certain clock frequencies.

Keywords:

Inverter, Ring Osillation, Clock Generation

3.1. INTRODUCTION

Figure 3.1 depicts the construction of a

simple inverter using one NMOS and one PMOS
transistors. To construct the ring oscillator, the use Fig. 3.1 A CMOS Inverter Circuit
of any odd number of inverters cascaded together
will work. Figure 3.2 shows that for ring oscillators
the only inputs come from either the power needed
to power the inverters or from the outputs from
other inverters in the circuit. To calculate the
frequency for the oscillators the equation is as
follows [1]:

f = 1 / 2Ndelay

Where N is the number of inverters in the

circuit and delay is the delay time for an
individual inverter.

Figure 3.2 CMOS 3 Ring Oscillator [2]

3.2. PROCEDURES, SIMULATION AND
EXPERIMENTAL SET-UP

For this lab the construction of a 9 ring

oscillator is all that is required because once the 9
ring is created it is easy to remove one wire
connecting excess inverters and have it go to the
input of the first inverter. Once Figure 3.6 was
created in the practical sense it is simple to
disconnect the circuit after the output of the third
inverter and have it connect to the input of the first
inverter. This essential would create figure 3.3.
Figure 3.4 A 5 ring Oscillator

Figure 3.5 A 7 ring Oscillator

Figure 3.3 A 3 ring Oscillator

To construct the 9 ring oscillator the only

required chip is the MC14007 inverters. Three
chips are required for this since each chip contains
three inverters.

Figure 3.6 A 9 ring Oscillator

 Using three chips with names A, B and C
representing the inverters in ascending order the
connections for this go as following:
13A, 8A, 3A: 1st  2nd inverter.
5A, 1A, 10A: 2nd 3rd input
2A, 14A, 11A: 5 voltage.
9A, 7A, 4A: Ground
12A , 6B: 3rd  4th inverter
14B, 2B, 11B: 5V
13B, 3B, 8B: 4th  5th inverter
1B, 7B, 4B: 5th  6th inverter.
12B, 6C: 6th  7th inverter.
3C, 13C, 8C: 7th  8th inverter
1C, 5C, 10C: 8th  9th inverter
12C, 6A: 9th  1st inverter Figure 3.8 Practical Results of 3 ring Oscillator.
11C, 2C, 14C: 5 volts
7C, 9C, 4C: Groundt Figures 3.7 and 3.8 show the results from
the construction of a 3 ring oscillator. From the
3.3 SIMULATION AND practical result we can see that it is running at
EXPERIMENTAL RESULTS 1.585MHz. From the PSpice simulation we can
calculate the frequency by dividing 1 by one period
After building this in a theoretical aspect of the oscillation. From this we chose point 715ns
(PSPICE) and then building it using actual physical and 767ns to represent the period.
chips we were able to check the frequency that
each of the oscillators created. We could determine 767ns – 715ns = 52ns
which one provided the fastest clock and which one 1 / 52ns = 19.231MHz
was the slowest.
This value is a roughly a tenth greater than
the practical and the only observation that could be
made by this is that the PSPICE simulation values
are different from the chip that we use.

Figure 3.7 The results of 3 ring oscillator Pspice

Fig. 3.9. Pspice results of 5 ring Oscillator. 10. This again is due to the different parameters of
the real inverter chips to the simulation parameters.
This however works like it is supposed to because
even though the parameters are not the same the
ration is probably similar.

Figure 3.10. Practical results of 5 ring Oscillator.

Figure 3.12 Practical results of 7 ring Oscillator

Figure 3.11 Pspice results of 7 ring Oscillator

The practical 5 ring oscillator has a

frequency of 1.29 MHz which is a lower frequency Figure 3.13 Pspice results of 9 ring oscillator
from the 3 ring oscillator. This is understandable
because now that there are more inverters in the
oscillators there is an increase of propagation delay
from each of the inverters introduced.
Now calculating what the frequency is
when running the Pspice simulation, we take the
first point when the input is starting to fall which is
749ns and the when that happens again at 835ns.

835ns – 749ns = 86ns

1 / 86ns = 11.63 Mhz
This value again is close the practical
simulation value except that is if off by a factor of
Figure 3.14 9 ring with different probe location. ring oscillator as the one in figure 3.13 except that
the probe was placed in a different position (after a
different inverter’s output). It gave us the values of

880ns – 720ns = 150ns

1 / 150ns = 6.67 MHz.

This was placed in this lab to show that it doesn’t

matter where the probe is placed since the
frequency won’t change. The only reason why the
reading looks changed is because it does show that
there is a phase shift due to the placement of the
probe.

3.4. DISCUSSION AND

Figure 3.15 Practical 9 ring oscillator results.
CONCLUSION:
For the 7 ring oscillator, the practical results
In conclusion ring oscillators make for good
state that the frequency is 1.09 MHz which goes
cheap clocks because all they require are low
with the current behavior of oscillators. For the
power CMOS inverters. They don’t require an
simulation results we first take the reading at 740ns
external input to cause them to oscillate. The cons
then take a reading at one period from it at 860ns.
of this device are that it is difficult to get precise
frequencies since the propagation delay of each
860ns – 740ns = 120ns
inverter can be different from each other. This will
1 / 120ns = 8.33 MHz.
make it impossible to make an oscillating
These results coincide with our past results
frequency right to set specifications.
of the oscillators with different amount of inverters.
This one though was a little more off than by a
REFERENCES
factor of 10.
For the next oscillator we added another
2. “Analysis and Design of Low Power Ring
two inverters to make this a 9 ring oscillator. This
Oscillators with Frequency ~10-100kHz”,
is the last oscillator created in this experiment. The
Piyush Keshri, University of Michigan, July
practical results state that this oscillator again
2008.
decreased the frequency, this time to 964.8 kHz.
3. “Ring Oscillator”. Wikipedia.org, January
The simulation then gave us the values of:
2012.
863ns – 708ns = 155ns
1 / 155ns = 6.45 MHz.

These results are shown in figure 3.13 and

3.15 respectively. Figure 3.14 shows the same 9
 DESIGN, SIMULATION AND EXPERIMENTAL TEST OF THE
SAMPLE AND HOLD CIRCUIT

Edgar Siles & Christian Gil

California State University, Northridge, College of Engineering and

Computer Science, Electrical and Computer Engineering Department
Edgarsiles88@yahoo.com, Christiangil88@gmail.com

Abstract: input is high and Table 2 illustrates the regions

when the input is low.
This is the experiment to test the TABLE 1
functionality and implementation of the Vin = Vdd
transmission gate. To test the transmission gate REGION 1 REGION 2 REGION 3
logic, it is used in the sample and hold circuit NMOS : SAT NMOS : SAT NMOS : OFF
design to test if it does work like a switch. It was PMOS : SAT PMOS : TRI PMOS : TRI
simulated and implemented with a pre and post Vdsn>Vgsn-Vtn Vdsn>Vgsn-Vtn Vgsn<Vtn
amplifier stage, to assimilate real life Vdsp<Vgsp-Vtp Vdsp>Vgsp-Vtp Vdsp>Vgsp-Vtp
implementations. To clock the design a square Vout= 0V |Vtp| Vdd-Vtn Vdd
wave was used and a sine wave was used as the
input. TABLE 2
Vin = 0
Keywords: Transmission gate, Sample and Hold. REGION 1 REGION 2 REGION 3
NMOS : TRI NMOS : TRI NMOS : SAT
4.1 INTRODUCTION PMOS : OFF PMOS : SAT PMOS : SAT
Vdsn<Vgsn-Vtn Vdsn<Vgsn-Vtn Vgsn> Vgsn-Vtn
In the real world very few things are found Vgsp< |Vtp| Vdsp>Vgsp-|Vtp| Vdsp>Vgsp-|Vtp|
to be digital, while analog is the ruler of most Vout= 0V |Vtp| Vdd-Vtn Vdd
signals found in nature. In order to for our
electronics to interact with signals found in nature
there must be analog to digital converters in order
to use the analog signals. A major component in
this circuit is the sample and hold, which takes an
analog circuit, samples it as a certain point in time
and holds the value until another sample is taken.
In order to take samples, a frequency at which
those samples are taken is required, and a switch to
turn on for the sampling period and off for the
holding time. This is where the transmission gate
becomes very useful because of its behavior as a
switch. Table 1 and Table 2 illustrate the stages of
the PMOS and NMOS and its behavior as the Fig. 4.1 [Transmission gate]
switch we want it to implement the sample and
hold. Table 1 demonstrates the transitions when the
4.2 PROCEDURES, SIMULATION AND
EXPERIMENTAL SET-UP

To begin introducing the transmission gates, it was

necessary to explain how it works and explain its
stages. The transmission gate works as a
bidirectional switch by allowing a low resistance
path from its input to its output when both
transistors are on as demonstrated in Table 1 and
Table 2. When both transistors are off the switch is
said to be off and a high impedance state is in
place. Since the two transistors are in parallel it
performs better than the pass transistor logic,
which is another type of logic switch, because this
design passes a strong logic 1 and strong logic 0.
By strong we refer to logic 1 being Vdd and logic 0
being ground. In comparison to the pass transistor
logic, where it depends on the type of
implementation, PMOS or NMOS, it would only
pass one type of strong logic; logic 1 for PMOS Fig. 4.2 Sample and Hold circuit Sin wave
and logic 0 for NMOS.
The first step was to utilize the CMOS
transmission gate as the essential building block in
implementing a sample and hold circuit. Using the
SPICE 1µm model, Vpulse, and its compliment
using an inverter, as an enable or also referred as
clock, the design was simulated.
To be used as an input, the Vsin signal
generator was used, because this allows the
simulation of very low voltage signals. These are
close to the analog signals that would be found in
nature and in the implementations this design. Fig.
4.2 illustrates the sample and hold design
implemented to test the transmission‘s gate
implementation. Fig. 4.3 demonstrates the results
obtained when the design is simulated. Lastly Fig.
4.4 illustrates the results separated to be able to see
their differences. Fig. 4.3 Results for the Sample and Hold
To test its performance at lower voltages, [Units: -20-20mV vs. 0-20µs]
the design was then tested with VPulse from 1.2V to
5V instead of the optimal 0V to 5V. The final step
was to plot the equivalent resistance of the
transmission gate versus the VOut as VOut is swept
from 0 to Vdd. The results are seen in Fig.
 Fig. 4.7 Separated results for the Sample and Hold
[Units: -200-200mV vs. 0-15µs]

4.3 EXPERIMENTAL RESULTS

Fig. 4.4 Separated results for the Sample and Hold
[Units: -20-20mV vs. 0-18µs] As expected from the simulations the
transmission gate works as a suitable switch for the
sample and hold design. Fig. 4.5 demonstrates how
the frequency response is dependent upon the
decisions made to implement the pre and post
amplifiers. The frequency at which that test was
conducted was at 3MHz, and the distortion is
clearly seen.

Fig. 4.5 Sample and Hold Triangle wave

Fig. 4.8 Sample and Hold at high frequencies

Fig. 4.6 Results for the Sample and Hold
[Units: -200-200mV vs. 0-15µs]
 After the proper implementation of the
sample and hold design using a sine wave, a
triangle wave was chosen to be the input. This was
done due to the fact that this is another posible
implementation of this design. In Fig. 4.8 the input
and output are displayed ovelapping to illustrate
the sampling state and the holding state. In Fig. 4.9
the results are seperated from the input to
distinguish their diffrences.

Fig. 4.8 Sample and Hold implementation results

Separated

Fig. 4.6 illustrates the results from the

sample and hold separated to clearly identify the
holding state of the design. It is also seen that
output of the design is starting to take the form of a
logic signal which is the main purpose of the
sample and hold. In Fig. 4.7 the output signals are
overlapped to demonstrate the comparisons found
in the input versus the output. The hold state is Fig.4.10 Sample and Hold implementation results
clearly illustrated at the specific clocked time.

Fig. 4.11 Sample and Hold implementation results

Fig. 4.9 Sample and Hold implementation results separated
 Fig. 4.13 Sample and Hold implementation results
Separated

4.4. DISCUSSION AND CONCLUSION:

The transmission gate works as a great

switch implementation to be used as the main
component in the sample and hold design. Its
drawback is the series resistance if placed in large
scale designs because it will cause voltage
threshold problems and not function according to
design specifications. All the implemented results
reflect the simulated results which illustrates
proper functionality. One other type of sample and
Fig. 4.12 Sample and Hold implementation results hold is one that simulates a TTL inverter. The
Separated circuitry is identified in Fig. 4.12.This sample and
hold circuitry includes its own 40ns pulse every
100ns and works the same way as the implemented
sample and hold. Fig. 4.13 illustrates its results.

REFERENCES
[1] Sedra/Smith, Microelectronic circuits 6th
edition.
[2]University Of Pennsylvania. 2006.
http://www.seas.upenn.edu/~ese319/Lecture_Notes
/Lec_21_Xmsn_Gate_RSFF_07.pdf
[3] Spectrum software, http://www.spectrum-
soft.com/news/summer2006/samplehold.shtm
 Design of a CMOS D-Latch and CMOS NAND based S-R Latch

Edgar Siles and Christian Gil

California State University, Northridge, College of Engineering and

Computer Science, Electrical and Computer Engineering Department
edgarsiles88@yahoo.com, christiangil88@gmail.com

be connected easily together to make shift

Abstract: regirsters. Some examples of these registers are the
Serial in serial out (SISO) register or even the
This paper explains the concepts in Parallel In Parallel Out (PIPO) register.
creating the memory unit called a D Flip Flop. It
explains how to use a Transmission gate and a few 5.2. PROCEDURES, SIMULATION AND
inverters to store one bit of data. EXPERIMENTAL SET-UP

Keywords: Memory, SR-Latch, D Flip-flop, For this experiment the use of past
Sequential circuit experiments is required for the entire process. The
use of the Tgate and the inverter is needed. For the
5.1. INTRODUCTION Tgate, the use of the middle transistors for both the
NMOS and PMOS need to be from separate chips
One type of memory that is most used in so that there will be no interference between any of
today's technology is the D Flip Flop. It is used the transistors.
registers to store data. There is different ways to
construct D Flip Flop, such as using NAND gates This circuit also requires that we use two
or the method we used with Transmission gates function generators, one for the data input D and
and inverters. Figure 5.1 shows the connections of the other for the clock that will clock the TGates.
two Tgates with inverters. The clock on the Tgates needs to be at least twice
as fast as the input D frequency.

Table 5.1: D Flip Flop Truth Table.

The D Flip Flop is one of the easiest

sequential memory types to implement but is also
one of the most powerful. Table 5.1 shows how the
D Flip Flop works where when the clock is rising
then the data in the D input will be outputted to the
Q output. This feature is was allows D flip flops to Figure 5.1: D Flip Flop circuit with TGates.
In this circuit there are two cascaded inverters that
are used to delay the output. This is because we
want a sequential circuit that needs to be clocked in
order to pass data across.

5.3 SIMULATION AND

EXPERIMENTAL RESULTS

Once the circuit was built in PSPICE and

using that schematic to build the practical version
the testing part of the experiment occurred. For this
experiment we are testing the D Flip Flop to make
sure that it follows the truth table described in
Figure 5.4: 1 MHz D Flip Flop.
Table 5.1. The circuit will be tested at speeds of
600 kHz, 800 kHz and 1 MHz.
Figures 5.2 to 5.4 demonstrate the function
of the D Flip Flop in theory and it is showing that
in theory our design is working perfectly. Even at
different frequencies the D Flip is outputting D to
Q when there is a rising clock. When the clock
isn’t rising though it is also doing what is supposed
to do by “Holding” the same value and displaying
it again until another rising clock edge.

In the practical circuit, the readings were

relatively good as well. The only fault with our
circuit’s readings was that there was a delay with
how fast the Q was outputted. As shown in figures
5.6, 5.8 and 5.10 the output would take slightly
Figure 5.2: 600 kHz D Flip Flop. longer to start changing its values, to the value that
was in D, after short amount of time.

Figure 5.3: 800 kHz D Flip Flop.

Figure 5.5: 600 kHz signal with D above Q.

Figure 5.6: 600 kHz input with Phase delay. Figure 5.9: 1 MHz input, D input on top, Q on
bottom.

Figure 5.7: 800 kHz D Flip Flop. D input on top.

Figure 5.10: 1 MHz D Flip Flop Phase Delay.

Figure 5.8: 800 kHz D flip Flop phase delay.

Figure 5.11: Clock readings vs D input.
 that can hold memory worked out fine. Something
Even with that delay of the output the circuit still we found was that if we had increased the clock
worked logically. This is seen in figures 5.5, 5.7 frequency even more than twice that of the D input
and 5.9. Observing figure 5.7, when D is high then then the output delay would have been decreased.
Q is high and when D is low then Q will also This is because it will be able to have more rising
become low. edges per D input which will allow it to have more
samples. If the circuit has more samples and
Figure 5.11 represents how the D input looks divisions of D, it will be able to change faster along
relative to the Clock. In this circuit the Clock is with the D input.
used as a sort of test and this is why that it is
required that the clock be at least twice as fast as REFERENCES
the D input so that its period will be able to be at
least covered within one Pulse Width of the D 1. “Circuit Design Layout and Simulation”, R.
input. Jacob Baker, second edition, Wiley & Sons,
INC (2005)
5.4. DISCUSSION AND 2. www.odyseus.nildram.co.uk/RFIC_Subcircuit
CONCLUSION: s_Files/CMOS_Cascode_Current_Mirror.pdf

In conclusion using Transmission gates and

inverters as a means of creating a sequential circuit
 DESIGN, SIMULATION AND EXPERIMENTAL TEST OF
SR FLIP FLOP [LATCH]

Edgar Siles & Christian Gil

California State University, Northridge, College of Engineering and

Computer Science, Electrical and Computer Engineering Department
Edgarsiles88@yahoo.com, Christiangil88@gmail.com

Abstract:

This is the set up and experimental

procedure of producing one of the basic dynamic
logic memory cells, the SR latch. It implemented
using the CMOS technology and explains its logic
functions in terms of the triggering inputs and
output results.

Keywords: SR flip flop, SR latch, Dynamic logic,

Nand Set/reset latch.
Fig. 6.1
6.1 INTRODUCTION
6.2 PROCEDURES, SIMULATION AND
EXPERIMENTAL SET-UP
In the dynamic logic realm there are
various types of ways of implementing memory. The latches are centered around the back to
One for the basic dynamic logic memory cell is the back inverters that will have two stable states and
Set/Reset flip flop or simply SR. The SR has 3 one quazistate. The inputs dictate which state the
combinations as acceptable inputs. These are controlling state is under and the other state is the
illustrated in Table.1. The Last stage is undefined inversion of it. The indertermined state occurs
because two opposite states conditions are trying to because in the state both inverters are in a
be satisfied at the same time. This is dealt with by quiazistate which causes the conflict. Fig. 6.2
properly sizing the design and treating the state as illustrates
a memory state. Fig. 6.1 demonstrates the Nand
gate implementation of the SR latch which was
used for the purposes of the lab.

TABLE 1
Inputs Outputs
S R Qn+1
0 0 Memory
0 1 0
Fig. 6.2
1 0 1
The goal was to design and simulate the 2-input
1 1 X CMOS Nand based S-R latch using PSPICE. In
this step it was necessary to size the transistors for
the worst case condition and it was also necessary
to measure the time delay between the switching.
Once the simulations ware providing desired
results as those in the S-R latch, it was time to
implement it and size it using the CD4007 IC. To
implement the latch, the design drawn up in
PSPICE was used, and sized by placing NMOS
transistors in parallel. Once implemented the
design was tested for all of its possible input and
output combinations. To implement all possible
combinations a D-Flip Flop was used to produce a
half frequency signal to be used as inputs. Fig. 6.4 B-set R-RST Two-Input NAND based SR
One way the latches can be turned on or off Latch at 600k [Units of Each Plot: 0-5V vs.0-8µs]
is by a simple and gate to one of the terminals
which are holding the data. Because of the back to
back inverters this will turn it on or off manually.
The same process can be used as an enable active
high which allows the output to be correct when
the enable[on/off] bit equals logic ‘1’.

6.3 SIMULATION AND EXPERIMENTAL

RESULTS

Fig. 6.5 G-set B-RST Two-Input NAND based SR

Latch at 600K [Units of Each Plot: 0-5V vs. 0-4µs]

Fig. 6.3 Two-Input NAND based SR Latch

Fig. 6.6 R-Reset, B-Set Two-Input NAND based

SR Latch at 1.25 MHz [Units of Each Plot: 0-5V
vs. 0-2µs]
 Fig. 6.7 Q & Q bar Simulation
Fig.6.9 The SR latch tested at 200KHz. Top is
The figures illustrate the desired results of
input for Set and the bottom is the output.
the experiment and their respective features. The
set and reset combination are working correctly .
The inverter is added to input because theis is a nan
implementation of the latch chuch means all the
output are inverted. With the integration of the
invertes the correct output combinations occur.

Fig. 6.10 The SR latch tested at 600KHz. Top is

input for Set and the bottom is the output.

Fig. 6.8 The input, coming from a D – Latch, to the

SR to test for all conditions.
 Fig. 6.12 The SR latch tested at 600KHz. Top is
input for Set and the bottom is the output.

6.4. DISCUSSION AND CONCLUSION:

The advantages of this circuitry over the D

latch are the possible input implementation sit can
take. With the SR, there is a larger logic space to
implement making a desirable design to implement
in larger circuits. The advantages of the D latch are
that it is the simplest method of implementing data
as a storage bit. A disadvantage of the SR latch is
the undefined state which may cause problem when
implementing logic, if that specific case is not
accounted for. Other types of sequential memory
Fig. 6.11 The SR latch tested at 1MHz. Top is
types are the T, and JK flip flops. Their operation
input for Set and the bottom is the output without
is the same as the SR with the integration of
sizing.
inverters to accommodate for the undefined case
and be used to implement all logic. These are
explained in detail in [2], and from which three
major conclusions are drawn. One is that Latches
are the basic storage elements, they are Edge
triggered versus conventional state triggered, and
finally that the purpose all these memory circuits is
their bi-stable element.

REFERENCES
[1] Sedra/Smith, Microelectronic circuits 6th
edition.
[2]University of California Riverside.
http://www.cs.ucr.edu/~ehwang/courses/cs120b/fli
pflops.pdf
 Design and Sizing of a 4x4 NOR ROM Array

Christian Gil and Edgar Siles

California State University, Northridge, College of Engineering and

Computer Science, Electrical and Computer Engineering Department
Christiangil88@gmail.com, edgarsiles88@yahoo.com

Abstract:

This paper gives details of the construction

of NOR based ROM. Given a table of 0 and 1’s it is
possible to create a non-changing circuit that will
be able to be quickly output the contents when
certain word lines are chosen.

Keywords:

Memory, ROM, NMOS, NOR implementation,

NAND Implementation.

7.1. INTRODUCTION Figure 7.2: NAND Based 4x4 ROM.

Read Only Memory (ROM), is a type of In NAND based ROM it is the opposite of
memory that only allows for the user to only view NOR based ROM because now when a high (1) is
the data in it and not edit it. The reason for this is required a NMOS is placed on the word line. For
because unlike other memory which can be read practical purposes ROMs can be used as lookup
and written too this memory is actually set into tables for when the same data needs to be
memory by placing physical hardware for every continuously read without it being able to be
bit. For NOR based ROM a NMOS is placed on the changed. This type of memory also never gets
word line when a 0 bit is required. deleted even if the power is taken away.

7.2. PROCEDURES, SIMULATION AND

EXPERIMENTAL SET-UP

For this lab we are going to create a NOR based

ROM that will follow the logic of table 7.1 below

C1 C2 C3 C4
R1 0 1 0 1
R2 0 0 1 1
R3 1 0 0 1
R4 0 1 1 0

Figure 7.1: NOR Based 4x4 ROM. Table 7.1: Look up table for our ROM.
 get multiple square pulses to output a square pulse
with a duty cycle of 20% at different times, is use
four separate VPULSE’s with the same frequency
except differ with the TD (time delay). A method
for designing a shift register is shown in figure 7.4
where only three D Flip Flops are used. They are
just connected in series with one output going into
the next input. This method also requires that there
be two function generators available: one to
provide 20% duty cycle input and the other to
provide the pulses for the clocks.

7.3 SIMULATION AND

EXPERIMENTAL RESULTS

Figure 7.3: PSPICE 4x4 Implementation.

Figure 7.4: Shift register using D Flip/Flop.

As stated in the introduction, since table 7.1

needs to be implemented in NOR based ROM the
use of 8 NMOS are required. This is due to the fact Figure 7.5: ROM Simulation at 200 kHz
that there are eight ‘0’s in the table. Figure 7.3
shows the resulting circuit with the NMOS’s on
certain bit lines to act as a ground value. If there is
no NMOS then there will be nothing connecting it
to ground so the value will be read as high.

The circuit needs to be constructed using

four CD4007 inverter chips. One chip alone will be
used for its PMOS transistors to pull up the bit-
line. The other three chips will use every other
NMOS to act as the pull down network.

Beside the construction of ROM for this

experiment, the construction of a shift register is
needed for the practical part. This is needed
because in PSPICE, all that is needed in order to Figure 7.6: ROM Simulation at 400 kHz
 When the third word line gets activated the
columns were read as:

C1  1
C2  0
C3 0
C4  1

Finally the last reading on the simulations was

when the last word line gets activated and the
columns were read as:

C1  0
C2  1
C3 1
Figure 7.7: ROM Simulation at 800 kHz.
C4  0
The previous figures represent the PSPICE
All of these readings coincide with the table
simulation results from three different frequencies.
showing that in simulation the ROM works as it is
The circuit was tested with input frequencies of
supposed to even at different frequencies.
200 kHz, 400 kHz and 800 kHz 20 % duty cycle
inputs. The top four waveforms on the simulations
represent the pulses to each word line, hence the
first waveform shows the input to the first word
line while the fourth wave shows the input to the
fourth word line. This is done so that only one
word line can be on at time, and this is done in the
practical part by using the shift register.

The next waves represent the columns of

the table. When the first word line went high the
readings from each column were:

C1  0
C2  1
C3 0 Figure 7.8: Clock wave and a 20 percent output
C4  1 wave.

When the next word line gets activated, after the In figure 7.8 to 7.10, it is shown that using three D
first wave pulse ends, the resulting column flip flops can simulate four different inputs at
readings were: different time delays without having to use four
function generators. Figure 7.8 shows that only two
C1  0 function generators are needed to construct four
C2  0 outputs. As long as the clock is running at five
C3 1 times the frequency as the signal you want shifted
C4  1 and delayed then that signal can be shifted after
every D Flip Flop.
Figure 7.9: Input to R1 and R2 at 200 kHz. Figure 7.12: C3 and C4 outputs with 200 kHz

Figure7.10: Input to R3 and R4 at 200 kHz.

Figure 7.13: C1 and C2 outputs with 400 kHz

Figure 7.11: C1 and C2 outputs at 200 kHz

Figure 7.14: C3 and C4 outputs at 400 kHz.
 In the early figures it is easy to see that the values
go up to VDD or go down to Ground and stay there
for a while, but when looking at this figure it only
stays high for a short period. This could cause
devices that are being used to read the values out of
this circuit to read errors because it wasn’t actually
high for long enough.

7.4. DISCUSSION AND

CONCLUSION:

In conclusion, if the memory that you want needs

to be unchangeable, fast and will still be there
when no power is supplied then ROM is the
memory is the memory you need. In this
Figure 7.15: C1 and C2 outputs at 800 kHz.
experiment we learned that a problem with using
two separate function generators to control our
inputs and the shift register that we are going to get
an asynchronous circuit which will have trouble in
the future. We saw that because they are not sync
with each that the readings will be hard to read due
to that fact that there will be phase shifts all the
time due having two clocks.

REFERENCES

4. “Serial – in / serial – out Shift Register”

http://www.allaboutcircuits.com/vol_4/chpt_1
2/2.html
5. http://www.sti.uniurb.it/bogliolo/didattica/prog
Figure 7.16: C3 and C4 outputs at 800 kHz. el/CDes-16.slides.2.pdf

Figures 7.11 through to 7.16 shows the readings

from the bit line at different frequencies and it is
seen that as the frequency increases the output
signal becomes harder to read due to transistor
limitations. With respect to figure 7.16, it is
reading bit line C3 and C4 where each bit line is
supposed to read:
C3  1 0 1 0
C4  1 1 1 0
 DESIGN, SIMULATION AND EXPERIMENTAL TEST OF
VOLTAGE CONTROLLED OSCILLATOR

Edgar Siles & Christian Gil

California State University, Northridge, College of Engineering and

Computer Science, Electrical and Computer Engineering Department
Edgarsiles88@yahoo.com, Christiangil88@gmail.com

Abstract:

The simulation and experimental

implementation of a seven stage voltage control 8.2 PROCEDURES, SIMULATION AND
oscillator. The experiment demonstrates how the EXPERIMENTAL SET-UP
VCO has a linear correlation between the voltage
applied as a source and the frequency at which it The pre-lab work was to explain in general
oscillates. terms how the VCO works. This design controls
the oscillation frequency with the DC voltage to
Keywords: seven stage voltage controlled which the inverters are running at. This then
oscillator, VCO, ring voltage controlled oscillator. propagates to a liner relation between DC voltage
and the period at which the inverters are working
8.1 INTRODUCTION at. The second part stated to relate the time delay of
the inverter with the voltage controlling it. So if N=
The voltage controlled oscillator is one of the the number of inverters, and τ = the time delay per
major components in signal analysis and inverter:
modulation. This oscillator is of special concern
since it is one that has an easy implementation and Ƒosc = Is/(2*N*Vtcrl *C) since the slew rate is
can be tuned very easily. It is highly implemented τ=CVcrtl/Is
in Phase lock loop for frequency generation. Here
the VCO is simulated, tested and implemented, by For the last part of the pre-lab work the number of
testing its linearity. The experiment also explores inverters was changed to 11 from 7, and required
the propagation delay found in the circuit. Fig.8.1 knowing whether Vctrl was increased or decreased
illustrates the overview design. The theory behind to keep the same oscillation. Vctrl mus be lowered
it is very similar to that of the ring oscillator just because the time delay was increased by adding
changing the fact that number of stages no longer inverters to the design. This means that at the same
controls the oscillation frequency. voltage there is more capacitance causing a longer
propagation delay and since frequency of
oscillation is inversely proportional it would
require to be lowered.
The procedure involved using the CD4007
IC chips to implement the 7-stage ring oscillator,
with the modification of the Vdd of the design be
Fig. 8.1 Vctrl and it would be manually controlled. Before
implementing the design it was simulated using
PSICE to see the voltage to oscillation relation.

Fig. 8.5 VCO when Vcrtl = 2.25V

[Units of Each Plot: 0-5V vs. 0-5ns]

Fig. 8.2 The Pspice implementation 7 stage VCO Frequency VS Vcntrl

1.0000E+07
8.0000E+06

Freq Hz
6.0000E+06
y = 537703x Series
4.0000E+06
R² = 0.812 2
2.0000E+06
0.0000E+00
1 3 5 7 9 11 13
Vcntrl V

Fig. 8.3 VCO when Vcrtl = 2.25V Fig. 8.6 Plot that results from the PSpice
[Units of Each Plot: 0-3V vs. 0-15µs] implementation

8.3. SIMULATION AND EXPERIMENTAL

RESULTS

Once all the simulation were correct, the

implementation step followed, this meant building
the design using the CD4007 IC chips. In this
experiment simulation the implementation of the
design are not entirely accurate. This is due to the
parameters used in the PSPICE calculations. They
are average values of the IC used but do not
Fig. 8.4 VCO when Vcrtl = 2.25V represent the exact model therefore yielding a
[Units of Each Plot: 0-4V vs. 0-5µs] small error in simulation and implementation
results
 Frequency VS Vcntrl
1.0000E+06
8.0000E+05
Freq Hz

6.0000E+05
y = 56891x Series
4.0000E+05
R² = 0.9551 2
2.0000E+05
0.0000E+00
1 3 5 7 9 11 13
Vcntrl V

Fig. 8.7 The relation of frequency vs voltage of the

implemented design. Fig. 8.9 The VCO running at 5V and 1.60MHz

Fig. 8.8 The VCO running at 3.5V and 535KHz Fig. 8.10 The propagation delay High to Low equal
to 216 ns
 circuitry to solve the issue. A simple solution
would be to add an inverter at the output to have a
full logic voltage swing.
The voltage controlled oscillator has many
implementations which are suitable in specific
implementation. Some of the few that were
researched were the integrator and the grounded
capacitor. The integrator type oscillator is as
reliable as the ring VCO but requires a harder
technique to tune and set the central frequency. The
grounded capacitor is of much easier
implementation since it can be implemented in as
little as two inverters but it has reliability issues if
not properly set up. The ring VCO is the moderate
Fig. 8.11 the propagation delay Low to
selection between both of the designs.
High equal to 208 ns.
REFERENCES
[1] Sedra/Smith, Microelectronic circuits 6th
8.4. DISCUSSION AND CONCLUSION:
edition.
[2]Wikepedia, 2012.
In comparison to the first ring oscillator this
http://en.wikipedia.org/wiki/Voltage-
design is better in terms of controlling the delay
controlled_oscillator
between stages since it does not require the
[3]Falstad 2012. http://www.falstad.com/circuit/e-
addition of components. But its drawback is that
vco.html
the voltage swing is only as big as the input as the
control voltage, meaning there must be extra
 Design of Cascode Voltage Switch Logic

Christian Gil and Edgar Siles

California State University, Northridge, College of Engineering and

Computer Science, Electrical and Computer Engineering Department
Christiangil88@gmail.com, edgarsiles88@yahoo.com

Abstract: Figure 9.1 represents a differential cascode

voltage switch logic (DCVSL) circuit which if not
In this report the details of how to construct a supplied with a differential section represents a
CVSL (Cascode Voltage Switch Logic) circuit are regular CVSL circuit. The special design of a
explained and the purpose of using this type of CVSL allows it to be able to when presented with a
circuit. It will explain how it uses complementary low input it will switch to a low output and vice
inputs and computes “true” outputs. versa for high inputs.

Keywords: 9.2. PROCEDURES, SIMULATION AND

EXPERIMENTAL SET-UP
CVSL, NMOS, PMOS, pull down logic.
The construction of a CVSL requires the
9.1. INTRODUCTION use of two PMOS used as the pull up network and
two NMOSs for the pull down network. If we had
Creating a cascade voltage switch logic wanted to create the DCVSL circuit then it would
circuit is an important concept that can be used to just require more NMOSs to implement the logic.
implement inputs that will be able to output “true” It also requires an inverter for every input to the
outputs. pull down network.

Figure 9.1: Differential Cascode Voltage Switch Figure 9.2: CVSL circuit design.
Logic.
 The way this circuit works is that the input
logic is connected to one NMOS while the inverter
input gets inputted to the other NMOS’s gate.
These NMOS’s drains are then connected to the
PMOS’s drain above it and the PMOS’s gate that is
opposite of the prior PMOS. That connection is
where the output is read. If the connection was
from the Input’s NMOS then the output reading
will be Output_Bar while vice versa for the
input_bar readings.

The way this circuit operates though is that

when the input is high output_bar will have a path
to ground. When output_bar is grounded then the
Figure 9.4: Practical reading of un-sized CVSL
PMOS gate that is connected to will then allow for
These circuits show that when the input
output to be pulled to VDD. This is what it means
level of the signal is too high then the output will
that the outputs will be “True” outputs because
not be able to pull the output all the way down. The
what you input is what you get as output.
output_bar tries to be pulled down but is never able
to go all the way to down to ground and that will
9.3 SIMULATION AND
not allow for the other PMOS to turn on and let
EXPERIMENTAL RESULTS
Output to go VDD.
The Next figures represent the data
After the construction of the CVSL circuit
simulated and read from an oscilloscope of the
in PSPICE and on the solder-less board multiple
CVSL circuit after the NMOS logic was sized
tests were implemented to check the functionality
correctly. It is noticed that now the outputs are able
of the circuit. Figure 9.3 and 9.4 show the results
to correctly switch from high to low based on the
from the first test where if the circuit is provided
inputs.
with these circumstances:
The different input frequencies that were
Input Level: 1.9 to 4.9 Volts.
used to test this circuit were 100 kHz, 300 kHz and
Output Level: Standard 5Volts.
600 kHz. As the inputs increased in frequency the
Input Frequency: 100 kHz.
phase shifts of the outputs increased a little bit and
that is due to the limitations of the transistors.

Figure 9.3: un-sized simulation of CVSL circuit

Figure 9.5: 100 kHz CVSL Simulation sized.
Figure 9.6: 100 kHz yellow is output and blue is Figure 9.9: 300 kHz: Yellow is Output_bar, Blue is
input Input.

Figure 9.7: 100 kHz Input vs Input_bar

Figure 9.10: 600 kHz simulation.

Figure 9.8: 300 kHz CVSL simulation Sized

Figure 9.11: 600 kHz wave, Blue is input and
Yellow is output.
 diagram will the input_bar and output_bar was on
the other side. This experiment required that they
be opposite of that.

We learned that using a Cascode Voltage

Switch circuit will provide the complement and un-
complemented logic which is especially important
when working with high speed logic systems. An
example of how this works would have been easy
to show by making the input a series connection.
Usually in this case the output would be a NAND
output but do to the features of CVSL it is possible
to get the NAND output from Output_bar and
AND from just Output.
Figure 9.12: 600 kHz, Blue is output and Yellow is
Output_bar
This lab also brought to light the
importance of proper sizing of transistors when
As shown in the last figure when the
working with level shifting logic. This circuit is
frequency gets high the signal is not able to be
able to switch from VDD to Ground and from
pulled up and down fast enough to make good even
Ground to VDD even though the input doesn’t
square waves. This could be fixed by re-adjusting
cross the normal voltage threshold.
the sizing of both the PMOS and NMOS so that the
switching voltage is easier to bypass.
REFERENCES
9.4. DISCUSSION AND
[1]http://www.ieee.org/portal/site/sscs/menuitem.8
CONCLUSION:
2c662ad8f3c2e3deef9cf105bac26c8/index.jsp?&p
Name=sscs_print_only&TheCat=&path=sscs/07Sp
In conclusion, after performing this lab it
ring&file=Bernstein.xml
was easy to understand the importance of not just
following instructions without understanding the
concept of the design. In this experiment the
diagram used as the base of our CVSL had an error
in the name of the readings. The diagram had the
input and output all on the same side of the