DMOS Microstepping Driver With Translator: Description Features and Benefits

A3984
DMOS Microstepping Driver with Translator
Features and Benefits Description

▪ Low RDS(ON) outputs The A3984 is a complete microstepping motor driver with
▪ Automatic current decay mode detection/selection built-in translator for easy operation. It is designed to
▪ Mixed and Slow current decay modes operate bipolar stepper motors in full-, half-, quarter-, and
▪ Synchronous rectification for low power dissipation sixteenth-step modes, with an output drive capacity of up to
▪ Internal UVLO and thermal shutdown circuitry 35 V and ±2 A. The A3984 includes a fixed off-time current
▪ Crossover-current protection regulator which has the ability to operate in Slow or Mixed
decay modes.
The translator is the key to the easy implementation of the
A3984. Simply inputting one pulse on the STEP input drives
the motor one microstep. There are no phase sequence
tables, high frequency control lines, or complex interfaces to
program. The A3984 interface is an ideal fit for applications
where a complex microprocessor is unavailable or is
overburdened.
Package: 24-pin TSSOP with exposed
The chopping control in the A3984 automatically selects
thermal pad (suffix LP) the current decay mode (Slow or Mixed). When a signal
occurs at the STEP input pin, the A3984 determines if
that step results in a higher or lower current in each of the
motor phases. If the change is to a higher current, then
the decay mode is set to Slow decay. If the change is to a
lower current, then the current decay is set to Mixed (set
Not to scale Continued on the next page…
Pin-out Diagram
CP1 1 24 GND
Charge
Pump
CP2 2 23 ENABLE
VCP 3 22 OUT2B
Reg
VREG 4 21 VBB2
MS1 5 20 SENSE2
& Control Logic
MS2 6 19 OUT2A
Translator
RESET 7 18 OUT1A
OSC
ROSC 8 17 SENSE1
SLEEP 9 16 VBB1
VDD 10 15 OUT1B
STEP 11 14 DIR
REF 12 13 GND
26184.30E
A3984 DMOS Microstepping Driver with Translator
Description (continued)
initially to a fast decay for a period amounting to 31.25% of Internal circuit protection includes: thermal shutdown with
the fixed off-time, then to a slow decay for the remainder of the hysteresis, undervoltage lockout (UVLO), and crossover-current
off-time). This current decay control scheme results in reduced protection. Special power-on sequencing is not required.
audible motor noise, increased step accuracy, and reduced power
dissipation. The A3984 is supplied in a low-profile (1.2 mm maximum),
Internal synchronous rectification control circuitry is provided to 24-pin TSSOP with exposed thermal pad (package LP). It is lead
improve power dissipation during PWM operation. (Pb) free, with 100% matte tin leadframe plating.
Selection Guide
Part Number Packing
A3984SLPTR-T 4000 pieces per 13-in. reel
Absolute Maximum Ratings

Characteristic Symbol Notes Rating Units
Load Supply Voltage VBB 35 V
Output current rating may be limited by duty cycle, ambient
temperature, and heat sinking. Under any set of conditions,
Output Current IOUT ±2 A
do not exceed the specified current rating or a junction tem-
perature of 150°C.
Logic Input Voltage VIN –0.3 to 7 V
Sense Voltage VSENSE 0.5 V
Reference Voltage VREF 4 V
Operating Ambient Temperature TA Range S –20 to 85 ºC
Maximum Junction TJ(max) 150 ºC
Storage Temperature Tstg –55 to 150 ºC
THERMAL CHARACTERISTICS
Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance RθJA 4-layer PCB, based on JEDEC standard 28 ºC/W
*Additional thermal information available on Allegro Web site.

Maximum Power Dissipation, PD(max)
5.5
5.0
4.5
Power Dissipation, PD (W)
4.0
(R
3.5 θJ
A =
28
3.0 ºC
/W
2.5 )
2.0
1.5
1.0
0.5
0.0
20 40 60 80 100 120 140 160 180
Temperature (°C)
Allegro MicroSystems, LLC 2

115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Block Diagram
0.1 uF
0.22 uF
VREG ROSC CP1 CP2
VDD Current Charge

OSC
Regulator Pump
VCP
REF 0.1 uF
DMOS Full Bridge

VBB1
DAC OUT1A
OUT1B
PWM Latch
Blanking
Mixed Decay SENSE1
STEP Gate RS1

Drive DMOS Full Bridge
DIR VBB2
RESET Control
Translator
Logic
MS1 OUT2A
MS2 OUT2B
PWM Latch
ENABLE Blanking SENSE2
Mixed Decay
SLEEP RS2
DAC
VREF

ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VBB = 35 V (unless otherwise noted)

Characteristics Symbol Test Conditions Min. Typ.2 Max. Units
Output Drivers
Operating 8 – 35 V
Load Supply Voltage Range VBB
During Sleep Mode 0 – 35 V
Logic Supply Voltage Range VDD Operating 3.0 – 5.5 V
Source Driver, IOUT = –1.5 A – 0.350 0.450 Ω
Output On Resistance RDSON
Sink Driver, IOUT = 1.5 A – 0.300 0.370 Ω
Source Diode, IF = –1.5 A – – 1.2 V
Body Diode Forward Voltage VF
Sink Diode, IF = 1.5 A – – 1.2 V
fPWM < 50 kHz – – 4 mA
Motor Supply Current IBB Operating, outputs disabled – – 2 mA
Sleep Mode – – 10 μA
fPWM < 50 kHz – – 8 mA
Logic Supply Current IDD Outputs off – – 5 mA
Sleep Mode – – 10 μA
Control Logic
VIN(1) VDD0.7 – – V
Logic Input Voltage
VIN(0) – – VDD0.3 V
IIN(1) VIN = VDD0.7 –20 <1.0 20 μA
Logic Input Current
IIN(0) VIN = VDD0.3 –20 <1.0 20 μA
Microstep Select 2 MS2 – 50 – kΩ
Input Hysteresis VHYS(IN) 150 300 500 mV
Blank Time tBLANK 0.7 1 1.3 μs
OSC > 3 V 20 30 40 μs
Fixed Off-Time tOFF
ROSC = 25 kΩ 23 30 37 μs
Reference Input Voltage Range VREF 0 – 4 V
Reference Input Current IREF –3 0 3 μA
VREF = 2 V, %ITripMAX = 38.27% – – ±15 %
Current Trip-Level Error3 errI VREF = 2 V, %ITripMAX = 70.71% – – ±5 %
VREF = 2 V, %ITripMAX = 100.00% – – ±5 %
Crossover Dead Time tDT 100 475 800 ns
Protection
Thermal Shutdown Temperature TJ – 165 – °C
Thermal Shutdown Hysteresis TJHYS – 15 – °C
UVLO Enable Threshold UVLO VDD rising 2.35 2.7 3 V
UVLO Hysteresis UVHYS 0.05 0.10 – V
1Negative current is defined as coming out of (sourcing from) the specified device pin.
2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for
individual units, within the specified maximum and minimum limits.
3err 
I = (ITrip – IProg ) ⁄ IProg , where IProg = %ITripMAX ITripMAX.

tA tB
STEP
tC tD
MS1, MS2,
RESET, or DIR
Time Duration Symbol Typ. Unit

STEP minimum, HIGH pulse width tA 1 μs
STEP minimum, LOW pulse width tB 1 μs
Setup time, input change to STEP tC 200 ns
Hold time, input change to STEP tD 200 ns
Figure 1. Logic Interface Timing Diagram
Table 1. Microstep Resolution Truth Table

MS1 MS2 Microstep Resolution Excitation Mode
L L Full Step 2 Phase
H L Half Step 1-2 Phase
L H Quarter Step W1-2 Phase
H H Sixteenth Step 4W1-2 Phase

Functional Description
Device Operation. The A3984 is a complete microstep- Microstep Select (MS1 and MS2). Selects the micro-
ping motor driver with a built-in translator for easy operation stepping format, as shown in table 1. MS2 has a 50 kΩ pull-
with minimal control lines. It is designed to operate bipolar down resistance. Any changes made to these inputs do not take
stepper motors in full-, half-, quarter-, and sixteenth-step effect until the next STEP rising edge.
modes. The currents in each of the two output full-bridges
and all of the N-channel DMOS FETs are regulated with Direction Input (DIR). This determines the direction of
fixed off-time PMW (pulse width modulated) control cir- rotation of the motor. When low, the direction will be clock-
cuitry. At each step, the current for each full-bridge is set by wise and when high, counterclockwise. Changes to this input
the value of its external current-sense resistor (RS1 or RS2), a do not take effect until the next STEP rising edge.
reference voltage (VREF), and the output voltage of its DAC Internal PWM Current Control. Each full-bridge is
(which in turn is controlled by the output of the translator). controlled by a fixed off-time PWM current control circuit
At power-on or reset, the translator sets the DACs and the that limits the load current to a desired value, ITRIP . Ini-
phase current polarity to the initial Home state (shown in fig- tially, a diagonal pair of source and sink DMOS outputs are
ures 2 through 5), and the current regulator to Mixed Decay enabled and current flows through the motor winding and
Mode for both phases. When a step command signal occurs the current sense resistor, RSx. When the voltage across RSx
on the STEP input, the translator automatically sequences the equals the DAC output voltage, the current sense compara-
DACs to the next level and current polarity. (See table 2 for tor resets the PWM latch. The latch then turns off either the
the current-level sequence.) The microstep resolution is set source DMOS FETs (when in Slow Decay Mode) or the sink
by the combined effect of inputs MS1 and MS2, as shown in and source DMOS FETs (when in Mixed Decay Mode).
table 1. The maximum value of current limiting is set by the selec-
When stepping, if the new output levels of the DACs are tion of RSx and the voltage at the VREF pin. The transcon-
lower than their previous output levels, then the decay mode ductance function is approximated by the maximum value of
for the active full-bridge is set to Mixed. If the new output current limiting, ITripMAX (A), which is set by
levels of the DACs are higher than or equal to their previous
levels, then the decay mode for the active full-bridge is set ITripMAX = VREF / ( 8  RS )
to Slow. This automatic current decay selection improves
where RS is the resistance of the sense resistor (Ω) and VREF
microstepping performance by reducing the distortion of
is the input voltage on the REF pin (V).
the current waveform that results from the back EMF of the
motor. The DAC output reduces the VREF output to the current
sense comparator in precise steps, such that
RESET Input (RESET). The RESET input sets the
translator to a predefined Home state (shown in figures 2
Itrip = (%ITripMAX / 100) × ITripMAX
through 5), and turns off all of the DMOS outputs. All STEP (See table 2 for %ITripMAX at each step.)
inputs are ignored until the RESET input is set to high.
It is critical that the maximum rating (0.5 V) on the SENSE1
Step Input (STEP). A low-to-high transition on the STEP and SENSE2 pins is not exceeded.
input sequences the translator and advances the motor one Fixed Off-Time. The internal PWM current control cir-
increment. The translator controls the input to the DACs and cuitry uses a one-shot circuit to control the duration of time
the direction of current flow in each winding. The size of that the DMOS FETs remain off. The one shot off-time, tOFF,
the increment is determined by the combined state of inputs is determined by the selection of an external resistor con-
MS1 and MS2. nected from the ROSC timing pin to ground. If the ROSC

pin is tied to an external voltage > 3 V, then tOFF defaults to 30 μs. are disabled until the fault condition is removed. At power-on, the
The ROSC pin can be safely connected to the VDD pin for this UVLO (undervoltage lockout) circuit disables the DMOS outputs
purpose. The value of tOFF (μs) is approximately and resets the translator to the Home state.
tOFF = ROSC ⁄ 825
Sleep Mode (SLEEP). To minimize power consumption when
Blanking. This function blanks the output of the current sense
the motor is not in use, this input disables much of the internal
comparators when the outputs are switched by the internal current
control circuitry. The comparator outputs are blanked to prevent circuitry including the output DMOS FETs, current regulator,
false overcurrent detection due to reverse recovery currents of the and charge pump. A logic low on the SLEEP pin puts the A3984
clamp diodes, and switching transients related to the capacitance of into Sleep mode. A logic high allows normal operation, as well as
the load. The blank time, tBLANK (μs), is approximately start-up (at which time the A3984 drives the motor to the Home
microstep position). When emerging from Sleep mode, in order to
tBLANK ≈ 1 μs
allow the charge pump to stabilize, provide a delay of 1 ms before
Charge Pump (CP1 and CP2). The charge pump is used to issuing a Step command.
generate a gate supply greater than that of VBB for driving the
source-side DMOS gates. A 0.1 μF ceramic capacitor, should be Mixed Decay Operation. The bridge can operate in Mixed
connected between CP1 and CP2. In addition, a 0.1 μF ceramic
Decay mode, depending on the step sequence, as shown in figures
capacitor is required between VCP and VBB, to act as a reservoir
for operating the high-side DMOS gates. 3 thru 5. As the trip point is reached, the A3984 initially goes into
a fast decay mode for 31.25% of the off-time. tOFF. After that, it
VREG (VREG). This internally-generated voltage is used to switches to Slow Decay mode for the remainder of tOFF.
operate the sink-side DMOS outputs. The VREG pin must be
decoupled with a 0.22 μF capacitor to ground. VREG is internally
monitored. In the case of a fault condition, the DMOS outputs of Synchronous Rectification. When a PWM-off cycle is
the A3984 are disabled. triggered by an internal fixed–off-time cycle, load current recir-
culates according to the decay mode selected by the control logic.
Enable Input (ENABLE). This input turns on or off all of the
This synchronous rectification feature turns on the appropriate
DMOS outputs. When set to a logic high, the outputs are disabled.
When set to a logic low, the internal control enables the outputs as FETs during current decay, and effectively shorts out the body
required. The translator inputs STEP, DIR, MS1, and MS2, as well diodes with the low DMOS RDSON. This reduces power dissipa-
as the internal sequencing logic, all remain active, independent of tion significantly, and can eliminate the need for external Schottky
the ENABLE input state. diodes in many applications. Turning off synchronous rectification
Shutdown. In the event of a fault, overtemperature (excess TJ) prevents the reversal of the load current when a zero-current level is
or an undervoltage (on VCP), the DMOS outputs of the A3984 detected.

STEP STEP
100.00 100.00
70.71 70.71
Slow Slow Slow
Phase 1 Slow Phase 1 Mixed Mixed Mixed
IOUT1A 0.00
IOUT1A 0.00
Direction = H Direction = H
Home Microstep Position


(%) (%)
–70.71 –70.71
–100.00 –100.00
100.00 100.00
70.71 70.71
Slow Slow Slow Slow
Phase 2 Phase 2 Mixed Mixed Mixed
IOUT2A IOUT2B
0.00 0.00
Direction = H Direction = H
(%) Slow (%)
–70.71 –70.71
–100.00 –100.00
Figure 2. Decay Mode for Full-Step Increments Figure 3. Decay Modes for Half-Step Increments
STEP
100.00
92.39
70.71
38.27
Phase 1
Slow Mixed Slow Mixed Slow
IOUT1A
0.00
Direction = H
(%) –38.27
–70.71
–92.39
–100.00
100.00
92.39
70.71
38.27 Slow
Phase 2
Mixed Slow Mixed Slow Mixed
IOUT2B
0.00
Direction = H
(%) –38.27
–70.71
–92.39
–100.00
Figure 4. Decay Modes for Quarter-Step Increments

STEP
100.00
95.69
88.19
83.15
77.30
70.71
63.44
55.56
47.14
38.27
29.03
19.51
Phase 1 9.8
IOUT1A Slow Mixed Slow Mixed
0.00
Direction = H –9.8
(%)
–19.51
–29.03
–38.27
–47.14
–55.56
–63.44
–70.71
–77.30
–83.15
–88.19
–95.69
–100.00
100.00
95.69
88.19
83.15
77.30
70.71
63.44
55.56
47.14
38.27
29.03
19.51
Slow
Phase 2 9.8
IOUT2B Mixed Slow Mixed Slow
0.00
Direction = H
–9.8
(%)
–19.51
–29.03
–38.27
–47.14
–55.56
–63.44
–70.71
–77.30
–83.15
–88.19
–95.69
–100.00
Figure 5. Decay Modes for Sixteenth-Step Increments

Table 2. Step Sequencing Settings

Home microstep position at Step Angle 45º; DIR = H
Phase 1 Phase 2 Phase 1 Phase 2
Full Half 1/4 1/16 Current Current Step Full Half 1/4 1/16 Current Current Step
Step Step Step Step [% ItripMax] [% ItripMax] Angle Step Step Step Step [% ItripMax] [% ItripMax] Angle
# # # # (%) (%) (º) # # # # (%) (%) (º)
1 1 1 100.00 0.00 0.0 5 9 33 –100.00 0.00 180.0
2 99.52 9.80 5.6 34 –99.52 –9.80 185.6
3 98.08 19.51 11.3 35 –98.08 –19.51 191.3
4 95.69 29.03 16.9 36 –95.69 –29.03 196.9
2 5 92.39 38.27 22.5 10 37 –92.39 –38.27 202.5
6 88.19 47.14 28.1 38 –88.19 –47.14 208.1
7 83.15 55.56 33.8 39 –83.15 –55.56 213.8
8 77.30 63.44 39.4 40 –77.30 –63.44 219.4
1 2 3 9 70.71 70.71 45.0 3 6 11 41 –70.71 –70.71 225.0
10 63.44 77.30 50.6 42 –63.44 –77.30 230.6
11 55.56 83.15 56.3 43 –55.56 –83.15 236.3
12 47.14 88.19 61.9 44 –47.14 –88.19 241.9
4 13 38.27 92.39 67.5 12 45 –38.27 –92.39 247.5
14 29.03 95.69 73.1 46 –29.03 –95.69 253.1
15 19.51 98.08 78.8 47 –19.51 –98.08 258.8
16 9.80 99.52 84.4 48 –9.80 –99.52 264.4
3 5 17 0.00 100.00 90.0 7 13 49 0.00 –100.00 270.0
18 –9.80 99.52 95.6 50 9.80 –99.52 275.6
19 –19.51 98.08 101.3 51 19.51 –98.08 281.3
20 –29.03 95.69 106.9 52 29.03 –95.69 286.9
6 21 –38.27 92.39 112.5 14 53 38.27 –92.39 292.5
22 –47.14 88.19 118.1 54 47.14 –88.19 298.1
23 –55.56 83.15 123.8 55 55.56 –83.15 303.8
24 –63.44 77.30 129.4 56 63.44 –77.30 309.4
2 4 7 25 –70.71 70.71 135.0 4 8 15 57 70.71 –70.71 315.0
26 –77.30 63.44 140.6 58 77.30 –63.44 320.6
27 –83.15 55.56 146.3 59 83.15 –55.56 326.3
28 –88.19 47.14 151.9 60 88.19 –47.14 331.9
8 29 –92.39 38.27 157.5 16 61 92.39 –38.27 337.5
30 –95.69 29.03 163.1 62 95.69 –29.03 343.1
31 –98.08 19.51 168.8 63 98.08 –19.51 348.8
32 –99.52 9.80 174.4 64 99.52 –9.80 354.4

Pin List Table
Name Description Number

CP1 Charge pump capacitor 1 1
CP2 Charge pump capacitor 2 2
VCP Reservoir capacitor 3
VREG Regulator decoupling 4
MS1 Logic input 5
MS2 Logic input 6
RESET Logic input 7
ROSC Timing set 8
SLEEP Logic input 9
VDD Logic supply 10
STEP Logic input 11
REF Current trip reference voltage input 12
GND Ground* 13
DIR Logic input 14
OUT1B DMOS Full Bridge 1 Output B 15
VBB1 Load supply 16
SENSE1 Sense resistor for Bridge 1 17
OUT1A DMOS Full Bridge 1 Output A 18
OUT2A DMOS Full Bridge 2 Output A 19
SENSE2 Sense resistor for Bridge 2 20
VBB2 Load supply 21
OUT2B DMOS Full Bridge 2 Output B 22
ENABLE Logic input 23
GND Ground* 24
*The two GND pins must be tied together externally by connecting
to the exposed pad ground plane under the device.

LP Package, 24-Pin TSSOP with Exposed Thermal Pad
0.65
7.80 ±0.10 0.45
4° ±4
24
+0.05
0.15 –0.06
B
3.00 4.40 ±0.10 6.40 ±0.20 0.60 ±0.15 3.00 6.10
A (1.00)
1 2
4.32
0.25
1.65
4.32
24X C SEATING PLANE
SEATING
0.10 C PLANE C PCB Layout Reference View
GAUGE PLANE
+0.05
0.25 –0.06 0.65
1.20 MAX For reference only
0.15 MAX (reference JEDEC MO-153 ADT)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (bottom surface)
C Reference land pattern layout (reference IPC7351
TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a multilayer
PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
Copyright ©2005-2013, Allegro MicroSystems, LLC

Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:

www.allegromicro.com


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A3984

DMOS Microstepping Driver with Translator

Features and Benefits Description

Not to scale Continued on the next page…

Absolute Maximum Ratings

*Additional thermal information available on Allegro Web site.

Allegro MicroSystems, LLC 2

Functional Block Diagram

VREG ROSC CP1 CP2

VDD Current Charge

DMOS Full Bridge

STEP Gate RS1

Allegro MicroSystems, LLC 3

ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VBB = 35 V (unless otherwise noted)

Allegro MicroSystems, LLC 4

Time Duration Symbol Typ. Unit

Table 1. Microstep Resolution Truth Table

Allegro MicroSystems, LLC 5

Allegro MicroSystems, LLC 6

Allegro MicroSystems, LLC 7

Home Microstep Position

Home Microstep Position

Home Microstep Position

Figure 4. Decay Modes for Quarter-Step Increments

Allegro MicroSystems, LLC 8

Figure 5. Decay Modes for Sixteenth-Step Increments

Allegro MicroSystems, LLC 9

Table 2. Step Sequencing Settings

Allegro MicroSystems, LLC 10

Pin List Table

Name Description Number

Allegro MicroSystems, LLC 11

LP Package, 24-Pin TSSOP with Exposed Thermal Pad

Copyright ©2005-2013, Allegro MicroSystems, LLC

For the latest version of this document, visit our website:

Allegro MicroSystems, LLC 12

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