HT12D
HT12D
Introduction:
HT12D is having 2^12 decoders are a series of CMOS LSIs (large scale integrated
circuits) for remote control system applications. It is an 18 Pin DIP/20 SOP package.
They are paired with Hotlink’s 2 12 series of encoders (refer to the encoder/decoder cross
reference table). For proper operation, a pair of encoder/decoder with the same number of
addresses and data format should be chosen. The decoders receive serial addresses and
data from a programmed 2 12 series of encoders that are transmitted by a carrier using an
RF or an IR transmission medium. They compare the serial input data three times
continuously with their local addresses. If no error or unmatched codes are found, the
input data codes are decoded and then transferred to the output pins. The VT pin also
goes high to indicate a valid transmission. The 2^12 series of decoders are capable of
decoding information that consist of N bits of address and 12_N bits of data. Of this
series, the HT12D is arranged to provide 8 address bits and 4 data bits, and HT12F is
used to decode 12 bits of address information.
Features:
PIN Diagram:
PIN Description:
A0~A11 (NMOS TRANSMISSION GATE) Input pins for address A0~A11 setting.
They can be externally set to VDD or VSS.
Operation:
The 2^12 series of decoders provides various combinations of addresses and data pins in
different packages so as to pair with the 2^12 series of encoders. The decoders receive
data that are transmitted by an encoder and interpret the first N bits of code period as
addresses and the last 12_N bits as data, where N is the address code number. A signal on
the DIN pin activates the oscillator which in turn decodes the incoming address and data.
The decoders will then check the received address three times continuously. If the
received address codes all match the contents of the decoder’s local address, the 12_N
bits of data are decoded to activate the output pins and the VT pin is set high to indicate a
valid transmission. This will last unless the address code is incorrect or no signal is
received. The output of the VT pin is high only when the transmission is valid. Otherwise
it is always low. Output type is latch (4 latch type data pins).
Address/Data sequence:
The following table provides address/data sequence for various models of the 2^12 series
of decoders. A correct device should be chosen according to the requirements of the
individual addresses and data.
Applications: