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Phison Electronics Corporation

Micro-SD 3.0 Memory Card

Specification
Non-UHS

(PS8035)

Version 1.1

All rights are strictly reserved. Any portion of this paper shall not be reproduced, copied, or
translated to any other forms without permission from Phison Electronics Corporation.

Document Number: S-12097

 Micro-SD 3.0 Memory Card Spec. v1.1

(PS8035)

Contents
A. General Description ............................................................................. 3
B. Features ................................................................................................ 4
C. Comparison of SD Card ....................................................................... 5
D. Pin Assignment .................................................................................... 6
E. Power Consumption ............................................................................ 8
F. Electrical Specifications ...................................................................... 8
G. DC Characteristic ................................................................................. 9
H. AC Characteristic ............................................................................... 10
H1. Micro SD Interface timing (Default) .......................................... 10
H2. Micro SD Interface timing (High-speed Mode) ......................... 12
H3. Flash Interface AC Characteristic ............................................. 14
H4. Flash memory timing ................................................................. 14
I. Dimension ........................................................................................... 16

Revision History
Revision History Draft Date Remark
1.0 First Release 2012-04-05 Cherry Li
1.1 Revised Physical Layer Specification Ver3.01 2012-08-13 Cherry Li

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A. General Description
The Micro Secure Digital (Micro SD) card version 3.0 is fully compliant to the specification

released by SD Card Association. The Command List supports [Part 1 Physical Layer

Specification Ver3.01 Final] definitions. Card Capacity of Non-secure Area, Secure Area

Supports [Part 3 Security Specification Ver3.0 Final] Specifications.

The Micro-SD 3.0 card is based on 8-pin interface, designed to operate at a maximum
operating frequency of 50MHz or 100MHz. It can alternate communication protocol between

the SD mode and SPI mode. It performs data error detection and correction with very low

power consumption. Its capacity could be more than 2GB and up to 16GB in the future with

FAT32 which is called Micro SDHC (Micro SD High Capacity).

Micro Secure Digital 3.0 card is one of the most popular cards today based on its high

performance, good reliability and wide compatibility.

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B. Features
 Support SD system specification version 2.0 and 3.0.

 Card Capacity of Non-secure Area, Secure Area Supports [Part 3 Security Specification
Ver3.1 Final] Specifications

 Support SD SPI mode

 Designed for read-only and read/write cards.

 Default mode : Variable clock rate 0-25MHz, up to 12.5MB/sec interface speed

 High-Speed mode : Variable clock rate 0-50MHz, up to 25MB/sec interface speed

 The Command List supports [Part 1 Physical Layer Specification Ver3.1 Final]
definitions

 Copyrights Protection Mechanism - Complies with highest security of SDMI standard

 Password Protection of cards (option)

 Built-in write protection features (permanent and temporary)]

 High transmission speed

 +4KV/-4KV ESD protection in contact pads.

 Dimension : 15mm(L) x 11mm(W) x 1mm(H)

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C. Comparison of SD Card
SD3.0 Standard SD3.0 SDHC
(Backward compatible to (Backward compatible to
2.0 host) 2.0 host)
Addressing Mode Byte (1 byte unit) Block (512 byte unit)
HCS/CCS bits of ACMD41 Support Support
CMD8 (SEND_IF_COND) Support Support
Support
CMD16 (SET_BLOCKLEN) Support
(Only CMD42)
Partial Read Support Not Support
Lock/Unlock Function Mandatory Mandatory
Write Protect Groups Optional Not Support
Supply Voltage 2.0v – 2.7v
Not Support Not Support
(for initialization)
Total Bus Capacitance for
40pF 40pF
each signal line
CSD Version
1.0 (0x0) 2.0 (0x1)
(CSD_STRUCTURE Value)
Mandatory
Speed Class Optional
(Class 2/4/6/10 )

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D. Pin Assignment

SD Mode SPI Mode

pin
Name Type1 Description Name Type Description
1 DAT2 I/O/PP Data Line[bit2] RSV
Card Detect/
2 CD/DAT3 2 I/O/PP 3 CS I3 Chip Select (neg true)
Data Line[bit3]
3 CMD PP Command/Response DI I Data In
4 VDD S Supply voltage VDD S Supply voltage
5 CLK I Clock SCLK I Clock
Supply voltage Supply voltage
6 VSS S VSS S
ground ground
7 DAT0 I/O/PP Data Line[bit0] DO O/PP Data Out
8 DAT1 I/O/PP Data Line[bit1] RSV

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(1) S: power supply, I:input; O:output using push-pull drivers; PP:I/O using push-pull drivers

(2) The extended DAT lines(DAT1-DAT3)are input on power up. They start to operate as DAT lines
after SET_BUS_WIDTH command. The Host shall keep its own DAT1-DAT3 lines in input mode,
as well, while they are not used. It is defined so, in order to keep compatibility to MultiMedia
Cards.

(3) At power up this line has a 50KOhm pull up enabled in the card. This resistor serves two functions
Card detection and Mode Selection. For Mode Selection, the host can drive the line high or let it
be pulled high to select SD mode. If the host wants to select SPI mode it should drive the line low.
For Card detection, the host detects that the line is pulled high. This pull-up should be
disconnected by the user during regular data transfer period , with
SET_CLR_CARD_DETECT(ACMD42) command.

Name Width Description

Card identification number; card individual number for identification.
CID 128bit
Mandatory
RCA1 Relative card address; local system address of a card, dynamically
16bit suggested by the card and approved by the host during initialization.
Mandatory
Driver Stage Register; to configure the card’s output drivers.
DSR 16bit
Optional
Card Specific Data; information about the card operation conditions.
CSD 128bit
Mandatory
SD Configuration Register; information about the SD Memory Card's
SCR 64bit
Special Features capabilities Mandatory
OCR 32bit Operation conditions register. Mandatory.
SD Status; information about the card proprietary features
SSR 512bit
Mandatory
Card Status; information about the card status
OCR 32bit
Mandatory

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E. Power Consumption
Table list as below is the power consumption of SD card with different type of flash memory.
(PS8035 + Flash Memory)

Max Power up Max Stand by Max Read Max Write

Flash mode
Current (uA) Current (uA) Current (mA) Current (mA)
(1)
Single
150 150 100@ 3.6V 100@ 3.6V
flash(1x8bit)
(1)Data transfer mode is single channel.

F. Electrical Specifications
Absolute Maximum Rating
Item Symbol Parameter MIN MAX Unit
1 VDD-VSS DC Power Supply -0.3 +3.3 V
2 VIN Input Voltage VSS-0.3 VDD+0.3 V
3 Ta Operating Temperature 0 +70 ℃
4 Tst Storage Temperature -25 +85 ℃

Parameter Symbol Min MAX Unit

Operating Temperature Ta 0 +70 ℃
VDD Voltage VDD 2.7 3.6 V

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G. DC Characteristic
 Threshold level for High Voltage Range
Parameter Symbol Min Max Unit Remarks
Supply voltage VDD 2.7 3.6 V
Output High Voltage VOH 0.75*VDD V IOH=-100uA VDDMin.
Output Low Voltage VOL 0.125*VDD V IOL = 100uA VDD min
Input High Voltage VIH 0.625*VDD VDD+0.3 V
Input Low Voltage VIL VSS-0.3 0.25 *VDD V
Power up time 250 ms from 0v to VDD min.

Bus Signal Levels

Bus signal levels

 General
Parameter Symbol Min Max. Unit Remarks
Peak voltage on all lines -0.3 VDD+0.3 V
All Inputs
Input Leakage Current -10 10 uA
All Outputs
Output Leakage Current -10 10 uA

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 Bus Signal Line Levels
Parameter symbol Min Max Unit Remark
Pull-up resistance RCMD 10 100 kΩ to prevent bus floating
RDAT
Total bus capacitance for each CL 40 pF 1 card
signal line CHOST+CBUS shall
not exceed 30 pF
Capacitance of the card for each CCARD 10 pF
signal pin
Maximum signal line inductance 16 nH fpp<20 MHz

Pull-up resistance inside card (pin1) RDAT3 10 90 kΩ May be used for

card detection

H. AC Characteristic
H1. Micro SD Interface timing (Default)

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Parameter Symbol Min Max Unit Remark

Clock CLK (All values are referred to min(VIH) and max(VIL)
Ccard≤ 10
Clock frequency Data fPP
0 25 MHz pF
Transfer Mode
(1 card)
Ccard≤ 10
Clock frequency
fOD 0(1)/100 400 kHz pF
Identification Mode
(1 card)
Ccard≤ 10
Clock low time tWL 10 ns pF
(1 card)
Ccard≤ 10
Clock high time tWH 10 ns pF
(1 card)
Ccard≤ 10
Clock rise time tTLH 10 ns pF
(1 card)
Ccard≤ 10
Clock fall time tTHL 10 ns pF
(1 card)
Inputs CMD, DAT (referenced to CLK)
Ccard≤ 10
Input set-up time tISU 5 ns pF
(1 card)
Ccard≤ 10
Input hold time tIH 5 ns pF
(1 card)
Outputs CMD, DAT (referenced to CLK)
Output Delay time during CL≤40 pF
tODLY 0 14 ns
Data Transfer Mode (1 card)
Output Delay time during CL≤40 pF
tODLY 0 50 ns
Identification Mode (1 card)

(1) 0Hz means to stop the clock. The given minimum frequency range is for cases were continues
clock is required.

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H2. Micro SD Interface timing (High-speed Mode)

Parameter Symbol Min Max Unit Remark

Clock CLK (All values are referred to min(VIH) and max(VIL)
Ccard≤ 10
Clock frequency Data fPP
0 50 MHz pF
Transfer Mode
(1 card)
Clock low time Ccard≤ 10
tWL 7 ns pF
(1 card)
Ccard≤ 10
Clock high time tWH 7 ns pF
(1 card)
Ccard≤ 10
Clock rise time tTLH 3 ns pF
(1 card)
Ccard≤ 10
Clock fall time tTHL 3 ns pF
(1 card)
Inputs CMD, DAT (referenced to CLK)
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Ccard≤ 10
Input set-up time tISU 6 ns pF
(1 card)
Ccard≤ 10
Input hold time tIH 2 ns pF
(1 card)
Outputs CMD, DAT (referenced to CLK)
Output Delay time during CL≤40 pF
tODLY 14 ns
Data Transfer Mode (1 card)
CL≤15 pF
Output Hold time TOH 2.5 50 ns
(1 card)
Total System capacitance of CL≤15 pF
CL 40 pF
each line¹ (1 card)
(1) In order to satisfy severe timing, host shall drive only one card.

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H3. Flash Interface AC Characteristic

Parameter Symbol Min Max Unit

CLE Set-up Time tCLS 50 - ns
CLE Hold Time tCLH 50 - ns
/CE Setup Time tCS 200 - ns
/CE Hold Time tCH 200 - ns
WE Pulse Width tWP 30 50 ns
ALE Setup Time tALS 50 - ns
ALE Hold Time tALH 50 - ns
Data Setup Time tDS 20 50 ns
Data Hold Time tDH 30 100 ns
Write Cycle Time tWC 50 200 ns
WE High Hold Time tWH 20 150 ns
Read Cycle Time tRC 50 - ns
/RE Pulse Width tRP 30 - ns
/RE High Hold Time tREH 20 - ns
Ready to /RE Low tRR 30 - ns

H4. Flash memory timing

(a) Command Latch Cycle

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(b) Address Latch Cycle

(c) Input Data Latch Cycle

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(d) Sequential Out Cycle after Read (CLE=L, /WE=H, ALE=L)

I. Dimension

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