TP2852

8051 MICROCONTROLLER WITH 8K FLASH AND ISP

General Description Features

The TP2852 is an 8-bit microcontroller which has an Fully static design of 8-bit CMOS microcontroller
in-system programmable FLASH EPROM for firmware Running clock up to 40MHz
updated. Its instruction set is fully compatible with 8K-byte FLASH EPROM
the standard 8051. It contains a 8K-byte FLASH Low standby current at full supply voltage
EPROM, 512-byte on-chip RAM, four 8-bit 512-byte on-chip RAM (including 256-byte
bi-directional and bit-addressable I/O ports, an AUX-RAM, software selectable)
additional 4-bit I/O port, three 16-bit timer/counters 64K-byte program memory address space and
and one serial port. 64K-byte data memory address space
Four 8-bit bi-directional ports
Applications One 4-bit multipurpose programmable port

Remote controller Three 16-bit timer/counters

LED controller One full duplex serial port

Toy Eight-source and two-level interrupt capability

Security Built-in power management

Communication Code protection

Industry control Two voltage types: 3.3V and 5V

Package Forms: DIP40, PLCC44 and PQFP44

Ordering Information
L: 3.3V
Voltage
TP2852 H: 5V
Package Type P: DIP
Package Type C: PLCC
Voltage Q: PQFP

Block Diagram

Data Sheet - Version 1.0 Page 1 of 18 http://www.topro.com.tw

May 2007
 TP2852
8051 MICROCONTROLLER WITH 8K FLASH AND ISP

Table of Contents

General Description…………………………………...1
Features………………………………………………....1
Applications…………………………………………….1
Ordering Information……………………………...…..1
Block Diagram………………………………………….1
Table of Contents……………………………………...2
Pin Configuration………………………………………3
Pin Description…………………………………………4
Functional Description…………………..……………4
Absolute Maximum Ratings…………………………..9
DC Electrical Characteristics…………...………….…9
AC Electrical Characteristics…………...……………10
Application Diagrams…………………………………11
Package Information…………………………………..15

Data Sheet - Version 1.0 Page 2 of 18 http://www.topro.com.tw

May 2007
 TP2852
8051 MICROCONTROLLER WITH 8K FLASH AND ISP

Pin Configuration

40-PIN DIP 44-PIN PQFP

P4.2,INT3

P0.0,AD0
P0.1,AD1
P0.2,AD2
P0.3,AD3
P1.4
P1.3
P1.2
P1.1
P1.0

VDD
44

43

42

41

40

39

38

37

36

35

34
P1.5 1 33 P0.4,AD4
P1.6 2 32 P0.5,AD5
P1.7 3 31 P0.6,AD6
RST 4 30 P0.7,AD7
RXD,P3.0 5 29 EA
INT2,P4.3 6 28 P4.1
TXD,P3.1 7 27 ALE
INT0,P3.2 8 26 PSEN
INT1,P3.3 9 25 P2.7,A15
T0,P3.4 10 24 P2.6,A14
T1,P3.5 11 23 P2.5,A13

12

13

14

15

16

17

18

19

20

21

22
WR,P3.6
RD,P3.7
XTAL2
XTAL1

A10,P2.2
A11,P2.3
A12,P2.4
P4.0
A8,P2.0
A9,P2.1
VSS

44-PIN PLCC
P1.1,T2EX

P4.2,INT3

P0.0,AD0
P0.1,AD1
P0.2,AD2
P0.3,AD3
P1.0,T2

VDD
P1.4
P1.3
P1.2

44

43

42

41

40
6

P1.5 7 39 P0.4,AD4
P1.6 8 38 P0.5,AD5
P1.7 9 37 P0.6,AD6
RST 10 36 P0.7,AD7
RXD,P3.0 11 35 EA
INT2,P4.3 12 34 P4.1
TXD,P3.1 13 33 ALE
INT0,P3.2 14 32 PSEN
INT1,P3.3 15 31 P2.7,A15
T0,P3.4 16 30 P2.6,A14
T1,P3.5 17 29 P2.5,A13
18

19

20

21

22

23

24

25

26

27

28
VSS
WR,P3.6
RD,P3.7
XTAL2
XTAL1

P4.0
A8,P2.0
A9,P2.1
A10,P2.2
A11,P2.3
A12,P2.4

Data Sheet - Version 1.0 Page 3 of 18 http://www.topro.com.tw

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8051 MICROCONTROLLER WITH 8K FLASH AND ISP

Pin Description
Symbol Type Description
EXTERIAL ACCESS ENABLE: This pin should be forced to high level and the program
EA I
counter is within the 64 KB area.

O/H PROGRAM STORE ENABLE: When internal ROM access is performed, no PSEN
PSEN
strobe signal output is originated from this pin.
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates the
ALE O/H address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. An ALE
pulse is omitted during external data memory accesses.
RESET: A high on this pin for two machine cycles resets the device while the oscillator is
RST I/L
running.
CRYSTAL 1: This is the crystal oscillator input. The pin may be driven by an external
XTAL1 I
clock.
XTAL2 O CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.
VSS I GROUND: Ground potential.
VDD I POWER SUPPLY: Supply voltage for operation.
P0.0 - P0.7 I/O/D PORT 0: Function is the same as that of standard 8051.
P1.0 - P1.7 I/O/H PORT 1: Function is the same as that of standard 8051.
P2.0 - P2.7 I/O/H PORT 2: Function is the same as that of standard 8051.
P3.0 - P3.7 I/O/H PORT 3: Function is the same as that of standard 8051.
P4.0 - P4.3 I/O/H PORT 4: A bi-directional I/O port with internal pull-ups.
NOTES: TYPE I: input; O: output; I/O: bi-directional; H: pull-high; L: pull-low; D: open drain.

Functional Description

The TP2852 architecture consists of a core controller with the MOVX instruction. Address pointers
surrounded by various registers, four general-purpose are R0 and R1 of the selected register bank and
I/O port, 512-byte RAM, three timer/counters, a serial DPTR register. The AUX-RAM is disabled
port. Its processor supports 111 different opcodes after a reset. Setting the bit 4 in CHPCON
and references, both 64K program address space and register will enable the access to on-chip
64K data storage space. AUX-RAM.

RAM Timers 0, 1, and 2

The internal data RAM of TP2852 has 512 bytes and Timers 0, 1, and 2 each consist of two 8-bit data
registers. These are called TL0 and TH0 for Timer 0,
is divided into two banks: scratchpad 256-byte RAM
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer
and 256-byte AUX-RAM. These RAMs are
2. The TCON and TMOD registers provide control
addressed by different ways: functions for timers 0 and 1. The T2CON register
provides control functions for Timer 2. RCAP2H and
RAM 00H-7FH can be addressed directly and RCAP2L are used as auto-reload or capture registers
indirectly as the same as in 8051. Address for Timer 2 as it in 8051.

pointers are R0 and R1 of the selected register The operations of Timer 0 and Timer 1 are the same
bank. as the standard 8051. Timer 2 is a 16-bit
timer/counter that is configured and controlled by the
RAM 80H-FFH can only be addressed indirectly T2CON register. Like timers 0 and 1, Timer 2 can

as the same as in 8051. Address pointers are operate as either an external event counter or as an
internal timer, depending on the setting of bit C/T2 in
R0 and R1 of the selected registers bank.
T2CON. Timer 2 has three operating modes:
capture, auto-reload, and baud rate generator. The
AUX-RAM 00H-FFH is addressed indirectly as
clock speed at capture or auto-reload mode is the
the same way to access external data memory
same as that of timers 0 and 1.

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8051 MICROCONTROLLER WITH 8K FLASH AND ISP

INT 2 / INT 3 EX3: External interrupt 3 enable if set.

Two additional external interrupts, INT 2 and IE3: If IT3 = 1, IE3 is set/cleared automatically by
INT 3 , whose functions are similar to those of hardware when interrupt is detected/serviced.
external interrupt 0 and 1 in the XICON (External
IT3: External interrupt 3 is falling-edge/low-level
Interrupt Control) register. The XICON register is
triggered when this bit is set/cleared by software.
bit-addressable but is not a standard register in the
standard 8051. Its address is at 0C0H. To set/clear PX2: External interrupt 2 priority high if set.
bits in the XICON register, one can use the “SETB
( INT 3 ) bit” instruction. EX2: External interrupt 2 enable if set.

XICON – external interrupt control IE2: If IT2 = 1, IE2 is set/cleared automatically by

(C0H) hardware when interrupt is detected/serviced.
PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2
IT2: External interrupt 2 is falling-edge/low-level
triggered when this bit is set/cleared by software.
PX3: External interrupt 3 priority high if set.

Eight-source Interrupt Information

Vector Polling Sequence Enable Required Interrupt Type
Interrupt Source
Address Within Priority Level Settings Edge/Level
External Interrupt 0 03H 0 (highest) IE.0 TCON.0
Timer/Counter 0 0BH 1 IE.1 -
External Interrupt 1 13H 2 IE.2 TCON.2
Timer/Counter 1 1BH 3 IE.3 -
Serial Port 23H 4 IE.4 -
Timer/Counter 2 2BH 5 IE.5 -
External Interrupt 2 33H 6 XICON.2 XICON.0
External Interrupt 3 3BH 7 (lowest) XICON.6 XICON.3

Watchdog Timer

The Watchdog timer is a free-running timer that can NOTES:

be programmed by the user to serve as a system ENW: Enable watchdog if set.
monitor, a time-base generator or an event timer. It CLRW: Clear watchdog timer and prescaler if set.
is basically a set of divider that divides the system This flag will be cleared automatically.
clock and the divider output is selectable and WIDL: If this bit is set, the watchdog is enabled under
determines the time-out interval for the time-out IDLE mode. If cleared, the watchdog is disabled
system monitor. This is important in the real-time under IDLE mode. Default is cleared.
control applications. In case of power glitches or WRST: watchdog reset flag
electro-magnetic interference, the processor may PS2, PS1, PS0: Watchdog prescaler timer select.
begin to execute errant code. If this is left Prescaler is selected when set PS2~0 as follows:
unchecked, the entire system may crash. The
PS2 PS1 PS0 Prescaler Select
watchdog time-out selection will result in different
0 0 0 2
time-out values depending on the clock speed, and 0 1 0 4
the watchdog timer will be disabled on reset. In 0 0 1 8
0 1 1 16
general, software should restart the watchdog timer to
1 0 0 32
put it into a known state. The control bits that 1 0 1 64
support the watchdog timer are discussed as follows: 1 1 0 128
1 1 1 256
Watchdog Timer Control Register (8FH)
Bit 7 6 5 4 3 2 1 0
ENW CLRW WIDL WRST - PS2 PS1 PS0

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8051 MICROCONTROLLER WITH 8K FLASH AND ISP

internal trigger circuit in the reset line is used to

Clock deglitch the reset line when the TP2852 is used with

The TP2852 should be used with either a crystal an external RC network. The reset logic also has a

oscillator or an external clock. Internally, the clock is special glitch removal circuit that ignores glitches on

divided by twelve before it is used by default. This the reset line. During reset, the ports are initialized

makes the TP2852 relatively insensitive to duty cycle to FFH, the stack pointer to 07H, PCON (with the

variations in the clock. exception of bit 4) to 00H, and all of the other SFR
registers except SBUF to 00H. SBUF is not reset.
Crystal Oscillator

The TP2852 incorporates a built-in crystal oscillator.

To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In
addition, a load capacitor must be connected from
each pin to ground, and a resistor must also be
connected from XTAL1 to XTAL2 to provide a DC bias
when the crystal frequency is above 24 MHZ.

External Clock

An external clock should be connected to pin XTAL1.

Pin XTAL2 should be left unconnected. The XTAL1
input is a CMOS-type input as required by the crystal
oscillator. Consequently, the external clock signal
should have an input of one level greater than 3.5
volts.

Power Management

Idle Mode

By setting the IDL bit in the PCON register, the idle

mode is set up. In the idle mode, the internal clock
to the processor is stopped. The peripherals and the
interrupt logic continue to be clocked. The processor
will exit idle mode when either an interrupt or a reset
occurs.

Power-down Mode

When the PD bit in the PCON register is set, the

processor enters the power-down mode. In this
mode, all of the clocks are stopped including the
oscillator. To exit from the power-down mode, it is by
a hardware reset or external interrupts INT 0 to
INT 3 when enabled and set to edge triggered.

Reset

The external RESET signal is sampled at S5P2. To

take effect, it must be held high for at least two
machine cycles while the oscillator is running. An

Data Sheet - Version 1.0 Page 6 of 18 http://www.topro.com.tw

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 TP2852
8051 MICROCONTROLLER WITH 8K FLASH AND ISP

TP2852 Special Function Registers (SFRs) and Reset Values

F8 FF
+B
F0 F7
00000000
ISP_CTRL ISP_ADDR
E8 EF
00000000 00000000
+ACC
E0 E7
00000000
+P4
D8 DF
xxxx1111
+PSW
D0 D7
00000000
+T2CON RCAP2L RCAP2H TL2 TH2
C8 CF
00000000 00000000 00000000 00000000 00000000
XICON
C0 C7
00000000
+IP CHPCON
B8 BF
00000000 0xx00000
+P3
B0 B7
00000000
+IE
A8 AF
00000000
+P2
A0 A7
11111111
+SCON SBUF
98 9F
00000000 xxxxxxxx
+P1
90 97
11111111
+TCON TMOD TL0 TL1 TH0 TH1 WDTC
88 8F
00000000 00000000 00000000 00000000 00000000 00000000 00000000
+P0 SP DPL DPH PCON
80 87
11111111 00000111 00000000 00000000 00110000

In-System Programming Control Register (CHPCON)

The TP2852 equips one main Flash EPROM bank of hardware. In the normal operation, the
8K bytes for application program, but it can be set for microcontroller executes the code in the 8K bytes. If
a 512-byte loader program and 7.5K-byte application the content of application program needs to be
program. User can enter ISP mode with two different modified, the TP2852 allows user to activate the
ways. One is by software, for example, using “JMP In-System Programming (ISP) mode by setting the
1E00h” to loader program address. The other is by CHPCON register.

CHPCON (BFH)
Bit Name Function
When this bit is and FPROGEN are set to 1, it will enforce microcontroller reset to initial
7 SWRESET
condition just like power on rest.
6 - Reserve.
5 - Reserve.
1: Enable on-chip AUX-RAM.
4 ENAUXRAM
0: Disable the on-chip AUX-RAM
3 - Reserve
2 0 Must set to 0.
1 0 Must set to 0
FLASH EPROM Programming Enable.
0 FPROGEN = 1: enable. The microcontroller enter the in-system programming mode.
= 0: disable. The on-chip flash memory is read-only. In-system programmability is disabled.

Data Sheet - Version 1.0 Page 7 of 18 http://www.topro.com.tw

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 TP2852
8051 MICROCONTROLLER WITH 8K FLASH AND ISP

ISP_CTRL(E8H)
The Reset Timing for Entering ISP Mode
Bit Name Function
7 ISP_EN 1:ISP enable
P2.7 Hi-Z
6 - Reserve.
5 - Reserve.
4 1 Must 1 P2.6 Hi-Z

3 0 Must 0
2 ERASE Erase bit RST
30ms
1 Write Program write into AUX RAM 10ms
0 READ Read program from AUX RAM

ISP_ADDR(E9H) Security
Bit Name Function
7 ADD7 Address bit 7 During the on-chip FLASH EPROM programming mode,
6 ADD6 Address bit 6
5 ADD5 Address bit 5 the FLASH EPROM can be programmed and verified
4 ADD4 Address bit 4
3 ADD3 Address bit 3 repeatedly. Until the code inside the FLASH EPROM is
2 ADD2 Address bit 2 confirmed OK, the code can be protected. The
1 ADD1 Address bit 1
0 ADD0 Address bit 0 protection of FLASH EPROM and those operations on it

are described below.

Hardware Enter ISP MODE

When the reset pin of TP2852 is at high level and any of The TP2852 has several Special Setting Registers,
the two conditions described below is fit in. including the Security Register that cannot be
programmed from low to high. They can only be reset
P4.3 P2.7 P2.6 Mode through erases-all operation.
X L L ISP
L X X ISP

Special Setting Registers

Lock bit

This bit is used to protect the customer’s program code finishes the programming and verifies the sequence.
in the TP2852. It may be set after the programmer Once this bit is set to logic 0, both the Flash EROM data

Data Sheet - Version 1.0 Page 8 of 18 http://www.topro.com.tw

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8051 MICROCONTROLLER WITH 8K FLASH AND ISP

and Setting Registers cannot be accessed again.

Absolute Maximum Ratings
(VDD-VSS = 5V ±10% for TP2852H, VDD-VSS = 3.3V ±10% for TP2852L)
Parameter Symbol Min Max Unit
DC Power Supply VDD-VSS -0.3 VDD+1 V
Input Voltage VIN VSS-0.3 VDD+0.3 V
Operation Temperature TA 0 70 °C
Storage Temperature TST -55 +150 °C
NOTE: Exposure to conditions beyond those listed under Absolute
Maximum Ratings may adversely affect the life and reliability of the
device.

DC Electrical Characteristics
(VDD-VSS = 5V ±10% for TP2852H, VDD-VSS = 3.3V ±10% for TP2852L, TA = 25°C,
Fosc = 12MHz, unless otherwise specified)
Parameter Symbol Min Max Unit Test Condition
Operating Voltage VDD 0.9 VDD 1.1 VDD V RST = 1, P0 = VDD
Operating Current IDD - 20/8 mA No load, VDD = 5V/3.3V
Idle Current IIDLE - 6/3 mA Idle mode, VDD = 5V/3.3V
Power-down mode,
Power Down Current IPWDN - 100 μA
VDD = 5V/3.3V
Input Current
IIN1 -50 +10 μA VIN = 0V or VDD
P1, P2, P3, P4
Input Current RST IIN2 -10 +300 μA 0＜VIN＜VDD
Input Low Voltage
VIL1 0 0.2VDD –0.2 V VDD
P0, P1, P3, P4, EA
Input Low Voltage RST VIL2 0 0.2VDD –0.2 V VDD
Input Low Voltage XTAL1﹝*4﹞ VIL3 0 0.2VDD –0.3 V VDD
Output Low Voltage
VIH1 3.5/2.6 VDD+0.2 V VDD = 5.5V/3.3V
P1, P2, P3, P4, EA
Input High Voltage RST VIH2 3.5/2.6 VDD+0.2 V VDD = 5.5V/3.3V
Input High Voltage XTAL1﹝*4﹞ VIH3 3.5/2.6 VDD+0.2 V VDD = 5.5V/3.3V
Output Low Voltage VDD = 5V/3.3V
VOL1 - 0.45 V
P1, P2, P3, P4 IOL = +2mA
Output Low Voltage VDD = 5V/3.3V,
VOL2 - 0.45 V
P0 , ALE, PSEN﹝*3﹞ IOL = +4mA
Sink Current
ISK1 - 8/6 mA VDD = 5V/3.3V, VIN = -0.45V
P1, P3, P4
Sink Current VDD = 5V/3.3V,
ISK2 - 8/6 mA
P0, P2, ALE, PSEN VIN = 0.45V
Output Low Voltage
VOH1 2.4/2.0 - V VDD = 5V/3.3V
P1, P2, P3, P4
Output High Voltage
VOH2 2.4/2.0 - V VDD = 5V/3.3V
P0 , ALE, PSEN﹝*3﹞
Source Current VDD = 5V/3.3V,
I S r1 -120/-80 -200/-120 μA
P0, P2, P3, P4 VIN = 2.4V
NOTES:
1. RST pin is an Schmitt trigger input.
2. P0, ALE and /PSEN are tested in the external access mode.
*3. XTAL1 is a CMOS input.
*4. Pins of P1, P2, P3 and P4 can source a transition current when they are being externally driven 1 to 0. The
transition current reaches its maximum value when VIN approximates to 2V.

Data Sheet - Version 1.0 Page 9 of 18 http://www.topro.com.tw

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 TP2852
8051 MICROCONTROLLER WITH 8K FLASH AND ISP

AC Electrical Characteristics

The AC specifications are a function of the particular process used to manufacture the part, the ratings of the I/O buffers, the
capacitive load, and the internal routing capacitance. Most of the specifications can be expressed in terms of multiple input
clock periods (TCP), and actual parts will usually experience less than a ±20 nS variation. The numbers below represent the
performance expected from a 0.6 micron CMOS process when using 2 and 4 mA output buffers.

Parameter Symbol Min Max Unit Test Conditions

Operating Speed FOP 0 40 MHz 1
Clock Period TCP 25 - nS 2
Clock High TCH 10 - nS 3
Clock Low TCL 10 - nS 3
NOTES:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL 1 input.

Clock lnput Waveform

XTAL1 TCH T CL
FOP. TCP

Data Read Cycle

Parameter Symbol Min. Typ. Max. Unit Notes
ALE Low to /RD Low TDAR 3 TCP-△ - -3 TCP+△ nS 1, 2
/RD Low to Data Valid TDDA - - 4 TCP nS 1
Data Hold from /RD High TDDH 0 - 2 TCP nS
Data Float from /RD High TDDZ 0 - 2 TCP nS
/RD Pulse Width TDRD 6 TCP-△ 6 TCP - nS 2
NOTES:
1. Data memory access time is 8 TCP.
2. 〝△〞（due to buffer driving delay and wire loading ）is 20 nS.

Data Write Cycle

Parameter Symbol Min. Typ. Max. Unit
ALE Low /WR Low TDAW 3 TCP-△ - 3 TCP nS
Data Valid to /WR Low TDAD 1 TCP-△ - - nS
Data Hold from /WR High TDWD 1 TCP-△ - - nS
/WR Pulse Width TDWR 6 TCP-△ 6 TCP - nS
NOTE: 〝△〞（due to buffer driving delay and wire loading ）is 20 nS.

Port Access Cycle

Parameter Symbol Min. Typ. Max. Unit
Port lnput Setup to ALE Low TPDS 1 TCP - - nS
Port lnput Hold from ALE Low TPDH 0 - - nS
Port Output to ALE TPDA 1 TCP - - nS
NOTES:
1. Ports are read during S5P2, and output data becomes available at the end of S6P2.
2. The timing data are referenced to ALE, since it provides a convenient reference.

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8051 MICROCONTROLLER WITH 8K FLASH AND ISP

Timing Waveforms

1. Data Read Cycle

S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3
XTAL1

ALE

PSEN

PORT 2 A8-A15

A0-A7 DATA
PORT 0

TDAR TDDA TDDH ,TDDZ

RD

TDRD

2. Data Write Cycle

S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3
XTAL1

ALE

PSEN

PORT 2 A8-A15

A0-A7
PORT 0 DATA OUT

TDAD TDWD

WR

TDAW TDWR

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8051 MICROCONTROLLER WITH 8K FLASH AND ISP

Timing Waveforms (continued)

3. Port Access Cycle

S5 S6 S1

XTAL1

ALE

TPDS T PDH TPDA

PORT DATA OUT

INPUT
SAMPLE

Data Sheet - Version 1.0 Page 12 of 18 http://www.topro.com.tw

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8051 MICROCONTROLLER WITH 8K FLASH AND ISP

Application Diagrams

1. Internal Program, Memory and Crystal

Figure A

CRYSTAL C1 C2 R2
6MHz 47P 47P -
16MHz 30P 30P -
24MHz 15P 15P -
32MHz 10P 10P 6.8K
40MHz 5P 5P 4.7K
NOTE: Above table shows the reference values for crystal applications.

Data Sheet - Version 1.0 Page 13 of 18 http://www.topro.com.tw

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 TP2852
8051 MICROCONTROLLER WITH 8K FLASH AND ISP

2. Expanded External Program and Data Memory and Oscillator

Figure B

Data Sheet - Version 1.0 Page 14 of 18 http://www.topro.com.tw

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8051 MICROCONTROLLER WITH 8K FLASH AND ISP

Package Information

40-pin DIP

Unit: Millimeter

Dimension in mm NOTES:
Symbol 1. Dimension D Max. includes mold flash or tie bar burrs.
Min. Nom. Max.
2. Dimension E1 does not include interlead flash.
A — — 5.588 3. Dimensions D and E1 include mold mismatch and are determined
at the mold parting line.
A1 0.381 — —
4. Dimension B1 does not include dam bar protrusion/intrusion.
A2 3.81 3.937 4.064 5. JEDEC Outline: MS-011 AC

B — 0.457 —

B1 — 1.27 —

D 52.197 52.324 52.578

E 15.24 BSC

E1 13.716 13.843 13.97

e1 — 2.54 —

L 2.921 3.302 3.81

a 0 177.8 381

eA 16.002 16.51 17.018

Data Sheet - Version 1.0 Page 15 of 18 http://www.topro.com.tw

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 TP2852
8051 MICROCONTROLLER WITH 8K FLASH AND ISP

44-pin PLCC
HD
D
6 1 44 40

7 39

GE
HE
E
17 29

18 28
c
GD

A2
A
L

e b b1 A1
Θ
Unit: Millimeter

Dimension in mm NOTES:
Symbol
Min. Nom. Max. 1. Dimensions D and E do not include interlead flash and
A — — 4.699 mold protrusion. Allowable protrusion is 10 mil per

A1 0.508 — — side.

A2 3.683 3.81 3.937 2. Dimension b1 does not include dam bar

b1 0.6604 0.7112 0.8128 protrusion/intrusion.

3. JEDEC Outline: M0-047 AC.
b 0.4064 0.4572 0.5588
c 0.1778 0.254 0.3302
D 16.4592 16.5862 16.7132
E 16.4592 16.5862 16.7132
e 1.27 BSC
GD 14.986 15.494 16.002
GE 14.986 15.494 16.002
HD 17.272 17.526 17.78
HE 17.272 17.526 17.78
L 2.286 2.54 2.794

Data Sheet - Version 1.0 Page 16 of 18 http://www.topro.com.tw

May 2007
 TP2852
8051 MICROCONTROLLER WITH 8K FLASH AND ISP

44-pin PQFP

Unit: Millimeter

Dimension in mm NOTES:
Symbol
Min. Nom. Max. 1. Dimensions D and E do not include interlead flash.
A — — 2.7 2. Dimension b does not include dam bar protrusion/intrusion.
A1 0.25 — 0.5
3. JEDEC Outline: MO-108 AA-1.
A2 1.9 2.0 2.2

b 0.3 TYP.

c 0.10 0.15 0.20

D 9.9 10.00 10.1

E 9.9 10.00 10.1

e 0.80 TYP.

HD 13 13.2 13.4

HE 13 13.2 13.4

L 0.73 0.88 0.93

L1 — 1.6 —

y 0.10

θ° 0∘ — 7∘

Data Sheet - Version 1.0 Page 17 of 18 http://www.topro.com.tw

May 2007
 TP2852
8051 MICROCONTROLLER WITH 8K FLASH AND ISP

◎Headquarters
5 F, No. 10, Prosperity Road 1, Science-Based Industrial Park, Hsinchu, Taiwan 300, R.O.C
Tel.: +886-3-563-2585 Fax: +886-3-563-2588

Data Sheet - Version 1.0 Page 18 of 18 http://www.topro.com.tw

May 2007