Advanced UVM
Modeling Transactions
Tom Fitzpatrick
Strategic Verification Architect
Separating Stimulus from the Testbench
A key to reusability is to separate Behavior from Structure
Transactions (a.k.a. Sequence Items) are the main communication vehicle
across the boundary
Configuration & Factory
Behavior
Structure
Testbench VIP
DUT
2 Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Review: Sequences
Decouple stimulus specification from
structural hierarchy
• Add/remove/modify stimulus scenarios independent
u1
of testbench
• Simplify test writer API u1 s1
Sequences define
transaction streams
• May start on any sequencer s3 s5
Sequences can call children s2
Sequences & transactions customizable
s4
via the factory
3 Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Designing a Sequence Item
class bus_item extends uvm_sequence_item;
`uvm_object_utils(bus_item) This is the
“transaction”
rand int delay;
rand logic[31:0] addr; Make all “input”
rand op_code_enum op_code; properties rand
rand logic[31:0] data[];
string slave_name;
bit response;
function new(string name);
super.new(name);
endfunction Methods for
do_copy()
do_compare() standard
convert2string() operation
do_print()
do_record() Users call copy(),
do_pack() compare()…
do_unpack()
endclass: bus_item
4 Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Designing a Sequence Item: Methods
class bus_item extends uvm_sequence_item; do_copy()
`uvm_object_utils(bus_item)
function void do_copy(uvm_object rhs);
bus_item rhs_;
Virtual method
do_copy()
do_compare()
convert2string()
do_print()
do_record()
endfunction
do_pack()
do_unpack()
endclass: bus_item
5 Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Designing a Sequence Item: Methods
class bus_item extends uvm_sequence_item; do_copy()
`uvm_object_utils(bus_item)
function void do_copy(uvm_object rhs);
bus_item rhs_; Make sure argument
is of correct type
if(!$cast(rhs_, rhs)) begin
uvm_report_error("do_copy:", "Cast failed");
return;
end
endfunction: do_copy
endclass: bus_item
6 Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Designing a Sequence Item: Methods
class bus_item extends uvm_sequence_item; do_copy()
`uvm_object_utils(bus_item)
function void do_copy(uvm_object rhs);
bus_item rhs_;
if(!$cast(rhs_, rhs)) begin
uvm_report_error("do_copy:", "Cast failed");
return;
end Chain the copy with
super.do_copy(rhs); parent classes
endfunction: do_copy
endclass: bus_item
7 Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Designing a Sequence Item: Methods
class bus_item extends uvm_sequence_item; do_copy()
`uvm_object_utils(bus_item)
function void do_copy(uvm_object rhs);
bus_item rhs_;
if(!$cast(rhs_, rhs)) begin
uvm_report_error("do_copy:", "Cast failed");
return;
end
super.do_copy(rhs);
this.delay = rhs_.delay;
this.addr = rhs_.addr; Copy members of
this.op_code = rhs_.op_code; rhs to this
this.slave_name = rhs_.slave_name;
this.data = rhs_.data;
this.response = rhs_.response;
endfunction: do_copy
endclass: bus_item
8 Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Designing a Sequence Item: Methods
class bus_item extends uvm_sequence_item; do_copy()
`uvm_object_utils(bus_item)
function void do_copy(uvm_object rhs);
bus_item rhs_;
if(!$cast(rhs_, rhs)) begin
uvm_report_error("do_copy:", "Cast failed");
return;
end
super.do_copy(rhs); USAGE:
delay = rhs_.delay; bus_item A, B;
addr = rhs_.addr; Deep copy
A.copy(B);
op_code = rhs_.op_code;
slave_name = rhs_.slave_name; OR
data = rhs_.data; $cast(A, B.clone());
response = rhs_.response;
endfunction: do_copy Clone returns
a uvm_object
endclass: bus_item
9 Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Designing a Sequence Item: Methods
class bus_item extends uvm_sequence_item; do_copy()
`uvm_object_utils(bus_item) do_compare()
function bit do_compare(uvm_object rhs,
uvm_comparer comparer);
bus_item rhs_;
Policy class: don’t use
if(!$cast(rhs_, rhs)) begin
return 0;
end 0 = MISMATCH
endfunction: do_compare
endclass: bus_item
10 Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Designing a Sequence Item: Methods
class bus_item extends uvm_sequence_item; do_copy()
`uvm_object_utils(bus_item) do_compare()
function bit do_compare(uvm_object rhs,
uvm_comparer comparer);
bus_item rhs_;
if(!$cast(rhs_, rhs)) begin Chain the compare
return 0; with parent classes
end
return((super.do_compare(rhs, comparer) &&
endfunction: do_compare
endclass: bus_item
11 Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Designing a Sequence Item: Methods
class bus_item extends uvm_sequence_item; do_copy()
`uvm_object_utils(bus_item) do_compare()
function bit do_compare(uvm_object rhs,
uvm_comparer comparer);
bus_item rhs_;
if(!$cast(rhs_, rhs)) begin
return 0;
end
return((super.do_compare(rhs, comparer) &&
(delay == rhs_.delay) && Compare members
(addr == rhs_.addr) && of rhs to this
(op_code == rhs_.op_code) &&
(slave_name == rhs_.slave_name) &&
close_enough(data, rhs_.data) && 1 = MATCH
(response == rhs_.response));
endfunction: do_compare
endclass: bus_item
12 Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Designing a Sequence Item: Methods
class bus_item extends uvm_sequence_item; do_copy()
`uvm_object_utils(bus_item) do_compare()
function string convert2string(); convert2string()
string s;
s = super.convert2string();
endfunction: convert2string
endclass: bus_item
13 Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Designing a Sequence Item: Methods
class bus_item extends uvm_sequence_item; do_copy()
`uvm_object_utils(bus_item) do_compare()
function string convert2string(); convert2string()
string s;
s = super.convert2string();
$sformat(s,
"%s\n %s\n delay \t%0d\n addr \t%0h\n op_code \t%s\n slave_name \t%s\n",
s, this.get_name(), delay, addr, op_code.name(), slave_name);
Returns enum
value as a string
endfunction: convert2string
endclass: bus_item
14 Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Designing a Sequence Item: Methods
class bus_item extends uvm_sequence_item; do_copy()
`uvm_object_utils(bus_item) do_compare()
function string convert2string(); convert2string()
string s;
s = super.convert2string(); Iterate through
array values
$sformat(s,
"%s\n %s\n delay \t%0d\n addr \t%0h\n op_code \t%s\n slave_name \t%s\n",
s, this.get_name(), delay, addr, op_code.name(), slave_name);
foreach(data[i]) begin
$sformat(s, "%s data[%0d] \t%0h\n", s, i, data[i]);
end
endfunction: convert2string
endclass: bus_item
15 Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Designing a Sequence Item: Methods
class bus_item extends uvm_sequence_item; do_copy()
`uvm_object_utils(bus_item) do_compare()
function string convert2string(); convert2string()
string s;
s = super.convert2string();
$sformat(s,
"%s\n %s\n delay \t%0d\n addr \t%0h\n op_code \t%s\n slave_name \t%s\n",
s, this.get_name(), delay, addr, op_code.name(), slave_name);
foreach(data[i]) begin
$sformat(s, "%s data[%0d] \t%0h\n", s, i, data[i]);
end
$sformat(s, "%s response \t%0b\n", s, response);
return s;
USAGE:
endfunction: convert2string bus_item A;
`uvm_info(“Bus_Item A”,A.convert2string(), UVM_NONE)
endclass: bus_item
16 Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Designing a Sequence Item: Methods
class bus_item extends uvm_sequence_item; Printer policy do_copy()
`uvm_object_utils(bus_item) class do_compare()
function void do_print(uvm_printer printer); convert2string()
printer.print_field(“delay”, delay, $bits(delay), do_print()
UVM_DEC);
printer.print_field(“addr”, addr, $bits(addr));
printer.print_string(“opcode”, opcode.name());
printer.print_string(“slave_name”, slave_name);
printer.print_array_header(“data”, data.size);
foreach(data[i]) begin
printer.print_field($sformatf(“data[%0d]”, i), data[i], $bits(data[i]));
end
printer.print_array_footer();
printer.print_field(“response”, response, 1); USAGE:
endfunction: do_print bus_item A;
A.print();
endclass: bus_item
17 Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Designing a Sequence Item: convert2string vs do_print
class bus_item extends uvm_sequence_item; do_copy()
`uvm_object_utils(bus_item) do_compare()
convert2string: convert2string()
# UVM_INFO tb.sv(73) @ 0: uvm_test_top [Bus_Item A] do_print()
# A
# delay 10
# addr abcd
# op_code ADD do_print:
# slave_name SLAVE1 # ----------------------------------------
# data[0] deadbeef # Name Type Size Value
# data[1] a0b1c2d3 # ----------------------------------------
# response 1 # A bus_item - @473
# delay integral 32 'd10
# addr integral 32 'habcd
# opcode string 3 ADD
# slave_name string 6 SLAVE1
# data array 2 -
# data[0] integral 32 'hdeadbeef
# data[1] integral 32 'ha0b1c2d3
# response integral 1 'h1
# ----------------------------------------
endclass: bus_item
18 Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Designing a Sequence Item: Methods
class bus_item extends uvm_sequence_item; do_copy()
`uvm_object_utils(bus_item) do_compare()
function void do_record(uvm_recorder recorder); convert2string()
super.do_record(recorder); do_print()
do_record()
Record inherited
data members
endfunction: do_record
endclass: bus_item
19 Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Designing a Sequence Item: Methods
class bus_item extends uvm_sequence_item; do_copy()
`uvm_object_utils(bus_item) do_compare()
function void do_record(uvm_recorder recorder); convert2string()
super.do_record(recorder); do_print()
`uvm_record_field("delay", delay) do_record()
`uvm_record_field("addr", addr)
`uvm_record_field("op_code", op_code.name())
`uvm_record_field("slave_name", slave_name)
Simulator-specific implementation
Questa uses $add_attribute
endfunction: do_record
endclass: bus_item
20 Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Designing a Sequence Item: Methods
class bus_item extends uvm_sequence_item; do_copy()
`uvm_object_utils(bus_item) do_compare()
function void do_record(uvm_recorder recorder); convert2string()
super.do_record(recorder); do_print()
`uvm_record_field("delay", delay) do_record()
`uvm_record_field("addr", addr)
`uvm_record_field("op_code", op_code.name())
`uvm_record_field("slave_name", slave_name)
foreach(data[i]) begin Iterate through array values
`uvm_record_field($sformatf("data[%0d]", i), data[i])
end
`uvm_record_field("response", response)
endfunction: do_record
USAGE:
uvm_config_db#(int)::set(this,”*”,”recording_detail”, UVM_FULL);
endclass: bus_item
21 Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Designing a Sequence Item: Methods
class bus_item extends uvm_sequence_item; do_copy()
`uvm_object_utils(bus_item) do_compare()
function void do_pack(uvm_packer packer); convert2string()
super.do_pack(packer); do_print()
… do_record()
endfunction: do_pack do_pack()
do_unpack()
function void do_unpack(uvm_packer packer);
super.do_unpack(packer);
…
endfunction: do_unpack
See the
Online UVM Cookbook
for details
endclass: bus_item
22 Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Sequence Item Composition
bus_item my_bus_item
extends uvm_sequence_item; extends bus_item;
rand int delay; bit status;
rand logic[31:0] addr; logic[31:0] result;
rand op_code_enum op_code;
rand logic[31:0] data[];
Extension constraint c {addr >= 0 &&
addr < 'h100;}
Composition
bus_item_pair
extends uvm_sequence_item;
rand bus_item a;
rand bus_item b;
23 Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Modeling Sequence Items
Encapsulate the information needed to process an operation
• Whatever that means for your application
Helper functions
• do_copy() • do_print()
• do_compare() • do_record()
• convert2string() • do_pack()/do_unpack()
Do not use `uvm_field* macros
• Decreases performance
• Hinders debug
Use inheritance for similar transactions
Use composition when needed
24 Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Summary: Rules for Sequence Items
Define sequence items by specifying data members only
• Do not override pre/mid/post_do
Create items via their type_id
• my_item::type_id::create(“tx”);
Execute items using start_item()/finish_item()
25 Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Advanced UVM
Modeling Transactions
Tom Fitzpatrick
Strategic Verification Architect
