COMPX203 Computer Systems

Exceptions and Interrupts

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Structure
• Recap
• Overview
• WRAMP Implementation

Recap
• Data representation, ASCII codes
• Memory-mapped style of Input and Output
• Special addresses are used to interact with I/O devices
• WRAMP implementation
• Addresses are mapped to I/O device “special registers”
• I/O with Parallel port
• I/O with Serial port
• Polling-based I/O

Exceptions and Interrupts

Overview
 Polling Example: Text Messages
loop: Check SMS inbox
Is there a new message?
If not, go to loop

Read the message

Reply to the message
Wait for some time
Go to loop

Is there a better way?

A Solution: Notifications
How about we have the phone tell you when a
message arrives?

Notification: new message!

Read the message

Reply to the message
Get back to what you were doing

Interrupts are like the notifications

• Polling is (often) inefficient if the time between two
events is long
• A better solution is for an external device to interrupt
the CPU when some event has occurred
• The CPU can handle the interrupt, do some
processing, and then return to what it was doing

Exceptions vs. Interrupts

• Interrupts are caused by hardware (devices)
• Exceptions are caused by software
• Examples of exceptions are
• arithmetic instruction (e.g. dividing by zero)
• trying to access an invalid memory position
• changing a CPU protection mode from user to privileged
• Exceptions and Interrupts are typically handled the
same way

Interrupt Example
Main Program

An interrupt occurs

Interrupt Handler

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Interrupt Handler vs. a subroutine
• An interrupt handler performs actions like a
subroutine but
• Is triggered by an event instead of called
• No “passed parameters”- info stored in status registers
• Rather than returning a value, usually reset triggers

• A CPU may support multiple handlers – one for each

exception source

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An Exception/Interrupt Handler will…

• Determine what caused the interrupt or exception
• Respond or deal with it, such as
• Read a character that has arrived
• Print a divide-by-zero error message
• Terminate a running program (e.g. ”core dump”)
• Return to the point at which the interrupt occurred

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An Exception/Interrupt Handler should…

• have no major effect on the main program:
• should return to the point where the main program was
interrupted
• should not change values stored in general registers

• be fast, so the main program isn’t held up for too

long (or other interrupts may be missed)
• If a lot of work needs to be done, the handler itself might
only set a flag and store a value – the actual work can then
be done later

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CPU should be able to
• Enable and disable specific interrupts (which to
notice and which to ignore)
• Automatically jump to a handler routine at interrupt
• Detect what caused the interrupt
• Return back to the main program when the interrupt
handler is finished

• Uses dedicated Interrupt Request wires (IRQ lines)

connected to external devices
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Device Support for Interrupts

• Many I/O devices support interrupts
• Interrupts can be enabled/disabled at the device (e.g. by
writing to a device register)
• To trigger an interrupt, a device sends a signal to the CPU
via its IRQ line
• When the CPU has finished handling the interrupt, it
must tell the device that it has finished
• This is known as “acknowledging the interrupt”
• This is normally done by writing to a register in the I/O device

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Device Support for Interrupts

• Some devices can generate interrupts for more than
one reason
• e.g. Serial Port
• Character received
• Character sent

• We need to be able to tell which of these events

caused the interrupt
• Look at the relevant device registers

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Exceptions and Interrupts – Summary

• Interrupts solve inefficiency of polled I/O
• Exceptions can handle error conditions
• Exceptions (software) are “internally generated” by
running instructions of a program
• Interrupts (hardware) are “externally generated”
• Interrupts allow the CPU to respond to external
events

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Exceptions and Interrupts – Summary

• When an interrupt or exception occurs during

program operation, control is transferred to an
interrupt or exception handler
• The handler routine deals with the exception or
interrupt and returns without affecting the running
program (at least in unpredictable ways)

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Exceptions and Interrupts

WRAMP Implementation
Interrupts Supported by WRAMP
• Support for eight interrupt sources (IRQ0 – IRQ7)
• Parallel Interface
• Serial Ports
• Timer
• Support for four exception sources
• Arithmetic Exception (divide-by-zero, overflow)
• General Protection Fault Exception (illegal instruction, memory
access fault)
• System Call Exception (syscall instruction)
• Breakpoint Exception (break instruction)

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WRAMP Interrupt Requests (IRQs)

IRQ0 Unused
IRQ1 User Interrupt Button
IRQ2 Timer Interrupt
IRQ3 Parallel Interrupt
IRQ4 Serial Port 1 Interrupt
IRQ5 Serial Port 2 Interrupt
IRQ6 Unused
IRQ7 Unused

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Example (pseudocode) for using Interrupts
main:
# Setup interrupts
…
loop:
# Main program loop ("Mainline" code)
…
j loop

handler:
# Check which exception occurred
# If it is the one we want, jump to
# handle_interrupt
# Otherwise, jump to the system handler

handle_interrupt:
# Do our handler stuff
# Acknowledge the interrupt
# Return from the interrupt (rfe)

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WRAMP Special Registers

• To support interrupts, we need to…
• Configure which (if any) interrupts are enabled
$cctrl, the CPU Control Register
• Set which address to go when an exception occurs
$evec, the Exception Vector Register
• Know what caused the exception
$estat, the Exception Status Register
• Know where to go back to once the handler is done
$ear, the Exception Address Register

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Access to WRAMP Special Registers
• Access achieved via instructions movsg and movgs
• movsg copies a value from a special register to a general
one, e.g. movsg $2, $cctrl
• movgs copies a value from a general register to a special
one, e.g. movgs $cctrl, $2
• We must be in kernel mode to be able to use these
instructions
• Otherwise we’d cause a General Protection Fault (GPF)

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 CPU Control Register

31 11 4 3 2 1 0

OKU

OIE
KU

IE
Undefined IntMask

IRQ7
Interrupt Mask Bits …
IRQ0

Kernel/User Mode (KU)

Old Kernel/User Mode (OKU)
Interrupt Enable (IE)
Old Interrupt Enable (OIE)

Interrupt Mask provides a way to selectively turn on and off individual interrupts (but not exceptions)

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Setting up WRAMP Interrupts

• Within the CPU:
• Global interrupts must be turned on (IE = '1')
• The interrupt(s) we want must be turned on
(corresponding bit(s) in IntMask = ‘1’) (more next slide)

• Within other hardware:

• The device(s) we’re interested in might need to be
explicitly configured to generate interrupts
• Writing to their special registers

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Interrupt mask (part of CPU Control Register)

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CPU Control Register ($cctrl)
e.g. We wish to setup the CPU to allow only IRQ1 (user interrupt button):

…
# Copy the current value of $cctrl into $2
movsg $2, $cctrl

# Mask (disable) all interrupts

andi $2, $2, 0x000f

# Enable IRQ1 and IE (global interrupt enable)

ori $2, $2, 0x22

# Copy the new CPU control value back to $cctrl

movgs $cctrl, $2
…

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Exception Vector Register

• The processor needs to know which address to jump
to when an exception occurs
• We use the Exception Vector Register ($evec) to tell
the processor where our exception handler is (i.e. its
address)
• If our handler doesn’t handle all types of interrupts
and exceptions, we need to remember the address of
the default exception handler so that we can call it
when needed

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Default (System) Exception Handler

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Exception Vector Register ($evec)
e.g. Set the CPU to go to our handler when an exception occurs …
…
# Copy the old handler’s address to $2
movsg $2, $evec

# Save it to memory
sw $2, old_vector($0)

# Get the address of our handler

la $2, handler

# And copy it into the $evec register

movgs $evec, $2
…
.bss
old_vector:
.word

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Exception Status Register

• When an exception has occurred we need to be able to
tell what caused it:
• Timer interrupt?
• Serial port interrupt?
• Divide-by-zero exception?
• When an interrupt occurs, this information is available in
the Exception Status Register ($estat).
• We use this to decide which handler to call.
• One of ours?
• The default handler that we saved earlier?

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 Exception Status Register

31 15 12 11 4 0
Undefined HW Ints Undef

Arithmetic
Software Breakpoint
Exceptions Syscall
GPF

IRQ7
Hardware
…
Interrupts
IRQ0

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Exception Status Register ($estat)

e.g. Decide whether the exception was caused by IRQ1
handler:
# Get the value of the exception status register
movsg $13, $estat
# Check if there are interrupts other than IRQ1
# All bits but 5 should be 0
andi $13, $13, 0xffd0
# If so, go to our handler
beqz $13, handle_irq1

# Otherwise, jump to the default handler

# that we saved earlier.
lw $13, old_vector($0)
jr $13

handle_irq1:
# Handle our interrupt
…

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Exception Address Register

• When an exception occurs, we need to remember
the value of the Program Counter
• This is stored automatically into the Exception
Address Register ($ear)
• When an rfe (return from exception) instruction is
executed, the Program Counter is set back to the
value of $ear

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 Return From Exception

e.g. Return to the main program after an exception.

handle_irq1:
# Handle our interrupt
…
# Acknowledge the interrupt
…
# Return to the main program
# (Return From Exception)
rfe

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Setting up a Device for Interrupts

• Most devices won’t generate interrupts without
being explicitly configured to do so
• This normally involves writing to its control register
• It’s good practice to acknowledge any outstanding
interrupts as well

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Example: Timer
Set up the timer to generate an interrupt every 10s

Basic steps:
1. Acknowledge interrupt
2. Reload timer
3. Restart timer

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Programmable Timer
• WRAMP contains a • The programmer sees:
programmable timer, which can • Four registers
create an interrupt at defined
intervals from 1 msec to 30 sec • Base address is 0x72000
with a resolution of about 0.5
msec. Register Name Offset
• The timer has an internal 16-bit
register, decremented at a Timer Control 0
constant rate of 2400 Hz. When
the count reaches 0, an Timer Load 1
interrupt is triggered.
• The starting value can be set Timer Count 2
(timer load register)
• The timer can be set to auto Timer IA 3
reload the value

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Timer Register: Control and Load

• Timer Control Register • Timer Load Register

• Location: 0x72000 • Location: 0x72001
• Read/write register • Read/write register
• Two basic modes: • The user can specify the
• Single shot starting value (and thus,
• Auto reload the delay)
• 16 bit value… upper bits
31 10 ignored.
undefined

Auto Reload Timer enable

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Timer Register: Count and IA

• Timer Count Register • Timer IA Register

• Location: 0x72002 • Location: 0x72003
• Read-only register • Read/write register
• Reading returns current • Detects timer overrun
value of register • If timer autoload is set
and last interrupt was
not acknowledged
before time expires
10
again.
31
• Manually reset
undefined
Overrun detected

Interrupt Ack

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Example: Timer
e.g. Setup the timer to generate an interrupt every 10s

…
# Acknowledge any outstanding interrupts
sw $0, 0x72003($0)
# Put our count value into the timer load reg
addi $11, $0, 24000
sw $11, 0x72001($0)
# Enable the timer and set auto-restart mode
addi $11, $0, 0x3
sw $11, 0x72000($0)
…

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Compliant Exception Handlers

• Registers are shared between mainline code and
exception handlers
• However, register $13 is automatically saved ($ers) and
restored, so may be used freely in a handler
• A compliant exception handler must save and restore
any other register values, including $1

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Interrupting an Interrupt Handler?

• What would happen if we got another exception
while inside our exception handler?
• The address stored in $ear would be overwritten.
• We could not get back to where we came from.
• We must ensure that no exceptions occur when in
the handler
• Hardware interrupts are prevented by disabling
interrupts while handling an exception
• WRAMP does this automatically

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$cctrl on an Exception

OKU

OIE
KU

IE
1 0

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$cctrl on RFE

OKU

OIE
KU

IE
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Interrupting an Interrupt Handler?
• Any interrupts that occur while interrupts are
disabled will be handled as soon as interrupts are
turned back on (e.g. after rfe)
• Software exceptions, however, cannot be disabled!
• To prevent software exceptions, we need to write our
handler code very carefully (no overflow, or divide-
by-zero)

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Interrupt Process
• The CPU checks if interrupts are enabled (IE = ‘1’)
• The CPU checks if that particular interrupt is enabled
• PC is saved to $ear
• Bits in $estat are set to indicate which exception(s) have
occurred
• The IE and KU bits in $cctrl are copied into the OIE and
OKU bits respectively
• Interrupts are disabled and the CPU is set to kernel mode (IE =
‘0’, KU = ‘1’)
• Value of register $13 is automatically saved to $ers
• The CPU jumps to the address stored in $evec
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Interrupt Process
• Once the handler is finished, and the interrupt has
been acknowledged, the rfe instruction must be
executed.
• rfe will:
• Copy the OIE and OKU bits back to IE and KU,
respectively
• Restore the value of register $13 from $ers
• Jump back to where the exception occurred ($ear)

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Exceptions and Interrupts – Summary

Exceptions and Interrupts – Summary
• Exceptions and Interrupts avoid the inefficiencies of
polling
• The CPU automatically jumps to an exception
handler when an exception occurs
• These handlers can be chained, for example by calling the
default handler if we don’t know how to handle a
particular interrupt
• Configuration is done with special registers on the
CPU (using movgs and movsg instructions), and
device registers on I/O devices (using lw and sw
instructions)

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Homework
• Read chapter 4 of the manual

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