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Pico Alu

This document describes a 4-bit ALU for use in a picoprocessor datapath. It includes entity and architecture definitions for the ALU in VHDL. The ALU performs addition, subtraction, AND, OR, and complement operations on 4-bit registers and sets status flags for negative, zero, overflow, and carry out in the ccr_out signal.

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134 views2 pages

Pico Alu

This document describes a 4-bit ALU for use in a picoprocessor datapath. It includes entity and architecture definitions for the ALU in VHDL. The ALU performs addition, subtraction, AND, OR, and complement operations on 4-bit registers and sets status flags for negative, zero, overflow, and carry out in the ccr_out signal.

Uploaded by

api-547507672
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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-- File Name: pico_alu.vhd


-- Engineer: Seth Cram
--
-- Create Date: 15:07:31 04/24/2021
-- Design Name: Picoprocessor Lab
-- Project Name: ECE 241 - Lab 13
-- Target Device: Spartan 2 XC2s30-6tq144
-- Tool versions: Xilinx ISE 9.2
-- Description: 4-bit ALU for use with Picoprocessor within the datapath
--
-- Dependencies: None
--
-- Additional Comments:
-- The ccr_out signal corresponds to four 1-bit signals, NZVC: (N) alu_out is
negative; (Z) alu_out is zero;
-- (V) overflow occurred under 2's complement arithmetic; and (C) a carry/borrow
occurred under unsigned arithmetic.
-- The last two signals (V and C) are only set on arithmetic operations and are
otherwise cleared.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity alu is
Port ( rega : in std_logic_vector(3 downto 0);
regb : in std_logic_vector(3 downto 0);
controls : in std_logic_vector(3 downto 0);
alu_out : out std_logic_vector(3 downto 0);
ccr_out : out std_logic_vector(3 downto 0));
end alu;

architecture Behavioral of alu is

signal carry_alu: std_logic_vector(4 downto 0); -- for C flag


signal temp_alu: std_logic_vector(3 downto 0); -- need to find Z and N flag bc
can't do signal assignment with an ouput signal on RHS
signal N,Z,V,C: std_logic; -- signal variables for flags

begin

process(controls,rega,regb,carry_alu,temp_alu)
begin

-- flags initialized to zero by default


N <= '0';
Z <= '0';
V <= '0';
C <= '0';

case controls is
when "0000" => -- addition opcode
carry_alu <= ( ('0' & rega) + ('0' & regb) ); -- appends zero for
extra bit then adds
C <= carry_alu(4); -- carry out if msb is 1
V <= ( ((rega(3) AND regb(3)) AND not(carry_alu(3)) ) OR
( not(rega(3) OR regb(3)) AND carry_alu(3) ) ); -- if resultant msb different than
operand msbs, V flag set
temp_alu <= rega + regb;
when "0001" => -- subtraction opcode
carry_alu <= ( ('0' & rega) - ('0' & regb) ); -- appends zero for
extra bit then subtracts
C <= carry_alu(4); -- carry out if msb is 1
V <= ( (rega(3) AND not(regb(3))) AND not(carry_alu(3)) ) OR
( ((not(rega(3)) AND regb(3)) AND carry_alu(3)) );
temp_alu <= rega - regb;
when "0010" => -- AND opcode
temp_alu <= rega AND regb;
when "0011" => -- OR opcode
temp_alu <= rega OR regb;
when "0100" => -- rega's complement opcode
temp_alu <= not(rega);
when "0101" => -- rega load opcode
temp_alu <= rega;
when others =>
temp_alu <= "0000"; -- default value
end case;

-- assignments regardless of opcode:


if temp_alu = "0000" then Z <= '1';
else Z <= '0';
end if;
N <= temp_alu(3); -- if msb is 1, N flag set

end process;

--need to do outside of process:


alu_out <= temp_alu;
ccr_out(3) <= N;
ccr_out(2) <= Z;
ccr_out(1) <= V;
ccr_out(0) <= C;

end Behavioral;

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